JP4336001B2 - IC test equipment - Google Patents

Description

[0001]
BACKGROUND OF THE INVENTION
The present invention relates to an IC test apparatus for testing, for example, a semiconductor integrated circuit element (IC), and more particularly to improvement of a timing generator.
[0002]
[Prior art]
FIG. 6 shows a schematic configuration of the IC test apparatus. In the figure, TES indicates the entire IC test apparatus. The IC test apparatus TES includes a main controller 111, a pattern generator 112, a timing generator 113, a waveform formatter 114, a logical comparator 115, a driver 116, an analog comparator 117, a failure analysis memory 118, a logical amplitude reference voltage source 121, The reference voltage source 122, the device power source 123, and the like are included.
[0003]
The main controller 111 is generally constituted by a computer system, controls the pattern generator 112 and the timing generator 113 according to a test program created by the user, generates test pattern data from the pattern generator 112, and generates the test pattern data. The waveform formatter 114 converts the test pattern signal into a test pattern signal having an actual waveform, and the test pattern signal is applied to and stored in the IC under test 119 through a driver 116 that amplifies the voltage into a waveform having an amplitude value set by the logic amplitude reference voltage source 121. .
[0004]
The response signal read from the IC under test 119 is compared with the reference voltage supplied from the comparison reference voltage source 122 by the analog comparator 117, and whether or not it has a predetermined logic level (H logic voltage, L logic voltage). The signal determined to have a predetermined logic level is compared with the expected value output from the pattern generator 112 by the logic comparator 115, and if a mismatch with the expected value occurs, the read address It is determined that there is a defect in the memory cell, a defect address is stored in the defect analysis memory 118 every time a defect occurs, and it is determined, for example, whether the defective cell can be repaired at the end of the test.
[0005]
Here, the timing generator 113 compares the timing specifying the rising timing and falling timing of the waveform of the test pattern signal supplied to the IC under test 119 according to the timing information supplied from the pattern generator 112 with the logical comparator 115. The timing of the strobe pulse that defines the timing is generated.
[0006]
Each of these timings is described in a test program created by the user, and the IC under test 119 is operated at a timing intended by the user, and whether or not the operation is normal can be tested.
Here, an outline of the timing generator will be described in advance. FIG. 7 shows a schematic configuration of a general standard timing generator. The timing generator 113 is roughly composed of a standard cycle generator 11 and a standard delay generator 12.
[0007]
The standard cycle generator 11 generates a cycle signal RATE for determining a test cycle, and supplies the cycle signal RATE to each standard delay generator 12. The standard delay generation unit 12 determines the periodic signal RATE supplied from the standard cycle generation unit 11 as a reference phase, and determines the rising timing and falling timing of the test pattern signal applied to each terminal of the IC under test. Perform the action to be performed.
[0008]
In order to facilitate understanding of the present invention, an outline of the configuration and operation of the standard cycle generator 11 and the standard delay generator 12 will be described in advance.
FIG. 8 shows the configuration of the standard cycle generator 11. The standard cycle generation unit 11 includes a cycle setting data memory 11A, an addition calculation unit 11B, a down counter 11C, and a zero detector 11D.
[0009]
TS indicates a timing set signal sent from the pattern generator 112. This timing set signal is sent in synchronization with the periodic signal RATE output from the zero detector 11D, and is used as a read address of the period setting data memory 11A. That is, for example, about 16 types of timing data are stored in the cycle setting data memory 11A, and these 16 types of timing data are read for each test cycle in accordance with the timing set signal TS.
[0010]
Here, D-type flip-flop DFF _1-1 ~DFF _1-6, and _{DFF 2-2 ~DFF 2-5, DFF 3-3 ~DFF} 3-5, DFF 4-3, DFF 4-7, DFF 5 Reference numerals _{-1 to} DFF _5-6 denote latch circuits that constitute pipelines for sequentially feeding data in synchronization with the periodic signal RATE output from the zero detector 11D. These reference clock REFCK respectively to the clock input terminal CK of the latch circuit DFF _1-1 ~DFF _5-6 is input, the feedback circuit 11E and an AND gate 11F via enable signal to further enable terminal EN from zero detection circuit 11D However, the clear signal CLR is given to the clear terminal. Accordingly, the data of each part is sequentially sent to the next stage in synchronization with the rising timing of the reference clock REFCK, for example, in the state where the periodic signal RATE is H logic, and pipeline processing is executed. The clear signal CLR is input at the start of the test and all the states are reset.
[0011]
The timing set signal TS passes through a six-stage latch circuit and is delivered to the standard delay generator 12 shown in FIG. 9 as the timing set signal TSR. While the timing set signal TS passes through the six-stage latch circuits DFF _{1-1 to} DFF _1-6 , the standard cycle generator 11 executes the generation process of the cycle signal RATE for determining the test cycle.
[0012]
That is, the timing set signal TS is input to the address input terminal AD of the cycle setting data memory 11A, and the cycle data is read from the cycle setting data memory 11A. As described above, about 16 types of cycle data are stored in advance in the cycle setting data memory 11A, and these 16 types of cycle data are read for each test cycle, and the cycle for each test cycle. Signal RATE is set.
[0013]
The period of the periodic signal RATE is set as follows. Period data for determining the period of the period signal RATE is read from the period setting data memory 11A. This period data is composed of integer data VDAT ₁ having an integer multiple of the reference clock REFCK and fraction data MDAT ₁ having a value shorter than one period of the reference clock REFCK. Here, since the presence of the fraction data MDAT ₁ is not directly related to the present invention, it is assumed that the value of the fraction data MDAT ₁ is 0.
[0014]
Activation and deactivation of the standard cycle generator 11 is controlled by a gate signal GATE given from the pattern generator 112. An example of the operation when the standard cycle generator 11 is activated will be described below. That is, when the gate signal GATE is inverted to H logic at the start of the test (see FIG. 10B), since the contents of the down counter 11C are all zero in the initial state, the zero detector 11D outputs H logic. Therefore, the AND gate 11F outputs H logic. The H logic is applied to all the enable terminal EN of the latch circuit DFF _1-1 ~DFF _5-6. As a result, the latch circuit DFF _1-1 ~DFF _5-6 latches the data for each timing of the leading example of a reference clock REFCK given to a clock terminal CK, the next stage of the latch in the state of fast-forward the latched data Executes the operation to pass to the circuit.
[0015]
In the example shown in FIG. 8, the latch circuit DFF _1-1 , the cycle setting data memory 11A, the latch circuits DFF _2-2 , DFF _2-3 , and DFF _2-4 are loaded before the cycle data is loaded into the down counter 11C. When six reference clocks REFCK are input from the timing when the gate signal GATE rises to H logic as shown in FIGS. 10A and B because it passes through the five-stage pipeline, it is first read from the period setting data memory 11A. The cycle data thus loaded is loaded into the down counter 11C.
[0016]
When the period data read from the period setting data memory 11A is loaded into the down counter 11C, the output of the down counter 11C outputs the loaded value, so that the output of the zero detector 11D falls to L logic ( see FIG. 10C), the output of aND gate 11F is also falls to the L logic (see FIG. 10D), by the output of aND gate 11F is falls to L logic, the latch circuit DFF _1-1 ~DFF _5-6 non The enabled state is entered, and the pipeline operations of the latch circuits DFF _{1-1 to} DFF _5-6 are stopped.
[0017]
Assuming that the period data first loaded into the down counter 11C is “4” as shown in FIG. 10E, for example, when 4 + 1 reference clocks REFCK are input to the down counter 11C, the contents are all zero. Return and hold in all-zero state. Since the contents of the down counter 11C is returned to the state of the all-zero-zero detector 11D outputs a logical H, the latch circuit DFF _1-1 enable ～DFF _5-6 through the H logic feedback circuit 11E and an AND gate 11F Input to terminal EN. In this state, when the reference clock REFCK rises to logic H, the pipeline operates and the period data of the next period latched in the latch circuit DFF _2-5 is loaded into the down counter 11C. The example shown in FIG. 10C shows a case where “4” is loaded again. In this way, after that, the cycle of the cycle signal RATE is determined according to the cycle data read from the cycle setting data memory 11A for each test cycle, and the cycle signal RATE is generated. Note that the value of the cycle data stored in the cycle setting data memory 11A stores the value of N-1 when the value to be set is N.
[0018]
Since the gate signal GATE falls to the L logic at the end of the test, the AND gate 11F is closed and the periodic signal RATE is not fed back as an enable signal, and the generation of the periodic signal RATE is stopped.
Next, the configuration and operation outline of the standard delay generator 12 will be described with reference to FIG. The standard delay generation unit 12 includes a delay setting data memory 12A, an addition processing unit 12B, a down counter 12C, a zero detector 12D, and a fractional delay unit 12E.
[0019]
The standard delay generator 12 also includes a pipeline composed of latch circuits DFF _{1-1 to} DFF _1-5, and a periodic signal RATE is supplied to this pipeline, and the H logic of the periodic signal RATE is lowered through this pipeline. Input to the load command terminal LD of the counter 12C. Therefore, when each standard delay generator 12 receives the supply of the periodic signal RATE from the standard cycle generator 11, the delay data read from the delay setting data memory 12A is loaded into the down counter 12C and output from the fraction delay unit 12E. When the generation of the delay timing signal P _OUT is started and the supply of the periodic signal RATE is stopped, the generation of the delay timing signal P _OUT output from the fractional delay unit 12E is stopped.
[0020]
Delay setting data to the address input terminal AD of the memory 12A timing set signal TSR fed from the standard period generating unit 11 via the latch circuit DFF _2-1 is inputted, the delay data is read is accessed by the timing set signal TSR . The delay data read from the delay setting data memory 12A also has integer data VDAT ₂ corresponding to one cycle of the reference clock REFCK and fraction data MDAT ₂ , and the integer data VDAT ₂ is loaded into the down counter 12C and is stored in the integer part. Get the delay value.
[0021]
The fraction data MDAT ₂ is added to the fraction data HDATA sent from the standard cycle generator 11 in the adder ADD3, and every time the added value reaches one integer value, a carry signal CY ₂ is generated. CY ₂ is added to the integer value, and the delay time of the integer portion generated by the down counter 12C is increased by one integer time in the period in which the carry signal CY ₂ is generated.
[0022]
Furthermore, the addition result is a latch circuit DFF _4-4 adder ADD3, DFF _4-5, DFF _4-6, is input to the control terminal of the fractional delay portion 12E through DFF _4-7, the delay time of the fractional delay unit 12E The delay time corresponding to the fractional value is controlled, the fractional delay time is added to the integer delay time given by the down counter 12C, and the rise timing or fall timing of the test pattern signal is defined by this delay time, for example. To do.
[0023]
FIG. 11 shows a timing chart for explaining the operations of the standard cycle generator 11 and the standard delay generator 12 described above. FIG. 11A shows a periodic signal RATE generated by the standard period generator 11 shown in FIG. In the example shown in FIG. 11, the period data is 64 ns for each test cycle. 11B shows test pattern data given from the pattern generator 112 to the waveform formatter 114, and FIG. 11C shows the delay timing signal P _OUT output from the standard delay generator 12. The case where the delay data set in the standard delay generator 12 is 16 ns in the first test cycle, the delay data is 12 ns in the second test cycle, and 18 ns in the third test cycle is shown.
[0024]
Although the reference clock REFCK is not shown in FIG. 11, if one period of the reference clock REFCK is 8 ns, the delay data is 16 ns in the first test cycle. In this case, 16/8 = 2. Yes, the delay time of the standard delay generator 12 is determined by the delay time of the integer part. In the second test cycle, the case where the delay data is 12 ns is shown. In this case, a fractional value of 4 ns is generated. This fractional value 4 ns is generated in the fraction part 12E, and this fractional value is added to the integer part 8 ns and output as 8 + 4 ns = 12 ns. In the third test cycle, the case of delay data 18 ns is shown. In this case, the integer is 2 and the fractional value is 2 ns. Accordingly, an integer delay time of 16 ns is given in the integer part, and the fractional delay part 12E adds and outputs a fractional value 2ns.
[0025]
Since “1” is specified for the test pattern data in the second test cycle, the test pattern signal rises to logic H as shown in FIG. 11D by the delay timing signal P _OUT output with a delay of 12 ns from the periodic signal RATE. It is done. In the next third test cycle, since “0” is designated as the test pattern data, the test pattern signal is lowered to the L logic by the delay timing signal output in the next test cycle.
[0026]
By the way, some devices under test have a PLL (phase lock loop) built therein. To test a device with a built-in PLL, apply a clock with a stable frequency to the clock input terminal of this device before starting the test to operate the PLL stably, and test when the PLL starts operating stably. It is necessary to start and start clocking continuously throughout the test. This clock is generally referred to as a free-run clock, and conventionally, a free-run clock is generated by providing a special timing generator for generating the free-run clock.
[0027]
FIG. 12 shows such a state. In the figure, 113A represents a standard timing generator, and 113B represents a free-run timing generator. The free-run timing generator 113B includes a free-run cycle generator 11 'and a free-run delay generator 12', and further includes a free-run start / stop controller 13 added thereto.
When the free-run timing generator 113B is provided, the waveforms of the delay generators 12 and 12 'and the waveform can be input so that the free-run clock can be input to the clock input terminal regardless of which terminal of the IC under test is the clock input terminal. A multiplexer MUX is connected between the formatters 114.
[0028]
[Problems to be solved by the invention]
Conventionally, a free-run timing generator 113B is provided in addition to the standard timing generator 113A, and all the channels are provided with multiplexers MUX, so that a configuration added to generate a free-run clock becomes large. There is.
[0029]
An object of the present invention is to provide an IC test apparatus capable of generating a free-run clock with a simple configuration.
[0030]
[Means for Solving the Problems]
In the present invention, by adding a slight configuration to the standard cycle generation unit 11 and the standard delay generation unit 12, a free run generation function is provided to the standard cycle generation unit 11 and the standard delay generation unit 12. Regardless of which terminal of the test IC is assigned to the clock input terminal, it is possible to generate a free-run clock by setting the standard delay generator assigned to the clock input terminal for free-run generation. Is.
[0031]
DETAILED DESCRIPTION OF THE INVENTION
FIG. 1 shows an outline of the timing generator used in the IC test apparatus according to the present invention. Reference numeral 113C denotes a timing generator with a free-run function according to the present invention. The timing generation unit 113C with a free run function according to the present invention is composed of a cycle generation unit 11 ″ with a free run function and a number of delay generation units 12 ″ with a free run function corresponding to the number of terminals of the IC under test. As usual, the waveform formatter 114 and the driver 116 are connected to the output side of each free-running delay generator 12 ″, and the output of the driver 116 is connected to each terminal of the IC under test, although not particularly shown. .
[0032]
FIG. 2 shows the configuration of a free-run function-equipped period generation unit 11 ″ according to the present invention, and FIG.
First, a description will be given of the configuration of the cycle generator 11 ″ with the free-run function shown in FIG. 2. The cycle generator 11 ″ with the free-run function according to the present invention is free on the front side of the standard cycle generator 11 described in FIG. A run start / stop control unit 13 is provided, and a free run clock gate signal FCLKRUN is generated by the free run start / stop control unit 13, and a gate signal GATE sent from the pattern generator 112 is provided. Is transferred to the delay generation unit 12 ″ with the free run function as it is, and even if either the gate signal GATE or the free run clock gate signal FCLKRUN rises to the H logic, this is used as the standard cycle generation unit. 11 and either the gate signal GATE or the free-run clock gate signal FCLKRUN is set to logic H In this example, the free-run start / stop control unit 13 is provided with an OR gate OR that starts the generation of the periodic signal RATE even if the standard cycle generation unit 11 starts. A case will be described in which the −R flip-flop SRFF, several latch circuits DFF _6-1 , DFF _6-2 , DFF _6-3 , and one AND gate AND are included.
[0033]
The characteristic configuration of the delay generation unit 12 ″ with the free-run function shown in FIG. 3 is shown in FIG. 2 according to the point that the register REG for setting the generation of the free-run clock is provided and the setting state of the register REG. The period signal RATE output from the period generator 11 ″ with free-run function is gated and input to the standard delay generator 12, or the period signal RATE is gated by the gate signal GATE shown in FIG. An AND gate AND that is input to the standard delay generator 12 and a gate circuit G that fixes the timing set data TS to a fixed value TS ₁ when free run generation is set in the register REG are provided. is there.
[0034]
When L logic is set in the register REG, the AND gate AND is controlled to be opened and closed by the gate signal GATE. That is, it operates in the normal mode shown in FIG. On the other hand, when H logic is set in the register REG, the AND gate AND operates in the free run setting mode shown in FIG. That is, the AND gate AND performs the cycle generation operation at the same time as the free run clock gate signal FCLKRUN generated by the free run start / stop control unit 13 shown in FIG. It starts, passes the generated periodic signal RATE, starts supplying the periodic signal RATE to the standard delay generator 12, and the standard delay generator 12 starts its operation.
[0035]
Accordingly, the delay generator with free run function 12 ″ in which L logic is set in the register REG operates as a normal test pattern signal generation delay generator, and the delay generator with free run function in which H logic is set in the register REG. 12 ″ operates as a free-run clock generation source.
Here, the operations of the free-running function-equipped cycle generation unit 11 ″ and the free-running function-added delay generation unit 12 ″ when testing a normal IC will be described. When testing a normal IC, the gate signal GATE shown in FIG. 4A is input from the pattern generator 112, and the standard cycle generator 11 starts generating the cycle signal RATE by the input of the gate signal GATE. The signal RATE is sent to each of the delay generators 12 ″ with free run function shown in FIGS. 1 and 3. Each of the delay generators 12 ″ with free run function receives a periodic signal RATE and generates a normal test pattern. A timing signal is generated, and various test pattern signals are generated in the waveform formatter 114.
[0036]
At the end of the test, the gate signal GATE falls to the L logic, whereby the cycle generator 11 ″ with free run function stops generating the cycle signal RATE, and the operation of the delay generator 12 ″ with free run function also stops. .
On the other hand, when testing an IC that needs to generate a free-run clock, an H logic is set in the register REG of the delay generator 12 ″ with a free-run function that needs to generate a free-run clock. L logic is set in the register REG of the delay generation unit 12 ″ with the free-run function.
[0037]
The pattern generator 112 generates a free run start signal generated in synchronization with the reference clock REFCK in the free run start / stop control unit 13 provided in the cycle generation unit with free run function 11 ″ before the timing of generating the test pattern data. The STRT FCLK is input, whereby the free-run start / stop control unit 13 generates a free-run clock gate signal FCLKRUN and inputs the free-run clock gate signal FCLKRUN to the standard cycle generation unit 11 through the OR gate OR. .
[0038]
When the free-run clock gate signal FCLKRUN is input to the standard cycle generator 11, the standard cycle generator 11 starts to generate the cycle signal RATE as shown in FIG. 5A.
When generation of the periodic signal RATE is started, this periodic signal RATE is supplied to each delay generation unit 12 ″ with free-run function. In this case, a delay generation unit with free-run function that needs to generate a free-run clock. In 12 ″, the AND gate AND is controlled to open by the H logic set in the register REG, so that the free-run function-equipped cycle generator 11 ″ starts to output the periodic signal RATE and is set to free-run at the same time. Further, the supply of the periodic signal RATE is started to the delay generation unit 12 ″ with the free-run function, and the standard delay generation unit 12 starts its operation without waiting for the rise of the gate signal GATE.
[0039]
Therefore, the delay generator 12 ″ with a free-run function that needs to generate a free-run clock starts the operation by being supplied with the periodic signal RATE from before the start of the test. This operation is performed by the gate G by the H logic set in the register REG. since closed and the timing set signal TS is fixed to a fixed value TS _1, delay setting data memory 12A by the fixed value TS ₁ (see FIG. 9) is, for example, a particular address is accessed, free from the specific address The delay data for the run clock is read out, which is read from the specific address of the delay setting data memory 12A as the rising timing and falling timing of the free run clock, and from the fraction delay unit 12E shown in FIG. A free-run clock with a fixed period is output.
[0040]
In another delay generation unit 12 ″ with a free run function in which L logic is set in the register REG, since the L logic is set in the register REG, the switching circuit MUX selects the gate signal GATE and uses this gate signal GATE for standard use. As shown in FIG. 5E, the standard delay generator 12 starts supplying the periodic signal RATE simultaneously with the start of the test, and outputs the delay timing signal P _OUT only during the test period. To do.
[0041]
【The invention's effect】
As described above, according to the present invention, the standard cycle generation unit 11 and the standard delay generation unit 12 can be replaced with the free-run function-added cycle generation unit 11 ″ and the free-run function-added delay generation unit by adding a few elements. 12 ″, which eliminates the need to connect the multiplexer MUX between each delay generator and the waveform formatter 114, thereby simplifying the configuration of the IC test apparatus with a free-run clock generation function. The advantage that can be obtained.
[Brief description of the drawings]
FIG. 1 is a block diagram for explaining a configuration of a main part of an IC test apparatus according to the present invention.
FIG. 2 is a block diagram for explaining the configuration of a period generator with a free-run function used in the IC test apparatus according to the present invention.
FIG. 3 is a block diagram for explaining the configuration of a delay generator with a free-run function used in the IC test apparatus according to the present invention.
4 is a timing chart for explaining the operation of the cycle generation unit with a free-run function shown in FIG. 2;
5 is a timing chart for explaining the operation of the delay generator with a free run function shown in FIG. 3;
FIG. 6 is a block diagram for explaining the outline of the IC test apparatus.
FIG. 7 is a block diagram for explaining the configuration of a conventional timing generator.
FIG. 8 is a block diagram for explaining the configuration and operation of a conventional standard cycle generator.
FIG. 9 is a block diagram for explaining the configuration and operation of a conventional standard delay generation unit;
FIG. 10 is a timing chart for explaining the operation of the standard delay generator shown in FIG. 8;
FIG. 11 is a timing chart for explaining the operation of a conventional standard delay generation unit;
FIG. 12 is a block diagram for explaining a configuration to which a conventional free-run timing generator is added.
[Explanation of symbols]
11 Standard cycle generator 12 Standard delay generator 11 ″ Free run function cycle generator 12 ″ Free run function delay generator

Claims (1)

A pattern generator for generating pattern data for generating a test pattern signal to be applied to the IC under test;
A standard period generator for generating a periodic signal according to a timing set signal included in the pattern data output by the pattern generator;
In accordance with the timing set signal included in the pattern data output by the pattern generator, a standard delay generator for generating a delay timing signal having an arbitrary phase from the reference phase with the periodic signal as a reference phase In the configured IC test equipment,
OR of the free run start / stop control unit and the free run clock gate signal output from the free run start / stop control unit and the gate signal sent from the pattern generator Is input to the standard cycle generator, and the period signal is supplied from the standard cycle generator while either the gate signal or the free-run clock gate signal is supplied to the standard cycle generator. In addition to adding a free-run function to the standard cycle generator, a register for setting free-run clock generation is provided in the standard delay generator, and the standard cycle generator outputs according to the setting state of this register. A feature is that a free-run clock function for capturing a periodic signal to start operation is added to the standard delay generator. That IC test equipment.

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