JP4336508B2 - Imaging device - Google Patents

Description

[0001]
BACKGROUND OF THE INVENTION
The present invention relates to an imaging apparatus that captures a subject image.
[0002]
[Prior art]
There are a CCD type and a CMOS type solid-state imaging device. Recently, a demand for a CMOS type solid-state imaging device which is attractive for low cost and low power consumption has increased.
[0003]
As an example of a CMOS type solid-state imaging device, there is one in which the number of MOS transistors constituting one pixel is three in order to reduce the pixel size in order to reduce the size, increase the number of pixels, and reduce the cost ( For example, see Patent Document 1).
[0004]
Each pixel receives a photodiode and a signal from the photodiode, amplifies and outputs the amplified MOS transistor to an output line, and transfers the photodiode signal to the gate electrode region of the amplifying MOS transistor. A transfer MOS transistor and a reset MOS transistor for supplying a reset potential to the gate electrode region of the amplifying MOS transistor.
[0005]
Then, a high potential (a potential within a range in which the amplification MOS transistor can operate) is supplied to the gate electrode region of the amplification MOS transistor of the pixel included in the selected row (row from which the signal is read), and the selection is performed. Selection or non-selection is performed by supplying a low potential to the gate electrode region of the amplification MOS transistor of the pixel included in a row that is not read (a row from which no signal is read).
[0006]
[Patent Document 1]
Japanese Patent Laid-Open No. 11-112018
[Problems to be solved by the invention]
However, when there is a purpose to reduce the pixel size as described above, when the size of the amplifying MOS transistor is reduced, another problem is newly generated. Since the 1 / f noise of the MOS transistor is inversely proportional to the gate electrode area (WxL), the influence of the 1 / f noise on the image quality increases with miniaturization.
[0008]
[Means for Solving the Problems]
In order to solve the above problems, as one means, each is electrically connected to a photoelectric conversion unit, a field effect transistor that amplifies and outputs a signal of the photoelectric conversion unit, and a control electrode of the field effect transistor. A plurality of pixels including: a floating capacitor ; a transfer switch that transfers a signal from the photoelectric conversion unit to the floating capacitor; a control electrode of the field effect transistor; and a reset switch that resets the potential of the floating capacitor ; A first potential and a second potential different from the first potential are applied to an output line for outputting signals from a plurality of pixels, a control electrode of the field effect transistor included in the plurality of pixels, and the floating capacitor . selection state of the pixel by selectively providing, and a potential supply means for switching the non-selected state, the field effect Transistors, to provide an imaging apparatus which is a depletion type.
[0009]
As another means, each includes a photoelectric conversion unit, a field effect transistor that amplifies the signal of the photoelectric conversion unit and outputs the signal from the first main electrode, and a signal from the photoelectric conversion unit as the field effect transistor A plurality of pixels including a transfer switch for transferring to the control electrode , a reset switch for resetting the potential of the control electrode of the field effect transistor, an output line for outputting signals from the plurality of pixels, and the output line And a first potential supply means for selectively supplying a first potential and a second potential different from the first potential; and a third potential and the second potential on the second main electrode of the field effect transistor. Second potential supply means for selectively supplying a fourth potential different from the third potential , wherein the reset switch electrically connects the output line and the control electrode of the field effect transistor. the Are arranged to control, for the selected pixel, the first potential is supplied from the through the output line and the reset switch first potential supply means to the control electrode of the field effect transistor At the same time, the third potential is supplied from the second potential supply means to the second main electrode of the field effect transistor, and the first potential is supplied to the non-selected pixels via the output line and the reset switch. The second potential is supplied from the second potential supply means to the control electrode of the field effect transistor, and the fourth potential is supplied from the second potential supply means to the second main electrode of the field effect transistor. The field effect transistor is a depletion type, and provides an imaging device.
[0011]
DETAILED DESCRIPTION OF THE INVENTION
(Embodiment 1)
FIG. 1 shows an equivalent circuit of the solid-state imaging device according to the first embodiment of the present invention.
[0012]
Reference numeral 1 denotes a photodiode which is a photoelectric conversion unit that converts light into an electric signal, 2 denotes a floating capacitor to which a signal from the photodiode is transferred, and 3 denotes a photodiode in which a gate electrode region is connected to the floating capacitor. This is an amplifying MOS transistor that is one of field effect transistors that amplifies and outputs a signal from a diode. In this embodiment, it is a depletion type amplifying MOS transistor. Here, in the depletion type, the value of 1 / f noise is about 20% to 50% smaller than the enhancement type MOS. In general, the 1 / f noise of a MOS transistor is inversely proportional to the gate electrode area. Therefore, the smaller the amplification MOS transistor, the larger the breakdown of the amplification MOS transistor in the noise component of the image quality, and the effect of this embodiment is more remarkable. become.
[0013]
Reference numeral 4 denotes a transfer MOS transistor which is a transfer switch for transferring a photodiode signal to the floating capacitor 3. Reference numeral 5 denotes a reset MOS transistor which is a reset switch for supplying a reset potential to the floating capacitor 3. is there. In this embodiment, one pixel is composed of 1 to 5. In practice, the pixels are arranged in a two-dimensional manner.
[0014]
Reference numeral 6 denotes a vertical output line from which a signal is output from the source electrode area which is the first main electrode area of the amplifying MOS transistor, and reference numeral 7 denotes a power supply for the drain electrode area which is the second main electrode area of the amplifying MOS transistor. An amplifier power supply wiring for supplying a voltage, 8 is a constant current source.
[0015]
A voltage supply circuit (voltage supply circuit) which is a voltage supply means for selectively supplying a first potential enabling the amplification MOS transistor 2 and a second potential lower than the first potential to the reset wiring 9. (Not shown) is connected.
[0016]
For example, when a signal is read out from the pixels in the first row, the first potential is supplied to the floating capacitor 3 that is an input unit of the amplification MOS transistor 2 included in each pixel in the first row. The second potential is supplied to the pixels included in the other pixels.
[0017]
As described above, in the present embodiment, in the configuration for the purpose of reducing the pixel size without separately providing a selection MOS transistor for selecting a pixel for reading a signal, amplification is performed. By making the MOS transistor a depletion type, it is possible to achieve both a reduction in pixel size and a reduction in 1 / f noise.
[0018]
(Embodiment 2)
FIG. 2 shows a pixel configuration in the case where the signal output line and the reset power supply are shared.
[0019]
Reference numeral 11 denotes a photodiode which is a photoelectric conversion unit for converting light into an electric signal, 12 denotes a floating capacitor to which a signal from the photodiode is transferred, and 13 denotes a photo diode having a gate electrode region connected to the floating capacitor. An amplifying MOS transistor that amplifies and outputs a signal from the diode, 14 is a transfer MOS transistor that transfers the photodiode signal to the amplifying MOS transistor, and 15 is a reset MOS transistor that supplies a reset potential to the floating capacitor And connected to a vertical output line (signal output line) 16. Reference numeral 17 denotes an amplifier power supply wiring for supplying a power supply voltage to the drain electrode region of the amplification MOS transistor, and reference numeral 18 denotes a constant current source.
[0020]
Next, a driving method having the configuration shown in FIG. 2 will be described.
[0021]
In the reset operation before the start of photocharge accumulation in the photodiode, the signal output line is fixed to the high potential, the reset MOS transistor is turned on, the transfer MOS transistor is turned on, and the charge in the photodiode is discharged. Next, the transfer MOS transistor is turned off and charge accumulation is started. In order to read a signal from each pixel after charge accumulation, first, a high potential is applied to the signal output line, and a low potential is written to the floating capacitors of all the pixels via the reset MOS transistor. Next, a high potential is applied to the signal output line while only the reset MOS transistor in the selected row is turned on, and the potential of the floating capacitor in the selected row is set to a potential within a range where the amplification MOS transistor can operate. In this state, since the low potential is held at the gate of the source follower of the non-selected row, the amplification MOS transistor is OFF and the amplification MOS transistor does not operate. Next, by closing the switch that fixes the potential of the signal output line and operating the constant current source, the signal line becomes a potential corresponding to the N output (noise signal) of the selected row. Furthermore, by turning on the transfer gate of the selected row, the charge in the photodiode is transferred to the floating capacitor, so that the potential of the signal output line corresponds to the S output (a signal including an optical signal and a noise signal) of the selected row. At the potential. Although not shown, an output corresponding to the amount of light can be obtained by taking the difference between the S signal and the N signal.
[0022]
However, as described above, when the size of the amplification MOS transistor is reduced as the pixel size is reduced, another problem is newly generated. Since the 1 / f noise of the MOS transistor is inversely proportional to the gate electrode area (WxL), the influence of the 1 / f noise on the image quality increases with miniaturization. It has been experimentally found that the 1 / f noise of NMOS is about two orders of magnitude greater in noise power than the PMOS transistor, and this problem is particularly serious when the pixel portion is composed of NMOS transistors. It has been confirmed that it is effective to make the MOS transistor a depletion type as a countermeasure against 1 / f noise of the NMOS transistor, and it is possible to improve the image quality by configuring the amplification MOS transistor to be a depletion type. .
[0023]
However, when the number of transistors described above is reduced and wiring is shared, the following problems occur.
[0024]
That is, during the operation of writing the low potential to the floating capacitors of all the pixels (timing 3), the source and the gate of the source follower MOS are supplied with the same potential from the signal output line. Since the transistor is a depletion type, this MOS transistor is in an ON state. That is, each signal output line is connected to the amplifier power supply wiring via the amplification MOS transistors of all the pixels connected thereto. As a result, the signal output line is pulled between the low potential applied via the switch outside the pixel region and the potential of the amplifier power supply wiring, and cannot be lowered to a desired potential.
[0025]
As a solution to this problem, in this embodiment, in the operation of writing a low potential to the floating capacitors of the amplifying MOS transistors of all the pixels, the same low potential as that applied to the signal output line is simultaneously applied to the amplifier power supply wiring. . This makes it possible to write a desired potential to the floating capacitor even when the amplification MOS transistor is not turned off.
[0026]
This will be specifically described below.
[0027]
In FIG. 3, each pixel is a photodiode 101 which is a photoelectric conversion unit, a transfer MOS transistor 102 which is a transfer switch for transferring a signal of the photodiode, a floating capacitor 103, and a reset switch for resetting the potential of the floating capacitor. A reset MOS transistor 104 and an amplifying MOS transistor which is one of field effect transistors for amplifying and outputting a signal from a photodiode having a gate electrode region connected to a floating capacitor. Actually, the pixels are two-dimensionally arranged, and the source, which is the first main electrode region of the amplification MOS transistor 105, is connected to the signal output line 106. The drain which is the second main electrode region of the amplification MOS transistor 105 is connected to the amplifier power supply wiring 107. Here, the amplifying MOS transistor 105 is a depletion type, and the value of 1 / f noise is about 20% to 50% smaller than that of the enhancement type MOS. In general, the 1 / f noise of a MOS transistor is inversely proportional to the gate electrode area. Therefore, the smaller the amplification MOS transistor, the larger the breakdown of the amplification MOS transistor in the noise component of the image quality, and the effect of this embodiment is more remarkable. become. In this embodiment, the signal output line 106 and the constant current source 108 can be separated by the MOS transistor 109. The potential of the signal output line 106 is connected via the MOS transistors 110 and 111 to the VH 112 supplied with the high potential as the first potential and the VL 113 supplied with the low potential as the second potential. The wiring 107 is connected to the amplifier power supply 115 via the MOS 114. The amplifier power supply wiring 107 is connected to the signal output line 106 via the MOS 116. The potential of the signal output line is output from the output 117 to the next circuit.
[0028]
As described above, the first potential and the second potential different from the first potential are applied to the signal output line 106 and the drain of the amplifying transistor by the MOS transistors 110, 111, 114, and 116 as power supply means. Can be selectively supplied.
[0029]
The driving method of the present embodiment will be described with reference to FIG. 201 indicates the potential of the amplifier power supply wiring 107, 202 indicates the gate potential of the reset MOS transistor 104, 203 indicates the gate potential of the transfer MOS transistor 102, 204 indicates the potential of the signal output line 106, and 205 indicates the source follower circuit (for amplification). The gate potential of the MOS 109 that turns on and off the connection of the constant current source of the MOS transistor 105 and the constant current source 108) is shown. First, at the timing T1, the signal output line 204 is fixed to the potential of VH112. This operation is possible by turning on the MOS 110. As a result, the potential of the floating capacitor 103 is reset to VH112. At the same time, by turning on the gate of the transfer MOS transistor 102, the inside of the photodiode 101 can be reset to a completely depleted state. From the moment when the transfer MOS transistor 102 is turned off (timing T2), accumulation of photocharge in the photodiode 101 is started. The accumulation can be terminated by shielding the light to the sensor with a mechanical shutter or the like. The reading of electric charges starts with resetting the floating capacitors 103 of all rows to VL. At timing T3, the potential of the signal output line 106 is fixed to the VL potential 113 by turning on the MOS 111 and turning off the MOS transistor 110. At the same time, the floating capacitors 103 in all rows are reset to VL by turning on the gates of the reset MOS transistors 104. At this time, as described above, it is necessary to set the potential 201 of the amplifier power supply wiring 107 to the same potential as VL. Therefore, this embodiment can be realized by turning off the MOS transistor 114 and turning on the MOS transistor 116.
[0030]
Next, reading for each row is started. At timing T4, the MOS transistor 111 is turned off and the MOS transistor 110 is turned on to fix the potential of the signal output line 106 to the VH potential 112. At timing T5, the reading is performed. Only in the row to be performed, the gate potential 202 of the reset MOS transistor 104 is turned on, and the floating capacitor 103 in the row to be read is reset to VH. Next, at time T6 after the reset MOS transistor 104 is turned off, the MOS transistor 110 and the MOS transistor 111 are turned off and the MOS transistor 109 is turned on to operate the constant current source 108, and the signal output line 106 is connected to the source follower. To be output. Between timings T6 and T7, the potential of the output 117 is captured as an N output. Next, by turning on the transfer MOS transistor 102 only for the selected row, the charge in the photodiode 101 is transferred to the floating capacitor 103, and the potential of the output 117 is taken in as the S output. Although not shown in the figure, by performing the S-N process in the circuit that has received the output 117, it is possible to perform imaging with noise removed. After the reading of the selected row is completed, the floating capacitor unit is reset to VL again only in the selected row (or in all pixels). Also in this case, the potential of the signal output line 106 and the potential of the amplifier power supply wiring 107 need to be the same. The method can be implemented in the same way as at timing T3. In order to sequentially read the next row, the entire screen can be read by repeating the timings T3 to T9 while changing the selected row.
[0031]
In this embodiment, an example in which a pixel is configured by three MOS transistors has been described. However, even when a pixel is formed by using an element other than a MOS type, such as a junction FET, for resetting or the like. Similar effects can be obtained.
[0032]
(Embodiment 3)
In the second embodiment, the driving in the case where all the pixels are simultaneously reset before the accumulation of photocharges in the photodiode has been described. The present invention is also effective in the case of driving without resetting all pixels.
[0033]
The driving method of the third embodiment will be described with reference to FIG. Reference numerals 301 to 305 denote the same potential as 201 to 205 in FIG. The difference from Embodiment 2 is that all pixels are not reset. The driving from T4 to T9 indicates a reading operation for one selected row. However, since all charges in the photodiode are transferred at the time of reading, the photodiode is in a reset state after reading. . All the pixels can be reset by repeating this drive for each row and scanning for one screen. The original image can be read out again by reading out line by line. This driving is shooting in a so-called rolling shutter mode, and the accumulation start corresponds to timing T10. In this case, although the accumulation time is the same for each row, there is a demerit that the imaging time differs depending on the top and bottom of the screen according to the vertical scanning time, but a great merit that a mechanical shutter is not necessary can be obtained.
[0034]
As described above, according to the first to third embodiments, when a selection switch (for selecting a pixel to be read out) is not provided and the output signal line and the amplifier power supply are made common to reduce the pixel size. In addition, a depletion type transistor can be used for the amplifying MOS transistor, and a small-sized or high-definition solid-state imaging device with a good SN ratio can be provided at low cost.
[0035]
(Embodiment 4)
Based on FIG. 6, an imaging measure using the solid-state imaging device described in Embodiments 1 to 3 described above will be described.
[0036]
In FIG. 6, reference numeral 51 denotes a barrier that serves as a lens switch and a main switch, 52 denotes a lens that forms an optical image of a subject on the solid-state image sensor 54, 53 denotes an aperture for changing the amount of light passing through the lens 52, and 54 denotes A solid-state imaging device 55 for capturing an object imaged by the lens 52 as an image signal, a gain variable amplifier unit for amplifying an image signal output from the solid-state imaging device 54, and a gain correction circuit for correcting a gain value An image signal processing circuit including a unit, 56 is an A / D converter that performs analog-digital conversion of an image signal output from the solid-state image sensor 54, and 57 is an image data output from the A / D converter 56. A signal processing unit 58 that corrects data and compresses data, 58 is connected to the solid-state imaging device 54, the imaging signal processing circuit 55, the A / D converter 56, and the signal processing unit 57. A timing generator 59 for outputting various timing signals, 59 is an overall control / arithmetic unit for controlling various computations and the entire imaging apparatus, 60 is a memory unit for temporarily storing image data, and 61 is recorded or read out on a recording medium. 62 is a removable recording medium such as a semiconductor memory for recording or reading image data, and 63 is an interface unit for communicating with an external computer or the like.
[0037]
Next, the operation of the image pickup apparatus at the time of shooting in the above configuration will be described.
[0038]
When the barrier 51 is opened, the main power supply is turned on, then the control system power supply is turned on, and the power supply of the imaging system circuit such as the A / D converter 56 is turned on.
[0039]
Then, in order to control the exposure amount, the overall control / calculation unit 59 opens the diaphragm 53, and the signal output from the solid-state imaging device 54 is converted by the A / D converter 56 and then sent to the signal processing unit 57. Entered.
[0040]
Based on the data, the exposure calculation is performed by the overall control / calculation unit 59.
[0041]
The brightness is determined based on the result of the photometry, and the overall control / calculation unit 59 controls the aperture according to the result.
[0042]
Next, based on the signal output from the solid-state image sensor 54, the high frequency component is extracted and the distance to the subject is calculated by the overall control / calculation unit 59. Thereafter, the lens is driven to determine whether or not it is in focus. When it is determined that the lens is not in focus, the lens is driven again to perform distance measurement.
[0043]
Then, after the in-focus state is confirmed, the main exposure starts.
[0044]
When the exposure is completed, the image signal output from the solid-state imaging device 54 is A / D converted by the A / D converter 56, passes through the signal processing unit 57, and is written in the memory unit by the overall control / calculation unit 59.
[0045]
Thereafter, the data stored in the memory unit 60 is recorded on a removable recording medium 62 such as a semiconductor memory through the recording medium control I / F unit under the control of the overall control / arithmetic unit 59.
[0046]
Further, the image may be processed by directly entering the computer or the like through the external I / F unit 63.
[0047]
【The invention's effect】
According to the present invention, it is possible to achieve both reduction in the pixel size and improvement in the SN ratio.
[Brief description of the drawings]
FIG. 1 is a diagram for explaining Embodiment 1;
FIG. 2 is a diagram for explaining Embodiment 2;
FIG. 3 is a diagram for explaining Embodiment 2;
FIG. 4 is a diagram for explaining Embodiment 2;
FIG. 5 is a diagram for explaining Embodiment 3;
6 is a diagram for explaining a fourth embodiment; FIG.
[Explanation of symbols]
1 Photodiode 2 Floating capacitance 3 Amplifying MOS transistor 4 Transfer MOS transistor 5 Reset MOS transistor 6 Vertical output line 7 Amplifier power supply wiring

Claims (2)

Each includes a photoelectric conversion unit, a field effect transistor that amplifies and outputs a signal of the photoelectric conversion unit, a floating capacitor electrically connected to a control electrode of the field effect transistor, and a signal from the photoelectric conversion unit A plurality of pixels including a transfer switch for transferring the floating capacitor to the floating capacitor , and a control electrode of the field effect transistor and a reset switch for resetting the potential of the floating capacitor ;
An output line for outputting signals from the plurality of pixels;
By selectively supplying a first potential and a second potential different from the first potential to the control electrode of the field effect transistor and the floating capacitor included in the plurality of pixels, the selected state of the pixel and the non-selected state Potential supply means for switching the state ,
The field effect transistor is a depletion type imaging device. Each of the photoelectric conversion unit, the field effect transistor that amplifies the signal of the photoelectric conversion unit and outputs the signal from the first main electrode, and the transfer that transfers the signal from the photoelectric conversion unit to the control electrode of the field effect transistor A plurality of pixels including a switch and a reset switch for resetting a potential of a control electrode of the field effect transistor;
An output line for outputting signals from the plurality of pixels;
First potential supply means for selectively supplying a first potential and a second potential different from the first potential to the output line ;
Second potential supply means for selectively supplying a third potential and a fourth potential different from the third potential to the second main electrode of the field effect transistor ;
The reset switch is arranged to control electrical connection between the output line and a control electrode of the field effect transistor ;
The first potential is supplied from the first potential supply means to the control electrode of the field effect transistor via the output line and the reset switch, and the second potential supply means is supplied to the selected pixel. The third potential is supplied to the second main electrode of the field effect transistor from
The second potential is supplied to the non-selected pixel from the first potential supply means to the control electrode of the field effect transistor via the output line and the reset switch, and the second potential supply. Means for supplying a fourth potential to the second main electrode of the field effect transistor;
The field effect transistor is a depletion type imaging device.

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