JP4337079B2 - Method for forming chamfered surface of semiconductor wafer - Google Patents

Description

[0001]
BACKGROUND OF THE INVENTION
The present invention relates to a method for forming a chamfered surface of a semiconductor wafer, and more particularly to a method for forming a chamfered surface of a semiconductor wafer in which a change in the shape of a chamfered portion of the wafer during processing is small and the damage remains small.
[0002]
[Prior art]
Generally, a silicon wafer obtained by slicing a single crystal silicon ingot is chamfered by a chamfering grindstone. During this chamfering, processing damage (distortion) occurs in the chamfered surface of the outer peripheral portion of the wafer in a thickness portion of about 10 to 20 μm.
In order to remove the processing damage, a method of etching only a chamfered surface called a CCR (Chemical Corner Rounding) process has been developed.
Conventionally, gather etching is known as one type of CCR processing, in which chamfer etching of a plurality of silicon wafers is performed collectively. Gather etching is a process of stacking a number of silicon wafers so that both front and back surfaces are in close contact with each other, contacting the outer periphery of each wafer while rotating it, and etching only the outer periphery of the silicon wafer. It is a method to do.
As another prior art, there is also known a method of etching the entire exposed surface of the silicon wafer in accordance with the processing damage of the surface layer of the outer peripheral portion of the silicon wafer.
After performing such damage removal processing, the chamfered surface of the wafer is subjected to PCR (Polished Corner Rounding) processing. Specifically, the polishing cloth stretched in a cylindrical shape is rotated, and the chamfered surface of the rotating silicon wafer is pressed while supplying an abrasive to the polishing cloth.
[0003]
[Problems to be solved by the invention]
However, these conventional methods for forming a chamfered surface of a silicon wafer have the following drawbacks.
In the above-described CCR process, wet etching is performed in which a large number of gathered silicon wafers are immersed in a hydrofluoric acid solution to dissolve only the surface layer of the wafer chamfered portion. During this operation, reaction gas is constantly generated from the surface of each wafer outer periphery. Therefore, for example, when this reactive gas adheres to the gap forming surface between the outer peripheral portions (valley portions) of each wafer, there is a possibility that uneven etching occurs. As a result, the shape of the chamfered surface of each silicon wafer is changed to a curved convex shape with a gently curved surface, and the maintainability of the shape of these chamfered surfaces (hereinafter referred to as shape maintainability) is reduced. . That is, in the CCR processing, it is difficult to uniformly remove the processing damage in the entire chamfered surface, and it is difficult to ensure the shape accuracy of the chamfered surface.
On the other hand, if the entire wafer exposed surface is etched in accordance with the processing damage on the surface layer of the outer peripheral portion of the wafer, the amount of etching on the wafer surface, which is mirror-finished to that extent and becomes the device formation surface, increases. This causes a problem that the flatness of the surface of the silicon wafer is lowered.
[0004]
Therefore, as a result of intensive research, the inventor formed an oxide film on the chamfered surface of the semiconductor wafer, and then removed this oxide film together with processing damage, without reducing the flatness of the wafer surface, The inventors have found that the shape maintaining property can be improved, and have completed the present invention.
[0005]
OBJECT OF THE INVENTION
The present invention provides a method for forming a chamfered surface of a semiconductor wafer capable of effectively removing damage on the chamfered surface while improving the shape maintaining property of the wafer chamfered surface without reducing the flatness of the wafer surface. And that is the purpose.
[0006]
[Means for Solving the Problems]
The invention according to claim 1 is a step of chamfering a chamfering grindstone on the outer peripheral portion of the semiconductor wafer, and a step of lapping the chamfered semiconductor wafer to increase the flatness of both front and back surfaces of the semiconductor wafer; A step of immersing the entire lapped semiconductor wafer in an etching solution, and performing etching to remove a part of the processing damage of the wafer outer peripheral portion caused by the chamfering and the processing damage of the front and back surfaces of the wafer caused by the lapping, Masking both the front and back sides of the etched semiconductor wafer, oxidizing the masked semiconductor wafer , forming an oxide film only on the chamfered surface of the semiconductor wafer , maintaining this masking state, Etching only the oxide film formed on the outer periphery of the semiconductor wafer In Rukoto, removing the remainder of the processing damage of the wafer outer peripheral portion of the whole left upon etching of the semiconductor wafer, after removal of the remainder of the oxide film, mirror polished chamfered surface of the semiconductor wafer A method for forming a chamfered surface of a semiconductor wafer comprising a process.
[0007]
Examples of the semiconductor wafer include a silicon wafer and a gallium arsenide wafer.
The chamfering grindstone used in this chamfering process is not limited. For example, a resinoid grinding wheel or a metal bond chamfering wheel may be used.
The count of the chamfering grindstone is not limited. However, in the case of a resinoid grinding wheel, # 1000 to # 2000, and in the case of a metal bond chamfering wheel, # 600 to # 1500.
The amount of grinding of the chamfered surface of the semiconductor wafer by the chamfering grindstone is not limited. However, it is usually 0.1 to 100 μm, preferably 0.1 to 20 μm.
The depth of processing damage due to the grindstone generated on the surface layer of the chamfered portion is, for example, 0.5 to 10 μm in the case of a resinoid grinding wheel and 2 to 20 μm in the case of a metal bond grinding wheel. This damage is removed together with the oxide film at the time of removing the oxide film, which is a subsequent process.
[0008]
The method for forming the oxide film is not limited. Dry O ₂ oxidation, thermal oxidation, such as wet O ₂ oxidation, by wet oxidation of ozone cleaning or the like.
The thickness of the oxide film is not limited. The thickness of the oxide film may be 0.01 to 10 μm.
The method for removing the oxide film is not limited. The oxide film is dissolved and removed with a diluted HF solution or a buffered hydrofluoric acid solution.
Prior to forming the oxide film, it is preferable to perform an etching step of immersing the entire semiconductor wafer in an etching solution. Thereby, the thickness of the oxide film formed on the wafer chamfered surface is reduced, and the formation time and removal time of the oxide film are shortened.
When it is necessary to protect both the front and back surfaces of the wafer, when forming this oxide film, the front and back surfaces of the semiconductor wafer may be covered with a masking material. The type of the masking material is appropriately changed depending on the method for forming the oxide film. For example, when the oxide film is formed by thermal oxidation, a heat resistant masking material is employed. In this case, in order to prevent the shape change of the chamfered surface, the thickness of the oxide film is desirably 1 μm or less.
The polishing apparatus for the wafer chamfered surface is not limited. For example, a PCR device or the like can be employed.
[0009]
As the etchant, an acidic etchant such as a mixed acid or an alkaline etchant such as NaOH or KOH can be employed.
The etching amount of the semiconductor wafer is about 20 μm on one side and about 40 μm on both sides.
[0010]
[Action]
According to this invention, after mechanical chamfering with a chamfering grindstone, an oxide film is formed on the chamfered surface of the semiconductor wafer by a predetermined method. Thereafter, by removing the oxide film, processing damage that appears on the surface layer of the outer periphery of the wafer during chamfering with the grindstone is removed together with the oxide film. As a result, it is possible to improve the shape maintenance of the chamfered surface of the semiconductor wafer without deteriorating the wafer flatness as in the case where the entire wafer exposed surface is etched in accordance with the processing damage of the surface layer of the outer periphery of the wafer. it can.
Since the entire exposed surface of the mechanically chamfered semiconductor wafer is etched, a part of the processing damage on the outer peripheral portion of the wafer is removed before the damage removal by the oxide film. Thereby, the thickness of the oxide film can be reduced, and the formation time and removal time of the oxide film can be shortened.
[0011]
DETAILED DESCRIPTION OF THE INVENTION
Embodiments of the present invention will be described below with reference to the drawings.
FIG. 1 is a cross-sectional view for explaining a method for forming a chamfered surface of a semiconductor wafer according to an embodiment of the present invention. FIG. 2 is a flow sheet of a method for forming a chamfered surface of a semiconductor wafer according to an embodiment of the present invention.
As shown in FIG. 2, in this embodiment, slicing, chamfering (GCR), lapping, acid etching, masking on both sides, formation of an oxide film on the chamfered surface, removal of the oxide film, PCR, polishing, A silicon wafer having a mirror finished surface and chamfered surface is produced through each cleaning step. Hereinafter, each process will be described in detail.
[0012]
The single crystal silicon ingot pulled up by the CZ method is sliced into an 8-inch silicon wafer having a thickness of about 860 μm in the slicing step (S201).
Next, in the subsequent chamfering step (S202), the sliced wafer W is chamfered into a predetermined shape by pressing a chamfering grindstone on the outer periphery thereof.
The chamfering grindstone has a # 800 metal bond cylindrical grindstone for rough chamfering and a # 1500 metal bond cylindrical grindstone for finishing, and each outer peripheral surface is a grinding working surface. The silicon wafer W and the chamfering grindstone are respectively chamfered by rotating at a predetermined rotation speed. The chamfering amounts are about 100 μm for rough chamfering and about several tens of μm for finishing chamfering inward in the radial direction of the wafer. Thereby, the outer peripheral part of the silicon wafer W is processed into a predetermined rounded shape (for example, a MOS type chamfered shape).
[0013]
Next, lapping is performed on the silicon wafer W to increase the parallelism between the front and back surfaces of the silicon wafer W (S203). In this lapping process, the silicon wafer W is disposed between lap surface plates parallel to each other, and thereafter, a wrap liquid that is a mixture of alumina abrasive grains, a dispersant, and water is poured between the wrap surface plates. Then, both front and back surfaces of the silicon wafer W are mechanically lapped by rotating and sliding under pressure.
Subsequently, the wrapped wafer W is etched (S204). Specifically, the silicon wafer W is immersed for a predetermined time in a mixed acid solution (normal temperature to 50 ° C.) in which hydrofluoric acid and nitric acid are mixed. At this time, a part of the processing damage on the outer peripheral portion of the wafer is removed (FIG. 1A).
[0014]
Next, both front and back surfaces of the silicon wafer W except for the outer peripheral portion are covered with two masking materials a and a (S205, FIG. 1B). As the masking materials a and a, a silicon nitride film (Si ₃ N ₄ ) having a heat resistance of 0.1 μm in thickness is employed.
Then, the silicon wafer W is inserted into the reaction tube of the thermal oxidizer and heated in an O ₂ gas atmosphere at 1000 ° C. for 60 minutes. As a result, an oxide film (silicon oxide film) b having a thickness of 0.5 μm is formed on the outer peripheral portion of the silicon wafer W not covered with the masking materials a and a (S206, FIG. 1C). At this time, since the disorder of the crystal arrangement and innumerable fine cracks are generated in the damaged portion on the outer peripheral portion of the wafer, the contact area with the O ₂ gas is increased, and the degree of oxidation in this portion is increased.
Subsequently, the diluted HF is washed for 10 minutes with a 5% diluted HF solution (room temperature). As a result, the oxide film b is removed together with the damaged portion of the surface layer on the outer periphery of the wafer (S207, FIG. 1 (d)).
[0015]
Thereafter, the masking materials a and a are removed (FIG. 1E), and the outer peripheral portion of the silicon wafer W is subjected to PCR processing (S208). As the PCR device, a device that rotates a cylindrical urethane buff by a motor is adopted. The urethane buff is rotated by a motor, and the outer peripheral surface of the silicon wafer W from which the oxide film b has been removed is brought into contact with the rotating buff outer peripheral surface. Thereby, the wafer outer peripheral surface is mirror-finished. At that time, only one surface of the silicon wafer W is sucked and held by the holding plate. The silicon wafer W is sucked by a negative pressure generator that is externally connected to the holding plate via a hose or the like.
In the subsequent polishing step (S209), the surface of the silicon wafer W is polished by 1 to 5 μm using a normal polishing apparatus, and then the adsorption / holding surface at the time of PCR processing is finished and polished with a polishing amount of 1 μm or less. . Thereby, the distortion of the silicon wafer W after etching is removed, and the adsorption surface of the silicon wafer W generated by PCR processing is removed. Then, final cleaning (S210) and inspection are performed, and the product is shipped to the device manufacturer of the order recipient.
[0016]
As described above, since the oxide film b is once formed on the surface layer of the outer peripheral portion of the silicon wafer W and then the oxide film b is removed, the wafer outer peripheral portion generated by chamfering with a grindstone when the oxide film b is removed. The processing damage is also eliminated. As a result, the shape maintainability of the chamfered surface of the silicon wafer W can be improved without causing a decrease in wafer flatness as in the case where the entire wafer exposed surface is etched in accordance with the processing damage of the surface layer of the outer peripheral portion of the wafer. it can.
Further, since the entire silicon wafer W is etched, a part of the processing damage formed on the surface layer of the outer peripheral portion of the wafer is removed before the damage removal by the oxide film b. As a result, the effect of the present invention can be obtained even with a thin oxide film b. Therefore, the formation time of the oxide film b and the removal time of the oxide film b can be shortened.
[0017]
【The invention's effect】
According to this invention, an oxide film is formed on the surface layer of the outer peripheral portion of the semiconductor wafer after chamfering, and processing damage that appears on the outer peripheral portion of the wafer by chamfering with a grindstone or the like is removed together with the oxide film when the oxide film is subsequently removed. Can be removed. As a result, the shape maintainability of the wafer chamfered surface can be enhanced without reducing the flatness of the wafer surface.
Since the entire exposed surface of the semiconductor wafer is etched after chamfering with the grindstone, part of the processing damage is removed before the damage removal using the oxide film. As a result, the formation time of the oxide film and the removal time of the oxide film can be shortened.
[Brief description of the drawings]
FIG. 1 is a cross-sectional view for explaining a method for forming a chamfered surface of a semiconductor wafer according to an embodiment of the present invention.
FIG. 2 is a flow sheet of a method for forming a chamfered surface of a semiconductor wafer according to an embodiment of the present invention.
[Explanation of symbols]
W Silicon wafer (semiconductor wafer),
b Oxide film.

Claims (1)

Chamfering with a chamfering grindstone on the outer periphery of the semiconductor wafer;
A step of lapping the chamfered semiconductor wafer to increase the flatness of both front and back surfaces of the semiconductor wafer;
A step of immersing the entire lapped semiconductor wafer in an etching solution, and performing etching to remove a part of the processing damage of the wafer outer peripheral portion caused by the chamfering and the processing damage of the front and back surfaces of the wafer caused by the lapping,
Masking both front and back surfaces of the etched semiconductor wafer;
Oxidizing the masked semiconductor wafer and forming an oxide film only on the chamfered surface of the semiconductor wafer; and
By maintaining this masking state and etching only the oxide film formed on the outer peripheral portion of the semiconductor wafer, the remaining processing damage remaining on the outer peripheral portion of the wafer left when the entire semiconductor wafer is etched is removed. Process,
After removal of the remainder of the oxide film, the method of forming the chamfered surface of the semiconductor wafer and a step of mirror-polishing the chamfered surface of the semiconductor wafer.

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