JP4338748B2 - Manufacturing method of semiconductor device - Google Patents

Description

  The present invention relates to a method for manufacturing a semiconductor device, and more particularly to a method for manufacturing a semiconductor device having a conductive plug filling a contact hole.

  Conventional conductive plugs are usually formed by the following method.

  First, a resist film having an opening is formed on the interlayer insulating film. Using this resist film as a mask, the interlayer insulating film is etched to form contact holes. Thereafter, the resist film is removed. The resist film is removed by ashing in oxygen plasma.

  An adhesive layer made of TiN or the like is formed on the inner surface of the contact hole and the surface of the resist film. A tungsten film is deposited on the surface of the adhesive layer and the contact hole is filled with tungsten. The tungsten film and the adhesive layer are removed by chemical mechanical polishing (CMP), leaving the adhesive layer and the tungsten film only in the contact holes. In this way, a conductive plug composed of the adhesive layer and the tungsten portion is formed.

  In recent years, in order to increase the speed of semiconductor integrated circuit devices, an insulating material having a low dielectric constant has attracted attention as a material for an interlayer insulating film. For example, fluorine-doped silicon oxide (SiOF), hydrogen silsesquioxane (HSQ), and the like are attracting attention. The inventor of the present application has found that it is difficult to fill the contact hole with good reproducibility when using such an insulating material having a low dielectric constant and forming a conductive plug by a conventional method.

  An object of the present invention is to provide a method for manufacturing a semiconductor device in which a contact hole can be filled with a conductive plug with good reproducibility even when an insulating material having a low dielectric constant is used.

According to one aspect of the invention,
Forming an interlayer insulating film containing SiOF or hydrogen silsesquioxane on the surface of the semiconductor substrate;
Forming an etching stop layer made of a material having a different etching resistance from the interlayer insulating film on the surface of the interlayer insulating film;
Forming a resist film having an opening on the surface of the etching stop layer;
Etching the etching stopper layer under the opening of the resist film using the resist film as a mask;
Under the condition that the etching rate of the resist film and the interlayer insulating film is faster than the etching rate of the etching stop layer, reactive ion etching without using oxygen plasma is performed under the opening of the resist film and the resist film. Etching the interlayer insulating film to form a contact hole penetrating the interlayer insulating film and removing the resist film;
Filling the contact hole with a conductive plug;
Forming a wiring connected to the conductive plug on the interlayer insulating film.

  Contact hole formation and resist film removal are performed simultaneously. Since the resist film is not ashed with oxygen plasma, the interlayer insulating film exposed on the inner peripheral surface of the contact hole can be prevented from being altered. For this reason, the contact hole can be filled with a conductive plug with good reproducibility.

  As described above, according to the present invention, the interlayer insulating film is not exposed to oxygen plasma during ashing of the resist film. Therefore, alteration of the interlayer insulating film can be prevented, and the contact hole formed in the interlayer insulating film can be filled with the conductive plug with good reproducibility.

  Before describing the embodiments of the present invention, the reason why a conductive plug cannot be formed with good reproducibility when an insulating material having a low dielectric constant is used will be described. According to experiments conducted by the inventors, when SiOF or HSQ is used as an interlayer insulating film, these films grow abnormally when an adhesive layer made of TiN is formed on the inner surface of the contact hole or when the contact hole is filled with tungsten. I found out that This is presumably because the interlayer insulating film is exposed to oxygen plasma during ashing of the resist film, and is easily altered or absorbs moisture. In the embodiments described below, the interlayer insulating film can be prevented from being exposed to oxygen plasma.

  A method for manufacturing a semiconductor device according to a first reference example of the present invention will be described with reference to FIGS. Each of FIGS. 1 and 2 is a cross-sectional view of a contact hole portion.

  As shown in FIG. 1A, a field oxide film 2 is formed on the surface of a silicon substrate 1, and an active region is defined by the field oxide film 2. Impurity diffusion regions 3 are formed in the substrate surface layer in the active region. The impurity diffusion region 3 is, for example, a MISFET source region or drain region.

On the surface of the field oxide film 2 and the impurity diffusion region 3, a SiO ₂ film 4A, a SiOF film 4B, and a SiO ₂ film 4C are laminated in this order, and an interlayer insulating film 4 composed of these three layers is formed. The SiO ₂ films 4A and 4C are formed by, for example, plasma enhanced chemical vapor deposition (CVD) using SiH ₄ and O ₂ as source gases. The SiOF film 4B is formed, for example, using high-density plasma by an inductively coupled plasma CVD apparatus and using SiF ₄ , SiH _4, and O ₂ as source gases.

As shown in FIG. 1B, a photoresist film 5 is formed on the interlayer insulating film 4. An opening 6 is formed in the resist film 5 at a position corresponding to the impurity diffusion region 3. The interlayer insulating film 4 is etched using the resist film 5 as a mask. Etching of the interlayer insulating film 4 is performed, for example, by reactive ion etching (RIE) using a mixed gas of CHF ₃ , CF ₄ , Ar, and N ₂ . Etching conditions are a pressure of 500 mTorr, an applied RF power of 800 W, a CHF ₃ gas flow rate of 13 sccm, a CF ₄ gas flow rate of 20 sccm, an Ar gas flow rate of 426 sccm, and an N ₂ gas flow rate of 10 sccm. A contact hole 7 is formed at a position corresponding to the opening 6 and the impurity diffusion region 3 is exposed on the bottom surface.

  After the contact hole 7 is formed, the resist film 5 is sintered by performing a heat treatment at a temperature of 180 to 250 ° C.

  FIG. 1B shows a state after the resist film 5 is sintered. Although the resist film 5 is deformed by sintering, it does not affect the shape of the contact hole 7 because the contact hole 7 has already been formed.

As shown in FIG. 1C, an adhesive layer 10 made of TiN is formed so as to cover the inner surfaces of the contact hole 7 and the opening 6 and the surface of the resist film 5. The adhesive layer 10 is formed by reactive sputtering using, for example, a Ti target and a mixed gas of Ar and N ₂ . A tungsten (W) film 11 is formed on the surface of the adhesive layer 10. The W film 11 is embedded in the contact hole 7 and the opening 6. The formation of the W film 11 is performed by CVD using WF ₆ at a substrate temperature of 400 to 460 ° C. The adhesive layer 10 prevents the W film 11 from peeling off.

  The steps up to FIG. 2A will be described. The W film 11, the adhesive layer 10, and the resist film 5 on the interlayer insulating film 4 are removed by CMP so that the adhesive layer 10 and the W film 11 remain only in the contact hole 7. Since the resist film 5 is sintered and hardened, polishing can be performed without causing clogging of the polishing cloth. Inside the contact hole 7, the conductive plug 15 composed of the adhesive layer 10 and the W film 11 remains.

  A wiring 16 connected to the conductive plug 15 is formed on the interlayer insulating film 4. The wiring 16 is formed by laminating a TiN layer, a Cu-containing Al layer, a Ti layer, and a TiN layer in order from the lower layer, and then patterning the laminated structure. The lowermost TiN layer is a barrier metal layer, and the uppermost TiN layer is an antireflection film. The Ti layer reduces the contact resistance between the Cu-containing Al layer and the TiN layer.

As shown in FIG. 2B, another wiring 17 is formed on the interlayer insulating film 4 simultaneously with the wiring 16. An interlayer insulating film 20 is formed on the interlayer insulating film 4 so as to cover the wirings 16 and 17. Similar to the interlayer insulating film 4, the interlayer insulating film 20 has a three-layer structure of a SiO ₂ film 20A, a SiOF film 20B, and a SiO ₂ film 20C.

  A contact hole 21 exposing a part of the upper surface of the wiring 17 is formed in the interlayer insulating film 20. The contact hole 21 is filled with a conductive plug 22. A wiring 23 connected to the conductive plug 22 is formed on the interlayer insulating film 20. The contact hole 21, the conductive plug 22, and the wiring 23 are formed in the same manner as the contact hole 7, the conductive plug 15, and the wiring 16, respectively.

  In the first reference example, after the contact hole 7 is formed in FIG. 1B, the adhesive layer 10 is formed without removing the resist film 5 by ashing. For this reason, the inner surface of the contact hole 7 is not exposed to the ashing atmosphere of the resist film. Thereby, alteration of the SiOF film 4B that defines the inner surface of the contact hole 7 can be prevented. By preventing alteration of the SiOF film 4B, abnormal growth of the adhesive layer 10 and the W film 11 can be prevented, and the contact hole 7 can be filled with the conductive plug 15 with good reproducibility. Similarly, the inside of the contact hole 21 can be filled with the conductive plug 22 with good reproducibility.

  In the first reference example, after forming the contact hole 7 in the step of FIG. 1B, the resist film 5 is sintered. Instead of sintering, curing by ultraviolet irradiation or curing in vacuum is performed. Etc. may be performed. The resist film 5 can also be hardened by ultraviolet curing or vacuum curing, and clogging of the polishing cloth during CMP can be prevented. If the growth temperature of the adhesive layer 10 and the W film 11 is high enough to sinter the resist film 5, the resist film 5 must not be sintered before the adhesive layer 10 is formed. Also good. Further, if the polishing cloth and slurry at the time of CMP are appropriately selected, CMP can be performed without causing clogging of the polishing cloth even when the resist film 5 is not sintered.

  In the first reference example, the case where the middle layer of the interlayer insulating film 4 is formed of the SiOF film 4B has been described. Even when another low dielectric constant material, such as HSQ, is used instead of the SiOF film 4B, the same effect as in the first reference example will be obtained.

In the first reference example, the case where the interlayer insulating film 4 has a three-layer structure of the SiO ₂ film 4A, the SiOF film 4B, and the SiO ₂ film 4C has been described. However, the interlayer insulating film 4 is composed of only the SiOF film. It may be configured. In this case, the upper surface of the SiOF film is exposed in the state shown in FIG. 2A after the resist film is removed. However, since the contact hole 7 is already filled with the conductive plug 15, the exposure of the SiOF film does not cause a decrease in reproducibility of the filling in the contact hole 7.

  Next, with reference to FIG. 3, a method for manufacturing a semiconductor device according to a second reference example will be described.

Processes up to the state shown in FIG. The contact hole 7 is formed through the same process as that up to the state shown in FIG. 1B of the first reference example. A coating film 25 made of SiO ₂ is formed so as to cover the opening 6, the inner surface of the contact hole 7, and the surface of the resist film 5. The coating film 25 is formed under the condition that the substrate temperature is in the range of room temperature to 400 ° C., for example, by plasma enhanced CVD using SiH ₄ and O ₂ .

  As shown in FIG. 3B, the coating film 25 is anisotropically etched to leave the coating film 25 only on the inner peripheral surfaces of the contact hole 7 and the opening 6. The surface of the impurity diffusion region 3 exposed on the bottom surface of the contact hole 7 is thinned by milling using Ar ions. Thereafter, the conductive plug 15 and the wiring 16 are formed through the same steps as the steps from FIG. 1C to FIG. 2B of the first reference example.

  FIG. 3C shows a state after the wiring 16 is formed. A part of the coating film 25 remains between the inner peripheral surface of the contact hole 7 and the conductive plug 15. Other configurations are similar to those of the first reference example shown in FIG.

  In the second reference example, in the step shown in FIG. 3B, the inner peripheral surface of the opening 6 is covered with a coating film 25 and the surface of the impurity diffusion region 3 is shaved while suppressing degassing from the resist film 5. ing. Thereby, the contact resistance between the conductive plug 15 and the impurity diffusion region 3 can be reduced.

  Next, an embodiment of the present application will be described with reference to FIG. In the embodiment, description will be given by taking as an example the formation of a conductive plug for connecting the lower layer wiring and the upper layer wiring. However, similar to the conductive plug 15 shown in FIG. The present invention can also be applied to the formation of a conductive plug that connects the upper wiring.

  As shown in FIG. 4A, a lower layer wiring 31 is formed on the interlayer insulating film 30. The lower layer wiring 31 has a four-layer structure including a TiN film, a Cu-containing Al film, a Ti film, and a TiN film. An interlayer insulating film 32 is formed on the interlayer insulating film 30 so as to cover the lower layer wiring 31. The interlayer insulating film 32 is formed of a low dielectric constant insulating material such as SiOF or HSQ.

  An etching stop layer 33 made of SiN is formed on the interlayer insulating film 32. The etching stop layer 33 is formed by, for example, plasma enhanced CVD. A photoresist film 34 is formed on the etching stop layer 33. An opening 35 is formed in the resist film 34. The lower layer of the opening 35 is located above the latitude line 31.

  Using the resist film 34 as a mask, the etching stop layer 33 is etched to form an opening 36.

As shown in FIG. 4B, the resist film 34 and the interlayer insulating film 32 are etched by RIE using CHF ₃ , CF ₄ , Ar, and N ₂ . Etching conditions are, for example, pressure 1000 mTorr, applied RF power 900 W, CHF ₃ gas flow rate 13 sccm, CF ₄ gas flow rate 20 sccm, Ar gas flow rate 426 sccm, and N ₂ gas flow rate 10 sccm. Under this condition, the ratio of the etching rate of the SiOF film to the resist film is about 2-3.

  Thus, since the etching selectivity is small, the resist film 34 and the interlayer insulating film 32 can be etched simultaneously. Under this etching condition, since the SiN film is hardly etched, the etching stop layer 33 serves as an etching mask for the interlayer insulating film 32. Accordingly, a contact hole 37 is formed corresponding to the opening 36.

  As shown in FIG. 4C, a conductive plug 38 is embedded in the contact hole 37. The conductive plug 38 is formed by the same method as the conductive plug 15 formed in the steps of FIGS. 1C and 2A of the first reference example.

  An upper layer wiring 39 connected to the conductive plug 38 is formed on the etching stop layer 33. The upper layer wiring 39 is formed by the same method as the formation of the wiring 16 shown in FIG. 2A of the first reference example.

  In the embodiment, after the state of FIG. 4A, the resist film 34 is not removed by ashing, but is removed simultaneously with the etching of the interlayer insulating film 32. For this reason, the interlayer insulating film 32 is not exposed to oxygen plasma during ashing. Alteration of the interlayer insulating film 32 exposed on the inner peripheral surface of the contact hole 37 is prevented, and the contact hole 37 can be filled with the conductive plug 38 with good reproducibility. Further, since the formation of the contact hole 37 and the removal of the resist film 34 are performed at the same time, the number of processes can be reduced and the production cost can be reduced.

  In the above embodiment, the case where the etching stopper layer 33 is formed of SiN has been described. However, the etching stopper layer 33 may be formed of another material having a different etching resistance from the interlayer insulating film 32. For example, it may be formed of SiON or the like. After the contact hole 37 shown in FIG. 4B is formed, milling using Ar ions may be performed before the conductive plug 38 is formed. By this milling, the surface of the lower layer wiring 31 exposed on the bottom surface of the contact hole 37 is thinned, and the contact resistance between the lower layer wiring 31 and the conductive plug 38 can be reduced. Further, the etching stop layer 33 may be removed by this milling. By removing the etching stop layer 33, the parasitic capacitance between the wirings can be reduced.

  In the above reference examples and examples, the case where SiOF or HSQ is used as the interlayer insulating film has been described. However, the same effect can be expected when other organic and inorganic spin-on-glass (SOG) materials are used. it can. The effect can also be expected when fluorocarbon, fluorine amorphous carbon, or fluororesin is used.

  Although the present invention has been described with reference to the embodiments, the present invention is not limited thereto. It will be apparent to those skilled in the art that various modifications, improvements, combinations, and the like can be made.

It is sectional drawing (the 1) of the electroconductive plug part for demonstrating the manufacturing method of the semiconductor device by the 1st reference example. It is sectional drawing (the 2) of the electroconductive plug part for demonstrating the manufacturing method of the semiconductor device by a 1st reference example. It is sectional drawing of the electroconductive plug part for demonstrating the manufacturing method of the semiconductor device by the 2nd reference example. It is sectional drawing of the electroconductive plug part for demonstrating the manufacturing method of the semiconductor device by an Example.

Explanation of symbols

DESCRIPTION OF SYMBOLS 1 Silicon substrate 2 Field oxide film 3 Impurity diffusion region 4, 20, 30, 32 Interlayer insulation film 5, 34 Resist film 6, 35, 36 Opening 7, 21, 37 Contact hole 10 Adhesion layer 11 W film 15, 22, 38 Conductive plugs 16 and 23 Wiring 25 Covering film 31 Lower layer wiring 33 Etching stop layer 39 Upper layer wiring

Claims (2)

Forming an interlayer insulating film containing SiOF or hydrogen silsesquioxane on the surface of the semiconductor substrate;
Forming an etching stop layer made of a material having a different etching resistance from the interlayer insulating film on the surface of the interlayer insulating film;
Forming a resist film having an opening on the surface of the etching stop layer;
Etching the etching stopper layer under the opening of the resist film using the resist film as a mask;
Under the condition that the etching rate of the resist film and the interlayer insulating film is faster than the etching rate of the etching stop layer, reactive ion etching without using oxygen plasma is performed under the opening of the resist film and the resist film. Etching the interlayer insulating film to form a contact hole penetrating the interlayer insulating film and removing the resist film;
Filling the contact hole with a conductive plug;
Forming a wiring connected to the conductive plug on the interlayer insulating film.   The method of manufacturing a semiconductor device according to claim 1, further comprising: removing the etching stop layer after removing the resist film and before filling the contact hole with the conductive plug.