JP4341443B2 - Constant voltage supply circuit - Google Patents

Description

  The present invention relates to a constant voltage supply circuit that generates a constant voltage.

An example of this type of constant voltage supply circuit is disclosed in Patent Document 1. According to this configuration, when the external power supply voltage is higher than a predetermined voltage, the nMOS regulator is utilized by taking advantage of the high flatness of the voltage generated by the pMOS regulator generation power supply, the area saving, and the noise resistance of the nMOS regulator generation power supply. By switching to the output voltage of the generated power supply and supplying it to the internal circuit, the influence of noise of the external power supply voltage can be reduced. When the external power supply voltage is lower than the predetermined voltage, the output voltage of the pMOS regulator is switched to the output voltage Thus, the supply voltage variation is eliminated by supplying the internal circuit.
JP 2003-168291 A

  In the configuration disclosed in Patent Document 1, when a high voltage is supplied, the influence of external noise can be reduced by using an nMOS regulator generation power source. Since the power source generated by the pMOS regulator is used without being used, there is a problem that the influence of noise due to the external power source voltage cannot be avoided.

  The present invention has been made in view of the above circumstances, and an object thereof is to provide a constant voltage supply circuit capable of suppressing the influence of noise caused by an external power supply voltage even when supplying a constant voltage to the internal circuit. There is.

According to invention of Claim 1, it acts as follows. In other words, the voltage follower circuit generates a constant voltage by voltage follower from the voltage of the node on the supply side, and the booster circuit boosts the voltage followered by the voltage follower circuit . For this reason, the voltage follower circuit can suppress the influence of the voltage fluctuation of the node on the supply side and supply it to the booster circuit. The voltage adjustment circuit adjusts this boosted voltage based on the voltage on the source side of the first MOS transistor. In an n-channel MOS transistor, a drain and a source are connected between a supply-type node to which an external power supply voltage is supplied and a node on the constant voltage output side, and is connected to the gate of the n-channel MOS transistor. Since the voltage boosted by the booster circuit and the voltage adjusted by the voltage regulator circuit are applied, a stable voltage is applied between the gate and source of the n-channel MOS transistor. It becomes like this.
Here, in the voltage adjustment circuit, the output voltage detection voltage dividing resistor detects the output voltage, and applies this divided voltage to the inverting input terminal of the operational amplifier. The operational amplifier compares the reference voltage applied to the non-inverting input terminal with the divided voltage and outputs it to the gate of the second MOS transistor. The resistors (R1, R2) are connected in series between the output of the booster circuit and the gate of the first MOS transistor, and the resistor (R3) is connected between the common connection point of the resistors (R1, R2) and the ground. Since the drain and source of the first MOS transistor are connected in series, the charge of the gate input capacitance of the first MOS transistor can be released to the ground, and the gate voltage of the first MOS transistor can be adjusted step-down. Thus, an appropriate constant voltage can be applied to the gate of the first MOS transistor, and an appropriate constant voltage can be output. In addition, since the filter circuit performs low-pass filtering with the resistors (R1, R2, R3) and the capacitor of the voltage adjustment circuit, switching noise can be removed.

Since the n-channel MOS transistor is used so as to function as a source follower, the influence of voltage fluctuations of the external power supply voltage can be suppressed even when a constant voltage is supplied to the internal circuit. Further, it is possible to configure a regulator circuit that is resistant to power supply voltage fluctuations (noise) while reducing the voltage source noise elimination filter.
According to the second aspect of the present invention, when the booster circuit is a charge pump circuit, because the filter circuit is adapted to low pass filter the boosted voltage of the booster circuit, MOS a more stable voltage It can be supplied to the gate of the transistor.

According to the invention 請 Motomeko 3 wherein, n-channel MOS transistor, even when the transistor n-type source / drain diffusion layer region of formed connected p-type semiconductor substrate to ground The present invention can be applied to the invention of claim 1 or 2 . That is, even when the potential of the back gate of the n-channel MOS transistor is not fixed to a high potential such as the source potential, the voltage is boosted by the booster circuit so that the voltage is applied to the gate of the MOS transistor. Thus, a necessary voltage can be applied to the gate of the MOS transistor.

An embodiment in which the present invention is applied to a regulator circuit formed in a semiconductor integrated circuit device will be described below with reference to FIGS.
FIG. 1 schematically shows a regulator circuit as a constant voltage supply circuit. In FIG. 1, a regulator circuit 1 as a constant voltage supply circuit is mounted on a vehicle, and a voltage + B as an external power supply voltage supplied from a battery mounted on the vehicle is set to a constant predetermined voltage. A constant voltage is output from an output terminal OUT on the voltage output side and supplied to an internal circuit (not shown).

An n-channel MOS transistor Tr1 (corresponding to the first MOS transistor of the present invention) is connected between a node N1 to which a voltage + B (for example, + 12V or + 9V) is supplied and a node N2 connected to the output terminal OUT. The drain-source is connected.
2A and 2B schematically show an example of the structure of the MOS transistor Tr1. In the MOS transistor Tr1 shown in FIG. 2 (a), n-type source / drain diffusion layer regions So and Dr are formed in a p-type semiconductor substrate H that is at a ground potential, and the source / drain diffusion layer regions So and A gate electrode Gate is formed on the semiconductor substrate H via the insulating film Z with the Dr formation region interposed therebetween. At this time, the p-type semiconductor substrate H coincides with the ground potential.

  As another example, in the MOS transistor Tr1 shown in FIG. 2B, an n-well region nw is formed in a p-type semiconductor substrate H having a ground potential, and the p-well region pw is formed in the n-well region nw. The source / drain diffusion layers So and Dr of the MOS transistor Tr1 are formed in the p well region pw, and the gate electrode Gate is formed on the semiconductor substrate H with the insulating film Z interposed therebetween. Show.

In the p well region pw, a p-type impurity region B having a high impurity concentration is formed in addition to the source / drain diffusion layers So and Dr of the MOS transistor Tr1, and the p-type impurity region B and the source diffusion are formed. The layer region So is connected. This connection functions as a back gate of the so-called MOS transistor Tr1.
In the case of the configuration of FIG. 2A, it is necessary to increase the voltage applied to the gate Gate of the MOS transistor Tr1 as compared with the configuration of FIG. In the configuration shown in FIG. 2B, the channel region of the MOS transistor Tr1 is kept at a high potential, so that the MOS transistor Tr1 can be operated in the saturation region even if a relatively low voltage is applied to the gate. In contrast, in the case of the configuration shown in FIG. 2A, the channel region of the MOS transistor Tr1 has a substantially ground potential, so that the MOS transistor Tr1 operates in the saturation region even when a relatively low voltage is applied to the gate. There is nothing.

In the present embodiment, the voltage applied to the gate electrode Gate of the MOS transistor Tr1 can be increased by using the booster circuit 2 to apply the boosted voltage to the gate of the transistor Tr1. Even if the circuit configuration is as shown in (a), a sufficient gate voltage can be supplied to the MOS transistor Tr1.
Further, between the node N1 to which the voltage + B is supplied and the ground GND, the constant current circuit 3, the gate-source of the n-channel MOS transistor Tr2, and a diode group formed by connecting a plurality of diodes in series. D is connected. At this time, the drain and gate of the MOS transistor Tr2 are connected. The gate voltage of the MOS transistor Tr2 is kept constant by the action of this circuit.

  The node N1 is connected to the drain of an n-channel MOS transistor Tr3, and the gates of the MOS transistors Tr2 and Tr3 are connected to each other. The MOS transistor Tr3 functions as a source follower (voltage follower) that voltage-follows the voltage at the node N1, and applies the voltage-followed voltage to the booster circuit 2.

FIG. 3 schematically shows an example of the booster circuit.
The booster circuit 2 is constituted by a so-called charge pump circuit, and boosts an input voltage when a clock signal CLK is given from a control circuit (not shown). As shown in FIG. 3, the charge pump circuit as the booster circuit 2 is configured by combining a plurality of NOT gates NT1 to NT2, a plurality of diodes D1 to D2, and a plurality of capacitors C2 to C4. Since the booster circuit 2 is a general charge pump circuit, the description of the operation is omitted. However, since the booster circuit 2 boosts the voltage by receiving the clock signal CLK, so-called switching noise is generated through the NOT gates NT1 to NT2 and the capacitors C2 to C4. The latter stage is also affected by switching noise.

So downstream of the booster circuit 2, a low-pass filter circuit LPF (corresponding to the filter circuit) is provided with the boosted voltage to the gate of the MOS transistor Tr1 is adapted to be supplied through the low pass filter circuit LPF .
A specific circuit configuration of the low-pass filter circuit LPF will be described. The low-pass filter circuit LPF includes resistors R1 to R3 and a capacitor C1. Resistors R1 and R2 are connected in series between the output of the booster circuit 2 and the gate of the MOS transistor Tr1, and a capacitor C1 is connected between the gate of the MOS transistor Tr1 and the ground GND.

Between the common connection point of the resistors R1 and R2 and the ground GND, the resistor R3 and the drain-source of the n-channel MOS transistor Tr4 for feedback (corresponding to the second MOS transistor) are connected in series. . In this way, a low pass filter circuit LPF using an RC filter is formed. Switching noise can be removed by the low-pass filter circuit LPF.

  Output voltage detection resistors R4 and R5 are connected in series between the source-side node N2 to which the output terminal OUT is connected and the ground GND. A divided voltage obtained by dividing the voltage of the output terminal OUT by these resistors R4 and R5 is applied to the inverting input terminal of the operational amplifier OP1. The reference voltage Vref is applied to the non-inverting input terminal of the operational amplifier OP1. The operational amplifier OP1 is supplied with the voltage applied to the node N1 as a power supply voltage, and the output of the operational amplifier OP1 is applied to the gate of the MOS transistor Tr4.

The operational amplifier OP1, resistors R1 to R5, and the MOS transistor Tr4 function as a voltage adjustment circuit 4 that adjusts the voltage applied to the gate of the MOS transistor Tr1.
The operation of the above configuration will be described.
In the present embodiment, the operation of a case where a large power supply voltage fluctuation (noise) voltage is applied to the supply-side node N1 will be described. That is, even if a power supply voltage fluctuation occurs such that the voltage + B drops to a voltage close to the threshold voltage of the MOS transistor Tr1, a stable constant voltage is applied to an internal circuit (not shown) connected to the output terminal OUT. Explain what can be supplied.

  Even when the voltage + B is lowered to a voltage close to the threshold voltage of the MOS transistor Tr1, the MOS transistor Tr3 functions as a source follower, and therefore, a voltage close to the voltage + B is supplied to the booster circuit 2 while removing the power supply voltage fluctuation. be able to. The booster circuit 2 boosts the applied voltage and supplies it to the low-pass filter circuit LPF. Then, the low-pass filter circuit LPF removes noise based on the clock signal CLK and applies it to the gate electrode Gate of the transistor Tr1.

  Since the voltage is applied to the gate electrode Gate of the MOS transistor Tr1 through the booster circuit 2, a higher voltage can be applied to the gate of the MOS transistor Tr1 than in the circuit without the booster circuit 2, and the transistor Tr1 The gate-source voltage can be made sufficiently high. In addition, even if the booster circuit Tr1 is configured by a charge pump circuit, a voltage is applied to the gate of the MOS transistor Tr1 through the low-pass filter circuit LPF, so that a voltage that suppresses digital noise based on the clock signal CLK is applied to the gate. Will be able to.

  Further, simultaneously with this action, a voltage is applied to the gate electrode Gate of the MOS transistor Tr1 while being stepped down by the voltage adjustment circuit 4. Since the divided voltage of the output voltage by the resistors R4 and R5 is applied to the inverting input terminal of the operational amplifier OP1, and the output of the operational amplifier OP1 is applied to the gate of the MOS transistor Tr4, the gate input capacitance of the MOS transistor Tr1. Can be released to the ground GND, and the gate voltage of the MOS transistor Tr1 can be stepped down. Therefore, an appropriate constant voltage can be applied to the gate of the MOS transistor Tr1, and an appropriate constant voltage can be output.

  As described above, according to the present embodiment, even if the power supply voltage fluctuation occurs such that the voltage + B drops to a voltage close to the threshold voltage Vth of the MOS transistor Tr1, the booster circuit 2 causes the n-channel type to change. Since the gate voltage of the MOS transistor Tr1 can be increased, a sufficient gate-source voltage can be obtained, and a stable constant voltage is supplied to an internal circuit (not shown) connected to the subsequent stage. become able to.

  In addition, since the MOS transistor Tr3 is configured to function as a voltage follower, adverse effects on the booster circuit 2 due to the voltage fluctuation of the voltage + B can be suppressed. Further, since the voltage is applied to the gate of the MOS transistor Tr1 through the low-pass filter circuit LPF, it is possible to further suppress the influence of voltage electric power (noise) of the voltage + B.

(Other embodiments)
The present invention is not limited to the above embodiment, and can be modified or expanded as shown below, for example.
Although an embodiment in which a charge pump circuit is applied as the booster circuit 2 has been described, any circuit may be used as long as the circuit boosts the voltage.

If necessary, a circuit such as a resistor may be added to the voltage + B supply side or the constant voltage output side.
A pMOS regulator circuit combining a p-type MOS transistor, an operational amplifier, and a resistor may be added to the subsequent stage of the circuit shown in FIG. With this configuration, a highly accurate regulator circuit that is resistant to external power supply fluctuations (noise) can be configured.

1 is a schematic electrical configuration diagram showing an embodiment of the present invention. Configuration diagram schematically showing configuration of MOS transistor in semiconductor integrated circuit device The figure which shows an example of a booster circuit roughly

Explanation of symbols

In the drawings, 1 is a regulator circuit (constant voltage supply circuit), LPF is a low-pass filter circuit (filter circuit), 4 is a voltage adjustment circuit, Tr1 is an n-channel MOS transistor, Tr1 to Tr4 are n-channel MOS transistors, N1 is a node on the supply side, N2 is a node on the constant voltage output side, and Gate is a gate electrode of the MOS transistor (gate of the MOS transistor).

Claims (3)

An n-channel first MOS transistor having a drain and a source connected between a node on the supply side to which an external power supply voltage is supplied and a node on the constant voltage output side;
A voltage follower circuit that generates a constant voltage by voltage follower from the voltage of the node on the supply side ;
A step-up circuit that generates a step-up voltage by stepping up a voltage that has been voltage-followed by the voltage follower circuit;
A voltage regulator circuit for adjusting the boosted voltage of the booster circuit based on the source side voltage of said first MOS transistor, connected in series output voltage between the source and ground of the first MOS transistor A voltage dividing resistor for detection and a voltage applied to the node on the supply side are applied as a power supply voltage, and a divided voltage of the voltage dividing resistor is applied to an inverting input terminal and a reference voltage is applied to a non-inverting input terminal. An operational amplifier, a second MOS transistor to which the output of the operational amplifier is applied to the gate, resistors (R1, R2) connected in series between the output of the booster circuit and the gate of the first MOS transistor, A resistor (R3) connected in series with the drain-source of the second MOS transistor between the common connection point of the resistors (R1, R2) and the ground A voltage regulator circuit which is configured by including bets,
A filter circuit that performs low-pass filtering with the resistors (R1, R2, R3) of the voltage regulator circuit and a capacitor ;
A voltage boosted by the boosting circuit, adjusted by the voltage adjusting circuit and low-pass filtered by the filter circuit is applied to the gate of the n-channel first MOS transistor. A characteristic constant voltage supply circuit. Constant voltage supply circuit according to claim 1, wherein the booster circuit, wherein the Dearuko charge pump circuit. 3. The n-channel first MOS transistor is a transistor in which an n-type source / drain diffusion layer region is formed on a p-type semiconductor substrate that is at a ground potential. Constant voltage supply circuit.

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