JP4342264B2 - Symbol clock synchronization method and apparatus - Google Patents

Description

  The present invention relates to a symbol clock synchronization apparatus for a radio communication device using a phase modulation method, and more particularly, to use a symbol clock synchronization method of a π / 4 shift QPSK method used in a demodulation device for a radio receiver such as mobile communication. The present invention relates to a high-speed symbol clock synchronization method and apparatus for synchronizing with a smaller number of bits than in the conventional method.

  In wireless communication such as PHS and mobile phones, the phase modulation method is widely used, and the receiver processes the received signal and extracts the transmitted information signal. It is necessary to perform processing such as frame synchronization, symbol timing synchronization, and frequency shift correction on the transmitted signal.

  FIG. 6 is a block diagram showing a conventional example of a demodulation circuit of a π / 4 shift QPSK (Quaternary Phase Shift Keying) modulation method. The demodulator circuit shown in FIG. 6 has symbol timing detection means in the demodulator 20, and in a circuit preceding the illustrated circuit, it receives a radio signal, amplifies the received signal, and a radio frequency (RF) of the received signal. The processing such as down-conversion from 1 to the intermediate frequency (IF) is executed, and the IF reception signal is input to the circuit portion shown in FIG. An AGC (Auto Gain Control) 1 inputs an IF reception signal variably amplified by gain control to an orthogonal demodulator 2.

  The quadrature demodulator 2 performs quadrature demodulation on this IF reception signal, and the obtained baseband signals of I (in-phase) and Q (quadrature phase) channels are used as low-pass filters 3 and 4 for removing unnecessary components. The symbol timing necessary for demodulating the digital information signal can be detected by the correlation function by the demodulator 20 that is converted to digital data by the A / D converters 5 and 6 via the.

  FIG. 7 is a schematic diagram showing a general frame format, and wireless communication is performed according to the frame format. As a frame format in wireless communication using a phase modulation method, generally, ramp up time for transient response (RU), start symbol (SS), preamble (PR), synchronization word (UW), data area (DATA) And ramp down time (RD) for transient response, and each information is represented by several bits to several tens of bits.

  FIG. 8 is an exemplary diagram illustrating a calculation method in the case of calculating a correlation function between a reference PR data pattern and a reception data pattern, and uses a preamble (PR) before a synchronization word (UW) to indicate the internal structure of the receiver. The reference PR data and the input data are successively compared until they match, and the received symbol timing is detected in the correlation function calculation interval (n) in which the correlation function value shows the maximum value as a method for determining the match.

  In addition, in a receiver using the orthogonal demodulation method as shown in FIG. 6, when a radio signal transmitted from a communication partner is received for the first time, information such as a received signal level, a received symbol timing shift, and a carrier frequency shift is known. In spite of the absence, since the data after the synchronization word (UW) is necessary data for performing the demodulation operation, it is necessary to obtain information such as the received signal level from the received signal up to the preamble (PR).

  FIG. 9 is a time chart showing temporal changes in transmission power at the transmitter and reception power at the receiver. The transmission power level in the transmitter is shown in FIG. At the start of transmission, the transmission power is gradually increased during the ramp-up (RU) period, and the maximum transmission power value is set when the start bit (SS) starts. Thereafter, a preamble (PR) for synchronization, a synchronization word (UW) including information such as a base station, and a data area (DATA) including voice information and data information are transmitted. At the end of transmission, the transmission power is gradually decreased in the ramp-down (RD) section, and a cycle is continuously performed so that the transmission power is turned off at the end of the ramp-down section.

There are the following four methods for obtaining the reception symbol clock synchronization.
(1) A method of obtaining the nearest sampling point by calculating a complex correlation function value between a reference preamble (PR) data pattern prepared in advance in a receiver and a received data pattern as shown in FIG.

FIG. 10 is an exemplary diagram showing a demodulation result on a phase plane when a reference sampling point is found while finely adjusting sampling data. Like the method of taking the received symbol synchronization from the phase error,
(2) A method of finding the symbol timing while finely adjusting the sampling data from the phase error of the demodulation result.

further,
(3) A method for detecting symbol timing using a preamble (PR) received signal pattern in a frame format disclosed in Patent Document 1.
(4) There is a method for detecting from the output vector of the sampling data one symbol before and the differential data disclosed in Patent Document 2.

JP 2001-237905 A JP 2002-171297 A

  The conventional symbol clock synchronization method has the following problems in symbol timing detection.

  The first problem is that in the method of calculating the correlation function value between the reference preamble (PR) data pattern and the received data pattern to obtain symbol clock synchronization, the output signal of the quadrature demodulator is at a frequency that is at least twice the symbol frequency. Sampling is performed by an A / D converter, and a correlation function value between the sampled received data and a preamble data pattern prepared in advance in the receiver is calculated. At this time, if the received signal level is high, the output of the quadrature demodulator may be saturated. In this case, information is lost due to saturation, and the correlation function value cannot be calculated accurately. Therefore, it is necessary to adjust the gain of the AGC in the previous stage so that the output of the quadrature demodulator is not saturated. If the input level is not constant, the correlation function value varies.

  The second problem is that if the preamble (PR) is used to adjust the input level, it cannot be used to calculate the correlation function value from the first bit of the preamble (PR), and the preamble (PR) It will be used to calculate the correlation function value from the intermediate data. If it takes a long time to correct the input level, the number of data that can be used to calculate the correlation function value decreases, and the number of data that can be used to calculate the correlation function value varies depending on the input level. Occurs.

  The third problem is that, as shown in the received power examples of FIGS. 9B and 9C, the received signal level in the receiver varies depending on the conditions of the propagation path and the like, and is 100 dB or more depending on the distance to the communication partner, etc. Input level differences may occur. Also, in an urban area or the like, the input level may drop sharply when entering the shadow of a building, and as a result, the correlation function value cannot be calculated from the first bit of the preamble (PR).

  The fourth problem is that in the method of finding the symbol timing while finely adjusting the sampling point, the reference phase point (± 45 degrees, ± 135 degrees) is compared with the phase point of the demodulation result, and it becomes close to the reference phase point. Adjust the sampling point as follows. The initial value may be shifted by a maximum of 1/2 symbol. In this case, it takes time to adjust the sampling point and correct it to the optimum value, and this is suitable when the number of bits of the preamble (PR) is small. Not.

  The present invention has been made in view of such a problem, and an object of the present invention is to provide a high-speed symbol clock synchronization method for efficiently synchronizing a received signal with a small number of bits for symbol timing detection.

In order to solve the above-described problem, a symbol clock synchronization method according to the present invention includes a quadrature demodulation process using a π / 4 shift QPSK system and a symbol clock synchronization method for a receiver having a detection process for synchronization. A sampling step of sampling the received signal at a frequency more than twice the symbol frequency to convert it to a quadrature demodulated signal, and delay detection on the sampled in-phase and quadrature component signal sequences to obtain a phase difference between one symbol a differential detection step of detecting that the square sum calculating step of calculating a sum of squares of differential detection signal sequence, an averaging step of averaging the signal sequence of the computed squared sum for each sampling sequence, averaging been averaged signal maximum value to become sampling point from among the signal sequence and a determination step of determining is that a symbol peak received Regardless of the issue of pattern, and detecting a symbol timing.

The symbol clock synchronization method according to the present invention is a symbol clock synchronization method for a receiver having an orthogonal demodulation step using a π / 4 shift QPSK system and a detection step for obtaining synchronization. A sampling step of sampling at a frequency twice or more the symbol frequency and converting it to a quadrature demodulated signal, and a delay detection step of detecting a phase difference between one symbol by performing delay detection on the sampled in-phase and quadrature component signal sequences When the square sum calculating step of calculating a sum of squares of differential detection signal sequence, an averaging step of averaging the signal sequence of the computed squared sum for each sampling sequentially averaged signal sequence It obtains a difference between the averaged signal and the 1/2 averaged signal of the symbol apart sample points from within the sampling POI that difference becomes the maximum value DOO is and a determination step of determining that the symbol peak, regardless of the pattern of the received signal, and detecting a symbol timing. Further, in the symbol clock synchronization method of wireless communication, the symbol timing is detected without processing the pattern of the received signal by the cross-correlation function .

The symbol clock synchronizer according to the present invention is a symbol clock synchronizer of a receiver having a quadrature demodulating means using a π / 4 shift QPSK system and a detecting means for achieving synchronization. Sampling means for sampling at a frequency more than twice the symbol frequency and converting it to a quadrature demodulated signal, and delay detecting means for detecting a phase difference between one symbol by performing delay detection on the sampled in-phase and quadrature component signal sequences When the square sum calculating means for calculating a sum of squares of differential detection signal sequence, an averaging means for averaging the signal sequence of the computed squared sum for each sampling sequentially averaged signal sequence sampling point with the maximum value of the averaged signal and a determining means and a symbol peak from within, the pattern of the received signal Not, and detecting a symbol timing.

Furthermore, a symbol clock synchronizer according to the present invention is a symbol clock synchronizer of a receiver having a quadrature demodulating means using a π / 4 shift QPSK system and a detecting means for achieving synchronization. Sampling means for sampling at a frequency more than twice the symbol frequency and converting it into a quadrature demodulated signal, delay detection means for performing delay detection on the sampled in-phase component and quadrature component signal sequences, and delay-detected signal sequences and square sum calculating means for calculating a sum of squares, and averaging means for averaging the signal sequence of the computed squared sum for each sampling sequence, signal averaged from the averaged signal sequence and 1 / 2 obtains a difference between the averaged signal of the symbol apart sample points, the sampling points where the difference is the maximum value is a symbol peak With a constant determining means, and regardless of the pattern of the received signal, and detecting a symbol timing.

  According to the present invention, it is possible to provide a symbol clock synchronization method that can efficiently perform clock synchronization of a received signal with a small number of bits.

  Hereinafter, embodiments of the present invention (hereinafter referred to as embodiments) will be described with reference to the drawings.

FIG. 1 is a block diagram of a symbol timing detection circuit using a symbol timing detection method according to an embodiment of the present invention. The demodulator 201 includes a delay detection module 21, an I / Qch square sum module 22, a sampling average module 23, a 1/2 symbol deviation determination module 24, a maximum value determination module 25, and a changeover switch 26.

  A first embodiment in which a sampling point closest to the symbol peak point is found using the maximum value determination module 25 by the changeover switch 26 of FIG. 1 and symbol clock synchronization is performed for each symbol will be described.

  First, the input signal level of ACG1 is adjusted so that the output of the quadrature demodulator is not saturated. If the phase modulation signal is distorted, an error occurs in the phase information. Therefore, the gain of the AGC at the preceding stage of the quadrature demodulator is adjusted so that the input signal level is not distorted, and the gain is not changed during the calculation. .

  When the input signal level decreases due to the condition of the transmission path, gain adjustment is performed. However, depending on the timing, it cannot always be used for detection of the received symbol timing from the first bit of the preamble (PR). In one embodiment, the calculation is performed by a method that does not depend on the correlation function value based on the data pattern of the preamble (PR).

  FIG. 2 is an exemplary diagram illustrating a π / 4 shift QPSK signal space arrangement according to an embodiment of the present invention. The case where the modulation method is received with π / 4 shift QPSK and 4 oversampling per symbol will be described with reference to FIG.

  In the case of π / 4 shift QPSK, when the input signal is viewed on the phase plane, the symbol peak points are gathered at 8 points on the circumference as shown in FIG. This data exists on a line connecting 8 points on the circumference. However, in actual communication, the band is limited by the filter, and therefore exists near the line.

  The π / 4 shift QPSK is a kind of QPSK, and the phase difference between consecutive symbols is ± π / 4 and ± 3π / 4. Since the phase difference between successive symbols is information to be transmitted, in order to obtain the phase difference between successive symbols, in one embodiment of the present invention, delayed detection is performed on the sampled data. Delayed detection is a detection method that obtains a demodulated signal by detecting a phase difference without using a reference carrier wave by performing complex multiplication with a sampled received signal by regarding the received PSK signal sampled one symbol before as a reference wave. is there.

  The sampling data after the delay detection is represented on the phase plane as shown in FIG. 2B, and the sampling data of the symbol peak points after the delay detection are collected at four points. In addition, sampling data that is not a symbol peak point exists inside a circle whose radius is four symbol peak points.

Furthermore, the sampling data can be synchronized with the symbol peak by moving on the line and taking symbol clock synchronization. In the signal space layout diagram, since the distance from the origin is the amplitude, if the sum of squares of the sampling data (Ich, Qch) after delay detection is calculated, the calculation result after delay detection is the sampling peak point or the nearest point. The value of the sum of squares is the largest. Then, to each other, the sampling points away two minutes (i.e. away 1/2 symbol) set of delayed sampling data (Ich, Qch) after detection determines the difference between the sum of squares of, this value is the most large This point can be determined as the point closest to the symbol peak, and symbol clock synchronization can be achieved.

  FIG. 3 is a flowchart for calculating a symbol peak from sampling data for one symbol according to the first embodiment of the present invention. The sampling data is oversampled four times.

  Hereinafter, the flow of processing will be described with reference to FIGS. 1 and 3. The initial setting (step S1) in FIG. 3 initializes a storage area for storing data. Thereafter, the process waits for sampling data (step S2).

  Processing such as down-conversion of the received signal from a radio frequency (RF) to an intermediate frequency (IF) not shown in FIG. 1 is performed, and the IF received signal is input to the circuit portion shown in FIG. An AGC (Auto Gain Control) 1 inputs an IF reception signal variably amplified by gain control to a quadrature demodulator 2, and passes the obtained in-phase component and quadrature component to low-pass filters 3 and 4 and A / D converters 5 and 6. To the demodulator 20 to obtain sampling data in the sampling wait (step S2).

  The in-phase component and the quadrature component input to the demodulator 20 in FIG. 1 are delay-detected by the delay detection module 21 by the operation shown in the delay detection (step S3) in FIG. 3, and the Ich / Qch square sum module 22 in FIG. The amplitude value (Power value) is obtained by the calculation shown in (4) (step S4), these processes are processed by the sampling average module 23 to process 4 oversampling, and the oversampling counter is counted up (step S5).

  Oversampling completion determination (step S6) and 1 symbol data counter are counted up (step S7), and 1 symbol data completion determination (step S8) is executed in the same manner. Thereafter, the maximum value determination module 25 performs processing (step S9) for detecting the maximum value of the square sum of Ich / Qch to synchronize the symbol clock.

  The second embodiment will be described below. Usually, the transmission signal is band-limited to reduce unnecessary radiated power outside the band, and in an actual system, a route roll-off filter is often used as a transmission filter. When the band is limited by the root roll-off filter, the harmonic component is removed and the phase transition becomes gentle. Although the distance from the origin is the amplitude, a portion having a larger amplitude than the symbol point appears by filtering, and the amplitude may be larger than the symbol point particularly when the phase transition is ± 45 degrees. In addition, the amplitude may be larger than the symbol point due to the influence of noise.

  Therefore, if a symbol peak point is detected using only sampling data for one symbol, a false detection may occur. Therefore, the error detection can be further reduced by taking an average of several symbols. Therefore, a second embodiment in which the sampling point closest to the symbol peak point is found using the maximum value determination module 25 by the changeover switch 26 of FIG. 1 and the symbol clock is synchronized every four symbols will be described.

  FIG. 4 is a flowchart for calculating a symbol peak from sampling data for four symbols according to the second embodiment of the present invention. The sampling data is oversampled four times.

  Hereinafter, the flow of processing will be described with reference to FIGS. 1 and 4. The initial setting (step S11) in FIG. 4 initializes a storage area for storing data. Thereafter, the process waits for sampling data (step S12).

  An IF reception signal is input to the circuit portion shown in FIG. An AGC (Auto Gain Control) 1 inputs an IF reception signal variably amplified by gain control to a quadrature demodulator 2 and outputs the in-phase component and the quadrature component via low-pass filters 3 and 4 and A / D converters 5 and 6. Then, the data is input to the demodulator 20 and the sampling data is acquired in the sampling wait (step S12).

  The in-phase component and the quadrature component input to the demodulator 20 in FIG. 1 are delay-detected by the delay detection module 21 by the operation shown in the delay detection (step S13) in FIG. 4, and the Ich / Qch square sum module 22 in FIG. The average value of the amplitude value (Power value) is obtained by the calculation shown in (4) (step S14), and processing is performed by the sampling average module 23 to process 4 oversampling, and the oversampling counter is counted up (step S15).

  The oversampling completion determination (step S16) and the 4-symbol data counter are counted up (step S17), and similarly the 4-symbol data completion determination (step S18) is executed. Then, the process returns to waiting for sampling data (step S12) and is repeatedly executed for 4 symbols. Thereafter, the maximum value determination module 25 performs processing (step S19) for detecting the maximum value of the square knowledge of Ich / Qch to synchronize the symbol clock.

The third embodiment will be described below. It can be seen that the phase transition after the delay detection exists near the orthogonal axis in the vicinity of the middle point between the two symbol peak points, and the value of the square sum of Ich and Qch approaches “0”. Therefore, the difference between the sums of squares of the sampling data (Ich, Qch) after one set of delay detection separated from each other by two sampling points (that is, separated by 1/2 symbol) is obtained, and this difference is the largest. It can be determined that the sampling point is a symbol peak.

  FIG. 5 is a flowchart for calculating a symbol peak by calculating a difference with a ½ symbol shift from 4 symbols of sampling data according to the third embodiment of the present invention. The sampling data is 4 oversampled. Yes. Therefore, the changeover switch 26 in FIG. 1 is used to calculate the difference from the average value of the sampling points separated by ½ symbol by using the ½ symbol deviation determination module 24 to find the sampling point having the largest difference. A third embodiment in which symbol clock synchronization is performed for each symbol will be described.

  Hereinafter, the flow of processing will be described with reference to FIGS. 1 and 5. The initial setting (step S21) in FIG. 5 initializes a storage area for storing data. Thereafter, the process waits for sampling data (step S22).

  An IF reception signal is input to the circuit portion shown in FIG. An AGC (Auto Gain Control) 1 inputs an IF reception signal variably amplified by gain control to a quadrature demodulator 2 and outputs the in-phase component and the quadrature component via low-pass filters 3 and 4 and A / D converters 5 and 6. Then, the data is input to the demodulator 20 and the sampling data is acquired in the waiting for sampling (step S22).

  The in-phase component and the quadrature component input to the demodulator 20 in FIG. 1 are delay-detected by the delay detection module 21 by the operation shown in the delay detection (step S23) in FIG. 5, and the Ich / Qch square sum module 22 in FIG. The average value of the amplitude value (Power value) is obtained by the calculation shown in (4) (step S24), and processing is performed by the sampling average module 23 to process 4 oversampling, and the oversampling counter is counted up (step S25).

  The oversampling completion determination (step S26) and the 4-symbol data counter are counted up (step S27), and similarly the 4-symbol data completion determination (step S28) is executed. Then, the process returns to waiting for sampling data (step S22) and is repeatedly executed for 4 symbols. Thereafter, a difference from the 1/2 symbol shift is obtained by the 1/2 symbol shift determination module 24 from the square sum of Ich / Qch, and a point at which this difference becomes the maximum value is detected (step S29) to synchronize the symbol clock. I take the.

  As described above, by calculating the difference from the average value of sampling points that are 1/2 symbol apart, it is possible to further reduce false detections compared to the second embodiment.

  In one embodiment of the present invention, this operation is performed a plurality of times, symbol peak points are detected, and clock synchronization is performed. In the case of four oversampling, numbers 0 to 3 are assigned to each sampling point, and the calculation result of the sum of squares of the in-phase component and the quadrature component is added for each sampling number, and the average value is calculated. Thereafter, the difference from the point separated by two sampling points is obtained, and the point having the largest value can be determined as the point closest to the symbol peak.

  This operation is performed a plurality of times, and it is determined that the sampling point having the highest number of times determined to be the symbol peak point is the symbol peak point. For example, if an average value of the sum of squares is calculated every four symbols and a symbol peak is detected from the result of performing this operation four times, the symbol peak can be detected at 16 symbols and clock synchronization can be achieved.

  In the embodiment of the present invention, the processing has been described according to the steps, but it goes without saying that processing by an electronic circuit can be suitably implemented in addition to processing by a program. In the embodiment, the embodiment has been described with the changeover switch 26 switched. However, it is also possible to suitably switch the process dynamically depending on the reception status.

It is a block diagram of a symbol timing detection circuit using the symbol timing detection method of one embodiment according to the present invention. FIG. 6 is an exemplary diagram illustrating a π / 4 shift QPSK signal space arrangement according to an embodiment of the present invention. It is a flowchart which calculates a symbol peak from the sampling data for 1 symbol which shows 1st Embodiment by this invention. It is a flowchart which calculates a symbol peak from the sampling data for 4 symbols which shows the 2nd Embodiment by this invention. It is a flowchart which calculates the difference with a 1/2 symbol shift from the sampling data for 4 symbols which shows the 3rd Embodiment by this invention, and calculates a symbol peak. It is a block diagram which shows the prior art example of the demodulation circuit of a (pi) / 4 shift QPSK modulation system. It is a schematic diagram which shows a general frame format. It is an illustration figure which shows the calculation method in the case of calculating the correlation function of a reference | standard PR data pattern and a received data pattern. It is a time chart which shows the time change of the example of transmission power in a transmitter, and the example of reception power in a receiver. It is the illustration figure which showed the demodulation result in the case of finding a reference | standard sampling point, adjusting sampling data finely on a phase plane.

Explanation of symbols

1 AGC, 2 quadrature demodulator, 3 low pass filter, 4 low pass filter, 5 A / D converter, 6 A / D converter, 201 demodulator, 21 delay detection module, 22 I / Qch square sum module, 23 sampling average Module, 24 1/2 symbol module, 25 maximum value determination module, 26 selector switch.

Claims (5)

In a symbol clock synchronization method for a receiver having an orthogonal demodulation process using a π / 4 shift QPSK system and a detection process for obtaining synchronization,
A sampling step of sampling the phase-modulated received signal at a frequency of at least twice the symbol frequency and converting it to a quadrature demodulated signal;
A delay detection step of performing delay detection on the sampled in-phase component and quadrature component signal sequences to detect a phase difference between one symbol;
A sum-of-squares calculation step of calculating a sum of squares of the signal sequence subjected to delay detection;
An averaging step of averaging the calculated square sum signal sequence for each sampling order;
A determination step of determining a sampling point with the maximum value of the averaged signal from the averaged signal sequence is the symbol peak,
With
A symbol clock synchronization method for wireless communication, wherein symbol timing is detected regardless of a pattern of a received signal. In a symbol clock synchronization method for a receiver having an orthogonal demodulation process using a π / 4 shift QPSK system and a detection process for obtaining synchronization,
A sampling step of sampling the phase-modulated received signal at a frequency of at least twice the symbol frequency and converting it to a quadrature demodulated signal;
A delay detection step of performing delay detection on the sampled in-phase component and quadrature component signal sequences to detect a phase difference between one symbol;
A sum-of-squares calculation step of calculating a sum of squares of the signal sequence subjected to delay detection;
An averaging step of averaging the calculated square sum signal sequence for each sampling order;
It obtains a difference between the averaged signal and the 1/2 averaged signal of the symbol apart sample points from the averaged signal sequence, the sampling points where the difference is the maximum value is a symbol peak A determination step for determining;
With
A symbol clock synchronization method for wireless communication, wherein symbol timing is detected regardless of a pattern of a received signal. The radio communication symbol clock synchronization method according to claim 1 or 2,
A symbol clock synchronization method for wireless communication, wherein a symbol timing is detected without processing a received signal pattern by a cross-correlation function. In a symbol clock synchronizer of a receiver having quadrature demodulation means using a π / 4 shift QPSK system and detection means for obtaining synchronization,
Sampling means for sampling the phase-modulated received signal at a frequency of at least twice the symbol frequency and converting it to a quadrature demodulated signal;
Delay detection means for delay-detecting a sampled in-phase component and quadrature component signal sequence and detecting a phase difference between one symbol;
Sum-of-squares computing means for computing the sum of squares of the signal sequence subjected to delay detection;
An averaging means for averaging the calculated square sum signal sequence for each sampling order;
A determining means and the sampling point with the maximum value of the averaged signal from the averaged signal sequence is the symbol peak,
With
A symbol clock synchronizer for wireless communication, characterized by detecting a symbol timing regardless of a pattern of a received signal. In a symbol clock synchronizer of a receiver having quadrature demodulation means using a π / 4 shift QPSK system and detection means for obtaining synchronization,
Sampling means for sampling the phase-modulated received signal at a frequency of at least twice the symbol frequency and converting it to a quadrature demodulated signal;
Delay detection means for performing delay detection on a sampled in-phase component and quadrature component signal sequence;
Sum-of-squares computing means for computing the sum of squares of the signal sequence subjected to delay detection;
An averaging means for averaging the calculated square sum signal sequence for each sampling order;
It obtains a difference between the averaged signal and the 1/2 averaged signal of the symbol apart sample points from the averaged signal sequence, the sampling points where the difference is the maximum value is a symbol peak Determination means for determining;
Equipped with a,
A symbol clock synchronizer for wireless communication, characterized by detecting a symbol timing regardless of a pattern of a received signal .

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