JP4343338B2 - Input buffer circuit - Google Patents

Description

[0001]
BACKGROUND OF THE INVENTION
The present invention relates to an input buffer circuit, and more particularly to an input buffer circuit having a capacitance in an input section.
[0002]
[Prior art]
Conventionally, a buffer circuit that inputs a clock signal or the like and outputs it as a desired waveform is used, and a capacitance is externally connected to an input portion of the circuit. The buffer circuit operates in accordance with the main power signal of the apparatus, but a circuit that operates under current control is also used. The capacitance of such a conventional input buffer circuit is charged or discharged to its operating point potential by current driving the buffer circuit.
[0003]
[Problems to be solved by the invention]
Therefore, for example, in a current-controlled conventional buffer circuit that operates in accordance with the main power-on signal of FIG. 6A, the input portion potential shown in FIG. 6B rises to an operating point at a predetermined DC potential. It takes time to reach. For this reason, as shown in FIG. 6C, there is a problem that the rise time T ′ until the input clock signal is output is delayed.
[0004]
Accordingly, the present invention has been made in view of the above-described problems, and an object of the present invention is to provide an input buffer circuit that can operate quickly by shortening the rise time when the power is turned on.
[0005]
[Means for Solving the Problems]
In order to achieve the above object, the present invention comprises buffer means that operates by being supplied with a predetermined DC potential, and a capacitance connected to an input section of the buffer means, and an input signal applied through the capacitance is supplied to the buffer. in the input buffer circuit for outputting from the device, a charge means for initiating the charging of the capacitance in accordance with the power-on signal for turning on the device, a timer means for counting said predetermined time after the power-on signal is input has elapsed, according the measurement result, for turning on said buffer means a buffer power-on signal after the input portion potential of the buffer means has passed the predetermined time has reached the predetermined DC voltage is outputted to said buffer means An input buffer circuit comprising a buffer control means is provided.
[0006]
Here, the timer means, other and capacitance initiated charging during on of the device is connected to the constant current source via a switch which is opened and closed by the power-on signal, the potential of one end of the other capacitance And a comparison means for outputting a binary signal that is inverted when the potential at one end of the other capacitance becomes the reference potential after the predetermined time has elapsed since the power-on signal was input. The buffer control means performs a logical operation based on the binary signal and the power-on signal, and inputs the power-on signal to the charge means until the predetermined time elapses after the power-on signal is input. A charge control signal for charging the capacitance and the buffer power-on signal can be generated.
[0007]
Further, the charging means is opened and closed by the charging control signal, and another switch whose one end is connected to the input unit and the capacitance between the input of the power-on signal and the elapse of the predetermined time. the current flows from the power supply until the the power-on signal is inputted a predetermined time has elapsed minute, the predetermined charging current to the input unit may include a current setting means supplies.
[0008]
DETAILED DESCRIPTION OF THE INVENTION
Embodiments according to the present invention will be described below in detail with reference to the drawings.
[0009]
FIG. 1 is a block diagram of an embodiment of an input buffer circuit according to the present invention.
[0010]
In FIG. 1, a crystal oscillator (TCXO) 10 generates a clock signal having a predetermined frequency, and its oscillation frequency is temperature compensated. The clock signal reaches the input portion of the input buffer circuit 20 through the series circuit of the resistor R1 and the capacitance C1, and is output as a rectangular wave when the input buffer circuit 20 operates at an operating point of a predetermined DC potential.
[0011]
The buffer activation control circuit 1 performs the characteristic function of the present invention. That is, in summary, when the main power-on signal is input to the analog timer / power control circuit 30 in the buffer activation control circuit 1, the charging current from the charge circuit (CHG) 50 is supplied to the input buffer. Charging of the input part of the circuit 20 is started and charging is performed for a certain time. The analog timer / power control circuit 30 measures the time required for the input section potential to reach the operating point potential of the input buffer circuit 20, and when the necessary time elapses, the input power-on signal is input to the input buffer circuit 20 To start the operation.
[0012]
FIG. 2 is an operation waveform diagram of each part in FIG. Each waveform shown in FIGS. 2A to 2F is an operation waveform of each part denoted by reference signs A to F in FIG. The operation of an embodiment of the input buffer circuit will be described in detail below with reference to FIGS.
[0013]
When the main power-on signal (a) comes in at time t ₀ in FIG. 2, the analog timer / power control circuit 30 simultaneously sends the charge circuit power-on signal (b) to the charge circuit 50. To send. As a result, the charge circuit 50 starts charging the input section of the input buffer circuit 20 and quickly charges it. By this charging operation, the input portion potential reaches the operating point within a fixed time T as shown in (e). While the main power-on signal (a) is at a high level, power is supplied to each part of the device. However, when the signal is at a low level, the power supply to each part of the device is stopped and the device operation is also stopped.
[0014]
The analog timer / power control circuit 30 sends an input power-on signal (c) to the input buffer circuit 20 at time t ₂ delayed by a predetermined time ΔT after the input section potential reaches the operating point. At this time, since the delay time ΔT is set, the input portion potential of the input buffer circuit 20 is set to the operating point potential, and the charge circuit 50 is reliably turned off. A predetermined operation is performed according to the power-on signal, and the clock (f) converted into a rectangular wave can be output.
[0015]
Next, time measurement by the analog timer provided in the analog timer / power control circuit 30 will be described with reference to the block diagram of FIG. 3 and FIG. 4 showing operation waveforms of each part in FIG.
[0016]
Reference numerals A, B, and C in FIG. 3 correspond to those in FIG. 1, and operation waveforms of the corresponding portions are shown in FIGS. 4 (a), (b), and (c), respectively. Also, both waveforms shown in FIGS. 4D and 4E are operation waveforms of both portions denoted by reference symbols D ′ and E ′ in FIG.
[0017]
In FIG. 3, a series circuit of a constant current source 31, a switch 32, and a capacitance C2 is connected to both ends of a power source (not shown), and the capacitance C2 is shunted by a switch 33. The switch 32 is turned on when the main power-on signal arrives, and is turned off in other cases. The switch 33 performs an opening / closing operation opposite to that of the switch 32 in accordance with the main power-on signal. That is, it turns off when the main power-on signal arrives, and turns on in other cases.
[0018]
Thus, when the device is off, one end D ′ of the comparator 34 is grounded and the capacitance C2 is discharged. When the main power-on signal arrives at time t ₀ in FIG. 4, charging of the capacitance C2 by the constant current source 31 is started, and the potential (d) at one end D ′ of the comparator 34 gradually increases. To do. The comparison reference voltage Vref is input to the other end of the comparator 34, and a binary signal (e) corresponding to the comparison result of both voltages is output from the output unit E ′ to the logic circuit 35.
[0019]
This binary signal is obtained by an analog configuration without using a reference clock or the like, and shows the result of measuring the time during which one end D ′ of the comparator 34 rises to a predetermined potential after the main power-on signal arrives.
[0020]
The main power-on signal is input to the logic circuit 35 including the exclusive OR gate together with the binary signal of the comparison measurement result. The logical operation of both signals is performed here, and the edge timing is processed as necessary. The calculated result is output. The charge circuit power-on signal (b) to the charge circuit 50 is obtained, for example, by taking the exclusive OR of the binary signal and the main power-on signal. The input buffer power-on signal to the input buffer circuit 20 is obtained, for example, by delaying a binary signal by ΔT and taking the logical product of the delayed signal and the main power-on signal. For example, a Schmitt trigger can be used for the delay processing.
[0021]
Thus, the timing when the charge circuit power-on signal (b) becomes low is set by comparing the charging voltage of the capacitance C2 with a constant current with a constant comparison reference voltage.
[0022]
The logic circuit 35 is not limited to the above-described configuration, but may be any circuit that can obtain an output signal having the same timing as described above from the binary signal and the main power-on signal.
[0023]
Next, the operation of the charge circuit 50 for rapidly charging the input portion of the input buffer circuit 20 by the charge circuit power-on signal will be described with reference to the circuit diagram of FIG.
[0024]
In FIG. 5, a series circuit of a resistor R2, a switch 51, a switch 52, and a resistor R3 is connected to both ends of a power source (not shown). The switch 51 and the switch 52 are opened and closed by a charge circuit power-on signal, and the common connection point of both switches is connected to the input part of the input buffer circuit 20, that is, the common connection point of the input part and the capacitance C1 (see FIG. 1). ).
[0025]
When a charge circuit power-on signal arrives when the device is turned on, the switch 51 and the switch 52 are closed, and a current flows through the series circuit. This current is determined by the combined impedance of the resistor R2 and the resistor R3 and the input unit, and the amount of the current divided to the input unit is the charging current. After the time T elapses, the switch 51 and the switch 52 are opened to stop charging, and during this time, the input unit is quickly charged to the operating point potential of a predetermined DC potential.
[0026]
The input buffer circuit 20 shown in FIG. 1 is supplied with an input power-on signal after a delay time ΔT has elapsed since the opening of the switch 51 and the switch 52, and thus operates normally and outputs a rectangular clock signal with a shortened rise time. Can do.
[0027]
According to the present embodiment described above, the elapsed time from the main power-on is measured in an analog manner by comparing the charging voltage by the constant current and the reference voltage without requiring a clock or the like, and during this time, the input buffer circuit 20 The input unit is charged to a predetermined potential, and the drive current of the input buffer circuit 20 is increased by turning on the input buffer circuit 20 to which the operating point potential is applied after a predetermined time has elapsed from the measured time. It is possible to shorten the rise time when the apparatus is turned on without necessity. Further, the power-on timing of the input buffer circuit is after the charge circuit 50 is reliably turned off by providing a delay of ΔT.
[0028]
【The invention's effect】
According as the present invention described above, a timer means for counting a charge means for initiating the charging of the capacitance of the buffer means input unit in accordance with the power-on signal, that a predetermined time has elapsed since power on signal is input, And a buffer control unit that turns on the buffer unit after the input unit potential of the buffer unit reaches a predetermined DC potential after a predetermined time has elapsed according to the time measurement result. The rise time is shortened without increasing the current supplied to the circuit, and an input buffer circuit capable of operating at high speed with a low current can be obtained.
[Brief description of the drawings]
FIG. 1 is a block diagram of an embodiment of an input buffer circuit according to the present invention.
FIG. 2 is an operation waveform diagram of each part in FIG. 1 for explaining the operation of the embodiment of the input buffer circuit according to the present invention;
FIG. 3 is a block diagram of a main part of an embodiment of an input buffer circuit according to the present invention.
4 is an operation waveform diagram of each part in FIG. 3 for explaining the operation of the embodiment of the input buffer circuit according to the present invention.
FIG. 5 is a main part circuit diagram of an embodiment of an input buffer circuit according to the present invention;
FIG. 6 is an operation waveform diagram illustrating a problem in an example of a conventional input buffer circuit.
[Explanation of symbols]
1 Buffer Start Control Circuit 10 Crystal Oscillator (TCXO)
20 Input buffer circuit 30 Analog timer / power control circuit 31 Constant current sources 32, 33, 51, 52 Switch 34 Comparator 35 Logic circuit 50 Charge circuit (CHG)
R1, R2, R3 Resistance C1, C2 Capacitance

Claims (3)

In an input buffer circuit comprising a buffer means that operates by being supplied with a predetermined DC potential and a capacitance connected to an input section of the buffer means, and an input signal applied through the capacitance is output from the buffer means.
Charging means for starting charging of the capacitance in accordance with a power-on signal to turn on the device;
A timer means for counting said power-on signal has a predetermined time elapses after the input,
According the measurement result, for turning on said buffer means a buffer power-on signal after the input portion potential of the buffer means has passed the predetermined time has reached the predetermined DC voltage is outputted to said buffer means An input buffer circuit comprising: a buffer control means. In claim 1,
Said timer means, other and capacitance to start charging during on of the device is connected to the constant current source via a switch which is opened and closed by the power-on signal, the one end of the other capacitance potential and a reference potential Comparing means for outputting a binary signal that reverses when the potential of one end of the other capacitance becomes the reference potential after the predetermined time has elapsed since the power-on signal was input ,
The buffer control unit performs a logical operation based on the binary signal and the power-on signal, and applies the capacitance to the charging unit until the predetermined time elapses after the power-on signal is input. input buffer circuit and generates a charge control signal and the buffer power-on signal for charging. In claim 2,
The charging means is
Another switch that is opened and closed by the charge control signal and connected at one end to the input unit and the capacitance until the predetermined time elapses after the power-on signal is input ;
Current setting means for shunting a current from a power source until the predetermined time elapses after the power-on signal is input, and for supplying a predetermined charging current to the input unit. Buffer circuit.

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