JP4345301B2 - Motion vector detection circuit - Google Patents

Description

【０１９０】
そして、参照ブロックを構成する＃１〜＃Ｍの全画素データに対応した計数値テーブルの各計数値を度数とし、この度数を探索範囲の画素位置毎に足し込んで、探索範囲の画素位置に対応して度数の累積値が配されたヒストグラムテーブルを生成する。そして、このヒストグラムテーブルの度数の極大値または極小値に基づいて、参照ブロックの動きベクトルを検出する。
【０１９１】
ここで、マッチングの度合いが高いときに配する計数値が正の値であるときは極大値であり、一方その計数値が負の値であるときは極小値である。このヒストグラムテーブルにおける度数の極大値または極小値の位置は、参照ブロック内に存在する動きに対応した動きベクトルを表すものとなる。
【０１９２】
この例の動きベクトル検出方法によれば、マッチングの度合いが高いときのみ計数値として０以外の値を配して計数値テーブルを生成するものであって、ヒストグラムテーブルはマッチング度合いが高いもののみによって生成されることとなり、その度数の分布はより先鋭化されたものとなる。そのため、参照ブロック内に動きの異なるものが複数混在する場合には、ヒストグラムテーブルに複数個の極大値または極小値が明瞭に分離して示され易くなる。したがって、参照ブロックの一個または複数個の動きベクトルを正しく検出できる。
【０１９３】
参照ブロック内に異なる２つの動きがある場合について、従来のブロックマッチング法における相関値テーブルおよびこの例の動きベクトル検出方法におけるヒスとグラムテーブルの一例を、それぞれ図２７および図２８に示す。図２７に示す相関値テーブルは、この発明に係るヒストグラムテーブルとの比較を容易にするため、相関値の大小関係を入れ換えて表示している。すなわち、いずれにおいても、最大値あるいは極大値の位置が動きベクトルを表す。
【０１９４】
図２７に示す相関値テーブルに基づいて動きベクトルを検出する従来のブロックマッチング法では、より支配的な方の動きを示す動きベクトルは検出されるが、他方の動きを示す動きは埋もれてしまって、その動きを示す動きベクトルの検出は困難である。これに対して、図２８に示すヒストグラムテーブルに基づいて動きベクトルを検出するこの例の動きベクトル検出方法では、ヒストグラムテーブルに明瞭に分離して２個の極大値が現れており、２つの動きをそれぞれ示す２個の動きベクトルを容易に検出できる。
【０１９５】
なお、上述では、マッチングの度合いを上位３位とそれ以外との４種類に分類したが、これに限る必要はなく、３種類以下あるいは５種類以上であっても構わない。また、上述では、各計数値をマッチングの度合いに応じて小さい方から「０」，「＋１」，「＋２」，「＋３」としたが、これについてもこの計数値の用い方に限るものではなく、例えば○〜×については全て「＋１」とし、それ以外を「０」としてもよい。ただし、マッチングの度合いがその閾値より高いときに配する計数値を一定値とするのではなく、マッチングの度合いが高い程、絶対値の大きな値とすることで、ヒストグラムテーブルの度数の分布を一層先鋭化できる利益がある。
【０１９６】
ところで、参照ブロックを構成する画素データの周囲におけるアクティビティが高い場合、すなわちその画素データとその周囲にある画素データとの値の違いが大きい場合（信号波形としてみた場合に波形振幅が大きい場合）、本来正しいとすべき動きベクトルの位置においてもマッチングの度合いが低くなってしまう。これは、一般的には１画素よりも小さな動き量の成分があり、そのため周囲画素データとの値の違いが大きいほど、マッチングすべき位置においても画素データ値間の差分が大きくなってしまうことによる。
【０１９７】
この場合の対処方法として、周囲におけるアクティビティが大きな参照ブロックに対応した計数値テーブルの計数値に関しては、その計数値の絶対値が大きくなるように設定することが有効である。
【０１９８】
具体的には、まず、参照ブロックを構成する各画素データ毎に、アクティビティＡをそれぞれ求める。例えば、図２９に示すように、アクティビティＡを求める対象の画素データをａとし、その周囲の４個の画素データをｂ〜ｄとし、（１）式により、アクティビティＡを算出する。
Ａ＝|a-b|+|a-c|+|a-d|+|a-e| ・・・（１）
【０１９９】
そして、参照ブロックを構成する各画素データ毎に、アクティビティＡの最大アクティビティＡ_maxに対する割合が高い程大きな値を補正係数ｋとして得るようにする。表２は、補正係数ｋの設定例を示している。この表２において、Ａ_norは、アクティビティＡを最大アクティビティＡ_maxで割って正規化したアクティビティであって、アクティビティＡの最大アクティビティＡ_maxに対する割合を示すものである。
【０２００】
【表２】

【０２０１】
そして、参照ブロックを構成する各画素データに対応した計数値テーブルの計数値に、それぞれこの各画素データに対応した補正係数ｋを掛けて補正する（表１の「補正した計数値」の項参照）。
【０２０２】
なお、上述したように、補正係数ｋを求め、この補正係数ｋを計数値に掛けて補正する代わりに、マッチングの度合いに応じて計数値を生成する際に用いられる閾値を、アクティビティが大きい程低くなるように変更してもよい。
【０２０３】
例えば、上述の表１の例では、差分絶対値が閾値３より小さいときは計数値を０以外の値（＋３〜＋１）とし、一方差分絶対値が閾値３以上のときは計数値を０としたが、この閾値をアクティビティが大きい程大きくなるように変更する。この場合、差分絶対値の閾値を大きくするということは、マッチングの度合いの閾値を低くすることを意味している。
【０２０４】
このように、閾値を変更する場合にあっても、上述した計数値を補正係数ｋで補正する場合と同様に、周囲におけるアクティビティが大きな参照ブロックの画素データに対応した計数値テーブルの計数値に関しては、その絶対値が大きくなる。これにより、アクティビティによるマッチングの度合いの変化による不具合を軽減できる。
【０２０５】
上述したように、この例に係る動きベクトル検出方法では、ヒストグラムテーブルに基づいて、参照ブロックの１個または複数個の動きベクトルを検出できる。なお、このように検出された動きベクトルに基づいて、さらに参照ブロックを構成する各画素データの動きベクトルを特定することができる。
【０２０６】
その場合、参照ブロックを構成する画素データと、この画素データの画素位置を基準として上述したように検出された動きベクトルに対応した探索フレームの画素位置の画素データとの間の相関情報、例えば差分絶対値あるいは差分二乗値等を求め、最も相関が高くなる場合の動きベクトルを、その参照ブロックを構成する画素データの動きベクトルとする。
【０２０７】
上述したように、参照ブロックの動きベクトルを正しく検出できることから、その動きベクトルに基づいて特定される各画素データの動きベクトルも精度の高いものとなる。なお、このように特定される参照ブロックを構成する各画素データの動きベクトルから孤立した動きベクトルを除去することで、この各画素データの動きベクトルの精度をさらに高めることができる。
【０２０８】
ここで、孤立した動きベクトルとは、ある画素データの動きベクトルがその周囲の画素データの動きベクトルと異なっている場合のそのある画素データの動きベクトルを意味している。そして、孤立した動きベクトルの除去とは、そのある画素データの動きベクトルをその周囲の画素データの動きベクトルに置き換えることを意味している。
【０２０９】
図３０は、上述した他の例としての動きベクトル検出回路２００の構成を示している。この動きベクトル検出回路２００においても、図３に示す動きベクトル検出回路１１１と同様に、図２に示すように、探索フレームに対して参照フレームは過去のフレームであり、入力フレームが探索フレームである。
【０２１０】
この動きベクトル検出回路２００は、回路全体の動作を制御するシステムコントローラ２０１と、探索フレームとしての入力フレームの画像データＤｉが入力される入力端子２０２と、この画像データＤｉを、次フレームの参照フレームの画像データとして蓄積する参照フレームメモリ２０３とを有している。フレームメモリ２０３の書き込み、読み出し等の動作は、システムコントローラ２０１によって制御される。
【０２１１】
また、動きベクトル検出回路２００は、マッチング演算としての差分絶対値演算を行う差分絶対値演算器２０４_-1〜２０４_-Nを有している。複数の演算器２０４_-1〜２０４_-Nは、入力端子２０２に入力される画像データＤｉを構成する画素データを探索フレームの画素データＤｃとして共通に入力すると共に、この画素データＤｃを探索範囲に含む参照フレームの所定の参照ブロック（同一タイミングでは最大２個）の画素データＤｒ_-1〜Ｄｒ_-Nをそれぞれ入力し、画素データＤｃと画素データＤｒ_-1〜Ｄｒ_-Nとの差分絶対値を演算するものである。
【０２１２】
この場合、図４に示すように、探索フレーム内の入力画素とマッチング演算をするべき参照フレーム内の参照画素は、その探索範囲内に入力画素が位置する複数の参照画素である。その複数の参照画素の位置する範囲は、ある参照画素の索範囲と表裏一体の関係にあり、入力画素を仮に参照画素と見なした場合の探索範囲を左右および上下で反転したものとなる。
【０２１３】
従って、これらの複数の参照画素は、多くの場合は複数の参照ブロックにわたって位置し、また１個の参照ブロックにおける画素数も１個から全てと一定ではない。また、これら参照ブロックの組み合わせおよび１個の参照ブロックにおける画素の組み合わせは、入力画素の位置によっても異なる。
【０２１４】
また、図３０に戻って、動きベクトル検出回路２００は、複数の演算器２０４_-1〜２０４_-Nで演算されて得られた複数の差分絶対値のそれぞれに対応して、計数値を生成する計数値生成部２０５を有している。この計数値生成部２０５は、計数値として、差分絶対値がその閾値より小さいときは、マッチングの度合いがその閾値より高いとして０以外の所定値を生成し、一方差分絶対値がその閾値以上のときは、マッチングの度合いがその閾値以下であるとして０を生成する。例えば、計数値生成部２０５は、上述した表１に示すように、差分絶対値が０，１，２のときは、それぞれ計数値として「＋３」，「＋２」，「＋１」を生成し、一方その差分絶対値が３以上であるときは計数値として「０」を生成する。この場合、閾値は３である。
【０２１５】
また、動きベクトル検出回路２００は、複数の演算器２０４_-1〜２０４_-Nにそれぞれ対応した記憶領域２０６_-1〜２０６_-Nを有する、計数値テーブル生成用の記憶手段としての半導体メモリ２０６を有している。半導体メモリ２０６の書き込み、読み出しの動作は、システムコントローラ２０１によって制御される。
【０２１６】
システムコントローラ２０１は、複数の演算器２０４_-1〜２０４_-Nで得られた差分絶対値にそれぞれ対応して計数値生成部２０５で生成された計数値を、その計数値に係る演算器および参照ブロックの画素位置に対応した半導体メモリ２０６の計数値記憶領域に書き込み、この半導体メモリ２０６に、参照ブロックを構成する各画素データに対応した計数値テーブルが得られるように制御する。ここで、計数値テーブルは、探索範囲の各画素位置に対応して計数値が配されたものである。
【０２１７】
図３１に示すように、この動きベクトル検出回路２００において、参照ブロックの大きさは８×８画素、探索範囲は（−３〜＋４）×（−３〜＋４）画素とされる。参照ブロックの探索範囲には、（３＋４＋１）×（３＋４＋１）＝６４個の候補ブロックが存在する。そのため、Ｎ＝６４とされる。つまり、複数の演算器２０４_-1〜２０４_-N、半導体メモリ２０６の複数の記憶領域２０６_-1〜２０６_-Nは、それぞれ６４個である。
【０２１８】
複数の演算器２０４_-1〜２０４_-Nは、各参照ブロックについて、それぞれ１個の候補ブロックに対応した差分絶対値を求める演算を担当する。また、半導体メモリ２０６の複数の記憶領域２０６_-1〜２０６_-Nは、それぞれ参照フレームの横一行の参照ブロック数に対応した個数のブロック記憶領域を有している。さらに、各ブロック記憶領域は、参照ブロックを構成する画素データの個数分の計数値記憶領域を有している。
【０２１９】
なおここで、入力端子２０２に入力される画像データＤｉはプログレッシブ方式によるものとする。入力端子２０２に入力される画像データＤｉは各ラインの画素データが連続したものとなっている。
【０２２０】
図３１に示すように、探索範囲は（−３〜＋４）×（−３〜＋４）画素であり、また参照ブロックの大きさは８×８画素である。そのため、ある参照ブロックに対する探索範囲の最も上の入力画素が含まれるラインを１ライン目とすると、この探索範囲の最も下の入力画素が含まれるラインは１５ライン目となる。したがって、ある参照ブロックを構成する各画素データに対応した計数値テーブルを得るためには、１５ラインの画素データが必要となる。なお、図３１には、１個の参照ブロックのみを示しているが、上述の１５ラインの画素データに基づいて、横一行分の全参照ブロックについて、それを構成する各画素データに対応した計数値テーブルを得ることができる。
【０２２１】
また、動きベクトル検出回路２００は、参照ブロックを構成する各画素データ毎に周囲におけるアクティビティＡを求め、この各画素データ毎にアクティビティＡの最大アクティビティＡ_maxに対する割合が高い程大きな値を補正係数ｋとして得る補正係数取得部２０７を有している。
【０２２２】
補正係数取得部２０７は、例えば以下のようにして、参照ブロックを構成する各画素データにそれぞれ対応した補正係数ｋを取得する。まず、例えば図２９に示すように、アクティビティＡを求める対象の画素データをａとし、その周囲の４個の画素データをｂ〜ｄとし、上述した（１）式により、参照ブロックを構成する各画素データ毎に、アクティビティＡを求める。次に、参照ブロックを構成する各画素データ毎に、アクティビティＡを最大アクティビティＡ_maxで割って正規化したアクティビティＡ_norを求め、例えば上述した表２のように補正係数ｋを設定する。
【０２２３】
また、動きベクトル検出回路２００は、上述した半導体メモリ２０６より読み出され、後述する複数の加算器２０９_-1〜２０９_-Nに供給される、参照ブロックを構成する各画素データに対応した計数値テーブルの計数値に、それぞれ補正係数取得部２０７で取得された各画素データに対応した補正係数ｋを掛けて補正する計数値補正部２０８を有している。
【０２２４】
また、動きベクトル検出回路２００は、複数の加算器２０９_-1〜２０９_-Nと、複数の記憶領域２１０_-1〜２１０_-Nを有するヒストグラムテーブル生成用の記憶手段としての半導体メモリ２１０とを有している。複数の加算器２０９_-1〜２０９_-Nは、半導体メモリ２０６より読み出され、計数値補正部２０８で補正された、参照ブロックを構成する所定の画素データに対応した計数値テーブルの計数値をそれぞれ度数として入力すると共に、半導体メモリ２１０の複数の記憶領域２１０_-1〜２１０_-Nに記憶されていた記憶データのそれぞれを入力し、度数を記憶データに足し込むものである。
【０２２５】
このように、複数の加算器２０９_-1〜２０９_-Nで得られた足し込みデータのそれぞれは、半導体メモリ２１０の複数の記憶領域２１０_-1〜２１０_-Nに記憶データとして書き戻される。半導体メモリ２１０の書き込み、読み出しの動作は、システムコントローラ２０１によって制御される。
【０２２６】
システムコントローラ２０１は、半導体メモリ２０６からの計数値テーブルの計数値の読み出し、複数の加算器２０９_-1〜２０９_-Nにおける足し込みの演算、半導体メモリ２１０の複数の記憶領域２１０_-1〜２１０_-Nへの足し込みデータの書き戻しを、参照ブロックを構成する各画素データに対応した複数の計数値テーブルの個数分だけ繰り返し、半導体メモリ２１０に、探索範囲の各画素位置に対応して度数の累積値が配されたヒストグラムテーブルが得られるように制御する。
【０２２７】
また、動きベクトル検出回路２００は、参照ブロック毎に、半導体メモリ２１０に得られたヒストグラムテーブルにおける極大値に基づいて、動きベクトルを検出する動きベクトル検出部２１１を有している。ヒストグラムテーブルにおける度数の極大値は、参照ブロック内に存在する動きに対応した動きベクトルを表している。そのため、参照ブロック内に動きの異なるものが複数混在する場合にはヒストグラムテーブルに複数個の極大値が示されることとなり、動きベクトル検出部２１１では複数個の動きベクトルが検出される。
【０２２８】
また、動きベクトル検出回路２００は、動きベクトル検出部２１１で検出された、参照ブロックの一個または複数個の動きベクトルＭＶ₁〜ＭＶ_n（ｎは１以上の整数）に基づいて、その参照ブロックを構成する各画素データの動きベクトルｍｖを特定する動きベクトル特定部２１２と、この動きベクトル特定部２１２で特定された各画素データの動きベクトルｍｖを出力する出力端子２１３とを有している。
【０２２９】
動きベクトル特定部２１２は、参照ブロックを構成する画素データとこの画素データの画素位置を基準として、動きベクトル検出部２１１で検出された各動きベクトルＭＶ₁〜ＭＶ_nに対応した探索フレームの画素位置の画素データとの間の相関情報、例えば差分絶対値あるいは差分二乗値を求め、最も相関が高くなる場合の動きベクトルをこの画素データの動きベクトルｍｖとする。
【０２３０】
図３２は、動きベクトル特定部２１２の具体的な構成を示している。
この動きベクトル特定部２１２は、全体の動作を制御するためのコントローラ２２１を有している。このコントローラ２２１には、入力端子２０２（図３０参照）に入力される入力フレーム（探索フレーム）の画像データＤｉが供給され、この画像データＤｉは探索画素用のメモリ２２２に蓄積される。また、このコントローラ２２１には、動きベクトル検出部２１１（図３０参照）で検出される動きベクトルＭＶ₁〜ＭＶ_nが供給される。
【０２３１】
また、動きベクトル特定部２１２は、相関演算部２２３_-1〜２２３_-nを有している。この相関演算部２２３_-1〜２２３_-nには、参照ブロックを構成する画素データ（参照画素データ）が、コントローラ２２１の制御によって、参照フレームメモリ２０３から読み出されて共通に供給される。また、この相関演算部２２３_-1〜２２３_-nには、それぞれ、その参照ブロックを構成する画素データの画素位置を基準として動きベクトルＭＶ₁〜ＭＶ_nに対応した探索フレームの画素位置の画素データ（探索画素データ）が、コントローラ２２１の制御によって、メモリ２２２から読み出されて供給される。相関演算部２２３_-1〜２２３_-nは、それぞれ、参照画素データと探索画素データとの間の相関情報、例えば差分絶対値あるいは差分二乗値等を求める。
【０２３２】
また、動きベクトル特定部２１２は、動きベクトル仮特定部２２４を有している。この仮特定部２２４には、動きベクトル検出部２１１で検出される動きベクトルＭＶ₁〜ＭＶ_nが供給される。また、この仮特定部２２４には、相関演算部２２３_-1〜２２３_-nで求められた相関情報が供給される。この仮特定部２２４は、相関演算部２２３_-1〜２２３_-nで求められた相関情報に基づいて、最も相関が高くなる場合の動きベクトルを、上述の参照画素データの動きベクトルｍｖとして特定する。
【０２３３】
なお、この場合、どの動きベクトルＭＶ₁〜ＭＶ_nについても相関が充分でない場合には、動きベクトルｍｖを出力する代わりに、動きが不定である旨の情報を出力する。この動きが不定である参照画素データとしては、ノイズが重畳した画素データあるいは動きのない部分の画素データが考えられる。
【０２３４】
また、動きベクトル特定部２１２は、仮特定部２２４で特定された参照ブロックを構成する各画素データの動きベクトルｍｖから孤立した動きベクトルを除去する等の補正処理を行う動きベクトル補正部２２５を有している。ここで、孤立した動きベクトルとは、上述したように、ある画素データの動きベクトルがその周囲の画素データの動きベクトルと異なっている場合のそのある画素データの動きベクトルを意味している。そして、孤立した動きベクトルの除去とは、そのある画素データの動きベクトルをその周囲の画素データの動きベクトルに置き換えることを意味している。
【０２３５】
図３２に示す動きベクトル特定部２１２の動作を説明する。
動きベクトル検出部２１１で検出された、所定の参照ブロックの動きベクトルＭＶ₁〜ＭＶ_nが、コントローラ２２１および動きベクトル仮特定部２２４に供給される。
【０２３６】
相関演算部２２３_-1〜２２３_-nには、上述した所定の参照ブロックを構成する画素データ（参照画素データ）が参照フレームメモリ２０３から読み出されて共通に供給される。また、この相関演算部２２３_-1〜２２３_-nには、それぞれその参照ブロックを構成する画素データの画素位置を基準として動きベクトルＭＶ₁〜ＭＶ_nに対応した探索フレームの画素位置の画素データ（探索画素データ）がメモリ２２２から読み出されて供給される。そして、相関演算部２２３_-1〜２２３_-nでは、それぞれ、参照画素データと探索画素データとの間の相関情報が求められる。
【０２３７】
相関演算部２２３_-1〜２２３_-nで求められた相関情報は仮特定部２２４に供給される。この仮特定部２２４では、相関情報に基づいて、最も相関が高くなる場合の動きベクトルが、参照画素データの動きベクトルｍｖとして特定される。この場合、どの動きベクトルＭＶ₁〜ＭＶ_nについても相関が充分でない場合には、動きベクトルｍｖの代わりに、動きが不定である旨の情報が出力される。
【０２３８】
以上の動作が、参照ブロックを構成する各画素データの全てに対して行われることで、この各画素データの動きベクトルｍｖが特定される。このように仮特定部２２４で特定された参照ブロックを構成する各画素データの動きベクトルＭＶ（動き不定情報も含む）は、動きベクトル補正部２２５で孤立した動きベクトルの除去（孤立点除去）等の補正処理が行われた後、順次あるいは同時に出力される。
【０２３９】
図３２に示す動きベクトル特定部２１２では、動きベクトルｍｖを１画素データ分ずつ得るものであるが、相関演算部２２３_-1〜２２３_-nおよび動きベクトル仮特定部２２４の組を複数組備えて、動きベクトルｍｖを複数画素データ分並行して得るようにしてもよい。これにより、例えば、参照ブロックを構成する全ての画素データ分を並行して得ることができる。
【０２４０】
なお、図３０に示す動きベクトル検出回路２００において、システムコントローラ２０１、計数値生成部２０５、半導体メモリ２０６、加算器２０９_-1〜２０９_-N、２１０・・・半導体メモリ、動きベクトル検出部２１１は、動きベクトル検出処理部を構成している。
【０２４１】
図３０に示す動きベクトル検出回路２００の動作を説明する。
入力端子２０２に入力される画像データＤｉを構成する画素データは、探索フレーム（入力フレーム）の画素データＤｃとして、複数の差分絶対値演算器２０４_-1〜２０４_-Nに共通に入力される。また、この画像データＤｉは、フレームメモリ２０３に供給され、次フレームで使用する参照フレームの画像データとして蓄積される。
【０２４２】
また、複数の演算器２０４_-1〜２０４_-Nには、フレームメモリ２０３から、画素データＤｃを探索範囲に含む、参照フレームの所定の参照ブロックの画素データＤｒ_-1〜Ｄｒ_-Nがそれぞれ入力される。そして、複数の演算器２０４_-1〜２０４_-Nでは、画素データＤｃと画素データＤｒ_-1〜Ｄｒ_-Nとの差分絶対値がそれぞれ演算される。この場合、複数の演算器２０４_-1〜２０４_-Nでは、各参照ブロックについて、それぞれ１個の候補ブロックに対応した差分絶対値を求める演算が行われる。
【０２４３】
複数の演算器２０４_-1〜２０４_-Nで得られた差分絶対値はそれぞれ計数値生成部２０５に供給される。計数値生成部２０５では、差分絶対値のそれぞれに対応して、差分絶対値がその閾値より小さいときは０以外の所定値を生成し、一方差分絶対値がその閾値以上のときは０を生成する（表１参照）。
【０２４４】
複数の演算器２０４_-1〜２０４_-Nで得られた差分絶対値に対応して計数値生成部２０５で生成された計数値は、それぞれ計数値テーブル生成用の半導体メモリ２０６の記憶領域２０６_-1〜２０６_-Nに書き込みデータとして供給される。
【０２４５】
上述したように、各記憶領域２０６_-1〜２０６_-Nには、それぞれ参照フレームの横一行の参照ブロック数に対応した個数のブロック記憶領域を有している。さらに、各ブロック記憶領域には、参照ブロックを構成する画素データの個数分の計数値記憶領域を有している。
【０２４６】
複数の演算器２０４_-1〜２０４_-Nで得られた差分絶対値にそれぞれ対応して計数値生成部２０５で生成された計数値は、その計数値に係る演算器および参照ブロックの画素位置に対応した、半導体メモリ２０６の記憶領域に書き込まれる。これにより、半導体メモリ２０６の各ブロック領域に、参照ブロックを構成する各画素データに対応した、探索範囲の各画素位置に対応して計数値が配された計数値テーブルが得られる。
【０２４７】
補正係数取得部２０７では、参照ブロックを構成する各画素データ毎に周囲におけるアクティビティＡが求められ、そしてこの各画素データ毎にアクティビティＡの最大アクティビティＡ_maxに対する割合が高い程大きな値が補正係数ｋとして取得される（図２９、表２参照）。
【０２４８】
半導体メモリ２０６に得られる参照ブロックを構成する各画素データに対応した計数値テーブルの計数値（Ｎ個）は順次読み出され、計数値補正部２０８を介して、複数の加算器２０９_-1〜２０９_-Nに供給される。計数値補正部２０８では、参照ブロックを構成する各画素データに対応した計数値テーブルの計数値に、それぞれ補正係数取得部２０７で取得された各画素データに対応した補正係数ｋが掛算されて補正が行われる。
【０２４９】
複数の加算器２０９_-1〜２０９_-Nには、半導体メモリ２０６より読み出され、計数値補正部２０８で補正された、参照ブロックを構成する所定の画素データに対応した計数値テーブルの計数値がそれぞれ度数として入力され、また半導体メモリ２１０の複数の記憶領域２１０_-1〜２１０_-Nに記憶されていた記憶データのそれぞれが入力される。
【０２５０】
そして、複数の加算器２０９_-1〜２０９_-Nでは、度数が記憶データに足し込まれる。複数の加算器２０９_-1〜２０９_-Nで得られた足し込みデータのそれぞれは、半導体メモリ２１０の複数の記憶領域２１０_-1〜２１０_-Nに記憶データとして書き戻される。
【０２５１】
半導体メモリ２０６からの計数値テーブルの計数値の読み出し、複数の加算器２０９_-1〜２０９_-Nにおける足し込みの演算、半導体メモリ２１０の複数の記憶領域２１０_-1〜２１０_-Nへの足し込みデータの書き戻しは、参照ブロックを構成する各画素データに対応した複数の計数値テーブルの個数分だけ繰り返し行われる。これにより、半導体メモリ２１０に、探索範囲の各画素位置に対応して度数の累積値が配された、当該参照ブロックに対応したヒストグラムテーブルが得られる。
【０２５２】
動きベクトル検出部２１１では、半導体メモリ２１０に得られる各参照ブロックに対応したヒストグラムにおける極大値に基づいて、各参照ブロックの動きベクトルＭＶ₁〜ＭＶ_nが検出される。上述したように、ヒストグラムテーブルにおける度数の極大値は、参照ブロック内に存在する動きに対応した動きベクトルを表している。そのため、参照ブロック内に動きの異なるものが複数混在する場合にはヒストグラムテーブルに複数個の極大値が示され、従って動きベクトル検出部２１１では複数個の動きベクトルが検出される。
【０２５３】
このように動きベクトル検出部２１１で検出される、参照ブロックの動きベクトルＭＶ₁〜ＭＶ_nは動きベクトル特定部２１２に供給される。この動きベクトル特定部２１２では、動きベクトルＭＶ₁〜ＭＶ_nに基づいて、その参照ブロックを構成する各画素データの動きベクトルｍｖが特定される。そして、この各画素データの動きベクトルｍｖは出力端子２１３に出力される。
【０２５４】
なお、上述したように、１５ラインの画素データに基づいて、横一行分の全参照ブロックについて、それを構成する各画素データに対応した計数値テーブルを得ることができる。この場合、この１５ラインの画素データの後半側のラインの画素データは参照フレームの次の横一行分の参照ブロックについての演算処理にも使用される。そのため、その後半側のラインの画素データの入力時には、次の横一行分の参照ブロックについての演算処理も並行して行う必要がある。したがって、実際には、図３０に示す動きベクトル検出回路２００における、差分絶対値演算器２０４_-1〜２０４_-N、計数値生成部２０５、半導体メモリ２０６、計数値補正部２０８、加算器２０９_-1〜２０９_-N、半導体メモリ２１０の部分は、少なくとも２系統設けられることとなる。
【０２５５】
次に、差分絶対値演算器２０４_-1〜２０４_-Nに関してさらに説明する。図３３Ａは、入力画素と演算器２０４_-1〜２０４_-N（（０，０）〜（７，７））の演算対称範囲の配置を示している。図３３Ｂは、参照ブロックを構成する８×８個の画素データ（ａ，ａ）〜（ｈ，ｈ）を示している。
【０２５６】
入力画素と差分絶対値演算をすべき参照ブロックの画素データの位置する範囲（演算対象範囲）は、各演算器（０，０）〜（７，７）が担当する範囲に分けられる。各演算器（０，０）〜（７，７）の担当範囲は１画素である。
【０２５７】
図３４に示すように、入力画素が参照ブロックの探索範囲の１ライン目にあり、その演算対象範囲が参照ブロックの画素データ（ａ，ａ）にかかるとき、当該参照ブロックを構成する８×８個の画素データに対応する計数値テーブルを得るための演算が始まる。このとき、演算器（７，７）にはフレームメモリ２０３（図３０に図示）から画素データ（ａ，ａ）が入力される。そして、この演算器（７，７）で、入力画素と画素データ（ａ，ａ）との差分絶対値が求められる。
【０２５８】
次に、図３５に示すように、１画素期間後には、入力画素が１画素だけ右のものに移り、入力画素の演算対象範囲が参照ブロックの画素データ（ｂ，ａ）にかかる。このとき、演算器（７，７）にはフレームメモリ２０３から画素データ（ｂ，ａ）が入力される。そして、この演算器（７，７）で、入力画素と画素データ（ｂ，ａ）と差分絶対値が求められる。このとき並行して、演算器（６，７）にはフレームメモリ２０３から画素データ（ａ，ａ）が入力される。そして、この演算器（６，７）で、入力画素と画素データ（ａ，ａ）との差分絶対値が求められる。
【０２５９】
以下、１ライン目については、入力画素が右隣のものに順次移っていき、担当範囲に参照ブロックの画素データを含む演算器では、それぞれ入力画素と参照ブロックの画素データとの演算が並行して行われる。
【０２６０】
図３６は、７画素期間後の状態を示している。この状態では、入力画素が７画素だけ右のものに移り、入力画素の演算対象範囲が参照ブロックの画素データ（ｈ，ａ）までかかる。このとき、演算器（７，７）〜（０，７）には、それぞれフレームメモリ２０３から画素データ（ｈ，ａ）〜（ａ，ａ）が入力される。そして、この演算器（７，７）〜（０，７）で、それぞれ入力画素と画素データ（ｈ，ａ）〜（ａ，ａ）との差分絶対値が求められる。
【０２６１】
また、図３７に示すように、入力画素が参照ブロックに対する探索範囲の２ライン目にあり、その演算対象範囲が参照ブロックの画素データ（ａ，ａ），（ａ，ｂ）にかかるとき、演算器（７，７）にはフレームメモリ２０３から画素データ（ａ，ｂ）が入力される。そして、この演算器（７，７）で、入力画素と画素データ（ａ，ｂ）との差分絶対値が求められる。このとき並行して、演算器（７，６）にはフレームメモリ２０３から画素データ（ａ，ａ）が入力される。そして、この演算器（７，６）で、入力画素と画素データ（ａ，ａ）との差分絶対値が求められる。
【０２６２】
以下、２ライン目については、入力画素が右隣のものに順次移っていき、担当範囲に参照ブロックの画素データを含む演算器では、それぞれ入力画素と参照ブロックの画素データとの演算が並行して行われる。
【０２６３】
以下の３ライン目〜１５ライン目についても同様であり、入力画素が右隣のものに順次移っていき、担当範囲に参照ブロックの画素データを含む演算器では、それぞれ入力画素と参照ブロックの画素データとの演算が並行して行われる。
【０２６４】
図３８は、入力画素が参照ブロックに対する探索範囲の８ライン目にあり、その演算対象範囲が参照ブロックの画素データ（ａ，ａ）〜（ａ，ｈ）までの８個の画素データにかかった状態を示している。この状態では、演算器（７，７）〜（７，０）には、フレームメモリ２０３から画素データ（ａ，ｈ）〜（ａ，ａ）が入力される。そして、この演算器（７，７）〜（７，０）で、入力画素と画素データ（ａ，ｈ）〜（ａ，ａ）との差分絶対値が求められる。
【０２６５】
図３９は、入力画素が参照ブロックに対する探索範囲の１５ライン目にあり、その演算対象範囲が参照ブロックの左下の画素データ（ａ，ｈ）にかかっている状態を示している。この状態では、演算器（７，０）には、フレームメモリ２０３から画素データ（ａ，ｈ）が入力される。そして、この演算器（７，０）で、入力画素と画素データ（ａ，ｈ）との差分絶対値が求められる。
【０２６６】
図４０は、上述した各演算器２０４_-1〜２０４_-N（（０，０）〜（７，７））における各ラインの差分絶対値演算の過程を示している。この図４０において、１〜６４の数字はそれぞれ入力画素と参照ブロックの画素データ（ａ，ａ）〜（ｈ，ｈ）との演算を示している。
【０２６７】
各演算器（０，０）〜（７，７）では、ある参照ブロックに関連して、それぞれ、入力画素データと参照ブロックを構成する６４個の画素データ（ａ，ａ）〜（ｈ，ｈ）との差分絶対値演算が行われる。つまり、各演算器（０，０）〜（７，７）では、それぞれ、ある参照ブロックとその参照ブロックに対する探索範囲に存在する１個の候補ブロックとの間の、対応する画素データ同士による６４個の差分絶対値演算が行われる。図４１は、一例として、演算器（７，７）における演算過程を示している。
【０２６８】
図４２は、動きベクトル（１個の参照画素に対する探索範囲の座標）を示している。参照ブロックの探索範囲には、動きベクトル（ｘ，ｙ）のそれぞれに対応した６４個の候補ブロックが存在する。そして、参照ブロックを構成する各画素データに対応した計数値テーブルは、それぞれ、動きベクトル（ｘ，ｙ）のそれぞれに対応した６４個の計数値からなっている。
【０２６９】
図４３は、半導体メモリ２０６のある１個の参照ブロックに対応した領域における、その参照ブロックを構成する各画素データ（(a,a)〜(h,h)）に対応したそれぞれ計数値テーブルにおける６４個の計数値（それぞれ動きベクトル（+4,+4）〜（-3,-3）に対応している）が、どの計数値記憶領域（アドレス）に記録されるかを示している。
【０２７０】
またこの図４３は、各演算器（０，０）〜（７，７）のそれぞれにおける演算によって、どの動きベクトルに対応した計数値を生成するための差分絶対値が得られるかを示している。すなわち、演算器（０，０）では、（+4,+4）の動きベクトルに対応した計数値を生成するための差分絶対値が求められる。同様に、演算器（１，０）〜（７，７）では、それぞれ（+3,+4）〜（-3,-3）の動きベクトルに対応した計数値を生成するための差分絶対値が求められる。
【０２７１】
なお、ある参照ブロックに対応して各演算器２０４_-1〜２０４_-N（（０，０）〜（７，７））では上述したように演算が行われるが、ある参照ブロックに関する演算と並行して、このある参照ブロック（参照ブロックＰ）に対して水平方向の前後に隣接する参照ブロックに関する演算も行われる。すなわち、図４０から明らかなように、参照ブロックＰに関する演算とその前後の参照ブロックＰ−１，Ｐ＋１に関する演算とが、時間的にだぶって行われていることがわかる。
【０２７２】
例えば、参照ブロックＰに関する演算は各ラインの１５画素を用いて行われる。１〜７番目の画素を用いるときは、参照ブロックＰに関する演算が行われると共に、これと並行して参照ブロックＰ−１に関する演算が行われる。同様に、９〜１５番目の画素を用いるときは、参照ブロックＰに関する演算が行われると共に、これと並行して参照ブロックＰ＋１に関する演算が行われる。なお、８番目の画素を用いるときは、参照ブロックＰに関する演算のみが行われる。
【０２７３】
例えば、１ライン目で、１番目の画素を用いるとき、演算器（７，７）では参照ブロックＰに関する演算が行われるが、演算器（６，７）〜（０，７）では参照ブロックＰ−１に関する演算が行われる。また例えば、１ライン目で、９番目の画素を用いるときは、演算器（６，７）〜（０，７）では参照ブロックＰに関する演算が行われるが、演算器（７，７）では参照ブロックＰ＋１に関する演算が行われる。
【０２７４】
上述したように半導体メモリ２０６の複数の記憶領域２０６_-1〜２０６_-Nには、それぞれ参照フレームの横一行の参照ブロック数に対応した個数のブロック記憶領域を有している。さらに、各ブロック記憶領域には、参照ブロックを構成する画素データの個数分の計数値記憶領域を有している。そして、複数の演算器２０４_-1〜２０４_-Nで得られた差分絶対値にそれぞれ対応して計数値生成部２０５で生成された計数値は、その計数値に係る演算器および参照ブロックの画素位置に対応した半導体メモリ２０６の計数値記憶領域に書き込まれる。このことから、半導体メモリ２０６は、カラム方向には、複数の演算器２０４_-1〜２０４_-Nのそれぞれに対応した所定メモリセル単位で、独立してアクセス可能に構成される。
【０２７５】
次に、半導体メモリ２０６の詳細構成について説明する。図４４は、半導体メモリ２０６の全体構成を示している。半導体メモリ２０６は、８個のメモリ部２５０_-1〜２５０_-8から構成されている。各メモリ部２５０_-1〜２５０_-8は、それぞれ読み出し用のロウデコーダ２５１と、８個の記憶領域と、書き込み用のメインロウデコーダ２５３と、書き込み用のサブロウデコーダ２５４とから構成されている。
【０２７６】
メモリ部２５０_-1，２５０_-2，２５０_-3，２５０_-4，２５０_-5，２５０_-6，２５０_-7，２５０_-8の８個の記憶領域は、それぞれ、演算器２０４_-1〜２０４_-8，２０４_-9〜２０４_-16，２０４_-17〜２０４_-24，２０４_-25〜２０４_-32，２０４_-33〜２０４_-40，２０４_-41〜２０４_-48，２０４_-49〜２０４_-56，２０４_-57〜２０４_-64にそれぞれ対応した、記憶領域２０６_-1〜２０６_-8，２０６_-9〜２０６_-16，２０６_-17〜２０６_-24，２０６_-25〜２０６_-32，２０６_-33〜２０６_-40，２０６_-41〜２０６_-48，２０６_-49〜２０６_-56，２０６_-57〜２０６_-64（Ｎ＝６４）である。
【０２７７】
また、上述したように、６４個の記憶領域２０６_-1〜２０６_-64は、それぞれ参照フレームの横一行の参照ブロック数に対応した個数のブロック記憶領域ＢＭを有している。さらに、各ブロック記憶領域ＢＭには、参照ブロックを構成する画素データの個数分、本実施の形態では６４個の計数値記憶領域を有している。
【０２７８】
図４５は、上述した６４個の記憶領域２０６_-1〜２０６_-64をさらに詳細に示したものである。各メモリ部２５０_-1〜２５０_-8の８個の記憶領域（例えば、２０６_-1〜２０６_-8）は、それぞれ、ロウ方向に６４ｍ個（ｍは横一行の参照ブロック数）、カラム方向に８ｎ（ｎは計数値生成部２０５からの計数値の出力ビット数）のメモリセルがマトリックス状に配置されて構成されている。
【０２７９】
上述したように、ある参照ブロック（参照ブロックＰ）に関する差分絶対値演算は１ライン目〜１５ライン目の画素データを用いて行われる。例えば、１ライン目の画素データを用いて演算が行われるときは、記憶領域２０６_-57〜２０６_-64の記憶位置に書き込みが行われる。１ライン目で４画素目の画素データを用いた演算が行われるとき、演算器（７，７）〜（４，７）で行われる演算は参照ブロックＰに関する演算であり、演算器（３，７）〜（０，７）で行われる演算は参照ブロックＰ−１に関する演算である。そのため、記憶領域２０６_-57〜２０６_-64の、例えば図４５（１ライン目）に格子縞で示した記憶位置に計数値の書き込みが行われる。
【０２８０】
また例えば８ライン目の画素データを用いて演算が行われるときは、記憶領域２０６_-1〜２０６_-64の記憶位置に書き込みが行われる。８ライン目で６画素目の画素データを用いた演算が行われるとき、演算器（７，７）〜（２，７）、（７，６）〜（２，６）、（７，５）〜（２，５）、（７，４）〜（２，４）、（７，３）〜（２，３）、（７，２）〜（２，２）、（７，１）〜（２，１）、（７，０）〜（２，０）で行われる演算は参照ブロックＰに関する演算であり、演算器（１，７）〜（０，７）、（１，６）〜（０，６）、（１，５）〜（０，５）、（１，４）〜（０，４）、（１，３）〜（０，３）、（１，２）〜（０，２）、（１，１）〜（０，１）、（１，０）〜（０，０）で行われる演算は参照ブロックＰ−１に関する演算である。そのため、記憶領域２０６_-1〜２０６_-64の、例えば図４５（８ライン目）に格子縞で示した記憶位置に計数値の書き込みが行われる。
【０２８１】
詳細説明は省略するが、メモリ部２５０_-1〜２５０_-8における書き込み用のメインロウデコーダ２５３およびサブロウデコーダ２５４に関しては、上述した図３の動きベクトル検出回路１１１の半導体メモリ１２６に関連して説明した足し込み用のメインロウデコーダ１５３およびサブロウデコーダ１５４の構成と同様とされる。すなわち、例えばメモリ部１５０_-1は、図２４において、デコーダ１５３，１５４をデコーダ２５３，２５４とし、記録領域１２６_-1〜１２６_-3を記録領域２０６_-1〜２０６_-3としたものとなる。これにより、半導体メモリ２０６は、カラム方向には、複数の演算器２０４_-1〜２０４_-Nのそれぞれに対応した所定メモリセル単位で、独立してアクセス可能となっている。
【０２８２】
次に、複数の加算器２０９_-1〜２０９_-Nおよびヒストグラムテーブル生成用の半導体メモリ２１０の詳細を説明する。複数の加算器２０９_-1〜２０９_-Nと半導体メモリ２１０は一体化されており、複数の加算器２０９_-1〜２０９_-Nを構成するそれぞれのビット単位の複数の加算部は、半導体メモリ２１０のカラムのピッチに揃えて配されている。
【０２８３】
図４６は、加算器２０９_-1およびそれに対応した半導体メモリ２１０の記憶領域２１０_-1の部分の詳細構成を示したものである。なお、説明は省略するが、加算器２０９_-2〜２０９_-Nおよびそれに対応した半導体メモリ２１０の記憶領域２１０_-2〜２１０_-Nの部分についても同様に構成されている。
【０２８４】
図４６において、記憶領域２１０_-1には、カラム方向にｎ個、ロウ方向に１個のメモリセル(Memory Cell)１３０が配されている。この場合、カラム方向に並ぶｎ個のメモリセル１３０によって、１つの度数記憶領域が構成されている。メモリセル１３０は、上述の図２３で説明したように、書き込みおよび読み出し用の第１のポートと読み出し専用の第２のポートとを有する２ポート構成のものである。
【０２８５】
カラム方向に並ぶメモリセル１３０に沿って、ワード線ＷＬ、および読み出し専用ワード線ＷＲＬが配されている。ワード線ＷＬはメモリセル１３０の端子１３に接続され、読み出し専用ワード線ＷＲＬはメモリセル１３０の端子１７に接続される。
【０２８６】
また、カラム方向に並ぶｎ個のメモリセル１３０に、それぞれビット線ＢＬ₀〜ＢＬ_n-1，/ＢＬ₀〜/ＢＬ_n-1、および読み出し専用ビット線ＢＲＬ₀〜ＢＲＬ_n-1が接続されている。上述したように、ビット線ＢＬ₀〜ＢＬ_n-1はメモリセル１３０の端子１４に接続され、ビット線/ＢＬ₀〜/ＢＬ_n-1はメモリセル１３０の端子１５に接続され、読み出し専用ビット線ＢＲＬ₀〜ＢＲＬ_n-1はメモリセル１３０の端子１６に接続される。
【０２８７】
この図４６におけるその他の構成は、図２２における加算器１２５_-1および記憶領域１２６_-1の構成と同様とされる。
図４６に示す加算器２０９_-1および記憶領域２１０_-1の部分の動作を説明する。
まず、カラム方向に並ぶｎ個のメモリセル１３０によって１個の度数記憶領域が構成されているが、このｎ個のメモリセル１３０の記憶データをクリアする動作について説明する。
【０２８８】
度数記憶領域を構成するｎ個のメモリセル１３０の記憶データをクリアする場合、書き込み制御信号φ_Wおよびクリア制御信号φ_CLRはアクティブ、つまり“１”とされ、読み出し制御信号φ_Rおよびイコライズ制御信号φ_EQはインアクティブ、つまり“０”とされ、さらにワード線ＷＬがワード線が活性化される。
【０２８９】
この場合、クリア制御信号φ_CLRがアクティブとされてトランジスタＱ５１がオンとなる。そのため、“０”のデータが生成され、このデータがビット線ＢＬ₀〜ＢＬ_n-1に出力される。したがって、ワード線ＷＬを活性化することで、度数記憶領域を構成するｎ個のメモリセル１３０には“０”のデータが書き込まれ、記憶データのクリアが行われる。
【０２９０】
次に、度数記憶領域（ｎ個のメモリセル１３０）に記憶されている記憶データＭＤ₀〜ＭＤ_n-1に、８ビットの計数値Ｄ₀〜Ｄ₇を、加算器２０９_-1（加算部１４０₁〜１４０_n-1）で足し込み、そして加算器２０９_-1で得られた足し込みデータＡＤ₀〜ＡＤ_n-1を、当該度数記憶領域に書き戻す動作について説明する。
【０２９１】
所定の度数記憶領域に記憶されている記憶データＭＤ₀〜ＭＤ_n-1に、８ビットの計数値Ｄ₀〜Ｄ₇を足し込む場合、最初に、イコライズ制御信号φ_EQはアクティブ、つまり“１”とされ、書き込み制御信号φ_W、読み出し制御信号φ_Rおよびクリア制御信号φ_CLRはインアクティブ、つまり“０”とされ、ビット線対ＢＬ₀，/ＢＬ₀〜ＢＬ_n-1，/ＢＬ_n-1のイコライズ（プリチャージ）が行われる。
【０２９２】
この場合、ビット線対ＢＬ₀，/ＢＬ₀に関しては、イコライズ制御信号φ_EQがアクティブとされてトランジスタＱ３１〜Ｑ３３の全てがオンとなり、ビット線ＢＬ₀およびビット線/ＢＬ₀に電源の電位が印加され、これらビット線ＢＬ₀およびビット線/ＢＬ₀は同電位となる。他のビット線対ＢＬ₁，/ＢＬ₁〜ＢＬ_n-1，/ＢＬ_n-1に関しても同様である。
【０２９３】
このようにビット線対ＢＬ₀，/ＢＬ₀〜ＢＬ_n-1，/ＢＬ_n-1のイコライズが行われた状態で、読み出し制御信号φ_Rはアクティブ、つまり“１”とされ、書き込み制御信号φ_W、イコライズ制御信号φ_EQおよびクリア制御信号φ_CLRはインアクティブ、つまり“０”とされ、さらにワード線ＷＬが活性化される。
【０２９４】
これにより、度数記憶領域を構成するｎ個のメモリセル１３０の記憶データＭＤ₀〜ＭＤ_n-1が、それぞれビット線対ＢＬ₀，/ＢＬ₀〜ＢＬ_n-1，/ＢＬ_n-1およびセンスアンプＳＡ₀〜ＳＡ_n-1を介して読み出され、加算部１４０₀〜１４０_n-1のＢ側の入力端子にそれぞれ入力される。したがって、度数記憶領域に記憶されている記憶データＭＤ₀〜ＭＤ_n-1に、８ビットの計数値Ｄ₀〜Ｄ₇が足し込まれる。
【０２９５】
そして、加算部１４０₀〜１４０_n-1における加算出力、つまり足し込みデータＡＤ₀〜ＡＤ_n-1が有効になったところで、書き込み制御信号φ_Wはアクティブ、つまり“１”とされ、読み出し制御信号φ_R、イコライズ制御信号φ_EQおよびクリア制御信号φ_CLRはインアクティブ、つまり“０”とされ、さらにワード線ＷＬが活性化される。
【０２９６】
この場合、加算部１４０₀の部分に関して、足し込みデータＳ₀が“１”である場合には、トランジスタＱ１１はオン、トランジスタＱ１２はオフとなり、ビット線/ＢＬ₀に“０”が出力されることから、度数記憶領域を構成するｎ個のメモリセル１３０のうち、当該加算部１４０₀に対応するメモリセル１３０には、“１”のデータが記憶される。一方、加算部１４０₀の部分に関して、足し込みデータＳ₀が“０”である場合には、トランジスタＱ１１はオフ、トランジスタＱ１２はオンとなり、ビット線ＢＬ₀に“０”が出力されることから、度数記憶領域を構成するｎ個のメモリセル１３０のうち、当該加算部１４０₀に対応するメモリセル１３０には、“０”のデータが記憶される。
【０２９７】
他の加算部１４０₁〜１４０_n-1の部分に関しても同様である。これにより、加算器２０９_-1で得られた足し込みデータＡＤ₀〜ＡＤ_n-1は、度数記憶領域を構成するｎ個のメモリセル１３０に書き戻される。
【０２９８】
なお、足し込みの動作において、オーバフローとなる場合には、加算部１４０_n-1のキャリ出力端子Ｃ_OUTに得られるＭＳＢのキャリ出力Ｃ_MSBが“１”となるため、トランジスタＱ１３はオフとなり、足し込みデータＡＤ₀〜ＡＤ_n-1が、度数記憶領域を構成するｎ個のメモリセル１３０に書き込まれることはない。
【０２９９】
その代わり、この場合、トランジスタＱ６１がオンとなる他に、トランジスタＱ６２もオンとなるので、ビット線/ＢＬ₀〜/ＢＬ_n-1にそれぞれ“０”の信号が出力される。したがって、度数記憶領域を構成するｎ個のメモリセル１３０のそれぞれに“１”のデータが書き込まれる。つまり、この度数記憶領域には最大値が記憶される。
【０３００】
次に、度数記憶領域に記憶された、度数（計数値）の累積値を、読み出す場合の動作を説明する。
最初に、プリチャージ制御信号/φ_RPCがアクティブ、つまり“１”とされ、読み出し専用ビット線ＢＲＬ₀〜ＢＲＬ_n-1のプリチャージが行われる。この場合、トランジスタＱ４１はオンとなり、読み出し専用ビット線ＢＲＬ₀〜ＢＲＬ_n-1のそれぞれに電源の電位が印加される。
【０３０１】
このように読み出し専用ビット線ＢＲＬ₀〜ＢＲＬ_n-1のプリチャージが行われた状態で、読み出し専用ワード線ＷＲＬが活性化される。これにより、度数記憶領域を構成するｎ個のメモリセル１３０の記憶データΣ₀〜Σ_n-1が、それぞれ読み出し専用ビット線ＢＲＬ₀〜ＢＲＬ_n-1に得られる。ここで、記憶データΣ₀〜Σ_n-1は、ｎビットの度数の累積値を構成している。
【０３０２】
以上説明したように、図３０に示す動きベクトル検出回路２００においては、参照フレームの所定の参照ブロックを構成する画素データとこの画素データに対応した探索フレームの探索範囲に存在する複数の画素データとの間の差分絶対値演算を行い、参照ブロックを構成する各画素データ毎に、探索範囲の各画素位置に対応して、差分絶対値がその閾値より小さいときは計数値として０以外の値を配し、差分絶対値がその閾値以上のときは計数値として０を配した計数値テーブルを生成し、参照ブロックを構成する各画素データに対応した計数値テーブルの各計数値を度数とし、この度数を探索範囲の画素位置毎に足し込んでヒストグラムテーブルを生成し、このヒストグラムテーブルの度数の極大値に基づいて参照ブロックの動きベクトルＭＶ₁〜ＭＶ_nを検出するものである。
【０３０３】
この場合、このヒストグラムテーブルにおける度数の極大値は、参照ブロック内に存在する動きに対応した動きベクトルを表している。マッチング度合いが高く差分絶対値がその閾値より小さいときのみ計数値として０以外の値を配して計数値テーブルを生成するものであって、ヒストグラムテーブルはマッチング度合いが高いもののみによって生成されることとなり、その度数の分布はより先鋭化されたものとなる。そのため、参照ブロック内に動きの異なるものが複数混在する場合には、ヒストグラムテーブルに複数個の極大値が明瞭に分離して示され易くなる。したがって、参照ブロックの一個または複数個の動きベクトルＭＶ₁〜ＭＶ_nを正しく検出できる。
【０３０４】
なお、差分絶対値がその閾値より小さいときに配する計数値を正の値としているが（表１参照）、これを負の値としてもよい。その場合、ヒストグラムテーブルには、参照ブロック内に存在する動きに対応した動きベクトルを表す度数の極小値が示される。この場合であっても、上述した実施の形態と同様に、ヒストグラムテーブルに基づいて、参照ブロックの動きベクトルを正しく検出できる。
【０３０５】
また、マッチング度合いが高く差分絶対値がその閾値より小さいときに配する計数値を一定値とするのではなく、差分絶対値が小さい程、つまりマッチングの度合いが高い程、絶対値の大きな値としているので、ヒストグラムテーブルの度数の分布を一層先鋭化できる利益がある。
【０３０６】
また、補正係数取得部２０７では、参照ブロックを構成する各画素データ毎にアクティビティＡを求め、この各画素データ毎に、アクティビティＡの最大アクティビティＡ_maxに対する割合が高い程大きな値を補正係数ｋとして得て、参照ブロックを構成する各画素データに対応した計数値テーブルの計数値に、それぞれこの各画素データに対応した補正係数ｋを掛けて補正するものであり、アクティビティＡによるマッチングの度合い、つまり差分絶対値の変化による不具合を軽減できる。
【０３０７】
なお、補正係数取得部２０７で補正係数ｋを求め、計数値補正部２０８でこの補正係数ｋを計数値に掛けて補正するものであったが、この代わりに、計数値生成部２０５で差分絶対値に対応して計数値を生成する際に用いられる閾値を、アクティビティが大きい程大きくするように変更してもよい。この場合、計数値を補正係数ｋで補正する場合と同様に、周囲におけるアクティビティが大きな参照ブロックの画素データに対応した計数値テーブルの計数値に関しては、その絶対値が大きくなる。これにより、アクティビティによるマッチングの度合い、つまり差分絶対値の変化による不具合を軽減できる。
【０３０８】
また、探索フレームとしての入力フレームを次フレームの参照フレームとして格納する参照フレームメモリ２０３を備え、複数の差分絶対値演算器２０４_-1〜２０４_-Nで、入力フレームの画素データが入力される都度、その画素データと、フレームメモリ２０３より読み出される、その画素データを探索範囲に含む参照フレームの所定の参照ブロックの画素データとの差分絶対値を演算するものである。したがって、探索フレームを一旦フレームメモリに記憶し、その後に改めて処理のために読み出すといった無駄な動作を排除でき、効率よく動きベクトルを検出できる。
【０３０９】
また、半導体メモリ２０６のカラム方向に延びる各ワード線は、複数の記憶領域２０６_-1〜２０６_-Nにそれぞれ対応して分割された複数のセクションワード線からなり、半導体メモリ２０６は任意のワード線を構成する複数のセクションワード線のうち任意のセクションワード線を選択的に活性化させるためのロウデコード手段としてのメインロウデコーダ２５３およびサブロウデコーダ２５４を有するものであり、半導体メモリ２０６には、カラム方向にセクションワード線単位で独立してアクセスできる。
【０３１０】
また、半導体メモリ２０６の複数の記憶領域２０６_-1〜２０６_-Nは、それぞれ複数の参照ブロックに係る計数値を記憶するための複数のブロック記憶領域ＢＭがロウ方向に配列されてなり、メインロウデコーダ２５３は２つの連続するブロック記憶領域ＢＭに対応したグローバルワード線を活性化させ、サブロウデコーダ２５４はその２つのグローバルワード線に対応してそれぞれ活性化させるセクションワード線を互いに異なる記憶領域に対応したセクションワード線とするものである。
【０３１１】
したがって、複数の差分絶対値演算器２０４_-1〜２０４_-Nで２つの参照ブロックに関係する差分絶対値演算が並行して行われても、計数値生成部２０５で生成された計数値を参照ブロック毎にロウ方向の異なるワード線位置に振り分けて書き込むことが可能となり、半導体メモリ２０６に参照ブロック別に、計数値テーブルを得ることができる。
【０３１２】
また、加算器２０９_-1〜２０９_-Nおよび半導体メモリ２１０が一体化され、加算器を構成するビット単位の複数の加算部１４０₀〜１４０_n-1が、半導体メモリ２１０のカラムのピッチに揃えて配されるものである（図４６参照）。したがって、加算器２０９_-1〜２０９_-Nから半導体メモリ２１０への足し込みデータの供給および半導体メモリ２１０から加算器２０９_-1〜２０９_-Nへの記憶データの供給を効率的に行うことができる。
【０３１３】
また、半導体メモリ２１０が、複数の加算器に関連して設けられた書き込みおよび読み出し用の第１のポートと、度数の累積値を読み出すための読み出し専用の第２のポートとを有するものである（図４６参照）。したがって、半導体メモリ２１０の記憶データの読み出しを、加算器２０９_-1〜２０９_-Nによる演算とは別個独立して行うことができる。
【０３１４】
また、動きベクトル検出部２１１で検出された参照ブロックの動きベクトルＭＶ₁〜ＭＶ_nに基づいて、動きベクトル特定部２１２で、その参照ブロックを構成する各画素データの動きベクトルｍｖを特定することができる。上述したように、参照ブロックの動きベクトルを正しく検出できることから、その動きベクトルに基づいて特定される各画素データの動きベクトルもより精度の高いものとなる。
【０３１５】
さらに、動きベクトル特定部２１２では、このように特定される参照ブロックを構成する各画素データの動きベクトルｍｖから孤立した動きベクトルを除去する等の補正処理を行うので、この各画素データの動きベクトルの精度をさらに高めることができる。
【０３１６】
なお、図３０の動きベクトル検出回路２００においては、半導体メモリ２０６は、２つの参照ブロックに対応した記憶領域に存在する２つのロウ位置のグローバルワード線（セクションワード線）を活性化させるものを示したが、同様の構成によって、２つ以上の参照ブロックに対応した記憶領域に存在する３つ以上のロウ位置のグローバルワード線（セクションワード線）を活性化させることもできる。参照ブロック内の１個の参照画素に対する探索範囲によっては、複数の差分絶対値演算器において、３つ以上の参照ブロックに係る演算が行われることも想定される。その場合には、３つ以上のロウ位置のグローバルワード線（セクションワード線）を活性化させることが必要となる。
【０３１７】
また、図３０の動きベクトル検出回路２００においては、半導体メモリ２１０を構成するメモリセル１３０が２ポート構成のものであったが（図２３参照）、メモリセルが２ポート構成でなくてもよく、半導体メモリ２１０の全体として２ポート構成であってもよい。さらには、半導体メモリ２１０として２ポート構成でなくとも、例えば映像信号におけるブランキング期間に度数（テーブルデータ）の読み出しを行ったり、同一機能ブロックを複数個有してフィールドまたはフレーム間でインターリーブさせて用いるなど、足し込みと度数の読み出しとを同一ポートにおいて異なる期間に行ってもよい。
【０３１８】
【発明の効果】
この発明に係る動きベクトル検出回路は、探索フレームの画素データが入力される都度、複数の差分絶対値演算器によってその画素データを探索範囲に含む参照フレームの所定の参照ブロックの画素データとの差分絶対値を求め、この差分絶対値に基づいて当該所定の参照ブロックの動きベクトルを検出するものであり、探索フレームが入力フレームである場合に、探索フレームを一旦フレームメモリに記憶しその後に改めて処理のために読み出すといった無駄な動作を排除でき、効率よく参照ブロックの動きベクトルを検出できる。
【図面の簡単な説明】
【図１】実施の形態としての動き補償予測符号化装置の構成を示すブロック図である。
【図２】入力フレームが探索フレームであって過去フレームが参照フレームである場合における、動きベクトル検出のためのブロックマッチング法を説明するための図である。
【図３】動きベクトル検出回路の構成を示すブロック図である。
【図４】入力フレームが探索フレームであって過去フレームが参照フレームである場合における、動きベクトル検出のためのマッチング演算を説明するための図である。
【図５】参照ブロックと探索範囲との関係を示す図である。
【図６】入力画素と参照ブロックの代表点と演算器との関係を示す図である。
【図７】１演算器における、代表点と入力画素との相対位置関係を示す図である。
【図８】入力画素の演算対象範囲と参照ブロックとの位置関係を示す図である。
【図９】入力画素の演算対象範囲と参照ブロックとの位置関係を示す図である。
【図１０】入力画素の演算対象範囲と参照ブロックとの位置関係を示す図である。
【図１１】入力画素の演算対象範囲と参照ブロックとの位置関係を示す図である。
【図１２】入力画素の演算対象範囲と参照ブロックとの位置関係を示す図である。
【図１３】入力画素の演算対象範囲と参照ブロックとの位置関係を示す図である。
【図１４】入力画素の演算対象範囲と参照ブロックとの位置関係を示す図である。
【図１５】所定の参照ブロックに対応した複数の候補ブロックの相関値を得る際の、複数の差分絶対値演算器における演算過程を示す図である。
【図１６】参照ブロックの４×４画素毎の代表点を示す図である。
【図１７】演算器（７，７）における演算過程を示す図である。
【図１８】動きベクトル（１参照画素の探索範囲の座標）を示す図である。
【図１９】動きベクトルとテーブル生成用メモリにおける記憶位置との対応関係を示す図である。
【図２０】半導体メモリの全体構成を示す図である。
【図２１】テーブル生成用メモリの構成を示す図である。
【図２２】半導体メモリと加算器とを一体化した構成を示す図である。
【図２３】メモリセルの構成を示す図である。
【図２４】メモリ部のメイン・サブロウデコーダとワード線の構成を示す図である。
【図２５】ブロックマッチング法の問題点（複数の動きがある場合）を説明するための図である。
【図２６】動きベクトル検出方法の概略を説明するための図である。
【図２７】相関値テーブルの一例（２つの動きがある場合）を示す図である。
【図２８】ヒストグラムテーブルの一例（２つの動きがある場合）を示す図である。
【図２９】アクティビティを求めるための画素データ例を示す図である。
【図３０】動きベクトル検出回路の構成を示すブロック図である。
【図３１】参照ブロックと探索範囲との関係を示す図である。
【図３２】動きベクトル特定部の構成を示すブロック図である。
【図３３】入力画素データと参照ブロックと演算器との関係を示す図である。
【図３４】入力画素データの演算対象範囲と参照ブロックとの位置関係を示す図である。
【図３５】入力画素データの演算対象範囲と参照ブロックとの位置関係を示す図である。
【図３６】入力画素データの演算対象範囲と参照ブロックとの位置関係を示す図である。
【図３７】入力画素データの演算対象範囲と参照ブロックとの位置関係を示す図である。
【図３８】入力画素データの演算対象範囲と参照ブロックとの位置関係を示す図である。
【図３９】入力画素データの演算対象範囲と参照ブロックとの位置関係を示す図である。
【図４０】所定の参照ブロックを構成する各画素データに対応した計数値テーブルを得る際の、複数の差分絶対値演算器における演算過程を示す図である。
【図４１】演算器（７，７）における演算過程を示す図である。
【図４２】動きベクトル（１参照画素の探索範囲の座標）を示す図である。
【図４３】動きベクトルと計数値テーブル生成用メモリにおける記憶位置との対応関係を示す図である。
【図４４】半導体メモリの全体構成を示す図である。
【図４５】半導体メモリの記憶領域の構成を示す図である。
【図４６】半導体メモリと加算器とを一体化した構成を示す図である。
【図４７】入力フレームが参照フレームであって過去フレームが探索フレームである場合における、動きベクトル検出のためのブロックマッチング法を説明するための図である。
【図４８】入力フレームが参照フレームであって過去フレームが探索フレームである場合における、動きベクトル検出のためのマッチング演算を説明するための図である。
【符号の説明】
１００・・・動き補償予測符号化装置、１０１・・・入力端子、１０２・・・減算器、１０３・・・ＤＣＴ回路、１０４・・・量子化回路、１０５・・・出力端子、１０６・・・逆量子化回路、１０７・・・逆ＤＣＴ回路、１０８・・・加算器、１０９・・・フレームメモリ、１１０・・・動き補償回路、１１１，２００・・・動きベクトル検出回路、１２１，２０１・・・システムコントローラ、１２２，２０２・・・入力端子、１２３，２０３・・・参照フレームメモリ、１２４_-1〜１２４_-N，２０４_-1〜２０４_-N・・・差分絶対値演算器、１２５_-1〜１２５_-N，２０９_-1〜２０９_-N・・・加算器、１２６・・・相関値テーブル用の半導体メモリ、１２６_-1〜１２６_-N・・・記憶領域、１２７・・・相関値テーブル評価器、１２８，２１３・・・出力端子、１３０・・・メモリセル、１４０₀〜１４０_n-1・・・加算部、１５０_-1〜１５０_-8・・・メモリ部、１５１，２５１・・・読み出し用のロウデコーダ、１５３・・・足し込み用のメインロウデコーダ、１５４・・・足し込み用のサブロウデコーダ、２０５・・・計数値生成部、２０６・・・計数値テーブル生成用の半導体メモリ、２０６_-1〜２０６_-N・・・記憶領域、２０７・・・補正係数取得部、２０８・・・計数値補正部、２１０・・・ヒストグラムテーブル生成用の半導体メモリ、２１１・・・動きベクトル検出部、２１２・・・動きベクトル特定部、２２１・・・コントローラ、２２２・・・探索画素用のメモリ、２２３_-1〜２２３_-n・・・相関演算部、２２４・・・動きベクトル仮特定部、２２５・・・動きベクトル補正部、２５３・・・書き込み用のメインロウデコーダ、２５４・・・書き込み用のサブロウデコーダ[0001]
BACKGROUND OF THE INVENTION
The present invention provides a motion vector detection circuit.On the roadRelated. Specifically, each time pixel data of a search frame is input, the present invention calculates a difference absolute value with respect to pixel data of a predetermined reference block of a reference frame including the pixel data in a search range by a plurality of difference absolute value calculators. By detecting the motion vector of the predetermined reference block based on the absolute value of the difference, when the search frame is an input frame, the motion vector of the reference block is efficiently detected by eliminating unnecessary operations. The present invention relates to a motion vector detection circuit that can be used.
[0003]
[Prior art]
In image processing, motion vector detection is one of important elements, and a typical method is a block matching method. This is to evaluate the correlation between a certain pixel block (reference block) constituting a part of a certain frame and the same shape pixel block (candidate block) at various positions in a frame at different times. A relative positional shift with the highest candidate block is regarded as a motion vector in the reference block.
[0004]
Here, an area that assumes a candidate block is a search range. For the evaluation of the correlation, the sum total of each pixel in the block of the absolute difference value of the pixel data between the corresponding pixels of the reference block and the candidate block, that is, the sum of absolute differences is often used. For one reference block, a sum of absolute differences (correlation values) for a plurality of candidate blocks existing within the search range is obtained, which is a correlation value table. In the correlation value table, the place where the sum of absolute differences is the smallest, that is, the place where the correlation is high is regarded as a motion vector in units of pixels. In practice, this processing has a very heavy calculation load, and various measures are taken with respect to the shape and size of the block, the pixel position used for the calculation, and the like.
[0005]
[Problems to be solved by the invention]
In the motion vector search based on the block matching method, as shown in FIG. 47, when the search frame is a past frame with respect to the reference frame, the input frame of the vector search system is used as the reference frame. The configuration and operation can be made simpler.
[0006]
This is because the input pixel data is stored in the frame memory for use as the pixel data of the search frame of the next frame, and at the same time, as shown in FIG. 48, the input pixel data (data of one reference pixel) and the search range This is because a one-to-N matching operation with N pieces of pixel data can be performed, and it is not necessary to read out as reference pixel data in order to perform a matching operation after writing to the frame memory.
[0007]
When trying to read such reference pixel data, since pixel data is written simultaneously in the same frame, these operations are required at the same time in the same memory block, and it is necessary to deal with them. In addition, the pixel data input to the system is used as it is for processing, but the operation itself of temporarily storing it in the frame memory and then reading it out again for processing is useless.
[0008]
On the other hand, as shown in FIG. 2, when the reference frame is a past frame with respect to the search frame, the input frame of the vector search system can be considered as the search frame.
[0009]
Conventionally, however, there has been little mention of this case, such as it is difficult to perform a matching operation and writing to the frame memory each time pixel data of a search frame is input.
[0010]
  An object of the present invention is to provide a motion vector detection circuit capable of efficiently detecting a motion vector by eliminating unnecessary operations when a search frame is an input frame..
[0011]
[Means for Solving the Problems]
  The motion vector detection circuit according to the present invention includes:SearchThe input frame as the search frameGo back and forth in timePixel data of a predetermined reference block of a reference frame that includes pixel data of an input frame that is input from the frame memory and is input from the frame memory in common with the frame memory that is stored as a reference frame and that is read from the frame memory Obtained by being calculated by a plurality of difference absolute value calculators that calculate the difference absolute value between the pixel data of the input frame and the pixel data of the predetermined reference block, and the plurality of difference absolute value calculators. A motion vector detection processing unit for detecting a motion vector of a predetermined reference block based on the absolute difference valueThe motion vector detection processing unit corresponds to each of the plurality of difference absolute values calculated by the plurality of difference absolute value calculators, and when the difference absolute value is smaller than the threshold value, a predetermined value other than 0 And a count value generation means for generating a count value so that the difference value is 0 when the difference absolute value is equal to or greater than the threshold, and a count value table generation having a plurality of storage areas respectively corresponding to a plurality of difference absolute value calculators The first storage means for use and the count value generated by the count value generation means corresponding to each of the difference absolute values calculated by the plurality of difference absolute value calculators are stored in the first storage means. A difference absolute value calculator related to the count value and a count value storage area in the storage area corresponding to the pixel position of the reference block are written, and a search corresponding to each pixel data constituting the reference block is stored in the first storage means At each pixel position in the range Write control means for controlling so as to obtain a count value table in which the count values are arranged in response, and each count value table corresponding to each pixel data constituting the reference block obtained in the first storage means Histogram table generation means for generating a histogram table in which the count value is a frequency, the frequency is added to each pixel position of the search range, and a cumulative value of the frequency is arranged corresponding to each pixel position of the search range; Motion vector detecting means for detecting the motion vector of the reference block based on the maximum or minimum value of the frequency in the histogram tableIs.
[0012]
In the present invention, each time the pixel data of the search frame (input frame) is input, the plurality of difference absolute value calculators include the pixel data and pixels of a predetermined reference block of the reference frame including the pixel data in the search range. The absolute value of the difference from the data is calculated. Then, a motion vector of a predetermined reference block is detected based on the difference absolute value obtained by calculation with the plurality of difference absolute value calculators. Thus, when the search frame is an input frame, it is possible to efficiently detect a motion vector by eliminating useless operations.
[0013]
For example, each of the difference absolute values obtained by the plurality of adders and the plurality of difference absolute value calculators is stored in the storage data stored in the plurality of storage areas of the storage means for generating the correlation value table. It is added. Thus, each of the addition data obtained by the plurality of adders is written in the plurality of storage areas of the storage means.
[0014]
The correlation corresponding to each of the plurality of candidate blocks existing in the search range of the predetermined reference block in the plurality of storage areas of the storage unit by repeating the above-described absolute difference calculation, addition calculation, and storage operation a predetermined number of times. A value (sum of absolute differences) is obtained. The correlation value table evaluation unit detects a motion vector corresponding to a predetermined reference block based on each correlation value obtained in the storage unit in this way.
[0015]
Note that the storage means is a semiconductor memory, and at least a plurality of adders and the semiconductor memory are integrated, and a plurality of bit-wise addition units constituting the adder are arranged in alignment with the column pitch of the semiconductor memory. Thus, the supply of the addition data from the adder to the semiconductor memory and the supply of the storage data from the semiconductor memory to the adder are efficiently performed.
[0016]
The storage means is a semiconductor memory, and the semiconductor memory includes a first port for writing and reading provided in association with a plurality of adders, and a second read-only for reading the correlation value. By having a port, it is possible to read data stored in the semiconductor memory independently of the operation by the adder.
[0017]
Further, the storage means is a semiconductor memory, and each word line extending in the column direction is composed of a plurality of divided word lines divided corresponding to a plurality of storage areas, and the semiconductor memory constitutes an arbitrary word line. By having row decode means for selectively activating any divided word line among a plurality of divided word lines, the semiconductor memory can be accessed independently in divided word lines in the column direction. It becomes.
[0018]
For example, each word line includes a continuous global word line and a plurality of section word lines that are divided corresponding to a plurality of storage areas and are connected to a predetermined number of memory cells. The row decoding means corresponds to a main row decoding means for selectively activating any global word line among the global word lines constituting each word line, and a global word line activated by the main row decoding means. The sub-row decoding means selectively activates an arbitrary section word line among the plurality of section word lines.
[0019]
In this case, a plurality of block areas for storing correlation values related to a plurality of reference blocks are respectively arranged in the row direction in the plurality of storage areas of the semiconductor memory, and the main row decoding means has a predetermined number of consecutive The sub-row decoding means simultaneously activates a section word line corresponding to a different storage area, and activates a predetermined number of global word lines corresponding to the block area to be activated. By using a word line, even if multiple absolute difference operations related to multiple reference blocks are performed in parallel by multiple differential absolute value calculators, addition related to multiple reference blocks is performed using multiple adders. The added data can be distributed and written to different word line positions in the row direction for each reference block. It is possible to obtain a correlation value for each reference block in 憶 means.
[0020]
In addition, for example, a count value is generated corresponding to each of a plurality of difference absolute values obtained by calculation with a plurality of difference absolute value calculators. In this case, the count value is generated so as to be a predetermined value other than 0 when the absolute difference value is smaller than the threshold value, and to 0 when the absolute difference value is equal to or greater than the threshold value.
[0021]
The count value generated corresponding to each of the difference absolute values calculated by the plurality of difference absolute value calculators is the difference absolute value calculator and reference block relating to the count value of the first storage means. Is written in the count value storage area corresponding to the pixel data constituting the. Thereby, the count value table for each pixel data constituting the reference block is obtained in the first storage means. In this count value table, count values are arranged corresponding to each pixel position in the search range.
[0022]
Then, with a plurality of adders, each of the plurality of count values in the count value table obtained in the first storage means is set as a frequency, and each of the plurality of frequencies is stored in a plurality of storage areas of the second storage means. It is added to the stored data. Thus, each of the addition data obtained by the plurality of adders is written in the plurality of storage areas of the second storage means.
[0023]
The addition operation and the storage operation are repeated by the number of the plurality of count value tables corresponding to each pixel data constituting the reference block obtained in the first storage unit, so that the second storage unit searches the second storage unit. A histogram table in which cumulative values of frequencies are arranged corresponding to each pixel position in the range is obtained.
[0024]
The motion vector of the reference block is detected based on the maximum or minimum value of the frequency in this histogram table. Here, when the count value provided when the degree of matching is high is a positive value, it is a maximum value, and when the count value is a negative value, it is a minimum value. The position of the maximum value or minimum value of the frequency in this histogram table represents a motion vector corresponding to the motion existing in the reference block.
[0025]
As described above, only when the degree of matching is high, a count value table is generated by assigning a value other than 0 as the count value, and the histogram table is generated only by a high matching degree. The frequency distribution is sharper. Therefore, when a plurality of different motions are mixed in the reference block, a plurality of maximum values or minimum values are easily clearly separated and shown in the histogram table. Therefore, the motion vector of the reference block can be detected correctly.
[0026]
In this case, the second storage means is a semiconductor memory, and at least a plurality of adders and the semiconductor memory are integrated, and a plurality of bit units that form the adder are aligned with the pitch of the columns of the semiconductor memory. Therefore, supply of addition data from the adder to the semiconductor memory and supply of storage data from the semiconductor memory to the adder are efficiently performed.
[0027]
In this case, the second storage means is a semiconductor memory, and the semiconductor memory reads the first port for writing and reading provided in association with the plurality of adders and the cumulative value of the frequency. The read-only second port can be used to read data stored in the semiconductor memory independently of the operation by the adder.
[0028]
Each word line extending in the column direction of the semiconductor memory is composed of a plurality of divided word lines divided corresponding to a plurality of storage areas, and the semiconductor memory includes a plurality of divided word lines constituting an arbitrary word line. By including a row decode means for selectively activating any divided word line, the semiconductor memory can be accessed independently in divided word line units in the column direction.
[0029]
For example, each word line includes a continuous global word line and a plurality of section word lines that are divided corresponding to a plurality of storage areas and are connected to a predetermined number of memory cells. The row decoding means corresponds to a main row decoding means for selectively activating any global word line among the global word lines constituting each word line, and a global word line activated by the main row decoding means. The sub-row decoding means selectively activates an arbitrary section word line among the plurality of section word lines.
[0030]
In this case, the plurality of block areas for storing the count values related to the plurality of reference blocks are arranged in the row direction in each of the plurality of storage areas of the semiconductor memory, and the main row decoding means has a predetermined number of consecutive The sub-row decoding means simultaneously activates a section word line corresponding to a different storage area, and activates a predetermined number of global word lines corresponding to the block area to be activated. By using the word line, the count value generated by the count value generation unit is calculated for each reference block even when the difference absolute value calculation related to the plurality of reference blocks is performed in parallel by the plurality of difference absolute value calculators. It is possible to write data in different word line positions in the row direction, and the count value test for each reference block in the semiconductor memory. It is possible to obtain a bull.
[0036]
DETAILED DESCRIPTION OF THE INVENTION
Hereinafter, embodiments of the present invention will be described with reference to the drawings.
FIG. 1 shows a configuration of a motion compensated prediction encoding apparatus 100 as an embodiment.
The encoding apparatus 100 has an input terminal 101 for inputting image data (frame data constituting a moving image) Di, image data Di supplied to the input terminal 101, and prediction supplied from a motion compensation circuit 110 described later. A subtractor 102 that calculates a difference with image data, a DCT circuit 103 that performs DCT (discrete cosine transform) on the difference data obtained by the subtractor 102, and a DCT coefficient obtained by the DCT circuit 103 A quantization circuit 104 that performs quantization and an output terminal 105 that outputs encoded data Do obtained by the quantization circuit 104 are provided.
[0037]
The encoding apparatus 100 also performs an inverse quantization circuit 106 that performs inverse quantization on the encoded data Do obtained by the quantization circuit 104, and performs inverse DCT on the output data of the inverse quantization circuit 106. An inverse DCT circuit 107 that obtains difference data, and an adder 108 that adds the difference data obtained by the inverse DCT circuit 107 and the predicted image data obtained by the motion compensation circuit 110 to restore the original image data; A frame memory 109 for storing the image data restored by the adder 108.
[0038]
Also, the encoding apparatus 100 reads the image data stored in the frame memory 109, performs motion compensation based on a motion vector MV from a motion vector detection circuit 111 described later, and then performs the subtractor 102 and the addition as described above. A motion compensation circuit 110 that supplies the image data 108 as predicted image data, and a motion vector detection circuit 111 that detects the motion vector MV of the image data Di supplied to the input terminal 101 and supplies the motion vector MV to the motion compensation circuit 110. Yes.
[0039]
The operation of the motion compensated predictive coding apparatus 100 shown in FIG. 1 will be described.
Image data Di input to the input terminal 101 is supplied to the subtractor 102 and the motion vector detection circuit 111. The subtractor 102 calculates the difference between the image data Di and the predicted image data supplied from the motion compensation circuit 110.
[0040]
The difference data obtained by the subtracter 102 is supplied to the DCT circuit 103 and subjected to discrete cosine transform. The DCT coefficient obtained by the DCT circuit 103 is supplied to the quantization circuit 104 and quantized. The encoded data Do obtained by the quantization circuit 104 is output to the output terminal 105.
[0041]
Also, the encoded data Do obtained by the quantization circuit 104 is supplied to the inverse quantization circuit 106 and inversely quantized, and the output data of the inverse quantization circuit 106 is further supplied to the inverse DCT circuit 107 to perform inverse DCT. The difference data is restored. The difference data and the prediction data from the motion compensation circuit 110 are added by the adder 108 to restore the original image data, and the restored image data is stored in the frame memory 109.
[0042]
In the motion compensation circuit 110, in a certain frame, image data stored in the frame memory 109 is read in the previous frame, and motion compensation is performed based on the motion vector MV from the motion vector detection circuit 111. Predictive image data is obtained. As described above, the predicted image data is supplied to the subtractor 102 to obtain difference data, and is also supplied to the adder 108 to restore the image data.
[0043]
Next, details of the motion vector detection circuit 111 will be described.
The motion vector detection circuit 111 detects a motion vector by a representative point block matching method. This is to obtain a motion vector by moving a candidate block of a search frame within a predetermined search range and detecting a candidate block that most closely matches the reference block of the reference frame. In the motion vector detection circuit 111, as shown in FIG. 2, the reference frame is a past frame with respect to the search frame, and the input frame is the search frame.
[0044]
FIG. 3 shows the configuration of the motion vector detection circuit 111.
The motion vector detection circuit 111 includes a system controller 121 that controls the operation of the entire circuit, an input terminal 122 to which image data Di of an input frame as a search frame is input, and the image data Di as a reference frame of the next frame. And a frame memory 123 for storing the image data. Operations such as writing and reading of the frame memory 123 are controlled by the controller 121.
[0045]
The motion vector detection circuit 111 also includes a difference absolute value calculator 124._-1~ 124_-Nhave. Multiple computing units 124_-1~ 124_-NThe pixel data constituting the image data Di inputted to the input terminal 122 is commonly inputted as the pixel data Dc of the search frame, and a predetermined reference block (same timing) of the reference frame including the pixel data Dc in the search range. In this case, pixel data Dr is a maximum of two)_-1~ Dr_-NAre respectively input, and pixel data Dc and pixel data Dr_-1~ Dr_-NThe absolute value of the difference is calculated.
[0046]
In this case, as shown in FIG. 4, the pixel data (input pixel) in the search frame and the pixel data (reference pixel) in the reference frame to be subjected to a matching operation include a plurality of input pixels located within the search range. Reference pixel. The range in which the plurality of reference pixels are located has a front-back relationship with the search range of a certain reference pixel, and the search range when the input pixel is regarded as a reference pixel is inverted horizontally and vertically.
[0047]
Therefore, the plurality of reference pixels are often located over a plurality of reference blocks, and the number of pixels (representative points) in one reference block is not constant from one to all. The combination of these reference blocks and the combination of pixels in one reference block also differ depending on the position of the input pixel.
[0048]
Returning to FIG. 3, the motion vector detection circuit 111 includes a plurality of adders 125._-1~ 125_-NAnd a plurality of storage areas 126_-1~ 126_-NAnd a semiconductor memory 126 as a storage device for generating a correlation value table. Multiple adders 125_-1~ 125_-NIs a plurality of computing units 124._-1~ 124_-NThe difference absolute values obtained by the calculation are input, and a plurality of storage areas 126 of the semiconductor memory 126 are input._-1~ 126_-NEach of the stored data stored in is input and the absolute difference value is added to the stored data.
[0049]
Thus, the plurality of adders 125_-1~ 125_-NEach of the addition data obtained in the above is stored in a plurality of storage areas 126 of the semiconductor memory 126._-1~ 126_-NIs written back as stored data. The writing and reading operations of the semiconductor memory 126 are controlled by the system controller 121.
[0050]
The system controller 121 includes a plurality of computing units 124._-1~ 124_-NOf the absolute difference value in the plurality of adders 125_-1~ 125_-NOf addition in the plurality of storage areas 126 of the semiconductor memory 126_-1~ 126_-NThe writing back of the additional data into the memory is repeated a predetermined number of times, and a plurality of storage areas 126 of the semiconductor memory 126_-1~ 126_-NIn addition, control is performed so that correlation values corresponding to a plurality of candidate blocks existing in the search range of each predetermined reference block are obtained.
[0051]
In the present embodiment, as described above, the motion vector MV is detected by the representative point block matching method. As shown in FIG. 5, the representative point interval is 1 pixel every 4 × 4 pixels, the reference block size is 32 × 32 pixels, and the search range is (−15 to +16) × (−15 to +16) pixels. It is said. There are (15 + 16 + 1) × (15 + 16 + 1) = 1024 candidate blocks in the reference block search range.
[0052]
N = 64. That is, the plurality of computing units 124_-1~ 124_-N, A plurality of adders 125_-1~ 125_-N, A plurality of storage areas 126 of the semiconductor memory 126_-1~ 126_-NAre 64 each.
[0053]
Then, a plurality of arithmetic units 124_-1~ 124_-NTakes charge of calculation for obtaining correlation values corresponding to 16 candidate blocks for each reference block. In addition, a plurality of storage areas 126 of the semiconductor memory 126_-1~ 126_-NEach has a number of block storage areas corresponding to the number of reference blocks in one horizontal row of the reference frame. Further, each block storage area has 16 correlation value storage areas for obtaining the correlation values of the 16 candidate blocks.
[0054]
Here, it is assumed that the image data Di input to the input terminal 122 is based on the progressive method. The image data Di input to the input terminal 122 is a series of pixel data of each line. As shown in FIG. 5, the search range is (−15 to +16) × (−15 to +16) pixels, and the size of the reference block is 32 × 32 pixels.
[0055]
Therefore, when the line including the uppermost input pixel in the search range for a certain reference block is the first line, the line including the lowermost input pixel in the search range is the 63rd line. Therefore, in order to obtain correlation values corresponding to a plurality of candidate blocks existing in the search range of a certain reference block, 60 lines of pixel data are required. In this case, since the representative point block matching method in which the representative point interval is one pixel every 4 × 4 pixels is adopted, the pixel data of 61 to 63 lines are not used. FIG. 5 shows only one reference block. However, based on the above-described 60-line pixel data, all reference blocks for one horizontal row are classified into a plurality of candidate blocks existing in the search range. Corresponding correlation values can be obtained.
[0056]
The motion vector detection circuit 111 also has a plurality of storage areas 126 in the semiconductor memory 126 for each reference block._-1~ 126_-NThe correlation value for detecting the motion vector MV corresponding to each reference block based on the correlation value (sum of absolute differences) corresponding to each of 1024 candidate blocks existing in the search range of the reference block obtained in A table evaluator 127 and an output terminal 128 for outputting a motion vector MV detected by the evaluator 127 are provided. The evaluator 127 detects the position of the candidate block that generates the minimum correlation value as the motion vector MV.
[0057]
In the motion vector detection circuit 111 shown in FIG. 3, the system controller 121 and the adder 125_-1~ 125_-NThe semiconductor memory 126 and the correlation value table evaluator 127 constitute a motion vector detection processing unit.
[0058]
The operation of the motion vector detection circuit 111 shown in FIG. 3 will be described.
Pixel data constituting the image data Di input to the input terminal 122 is a plurality of absolute difference calculators 124 as pixel data Dc of a search frame (input frame)._-1~ 124_-NAre input in common. The image data Di is supplied to the reference frame memory 123 and stored as image data of a reference frame used in the next frame.
[0059]
Further, the pixel data Dr of the predetermined reference block of the reference frame including the pixel data Dc in the search range from the frame memory 123._-1~ Dr_-NAre entered respectively. And the calculator 124_-1~ 124_-NThen, the pixel data Dc and the pixel data Dr_-1~ Dr_-NThe difference absolute value is calculated. In this case, the arithmetic unit 124_-1~ 124_-NIn each of the above, for each reference block, an operation for obtaining correlation values corresponding to 16 candidate blocks in charge is performed.
[0060]
Also, a plurality of computing units 124_-1~ 124_-NThe difference absolute value obtained by the calculation in step S1 is a plurality of adders 125._-1~ 125_-NIs input. The plurality of adders 125_-1~ 125_-NIncludes a plurality of storage areas 126 of the semiconductor memory 126._-1~ 126_-NThe stored data stored in is input respectively.
[0061]
As described above, each storage area 126_-1~ 126_-NIncludes a number of block storage areas corresponding to the number of reference blocks in one horizontal row of the reference frame, and each block storage area further includes 16 correlation values for obtaining the correlation values of 16 candidate blocks. A storage area exists. Multiple adders 125_-1~ 125_-NThe stored data input to the calculator 124_-1~ 124_-NIs read from the correlation value storage area of the correlation value of the predetermined candidate block obtained using the absolute difference value calculated in step (1).
[0062]
Multiple adders 125_-1~ 125_-NThen, the absolute difference value is added to each stored data. In this way, the plurality of adders 125_-1~ 125_-NEach of the addition data obtained in the above is stored in a plurality of storage areas 126 of the semiconductor memory 126._-1~ 126_-NIs written back as stored data.
[0063]
The plurality of difference absolute value calculators 124 described above._-1~ 124_-NOf the absolute difference value in the plurality of adders 125_-1~ 125_-NOf addition in the plurality of storage areas 126 of the semiconductor memory 126_-1~ 126_-NThe writing back of the addition data is repeatedly performed a predetermined number of times. A plurality of storage areas 126 of the semiconductor memory 126_-1~ 126_-NCorrelation values (sum of absolute differences) corresponding to 16 candidate blocks existing in the search range of a predetermined reference block are obtained in the 16 correlation value storage areas of each block storage area.
[0064]
The correlation value table evaluator 127 includes a plurality of storage areas 126 of the semiconductor memory 126._-1~ 126_-NThe correlation values corresponding to each of the 1024 candidate blocks existing in the search range of each reference block are sequentially read out and supplied to the correlation value table evaluator 127. In the evaluator 127, the position of the candidate block that generates the minimum correlation value is detected as the motion vector MV for each reference block. Thus, the motion vector MV for each reference block detected by the evaluator 127 is sequentially output to the output terminal 128.
[0065]
As described above, based on the 60-line pixel data, correlation values corresponding to a plurality of candidate blocks existing in the search range can be obtained for all reference blocks for one horizontal row. In this case, the pixel data of the latter half of the 60-line pixel data is also used for the arithmetic processing for the reference block for the next horizontal row of the reference frame. For this reason, when the pixel data of the latter half of the line is input, it is necessary to perform the arithmetic processing for the reference block for the next horizontal line in parallel. Therefore, actually, the difference absolute value calculator 124 in the motion vector detection circuit 111 shown in FIG._-1~ 124_-N, Adder 125_-1~ 125_-NThus, at least two systems of the semiconductor memory 126 are provided.
[0066]
Next, the absolute difference calculator 124_-1~ 124_-NWill be further described. FIG. 6A shows an input pixel and computing unit 124._-1~ 124_-NThe arrangement of the operation symmetry range ((0, 0) to (7, 7)) is shown. FIG. 6B shows 64 representative points (a, a) to (h, h) in a reference block of 32 × 32 pixels. The representative point is one pixel for every 4 × 4 pixels.
[0067]
The range (calculation target range) where the reference pixel to be matched with the input pixel is calculated is divided into ranges in which the respective calculators (0, 0) to (7, 7) are in charge. The assigned range of each of the computing units (0, 0) to (7, 7) is 4 × 4 pixels. Therefore, a maximum of one representative point (corresponding reference pixel) is located in this assigned range. The relative phase between the representative point and the input pixel in one calculator is 16 types of phases 1 to 16, as shown in FIG.
[0068]
As shown in FIG. 8, when the input pixel is on the first line of the search range of the reference block and the calculation target range is on the representative point (a, a) of the reference block, 1024 candidates related to the reference block The calculation for obtaining the correlation value of the block starts. At this time, the pixel data of the representative point (a, a) is input from the frame memory 123 (shown in FIG. 3) to the arithmetic unit (7, 7). Then, the calculator (7, 7) obtains the absolute difference between the input pixel and the pixel data of the representative point (a, a). The relative phase between the input pixel and the representative point at this time is phase 1.
[0069]
Next, although not shown, after 1 to 3 pixel periods, the input pixel moves to the right by 1 to 3 pixels, and the calculation target range of the input pixel is on the right side of the representative point (a, a) of the reference block. It takes up to the 1st to 3rd pixels located in order. Also at this time, the pixel data of the representative point (a, a) is input from the frame memory 123 (shown in FIG. 3) to the calculator (7, 7). Then, the calculator (7, 7) obtains the absolute difference between the input pixel and the pixel data of the representative point (a, a). At this time, the relative phases of the input pixel and the representative point are phases 2 to 4, respectively.
[0070]
Next, as shown in FIG. 9, after the four-pixel period, the input pixel shifts to the right by four pixels, and the calculation target range of the input pixel is applied to the representative point (b, a) of the reference block. At this time, the pixel data of the representative point (b, a) is input from the frame memory 123 (shown in FIG. 3) to the calculator (7, 7). Then, the arithmetic unit (7, 7) obtains the absolute difference between the input pixel and the pixel data of the representative point (b, a). The relative phase between the input pixel and the representative point at this time is phase 1.
[0071]
At the same time, pixel data of the representative point (a, a) is input from the frame memory 123 to the calculator (6, 7). Then, the calculator (6, 7) obtains the absolute difference between the input pixel and the pixel data of the representative point (a, a). The relative phase between the input pixel and the representative point at this time is phase 1.
[0072]
In the following, for the first line, the input pixels sequentially move to the one on the right, and the arithmetic unit including the representative point in the assigned range performs the calculation of the input pixel and the representative point in parallel. In this case, the relative phase between the input pixel and the representative point shifts in the order of phase 2 → phase 3 → phase 4 → phase 1 →.
[0073]
FIG. 10 shows a state after 28 pixel periods. In this state, the input pixel shifts to the right by 28 pixels, and the calculation target range of the input pixel extends to the representative point (h, a) of the reference block. At this time, the pixel data of the representative points (h, a) to (a, a) are input from the frame memory 123 (shown in FIG. 3) to the computing units (7, 7) to (0, 7), respectively. . Then, the arithmetic units (7, 7) to (0, 7) obtain absolute differences between the input pixel and the pixel data of the representative points (h, a) to (a, a), respectively. The relative phases of the input pixel and the representative point at this time are all phase 1.
[0074]
Further, as shown in FIG. 11, when the input pixel is on the second line of the search range for the reference block, and the calculation target range is related to the representative point (a, a) of the reference block and the reference pixel adjacent thereto, The pixel data of the representative point (a, a) is input from the frame memory 123 (shown in FIG. 3) to the calculator (7, 7). Then, the calculator (7, 7) obtains the absolute difference between the input pixel and the pixel data of the representative point (a, a). The relative phase between the input pixel and the representative point at this time is phase 5.
[0075]
Next, although not shown, after 1 to 3 pixel periods, the input pixel moves to the right by 1 to 3 pixels, and the calculation target range of the input pixel is the representative point (a, a) of the reference block and below it. The first to third pixels are sequentially placed on the right side of the two adjacent reference pixels. At this time, the pixel data of the representative point (a, a) is input from the frame memory 123 (shown in FIG. 3) to the calculator (7, 7). Then, the calculator (7, 7) obtains the absolute difference between the input pixel and the pixel data of the representative point (a, a). The relative phases of the input pixel and the representative point at this time are phases 6 to 8, respectively.
[0076]
In the following, for the second line, the input pixels are sequentially shifted to the one on the right, and in the arithmetic unit including the representative point in the assigned range, the calculation of the input pixel and the representative point is performed in parallel. In this case, the relative phase between the input pixel and the representative point is a repetition of phase 5 to phase 8.
[0077]
Although not shown, the same applies to the third line and the fourth line, and the input pixels sequentially move to the one on the right, and in the arithmetic unit including the representative point in the assigned range, the input pixel and the representative point respectively. Operations are performed in parallel. In this case, for the third line, the relative phase between the input pixel and the representative point is a repetition of phase 9 to phase 12. On the other hand, for the fourth line, the relative phase between the input pixel and the representative point is a repetition of phase 13 to phase 16.
[0078]
As shown in FIG. 12, the input pixel is on the fifth line of the search range for the reference block, and the calculation target range is 5 from the representative point (a, a) to the representative point (a, b) of the reference block. When the number of reference pixels is applied, the pixel data of the representative point (a, b) is input from the frame memory 123 (shown in FIG. 3) to the calculator (7, 7). Then, the calculator (7, 7) obtains the absolute difference between the input pixel and the pixel data of the representative point (a, b). The relative phase between the input pixel and the representative point at this time is phase 1.
[0079]
At the same time, pixel data of the representative point (a, a) is input from the frame memory 123 to the calculator (7, 6). Then, the calculator (7, 6) obtains the absolute difference between the input pixel and the pixel data of the representative point (a, a). The relative phase between the input pixel and the representative point at this time is phase 1.
[0080]
Next, although not shown, after 1 to 3 pixel periods, the input pixel shifts to the right by 1 to 3 pixels, and the calculation target range of the input pixel is the representative point (a, a), (a , B) to the first to third pixels located in order on the right side of the five reference pixels. At this time, the pixel data of the representative point (a, b) is input from the frame memory 123 to the calculator (7, 7). Then, the calculator (7, 7) obtains the absolute difference between the input pixel and the pixel data of the representative point (a, b). At this time, the relative phases of the input pixel and the representative point are phases 2 to 4, respectively.
[0081]
At the same time, pixel data of the representative point (a, a) is input from the frame memory 123 to the calculator (7, 6). Then, the calculator (7, 6) obtains the absolute difference between the input pixel and the pixel data of the representative point (a, a). At this time, the relative phases of the input pixel and the representative point are phases 2 to 4, respectively.
[0082]
The same is true for the following 6th to 60th lines, and the input pixels move to the next one on the right sequentially, and in the computing unit including the representative point in the assigned range, the calculation of the input pixel and the representative point is performed in parallel. Done. In this case, the relative phase between the input pixel and the representative point is the repetition of the phase 5 to phase 8 for the sixth line, the repetition of the phases 9 to 12 for the seventh line, and the repetition of the phases 13 to 16 for the eighth line. The ninth line is a repetition of phase 1 to phase 4, and so on. That is, regarding the relative phase between the input pixel and the representative point, the relationship of the first line to the fourth line is repeated in the following lines.
[0083]
In FIG. 13, the input pixel is on the 29th line of the search range for the reference block, and the calculation target range is 29 reference pixels from the representative point (a, a) to the representative point (a, h) of the reference block. This shows the state. In this state, pixel data of representative points (a, h) to (a, a) are input from the frame memory 123 (shown in FIG. 3) to the arithmetic units (7, 7) to (7, 0). . Then, the arithmetic units (7, 7) to (7, 0) obtain the absolute difference value between the input pixel and the pixel data of the representative points (a, h) to (a, a). The relative phase between the input pixel and the representative point at this time is phase 1.
[0084]
FIG. 14 shows a state in which the input pixel is in the 60th line of the search range for the reference block, and the calculation target range covers four reference pixels including the lower left representative point (a, h) of the reference block. ing. In this state, pixel data of the representative point (a, h) is input from the frame memory 123 (shown in FIG. 3) to the calculator (7, 0). Then, the arithmetic unit (7, 0) obtains the absolute difference value between the input pixel and the pixel data of the representative point (a, h). At this time, the relative phase between the input pixel and the representative point is the phase 13.
[0085]
FIG. 15 shows each arithmetic unit 124 described above._-1~ 124_-NThe process of calculating the absolute difference of each line in ((0, 0) to (7, 7)) is shown. In each of the calculators (0, 0) to (7, 7), an absolute difference calculation relating to the phases 1 to 16 is performed in relation to a certain reference block. Further, the difference absolute value calculation relating to each phase is 64 times. That is, in each of the calculators (0, 0) to (7, 7), 64 differential absolute calculations are performed to obtain correlation values of 16 candidate blocks existing in the search range for a certain reference block. .
[0086]
FIG. 16 shows a reference block of 32 × 32 pixels. As described above, one pixel for every 4 × 4 pixels is used as a representative point for the matching calculation. In FIG. 6B, 64 representative points are represented as (a, a) to (h, h), but here, each is represented by a number from 1 to 64.
[0087]
FIG. 17 shows a calculation process in the calculator (7, 7) as an example. The numerical value in the upper stage indicates which of the phases 1 to 16 is used for the calculation. The numerical values in the lower row indicate the representative points of the reference block that are calculated at that time. As is clear from this figure, in the computing units (7, 7), the absolute difference calculation relating to phase 1 to phase 16 is performed 64 times. Each 64 times absolute difference calculation is an operation with 64 representative points of each reference block.
[0088]
FIG. 18 shows a motion vector (coordinates of a search range with respect to one reference pixel). In the reference block search range, there are 1024 candidate blocks corresponding to the respective motion vectors (x, y). FIG. 19 shows positions (addresses) where correlation values of candidate blocks corresponding to each motion vector are stored in an area corresponding to one reference block in the semiconductor memory 126.
[0089]
This figure also shows the correlation values of the 16 candidate blocks corresponding to which motion vector by the absolute difference calculation relating to phase 1 to phase 16 in each of the calculators (0, 0) to (7, 7). It shows whether a difference absolute value for obtaining is obtained.
[0090]
For example, (-15, -15) to (-12, -15), (-15, -14) to (- 12, -14), (-15, -13) to (-12, -13), (-15, -12) to (-12, -12) of candidate blocks corresponding to 16 motion vectors The absolute difference value for obtaining the value is obtained.
[0091]
Similarly, (-11, -15) to (-8, -15), (-11, -14) to (-11) are calculated by calculating the absolute difference values relating to the phases 1 to 16 in the calculators (6, 7), respectively. -8, -14), (-11, -13) to (-8, -13), (-11, -12) to (-8, -12) of candidate blocks corresponding to 16 motion vectors An absolute difference value for obtaining a correlation value is obtained.
[0092]
Hereinafter, similarly, each of the calculators (5, 7) to (7, 7) is included in each 8 × 8 rectangular range obtained by dividing the reference pixel search range horizontally and vertically into 8 equal parts, respectively. The difference absolute value for obtaining the correlation value of the candidate block corresponding to the 16 motion vectors.
[0093]
Note that each computing unit 124 corresponds to a certain reference block._-1~ 124_-NIn ((0, 0) to (7, 7)), the calculation is performed as described above. In parallel with the calculation related to a certain reference block, the calculation is performed in the horizontal direction with respect to the certain reference block (reference block P). An operation relating to a reference block adjacent to is also performed.
[0094]
That is, as is clear from FIG. 15, it can be seen that the calculation for the reference block P and the calculation for the reference blocks P-1 and P + 1 before and after the calculation are performed in time.
[0095]
For example, the calculation regarding the reference block P is performed using 60 pixels of each line. In this case, the search range for one reference block is 63 pixels in the horizontal direction, but the representative point block matching method in which the representative point interval is 1 pixel every 4 × 4 pixels is adopted. This pixel data is not used.
[0096]
Here, when the 1st to 28th pixels are used, the calculation for the reference block P is performed, and the calculation for the reference block P-1 is performed in parallel therewith. Similarly, when the 33rd to 60th pixels are used, an operation related to the reference block P is performed, and an operation related to the reference block P + 1 is performed in parallel therewith. When the 29th to 32nd pixels are used, only the calculation for the reference block P is performed.
[0097]
For example, when the 1st to 4th pixels are used in the first line, the arithmetic unit (7, 7) performs an operation related to the reference block P, but the arithmetic units (6, 7) to (0, 7) refer to it. An operation relating to block P-1 is performed. Further, for example, when the 33rd to 36th pixels are used in the first line, the arithmetic units (6, 7) to (0, 7) perform arithmetic operations on the reference block P, but the arithmetic units (7, 7). Then, the calculation for the reference block P + 1 is performed.
[0098]
For example, when the 1st to 4th pixels are used on the 29th line, the computing units (7, 7), (7, 6),..., (7, 0) perform computations on the reference block P. However, the arithmetic units (6, 7) to (0, 7), (6, 6) to (0, 6), ..., (6, 0) to (0, 0) relate to the reference block P-1. An operation is performed. For example, when the 33rd to 36th pixels are used on the 29th line, the arithmetic units (6, 7) to (0, 7), (6, 6) to (0, 6),. 6, 0) to (0, 0), the calculation related to the reference block P is performed. In the calculators (7, 7), (7, 6), ..., (7, 0), the calculation related to the reference block P + 1. Is done.
[0099]
As described above, the plurality of storage areas 126 of the semiconductor memory 126._-1~ 126_-NEach has a number of block storage areas corresponding to the number of reference blocks in one horizontal row of the reference frame. Further, each block storage area has 16 correlation value storage areas for obtaining the correlation values of the 16 candidate blocks of phases 1 to 16.
[0100]
As described above, the plurality of adders 125_-1~ 125_-NThen, each of the plurality of storage areas 126 of the semiconductor memory 126 will be described._-1~ 126_-NIs stored in the stored data._-1~ 124_-NThe difference absolute value obtained by calculation in ((0, 0) to (7, 7)) is added. In this way, the plurality of adders 125_-1~ 125_-NEach of the addition data obtained in the above is stored in a plurality of storage areas 126 of the semiconductor memory 126._-1~ 126_-NIs written back as stored data.
[0101]
In each of the calculators (0, 0) to (7, 7), as described above, calculations related to one or two reference blocks are performed according to the input pixel. Accordingly, the plurality of adders 125_-1~ 125_-NThe storage data added by is selectively from one or two block storage areas depending on which reference block the calculation performed by each of the calculators (0, 0) to (7, 7) relates to. Read out. Also, a plurality of adders 125_-1~ 125_-NThe addition data obtained in (1) is selectively written back as storage data in the one or two block storage areas.
[0102]
Therefore, the semiconductor memory 126 has a plurality of adders 125 in the column direction._-1~ 125_-NAre configured to be independently accessible in units of predetermined memory cells.
[0103]
Next, a detailed configuration of the semiconductor memory 126 will be described. FIG. 20 shows the overall configuration of the semiconductor memory 126. The semiconductor memory 126 includes eight memory units 150._-1~ 150_-8It is composed of Each memory unit 150_-1~ 150_-8Each includes a row decoder 151 for reading, eight storage areas, a main row decoder 153 for addition, and a sub-row decoder 154 for addition.
[0104]
Memory unit 150_-1150_-2, 150_-3, 150_-Four, 150_-Five, 150_-6, 150_-7, 150_-8Each of the eight storage areas is an adder 125._-1~ 125_-8, 125_-9~ 125_-16, 125_-17~ 125_{-twenty four}, 125_{-twenty five}~ 125_-32, 125_-33~ 125_-40, 125_-41~ 125_-48, 125_-49~ 125_-56, 125_-57~ 125_-64Storage areas 126 respectively corresponding to_-1~ 126_-8126_-9~ 126_-16126_-17~ 126_{-twenty four}126_{-twenty five}~ 126_-32126_-33~ 126_-40126_-41~ 126_-48126_-49~ 126_-56126_-57~ 126_-64(N = 64).
[0105]
In addition, as described above, the 64 storage areas 126_-1~ 126_-64Each has a number of block storage areas BM corresponding to the number of reference blocks in one horizontal row of the reference frame. Further, each block storage area BM has 16 correlation value storage areas for obtaining the correlation values of the 16 candidate blocks of phases 1 to 16.
[0106]
FIG. 21 shows the 64 storage areas 126 described above._-1~ 126_-64Is shown in more detail. Each memory unit 150_-1~ 150_-88 storage areas (for example, 126_-1~ 126_-8) Is configured by arranging 16m memory cells in the row direction (m is the number of reference blocks in one horizontal row) and 8n (n is the number of output bits of the adder) in the column direction.
[0107]
As described above, the difference absolute value calculation regarding a certain reference block (reference block P) is performed using the pixel data of the first line to the 60th line. For example, when calculation is performed using the pixel data of the first to fourth lines, the storage area 126_-57~ 126_-64Is added using the stored data, and the added data is written back to the same storage location. When the calculation using the pixel data of the 15th pixel is performed on the first line (corresponding to phase 3), the calculations performed by the calculators (7, 7) to (4, 7) are calculations related to the reference block P. The operations performed by the calculators (3, 7) to (0, 7) are operations related to the reference block P-1. Therefore, the storage area 126_-57~ 126_-64For example, the storage data at the storage positions indicated by the checkered pattern in FIG. 21 (first line) is used for addition, and the obtained addition data is written back to the same storage position.
[0108]
For example, when calculation is performed using the pixel data of the 29th to 32nd lines, the storage area 126 is stored._-1~ 126_-64Is added using the stored data, and the added data is written back to the same storage location. When calculation is performed using the pixel data of the 22nd pixel in the 29th line (corresponding to phase 2), the calculators (7, 7) to (2, 7), (7, 6) to (2, 6) , (7,5) to (2,5), (7,4) to (2,4), (7,3) to (2,3), (7,2) to (2,2), ( 7, 1) to (2, 1), (7, 0) to (2, 0) are operations related to the reference block P, and the arithmetic units (1, 7) to (0, 7), ( 1,6)-(0,6), (1,5)-(0,5), (1,4)-(0,4), (1,3)-(0,3), (1, 2) to (0, 2), (1, 1) to (0, 1), and (1,0) to (0, 0) are operations related to the reference block P-1. Therefore, the storage area 126_-1~ 126_-64For example, the storage data at the storage positions indicated by the checkered pattern in FIG. 21 (29th line) is used for addition, and the obtained addition data is written back to the same storage position.
[0109]
In this embodiment, a plurality of adders 125 are used._-1~ 125_-NAnd the semiconductor memory 126 are integrated, and a plurality of adders 125 are integrated._-1~ 125_-NThe plurality of adders in bit units constituting the same are arranged in alignment with the column pitch of the semiconductor memory 126.
[0110]
FIG. 22 shows the adder 125_-1And the storage area 126 of the semiconductor memory 126 corresponding thereto_-1The detailed structure of the part is shown. Although not described, the adder 125_-2~ 125_-NAnd the storage area 126 of the semiconductor memory 126 corresponding thereto_-2~ 126_-NThis part is similarly configured.
[0111]
In FIG. 22, the storage area 126_-1, N memory cells 130 in the column direction and X + 1 (X = 16m−1) in the row direction are arranged in a matrix. In this case, a correlation value storage area of one candidate block is constituted by n memory cells 130 in each row extending in the column direction.
[0112]
FIG. 23 shows a configuration example of the memory cell 130. The memory cell 130 has a two-port configuration having a first port for writing and reading and a second port dedicated for reading.
[0113]
A P-type MOS transistor Q1 and an N-type MOS transistor Q3, which are load elements, are connected in series between a power source and a ground to form a CMOS inverter 11, and a P-type MOS transistor Q2 and an N-type MOS transistor, which are load elements, A CMOS inverter 12 is formed by connecting the type MOS transistor Q4 in series between the power source and the ground. The outputs of the CMOS inverters 11 and 12, that is, the potentials of the storage nodes N1 and N2, are the inputs of the other CMOS inverters 12 and 11, that is, the gate inputs of the N-type MOS transistors Q4 and Q3.
[0114]
The storage node N1 of the CMOS inverter 11 is connected to the terminal 14 via an access transistor Q5 whose gate is connected to the terminal 13. On the other hand, the storage node N2 of the CMOS inverter 12 is connected to the terminal 15 via an access transistor Q6 whose gate is connected to the terminal 13. The word line WL is connected to the terminal 13, the bit line BL is connected to the terminal 14, and the bit line / BL (/ BL represents BL bar) is connected to the terminal 15.
[0115]
N-type MOS transistors Q7 and Q8 are connected in series, one end thereof is grounded, and the other end is connected to the terminal 16. The gate of transistor Q7 is connected to storage node N1, and the gate of transistor Q8 is connected to terminal 17. A read-only bit line BRL is connected to the terminal 16, and a read-only word line WRL is connected to the terminal 17.
[0116]
In such a memory cell 130, data “1” or “0” is stored in the memory cell portion formed by the pair of CMOS inverters 11 and 12. Then, read and write data transfer is performed between the memory cell portion and the bit lines BL and / BL via the access transistors Q5 and Q6. Further, read data transfer is performed between the memory cell portion and the read-only bit line BRL via the access transistor Q8.
[0117]
The configuration example of the memory cell 130 shown in FIG. 23 is based on an SRAM (Static Random Access Memory) cell, but other memory cells such as a DRAM (Dynamic Random Access Memory), FeRAM (Ferro-electric), and the like. Random Access Memory (Random Access Memory), MRAM (Magnetic Random Access Memory) or the like may be used as a base.
[0118]
Returning to FIG. 22, along the memory cells 130 in each row aligned in the column direction, the word line WL₀~ WL_X(These word lines correspond to section word lines to be described later), and read-only word line WRL₀~ WRL_XIs arranged. As described above, the word line WL₀~ WL_XAre connected to the terminal 13 of the memory cell 130 and read-only word line WRL.₀~ WRL_XIs connected to the terminal 17 of the memory cell 130.
[0119]
In addition, along the memory cells 130 in each column aligned in the row direction, the bit line BL₀~ BL_n-1, / BL₀~ / BL_n-1, And read-only bit line BRL₀~ BRL_n-1Is arranged. As described above, the bit line BL₀~ BL_n-1Is connected to the terminal 14 of the memory cell 130 and the bit line / BL₀~ / BL_n-1Are connected to the terminal 15 of the memory cell 130 and read-only bit line BRL.₀~ BRL_n-1Is connected to the terminal 16 of the memory cell 130.
[0120]
This read-only bit line BRL₀~ BRL_n-1Before entering the read mode by the bit line BRL₀~ BRL_n-1Must be precharged. Therefore, the bit line BRL₀Is connected to the power supply via a P-type MOS transistor Q41. The gate of the transistor Q41 has a precharge control signal / φ_RPC(/ Φ_RPCIs φ_RPCRepresents the precharge control signal φ_RPCIs inverted). Bit line BRL₁~ BRL_n-1It is configured in the same way.
[0121]
In addition, the memory area 126_-1Sense amplifier SA corresponding to each column of memory cells 130 arranged in the row direction.₀~ SA_n-1Is arranged. Each sense amplifier SA₀~ SA_n-1Are bit lines BL respectively.₀~ BL_n-1, / BL₀~ / BL_n-1It is connected to the. As a result, the storage area 126_-1Bit line pair BL from memory cells 130 in each column aligned in the row direction₀, / BL₀~ BL_n-1, / BL_n-1And sense amplifier SA₀~ SA_n-1Storage data MD via₀~ MD_n-1Is read out.
[0122]
Here, the sense amplifier SA₀Details of the configuration of this part will be described.
Bit line BL₀Is connected to the gate of the N-type MOS transistor Q22 via the P-type MOS transistor Q21. Also, bit line / BL₀Is connected to the gate of the N-type MOS transistor Q24 via the P-type MOS transistor Q23. The sources of the transistors Q22 and Q24 are connected to each other, and the connection point is grounded via the N-type MOS transistor Q25. The gates of the transistors Q21 and Q23 are connected to the read control signal / φ._R(/ Φ_RIs φ_RRepresents the bar, and the read control signal φ_RAnd the equalization control signal / φ is applied to the gate of the transistor Q25._EQ(/ Φ_EQIs φ_EQRepresents the equalization control signal φ_EQIs inverted).
[0123]
The drain of the transistor Q22 is connected to a power supply via a parallel circuit of P-type MOS transistors Q26 and Q27, and the drain of the transistor Q24 is connected to a power supply via a parallel circuit of P-type MOS transistors Q28 and Q29. The drain of transistor Q22 is connected to the gate of transistor Q29, and the drain of transistor Q24 is connected to the gate of transistor Q27. The equalization control signal / φ is applied to the gates of the transistors Q26 and Q28._EQIs entered.
[0124]
Before entering the read mode, the bit line pair BL₀, / BL₀Must be equalized (precharged). Therefore, the bit line BL₀Is connected to the power supply via a P-type MOS transistor Q31, and the bit line / BL₀Is connected to the power supply via a P-type MOS transistor Q32 and the bit line BL₀, / BL₀Are connected via a P-type MOS transistor Q33. The equalization control signal / φ is applied to the gates of the transistors Q31 to Q33._EQIs entered.
[0125]
Sense amplifier SA₂~ SA_n-1The configuration of this part is also the above-described sense amplifier SA.₀This is the same as the configuration of the part.
[0126]
Further, as described above, the n memory cells 130 in each row extending in the column direction form a correlation value storage area of one candidate block. Before starting to sequentially add the candidate block addition data in the predetermined correlation value storage area, it is necessary to clear the storage data of the memory cells 130 constituting the predetermined correlation value storage area. Therefore, the bit line pair BL₀, / BL₀~ BL_n-1, / BL_n-1Corresponding to each of the above, data “0” is generated, and this data is supplied to the memory cell 130 as write data.
[0127]
That is, the bit line BL₀Are grounded via an N-type MOS transistor Q51. The clear control signal φ is supplied to the gate of the transistor Q51._CLRIs entered. Bit line pair BL₁, / BL₁~ BL_n-1, / BL_n-1This part is also configured in the same manner.
[0128]
Also, adder 125_-1Are n adders 140 for adding each bit of n bits.₀~ 140_n-1These n adders 140₀~ 140_n-1Is the memory area 126_-1It is arranged in line with the pitch of the column.
[0129]
Adder 140₀~ 140₇The difference absolute value calculator 124 is connected to each A-side input terminal._-18-bit difference absolute value bit data from₀~ D₇Is entered. Also, the adding unit 140₈~ 140_n-1Each A side input terminal is grounded, and "0" is input. Meanwhile, the addition unit 140₀~ 140_n-1These adders 140 are connected to the input terminals on the B side.₀~ 140_n-1Corresponding to each of the storage areas 126_-1From the memory cells 130 arranged in the row direction of the bit line pair BL₀, / BL₀~ BL_n-1, / BL_n-1And sense amplifier SA₀~ SA_n-1Data MD read via₀~ MD_n-1Are entered respectively.
[0130]
Adder 140₀The non-inverting output terminal S is connected to the gate of the N-type MOS transistor Q11. The drain of the transistor Q11 is connected to the adding unit 140.₀Corresponding to the bit lines / BL connected to the memory cells 130 arranged in the row direction.₀Connected to. On the other hand, the adding unit 140₀Inverted output terminal / S (/ S represents S bar) is connected to the gate of N-type MOS transistor Q12. The drain of the transistor Q12 is connected to the adding unit 140.₀Corresponding to the bit line BL connected to the memory cells 130 arranged in the row direction.₀Connected to.
[0131]
The sources of the transistors Q11 and Q12 are connected to each other, and the connection point is grounded via a series circuit of N-type MOS transistors Q13 and Q14. A write control signal φ is applied to the gate of the transistor Q14._WIs added to the gate of the transistor Q13._n-1Carry output terminal C_OUTMSB (Most Significant Bit) carry output C_MSBIs input via the inverter 141.
[0132]
Adder 140₁~ 140_n-1The configuration of the output terminals S, / S side of the adder 140 is also described above.₀This is the same as the configuration on the output terminals S, / S side.
[0133]
Also, the adding unit 140₀Carry input terminal C_INIs grounded and "0" is input. Also, the adding unit 140₀~ 140_n-2Carry output terminal C_OUTRespectively, adder 140₁~ 140_n-1It is connected to the. Thus, the adding unit 140₀~ 140_n-1Constitutes an n-bit adder.
[0134]
Also, bit line / BL₀Are grounded via N-type MOS transistors Q61 and Q62. The clear control signal / φ is applied to the gate of the transistor Q61._CLR(/ Φ_CLRIs φ_CLRRepresents the bar and the clear control signal φ_CLRIs added to the gate of the transistor 62._n-1Carry output terminal C_OUTMSB carry output C obtained_MSBIs entered.
[0135]
Adder 125 shown in FIG._-1And storage area 126_-1The operation of this part will be described.
First, a correlation value storage area of one candidate block is configured by n memory cells 130 in each row extending in the column direction, but the storage data of the memory cells 130 constituting a predetermined correlation value storage area is cleared. The operation will be described.
[0136]
When clearing the stored data of the memory cell 130 constituting the predetermined correlation value storage area, the write control signal φ_WAnd clear control signal φ_CLRIs active, that is, “1”, and the read control signal φ_RAnd equalize control signal φ_EQIs inactive, ie, “0”, and the word line WL₀~ WL_XAmong these, the word line corresponding to a predetermined correlation value storage area is activated.
[0137]
In this case, the clear control signal φ_CLRIs activated and the transistor Q51 is turned on. Therefore, data “0” is generated, and this data is stored in the bit line BL.₀~ BL_n-1Is output. Therefore, by activating a word line corresponding to a predetermined correlation value storage area, data “0” is written in n memory cells 130 constituting the predetermined correlation value storage area, and the stored data Clearing is performed.
[0138]
Next, storage data MD stored in a predetermined correlation value storage area₀~ MD_n-18 bits of absolute difference D₀~ D₇, Adder 125_-1(Adder 140₁~ 140_n-1) And adder 125_-1Addition data AD obtained in₀~ AD_n-1Will be described for the operation of writing back to the predetermined correlation value storage area.
[0139]
Storage data MD stored in a predetermined correlation value storage area₀~ MD_n-18 bits of absolute difference D₀~ D₇First, equalize control signal φ_EQIs active, that is, “1”, and the write control signal φ_WRead control signal φ_RAnd clear control signal φ_CLRIs inactive, ie, “0”, and the bit line pair BL₀, / BL₀~ BL_n-1, / BL_n-1Is equalized (precharged).
[0140]
In this case, the bit line pair BL₀, / BL₀Is equalized control signal φ_EQIs activated, all of the transistors Q31 to Q33 are turned on, and the bit line BL₀And bit line / BL₀The power supply potential is applied to the bit lines BL.₀And bit line / BL₀Are at the same potential. Other bit line pairs BL₁, / BL₁~ BL_n-1, / BL_n-1The same applies to.
[0141]
In this way, the bit line pair BL₀, / BL₀~ BL_n-1, / BL_n-1In the state where equalization is performed, the read control signal φ_RIs active, that is, “1”, and the write control signal φ_W, Equalize control signal φ_EQAnd clear control signal φ_CLRIs inactive, ie, “0”, and the word line WL₀~ WL_XAmong these, the word line corresponding to a predetermined correlation value storage area is activated.
[0142]
Thereby, the storage data MD of the n memory cells 130 constituting the predetermined correlation value storage area₀~ MD_n-1Are bit line pairs BL₀, / BL₀~ BL_n-1, / BL_n-1And sense amplifier SA₀~ SA_n-1And the adder 140₀~ 140_n-1Are respectively input to the B side input terminals. Therefore, the stored data MD stored in the predetermined correlation value storage area₀~ MD_n-18 bits of absolute difference D₀~ D₇Is added.
[0143]
Then, the adding unit 140₀~ 140_n-1Addition output at, that is, addition data AD₀~ AD_n-1When becomes effective, write control signal φ_WIs active, that is, “1”, and the read control signal φ_R, Equalize control signal φ_EQAnd clear control signal φ_CLRIs inactive, ie, “0”, and the word line WL₀~ WL_XAmong these, the word line corresponding to a predetermined correlation value storage area is activated.
[0144]
In this case, the adding unit 140₀The additional data S for the part₀Is "1", the transistor Q11 is on, the transistor Q12 is off, and the bit line / BL₀Since “0” is output to the adder 140, the adder 140 out of the n memory cells 130 constituting the predetermined correlation value storage area.₀Data “1” is stored in the memory cell 130 corresponding to. Meanwhile, the addition unit 140₀The additional data S for the part₀Is "0", the transistor Q11 is off, the transistor Q12 is on, and the bit line BL₀Since “0” is output to the adder 140, the adder 140 out of the n memory cells 130 constituting the predetermined correlation value storage area.₀Data “0” is stored in the memory cell 130 corresponding to.
[0145]
Other adder 140₁~ 140_n-1The same applies to the portion of. Thus, the adder 125_-1Addition data AD obtained in₀~ AD_n-1Is written back to n memory cells 130 constituting a predetermined correlation value storage area.
[0146]
In addition, in the case of overflow in the adding operation, the adding unit 140_n-1Carry output terminal C_OUTMSB carry output C obtained_MSBBecomes “1”, the transistor Q13 is turned off, and the additional data AD₀~ AD_n-1However, it is not written in the n memory cells 130 constituting the predetermined correlation value storage area.
[0147]
Instead, in this case, in addition to the transistor Q61 being turned on, the transistor Q62 is also turned on, so that the bit line / BL₀~ / BL_n-1In this case, a signal of “0” is output. Therefore, data “1” is written in each of the n memory cells 130 constituting the predetermined correlation value storage area. That is, the maximum value is stored in the predetermined correlation value storage area.
[0148]
Next, an operation for reading out final addition data corresponding to a reference block, that is, a correlation value (sum of absolute differences) stored in a predetermined correlation value storage area will be described.
[0149]
First, precharge control signal / φ_RPCIs active, ie, “1”, and the read-only bit line BRL₀~ BRL_n-1Is precharged. In this case, the transistor Q41 is turned on, and the read-only bit line BRL₀~ BRL_n-1The potential of the power supply is applied to each of the above.
[0150]
In this way, the read-only bit line BRL₀~ BRL_n-1Read-only word line WRL in the precharge state₀~ WRL_XAmong these, the read-only word line corresponding to the predetermined correlation value storage area is activated. As a result, the storage data Σ of the n memory cells 130 constituting the predetermined correlation value storage area₀~ Σ_n-1Are read-only bit lines BRL, respectively.₀~ BRL_n-1Is obtained. Here, the stored data Σ₀~ Σ_n-1Constitutes an n-bit correlation value (difference absolute value sum).
[0151]
Next, the memory unit 150_-1~ 150_-8The addition main row decoder 153 and the addition sub row decoder 154 will be further described.
As described above, the memory unit 150_-1, The plurality of memory cells 130 arranged in the column direction are converted into a difference absolute value calculator 124._-1~ 124_-8Each of ((0,0)-(7,0)), and therefore the adder 125_-1~ 125_-8It is necessary to independently access every n sections corresponding to each of. Therefore, the memory unit 150_-1The row position to be accessed is designated by the main row decoder 153, and the section to be accessed is designated from among the eight sections at the designated row position by the sub row decoder 154.
[0152]
In addition, as described above, the memory unit 150_-1In this case, it is necessary to simultaneously access two row positions existing in the block storage area BM corresponding to two reference blocks. In that case, it is necessary to access different sections in the column direction at the two row positions. Therefore, the memory unit 150_-1In FIG. 2, two row positions to be accessed are simultaneously designated by the main row decoder 153, and different sections are designated in the column direction at the two designated row positions by the sub row decoder 154.
[0153]
The above is the description of the memory unit 150._-2~ 150_-8The same applies to. Hereinafter, the memory unit 150_-1Referring to FIG. 24, a specific example of the main row decoder 153 and the sub row decoder 154, and further a word line configuration will be described. Here, the description will focus on the storage area corresponding to the reference block P and the storage area corresponding to the reference block P + 1 adjacent thereto, but the storage areas corresponding to the other reference blocks are configured by repeating those storage areas. It has become.
[0154]
In the figure, global word lines WL continuous in the column direction._i, WL_{i + 1}, WL_{i + 2}, WL_{i + 3},... Are arranged in a storage area corresponding to the reference block P. Global word line WL_i, WL_{i + 1}, WL_{i + 2}, WL_{i + 3},..., Section word lines WLs as divided word lines divided for each section.₀, WLs₁, WLs₂, ..., WLs₇(WLs₀, WLs₁, WLs₂Only shown).
[0155]
In addition, global word lines WL continuous in the column direction_{i + 16}, WL_{i + 17}, WL_{i + 18}, WL_{i + 19},... Are arranged in a storage area corresponding to the reference block P + 1. Global word line WL_{i + 16}, WL_{i + 17}, WL_{i + 18}, WL_{i + 19},..., Section word lines WLs as divided word lines divided for each section.₀, WLs₁, WLs₂, ..., WLs₇(WLs₀, WLs₁, WLs₂Only shown).
[0156]
Here, one section word line corresponds to one correlation value storage area existing in a certain block storage area BM. N memory cells 130 arranged in the column direction are connected to this one section word line. The section word line WLs₀, WLs₁, WLs₂, ..., WLs₇In the storage area 126, respectively._-1126_-2126_-3, ..., 126_-8It corresponds to.
[0157]
The main row decoder 153 includes a row decoder RDEC, and an OR gate and a NOR gate arranged corresponding to each global word line.
[0158]
Global word line WL in the storage area corresponding to the reference block P_i, WL_{i + 1}, WL_{i + 2}, WL_{i + 3}OR gate GT corresponding to_i, GT_{i + 1}, GT_{i + 2}, GT_{i + 3}Are arranged. These or gates GT_i, GT_{i + 1}, GT_{i + 2}, GT_{i + 3},... Are connected to the global word line WL, respectively._i, WL_{i + 1}, WL_{i + 2}, WL_{i + 3},···It is connected to the.
[0159]
Global word line WL in the storage area corresponding to reference block P + 1_{i + 16}, WL_{i + 17}, WL_{i + 18}, WL_{i + 19}In response to NOR gate GT_{i + 16}, GT_{i + 17}, GT_{i + 18}, GT_{i + 19}Are arranged. These NOR gates GT_{i + 16}, GT_{i + 17}, GT_{i + 18}, GT_{i + 19},... Are respectively connected to the global word lines WL._{i + 16}, WL_{i + 17}, WL_{i + 18}, WL_{i + 19},···It is connected to the.
[0160]
The row decoder RDEC has a signal output terminal and an inverted signal output terminal corresponding to each global word line. Global word line WL_i, WL_{i + 1}, WL_{i + 2}, WL_{i + 3}The signals ("1" or "0") output to the signal output terminals corresponding to._i, GT_{i + 1}, GT_{i + 2}, GT_{i + 3},... Are supplied to one input side. These or gates GT_i, GT_{i + 1}, GT_{i + 2}, GT_{i + 3},... Are inverted and supplied to the inverted signal output terminal of the row decoder RDEC corresponding to the global word line in the storage area corresponding to the reference block P-1. .
[0161]
The global word line WL_{i + 16}, WL_{i + 17}, WL_{i + 18}, WL_{i + 19}The signals ("1" or "0") output to the inverted signal output terminals corresponding to._{i + 16}, GT_{i + 17}, GT_{i + 18}, GT_{i + 19},... Are inverted and supplied to one input side. These NOR gates GT_{i + 16}, GT_{i + 17}, GT_{i + 18}, GT_{i + 19},... On the other input side, the global word line WL of the storage area corresponding to the reference block P, respectively._i, WL_{i + 1}, WL_{i + 2}, WL_{i + 3},..., The signals output to the signal output terminals of the row decoder RDEC are supplied as they are.
[0162]
The sub-row decoder 154 includes AND gates arranged corresponding to the section word lines. The output side of each AND gate is connected to the corresponding section word line. For each section word line of the storage area corresponding to the reference block P, the AND gate AG_PIs arranged. Each AND gate AG_PA signal (“1” or “0”) obtained on the corresponding global word line is supplied to one of the input sides. For each section word line in the storage area corresponding to the reference block P + 1, each AND gate AG_{P + 1}Is arranged. Each AND gate AG_{P + 1}A signal (“1” or “0”) obtained on the corresponding global word line is inverted and supplied to one input side of the.
[0163]
And gates AG lined up in the row direction_P, AG_{P + 1}In the buffer BF₀, BF₁, BF₂, ..., BF₇(BF₀, BF₁, BF₂A common control signal ("1" or "0") is supplied via only the figure. In this case, the control signal is AND gate AG_PIs supplied as is, but Andgate AG_{P + 1}Inverted and supplied.
[0164]
In the above configuration, a predetermined global word line in the storage area corresponding to the reference blocks P and P + 1, for example, WL_{i + 2}, WL_{i + 18}And the global word line WL_{i + 2}Section word lines WLs corresponding to₀, WLs₁And the global word line WL_{i + 18}Section word lines WLs corresponding to₂~ WLs₇The operation when activating is described.
[0165]
In this case, the row decoder RDEC uses the global word line WL._i, WL_{i + 1}, WL_{i + 2}, WL_{i + 3}.. Among the signal output terminals corresponding to..._{i + 2}"1" is output to the signal output terminal corresponding to the above, and "0" is output to the other signal output terminals. The row decoder RDEC is a global word line WL._{i + 16}, WL_{i + 17}, WL_{i + 18}, WL_{i + 19},... Are output to all of the signal output terminals corresponding to. In this case, “1” is output to all the signal output terminals corresponding to the global word lines in the storage area corresponding to the reference block P-1.
[0166]
As a result, OR gate GT_{i + 2}"1" is obtained on the output side of the OR gate GT._{i + 2}Global word line WL connected to the output side of_{i + 2}Is activated. At the same time, the NOR gate GT_{i + 18}"0" is obtained on the output side of the NOR gate GT._{i + 18}Global word line WL connected to the output side of_{i + 18}Is activated.
[0167]
The section word line WLs₀, WLs₁AND gates AG lined up in the row direction_P, AG_{P + 1}"1" is input as a control signal respectively. The section word line WLs₂~ WLs₇AND gates AG lined up in the row direction_P, AG_{P + 1}"0" is input as a control signal respectively.
[0168]
As a result, the global word line WL_{i + 2}Of the seven section word lines corresponding to the section word line WLs₀, WLs₁Only “1” is applied and activated. At the same time, the global word line WL_{i + 18}Of the seven section word lines corresponding to the section word line WLs₂~ WLs₇Only “1” is applied and activated.
[0169]
The above describes the operation of simultaneously activating the global word lines (section word lines) at the two row positions of the storage area corresponding to the reference blocks P and P + 1. However, the storage areas corresponding to the other two reference blocks The same operation can be performed when the global word lines (section word lines) at the two row positions are simultaneously activated.
[0170]
For example, when simultaneously activating global word lines (section word lines) at two row positions in the storage area corresponding to the reference blocks P + 1 and P + 2, the row decoder RDEC has eight storage areas corresponding to the reference block P + 1. Among the global word lines, "0" is output to the inverted signal output terminal corresponding to the global word line to be activated, and "1" is output to the other inverted signal output terminals. The row decoder RDEC outputs “0” to all the signal output terminals corresponding to the eight global word lines in the storage area of the reference block P + 2. In this case, the row decoder RDEC outputs “0” to all the signal output terminals corresponding to the eight global word lines in the storage area of the reference block P.
[0171]
As described above, in the motion vector detection circuit 111 shown in FIG. 3, each time pixel data of a search frame is input, a plurality of difference absolute value calculators 124._-1~ 124_-NThe difference absolute value of the reference frame including the pixel data in the search range from the pixel data of the predetermined reference block is obtained by ((0, 0) to (7, 7)), and the adder 125_-1~ 125_-NAnd the semiconductor memory 126 for generating the correlation value table, the difference absolute values are accumulated, and a plurality of candidates existing in the search range of the predetermined reference block are stored in the plurality of correlation value storage areas of the semiconductor memory 126. A correlation value corresponding to each block is obtained, and a motion vector MV of the predetermined reference block is detected. Therefore, it is possible to eliminate useless operations such as temporarily storing the search frame in the frame memory and then reading it again for processing, and the motion vector can be detected efficiently.
[0172]
Also, adder 125_-1~ 125_-NAnd the semiconductor memory 126 are integrated, and a plurality of bit addition units 140 constituting an adder.₀~ 140_n-1However, they are arranged in alignment with the column pitch of the semiconductor memory 126 (see FIG. 22). Therefore, adder 125_-1~ 125_-NFrom the semiconductor memory 126 to the adder 125_-1~ 125_-NThe storage data can be efficiently supplied to the storage device.
[0173]
Further, the semiconductor memory 126 has a first port for writing and reading provided in association with a plurality of adders and a second port dedicated for reading for reading the correlation value (see FIG. 22). Therefore, reading of the storage data of the semiconductor memory 126 is performed by the adder 125._-1~ 125_-NIt can be performed independently of the calculation according to.
[0174]
In addition, each word line extending in the column direction related to the first port of the semiconductor memory 126 has a plurality of storage areas 126._-1~ 126_-NThe semiconductor memory 126 is a row decode for selectively activating an arbitrary section word line among the plurality of section word lines constituting the arbitrary word line. It has a main row decoder 153 and a sub row decoder 154 as means, and the semiconductor memory 126 can be accessed independently in the section word line unit in the column direction.
[0175]
In addition, a plurality of storage areas 126 of the semiconductor memory 126_-1~ 126_-NIs formed by arranging a plurality of block areas BM for storing count values of a plurality of reference blocks in the row direction, and the main row decoder 153 activates global word lines corresponding to two consecutive block areas BM. The sub-row decoder 154 uses section word lines activated corresponding to the two global word lines as section word lines corresponding to different storage areas (see FIG. 24).
[0176]
Accordingly, the plurality of absolute difference calculators 124_-1~ 124_-NEven if the absolute difference calculation related to a plurality of reference blocks is performed in parallel, the plurality of adders 125_-1~ 125_-NThus, addition related to a plurality of reference blocks can be performed, and the added data can be distributed and written to different word line positions in the row direction for each reference block, and a correlation value can be obtained for each reference block in the semiconductor memory 126. It becomes possible.
[0177]
In addition, in the motion vector detection circuit 111 shown in FIG._-1~ 125_-NAnd a semiconductor memory 126 for generating a correlation value table are integrated._-1~ 124_-NAlternatively, the correlation value table evaluator 127 may be integrated.
[0178]
In the motion vector detection circuit 111 shown in FIG. 3, the memory cell 130 has a 2-port configuration (see FIG. 23), but the memory cell may not have a 2-port configuration. A port configuration may be used. Further, even if the semiconductor memory 126 does not have a two-port configuration, for example, correlation values (table data) are read during a blanking period in a video signal, or a plurality of identical functional blocks are interleaved between fields or frames. For example, the addition and the reading of the correlation value may be performed in different periods in the same port.
[0179]
In the motion vector detection circuit 111 shown in FIG. 3, the semiconductor memory 126 has a two-port configuration, and each word line extending in the column direction related to the first port for writing and reading has a plurality of storage areas 126._-1~ 126_-NAre made up of a plurality of section word lines which are divided in correspondence with each other. However, in a semiconductor memory having a plurality of ports, each word line extending in the column direction related to at least one port has the same configuration, so that it can be accessed independently in section word line units in the column direction. Obtainable.
[0180]
Further, in the motion vector detection circuit 111 shown in FIG._-1~ 125_-NAlthough the addition using the semiconductor memory 126 is applied to the addition of the absolute difference value in the motion vector search, it can be applied to the same addition in other signal processing.
[0181]
Further, in the motion vector detection circuit 111 shown in FIG._-1~ 125_-NIn addition, the semiconductor memory 126 for generating the correlation value table is integrated. However, a semiconductor memory integrated with other arithmetic units such as a subtractor, a multiplier, and a divider can be configured in the same manner. Data can be exchanged efficiently between the memory and the semiconductor memory.
[0182]
Further, in the motion vector detection circuit 111 shown in FIG. 3, the motion vector is detected by the representative point block matching method, but parameters such as the representative point interval, the size of the reference block, and the search range are examples. However, the present invention is not limited to this. The present invention can also be applied when detecting a motion vector by an ordinary block matching method.
[0183]
In addition, in the motion vector detection circuit 111 shown in FIG. 3, the semiconductor memory 126 activates the global word lines (section word lines) at the two row positions existing in the storage areas corresponding to the two reference blocks. Although shown, it is also possible to activate three or more row global word lines (section word lines) existing in a storage area corresponding to two or more reference blocks with the same configuration. Depending on the search range for one reference pixel in the reference block, it is also assumed that a plurality of absolute difference calculators perform operations related to three or more reference blocks. In this case, it is necessary to activate three or more row position global word lines (section word lines).
[0184]
Next, another example of the motion vector detection circuit will be described with reference to FIG.
First, the motion vector detection method in this example will be described.
The conventional block matching method obtains a sum of absolute differences obtained by adding all the absolute differences between corresponding pixel data between the reference block and each candidate block for the block as a correlation value, and generates a search range generated thereby. In the correlation value table of the corresponding size, the shift between the center position of the table and the position where the correlation value is minimum is used as the motion vector in the reference block.
[0185]
In this method, a correlation value table is generated including all unmatched information, and the distribution of correlation values is widened. Therefore, as shown in FIG. 25, when a plurality of different motions are mixed in the reference block, the minimum correlation value indicating each motion is buried in the distribution in other motions, and the minimum value is in the wrong position. May occur.
[0186]
Here, the processing procedure of the conventional block matching method will be described. As shown in the center column of FIG. 26, a 1-to-N matching operation, for example, a difference absolute value operation, is performed between the pixel data constituting the reference block and each pixel data in the search range corresponding thereto, A temporary correlation value table is obtained. Then, each difference absolute value of the provisional correlation value table corresponding to all the pixel data of # 1 to #M constituting the reference block is added for each pixel position in the search range to generate a correlation value table. Then, the motion vector of the reference block is detected based on this correlation value table.
[0187]
On the other hand, in the motion vector detection method according to this example, as shown in the right column of FIG. 26, for each pixel data constituting the reference block, the matching degree is based on the threshold value based on the result of the matching calculation. When the value is high, a value other than 0 is assigned as the count value, and when the degree of matching is equal to or less than the threshold value, a count value table is generated in which 0 is assigned as the count value.
[0188]
In the illustrated count value table, a circle is marked at the pixel position with the highest degree of matching, a triangle is marked at the pixel value with the next highest degree of matching, and an x is marked at the pixel position with the next highest degree of matching. ing. The count values are “+3”, “+2”, “+2”, “+1”, and “0” for an unmarked pixel position. For example, as shown in Table 1, for example, when the difference absolute value is 0, 1, or 2 as a matching calculation result, “+3”, “+2”, and “+1” are generated as count values, respectively, while the difference is When the absolute value is 3 or more, “0” is generated as the count value.
[0189]
[Table 1]

[0190]
Then, each count value in the count value table corresponding to all the pixel data of # 1 to #M constituting the reference block is set as a frequency, and this frequency is added for each pixel position in the search range, and is added to the pixel position in the search range. Correspondingly, a histogram table in which cumulative values of frequencies are arranged is generated. The motion vector of the reference block is detected based on the maximum or minimum value of the frequency in the histogram table.
[0191]
Here, when the count value provided when the degree of matching is high is a positive value, it is a maximum value, and when the count value is a negative value, it is a minimum value. The position of the maximum value or minimum value of the frequency in this histogram table represents a motion vector corresponding to the motion existing in the reference block.
[0192]
According to the motion vector detection method of this example, only when the degree of matching is high, a count value table is generated by assigning a value other than 0 as a count value. As a result, the frequency distribution becomes sharper. Therefore, when a plurality of different motions are mixed in the reference block, a plurality of maximum values or minimum values are easily clearly separated and shown in the histogram table. Accordingly, it is possible to correctly detect one or a plurality of motion vectors of the reference block.
[0193]
FIG. 27 and FIG. 28 show an example of a correlation value table in the conventional block matching method and an example of a hysteresis and gram table in the motion vector detection method of this example when there are two different motions in the reference block. The correlation value table shown in FIG. 27 is displayed with the magnitude relationship of the correlation values interchanged to facilitate comparison with the histogram table according to the present invention. That is, in any case, the position of the maximum value or the maximum value represents the motion vector.
[0194]
In the conventional block matching method for detecting a motion vector based on the correlation value table shown in FIG. 27, a motion vector indicating the more dominant motion is detected, but the motion indicating the other motion is buried. It is difficult to detect a motion vector indicating the motion. On the other hand, in the motion vector detection method of this example for detecting a motion vector based on the histogram table shown in FIG. 28, two local maximum values appear clearly separated in the histogram table, and the two motions are Two motion vectors shown respectively can be easily detected.
[0195]
In the above description, the degree of matching is classified into four types, that is, the top three and others, but it is not necessary to be limited to this, and it may be three or less or five or more. In the above description, each count value is set to “0”, “+1”, “+2”, “+3” in ascending order according to the degree of matching. However, this is not limited to the use of this count value. For example, all of “O” to “X” may be “+1”, and the others may be “0”. However, the count value distributed when the degree of matching is higher than the threshold value is not set to a constant value, but the higher the degree of matching, the larger the absolute value, thereby further increasing the frequency distribution of the histogram table. There is a profit that can be sharpened.
[0196]
By the way, when the activity around the pixel data constituting the reference block is high, that is, when the value difference between the pixel data and the surrounding pixel data is large (when the waveform amplitude is large when viewed as a signal waveform), Even at the position of the motion vector that should be correct, the degree of matching is low. This is because there is generally a component with a motion amount smaller than one pixel, and as the difference in value from surrounding pixel data increases, the difference between pixel data values also increases at the position to be matched. by.
[0197]
As a coping method in this case, it is effective to set the count value of the count value table corresponding to the reference block having a large activity in the surrounding so that the absolute value of the count value becomes large.
[0198]
Specifically, first, the activity A is obtained for each pixel data constituting the reference block. For example, as shown in FIG. 29, the pixel data that is the target of activity A is a, the surrounding four pixel data are b to d, and activity A is calculated by equation (1).
A = | a-b | + | a-c | + | a-d | + | a-e | (1)
[0199]
For each pixel data constituting the reference block, a larger value is obtained as the correction coefficient k as the ratio of the activity A to the maximum activity A_max is higher. Table 2 shows an example of setting the correction coefficient k. In Table 2, A_nor is an activity normalized by dividing the activity A by the maximum activity A_max, and indicates the ratio of the activity A to the maximum activity A_max.
[0200]
[Table 2]

[0201]
Then, the count value of the count value table corresponding to each pixel data constituting the reference block is multiplied by the correction coefficient k corresponding to each pixel data (see the section “corrected count value” in Table 1). ).
[0202]
Note that, as described above, instead of obtaining the correction coefficient k and correcting the correction coefficient k by multiplying the count value, the threshold used when generating the count value according to the degree of matching is increased as the activity increases. You may change so that it may become low.
[0203]
For example, in the example of Table 1 described above, when the difference absolute value is smaller than the threshold 3, the count value is a value other than 0 (+3 to +1), while when the difference absolute value is greater than or equal to the threshold 3, the count value is 0. However, this threshold value is changed so as to increase as the activity increases. In this case, increasing the difference absolute value threshold means lowering the matching degree threshold.
[0204]
As described above, even when the threshold value is changed, the count value in the count value table corresponding to the pixel data of the reference block having a large activity in the surrounding area is the same as when the count value is corrected with the correction coefficient k. The absolute value becomes larger. As a result, it is possible to reduce problems caused by changes in the degree of matching due to activities.
[0205]
As described above, in the motion vector detection method according to this example, one or a plurality of motion vectors of the reference block can be detected based on the histogram table. Note that the motion vector of each pixel data constituting the reference block can be further specified based on the motion vector thus detected.
[0206]
In that case, correlation information between the pixel data constituting the reference block and the pixel data of the pixel position of the search frame corresponding to the motion vector detected as described above with reference to the pixel position of this pixel data, for example, the difference An absolute value, a square difference value or the like is obtained, and the motion vector when the correlation is highest is set as the motion vector of the pixel data constituting the reference block.
[0207]
As described above, since the motion vector of the reference block can be correctly detected, the motion vector of each pixel data specified based on the motion vector is also highly accurate. It should be noted that the accuracy of the motion vector of each pixel data can be further improved by removing the isolated motion vector from the motion vector of each pixel data constituting the reference block specified in this way.
[0208]
Here, the isolated motion vector means a motion vector of a certain pixel data in a case where the motion vector of a certain pixel data is different from the motion vector of the surrounding pixel data. The removal of the isolated motion vector means replacing the motion vector of the certain pixel data with the motion vector of the surrounding pixel data.
[0209]
FIG. 30 shows a configuration of a motion vector detection circuit 200 as another example described above. In the motion vector detection circuit 200 as well, as in the motion vector detection circuit 111 shown in FIG. 3, the reference frame is a past frame and the input frame is a search frame as shown in FIG. .
[0210]
The motion vector detection circuit 200 includes a system controller 201 that controls the operation of the entire circuit, an input terminal 202 to which image data Di of an input frame as a search frame is input, and the image data Di as a reference frame of the next frame. A reference frame memory 203 for storing the image data. Operations such as writing and reading of the frame memory 203 are controlled by the system controller 201.
[0211]
Also, the motion vector detection circuit 200 includes a difference absolute value calculator 204 that performs a difference absolute value calculation as a matching calculation._-1~ 204_-Nhave. Multiple computing units 204_-1~ 204_-NThe pixel data constituting the image data Di input to the input terminal 202 is commonly input as the pixel data Dc of the search frame, and a predetermined reference block (same timing) of the reference frame including the pixel data Dc in the search range. In this case, pixel data Dr is a maximum of two)_-1~ Dr_-NAre respectively input, and pixel data Dc and pixel data Dr_-1~ Dr_-NThe absolute value of the difference is calculated.
[0212]
In this case, as shown in FIG. 4, the reference pixels in the reference frame to be matched with the input pixels in the search frame are a plurality of reference pixels in which the input pixels are located within the search range. The range in which the plurality of reference pixels are located has a front-back relationship with the search range of a certain reference pixel, and the search range when the input pixel is regarded as a reference pixel is inverted horizontally and vertically.
[0213]
Therefore, the plurality of reference pixels are often located over a plurality of reference blocks, and the number of pixels in one reference block is not constant from one to all. The combination of these reference blocks and the combination of pixels in one reference block also differ depending on the position of the input pixel.
[0214]
Returning to FIG. 30, the motion vector detection circuit 200 includes a plurality of computing units 204._-1~ 204_-NA count value generation unit 205 that generates a count value corresponding to each of the plurality of absolute difference values obtained by the calculation in step (b). When the difference absolute value is smaller than the threshold value, the count value generation unit 205 generates a predetermined value other than 0 assuming that the degree of matching is higher than the threshold value, while the difference absolute value is greater than or equal to the threshold value. When the degree of matching is less than the threshold value, 0 is generated. For example, as shown in Table 1 described above, the count value generation unit 205 generates “+3”, “+2”, and “+1” as the count values when the absolute difference values are 0, 1, and 2, respectively. On the other hand, when the difference absolute value is 3 or more, “0” is generated as the count value. In this case, the threshold is 3.
[0215]
The motion vector detection circuit 200 includes a plurality of arithmetic units 204._-1~ 204_-NStorage areas 206 respectively corresponding to_-1~ 206_-NAnd a semiconductor memory 206 as a storage means for generating a count value table. The writing and reading operations of the semiconductor memory 206 are controlled by the system controller 201.
[0216]
The system controller 201 includes a plurality of computing units 204._-1~ 204_-NThe count value generated by the count value generation unit 205 corresponding to each of the absolute difference values obtained in the above is stored in the count value storage area of the semiconductor memory 206 corresponding to the computing unit related to the count value and the pixel position of the reference block. Writing is controlled so that a count value table corresponding to each pixel data constituting the reference block is obtained in the semiconductor memory 206. Here, the count value table is a table in which count values are arranged corresponding to each pixel position in the search range.
[0217]
As shown in FIG. 31, in this motion vector detection circuit 200, the size of the reference block is 8 × 8 pixels, and the search range is (−3 to +4) × (−3 to +4) pixels. There are (3 + 4 + 1) × (3 + 4 + 1) = 64 candidate blocks in the reference block search range. Therefore, N = 64. That is, a plurality of computing units 204_-1~ 204_-N, A plurality of storage areas 206 of the semiconductor memory 206_-1~ 206_-NAre 64 each.
[0218]
Multiple computing units 204_-1~ 204_-NIs responsible for the calculation for obtaining the absolute difference value corresponding to one candidate block for each reference block. In addition, a plurality of storage areas 206 of the semiconductor memory 206_-1~ 206_-NEach has a number of block storage areas corresponding to the number of reference blocks in one horizontal row of the reference frame. Furthermore, each block storage area has a count value storage area for the number of pixel data constituting the reference block.
[0219]
Here, it is assumed that the image data Di input to the input terminal 202 is based on the progressive method. The image data Di input to the input terminal 202 is a series of pixel data of each line.
[0220]
As shown in FIG. 31, the search range is (−3 to +4) × (−3 to +4) pixels, and the size of the reference block is 8 × 8 pixels. Therefore, if the line including the uppermost input pixel in the search range for a certain reference block is the first line, the line including the lowermost input pixel in the search range is the 15th line. Accordingly, in order to obtain a count value table corresponding to each pixel data constituting a certain reference block, 15 lines of pixel data are required. FIG. 31 shows only one reference block. Based on the above-mentioned 15 lines of pixel data, all reference blocks for one horizontal row are calculated corresponding to the pixel data constituting the reference block. A numerical table can be obtained.
[0221]
In addition, the motion vector detection circuit 200 obtains an activity A in the periphery for each pixel data constituting the reference block, and sets a larger value as the correction coefficient k as the ratio of the activity A to the maximum activity A_max is higher for each pixel data. A correction coefficient acquisition unit 207 is obtained.
[0222]
The correction coefficient acquisition unit 207 acquires the correction coefficient k corresponding to each pixel data constituting the reference block as follows, for example. First, as shown in FIG. 29, for example, the pixel data for which the activity A is obtained is set to a, and the surrounding four pieces of pixel data are set to b to d. Activity A is obtained for each pixel data. Next, for each pixel data constituting the reference block, the activity A_nor is obtained by dividing the activity A by the maximum activity A_max, and the correction coefficient k is set as shown in Table 2, for example.
[0223]
The motion vector detection circuit 200 is read from the semiconductor memory 206 described above, and a plurality of adders 209 to be described later._-1~ 209_-NThe correction value obtained by multiplying the count value of the count value table corresponding to each pixel data constituting the reference block by the correction coefficient k corresponding to each pixel data acquired by the correction coefficient acquisition unit 207 is supplied to A correction unit 208 is included.
[0224]
The motion vector detection circuit 200 includes a plurality of adders 209._-1~ 209_-NAnd a plurality of storage areas 210_-1~ 210_-NAnd a semiconductor memory 210 as storage means for generating a histogram table. Multiple adders 209_-1~ 209_-NIs input from the semiconductor memory 206 as a frequency each of the count values of the count value table corresponding to the predetermined pixel data constituting the reference block, which is read from the semiconductor memory 206 and corrected by the count value correction unit 208. Multiple storage areas 210_-1~ 210_-NEach of the stored data stored in is input and the frequency is added to the stored data.
[0225]
Thus, the plurality of adders 209_-1~ 209_-NEach of the addition data obtained in the above is stored in a plurality of storage areas 210 of the semiconductor memory 210_-1~ 210_-NIs written back as stored data. The writing and reading operations of the semiconductor memory 210 are controlled by the system controller 201.
[0226]
The system controller 201 reads the count value of the count value table from the semiconductor memory 206, and adds a plurality of adders 209._-1~ 209_-NOf addition in the plurality of storage areas 210 of the semiconductor memory 210_-1~ 210_-NThe addition data is written back by the number of count value tables corresponding to each pixel data constituting the reference block, and the frequency is accumulated in the semiconductor memory 210 corresponding to each pixel position in the search range. Control is performed to obtain a histogram table in which values are arranged.
[0227]
Further, the motion vector detection circuit 200 includes a motion vector detection unit 211 that detects a motion vector based on the maximum value in the histogram table obtained in the semiconductor memory 210 for each reference block. The maximum value of the frequency in the histogram table represents a motion vector corresponding to the motion existing in the reference block. Therefore, when a plurality of different motions are mixed in the reference block, a plurality of maximum values are shown in the histogram table, and the motion vector detecting unit 211 detects a plurality of motion vectors.
[0228]
In addition, the motion vector detection circuit 200 includes one or a plurality of motion vectors MV detected by the motion vector detection unit 211.₁~ MV_n(N is an integer equal to or greater than 1), a motion vector specifying unit 212 that specifies a motion vector mv of each pixel data constituting the reference block, and a motion of each pixel data specified by the motion vector specifying unit 212 And an output terminal 213 that outputs a vector mv.
[0229]
The motion vector specifying unit 212 uses each of the motion vectors MV detected by the motion vector detection unit 211 based on the pixel data constituting the reference block and the pixel position of the pixel data.₁~ MV_nCorrelation information with the pixel data at the pixel position of the search frame corresponding to, for example, the difference absolute value or the difference square value is obtained, and the motion vector when the correlation is the highest is taken as the motion vector mv of this pixel data.
[0230]
FIG. 32 shows a specific configuration of the motion vector identification unit 212.
The motion vector specifying unit 212 includes a controller 221 for controlling the entire operation. The controller 221 is supplied with image data Di of an input frame (search frame) input to the input terminal 202 (see FIG. 30), and the image data Di is stored in a memory 222 for search pixels. Further, the controller 221 includes a motion vector MV detected by the motion vector detection unit 211 (see FIG. 30).₁~ MV_nIs supplied.
[0231]
The motion vector specifying unit 212 also includes a correlation calculation unit 223._-1~ 223_-nhave. This correlation calculation unit 223_-1~ 223_-nThe pixel data (reference pixel data) constituting the reference block is read from the reference frame memory 203 and supplied in common under the control of the controller 221. Further, the correlation calculation unit 223_-1~ 223_-nEach includes a motion vector MV based on the pixel position of the pixel data constituting the reference block.₁~ MV_nThe pixel data (search pixel data) at the pixel position of the search frame corresponding to is read from the memory 222 and supplied under the control of the controller 221. Correlation calculator 223_-1~ 223_-nObtains correlation information between the reference pixel data and the search pixel data, for example, a difference absolute value or a difference square value.
[0232]
The motion vector specifying unit 212 includes a motion vector temporary specifying unit 224. The temporary identification unit 224 includes a motion vector MV detected by the motion vector detection unit 211.₁~ MV_nIs supplied. Further, the temporary specifying unit 224 includes a correlation calculation unit 223._-1~ 223_-nCorrelation information obtained in is supplied. The provisional specifying unit 224 includes a correlation calculation unit 223._-1~ 223_-nBased on the correlation information obtained in step (1), the motion vector with the highest correlation is specified as the motion vector mv of the reference pixel data described above.
[0233]
In this case, which motion vector MV₁~ MV_nIf the correlation is not sufficient, information indicating that the motion is indefinite is output instead of outputting the motion vector mv. As the reference pixel data in which the motion is indefinite, pixel data on which noise is superimposed or pixel data in a portion without motion can be considered.
[0234]
The motion vector specifying unit 212 includes a motion vector correcting unit 225 that performs correction processing such as removing an isolated motion vector from the motion vector mv of each pixel data constituting the reference block specified by the temporary specifying unit 224. is doing. Here, the isolated motion vector means a motion vector of a certain pixel data when the motion vector of the certain pixel data is different from the motion vector of the surrounding pixel data as described above. The removal of the isolated motion vector means replacing the motion vector of the certain pixel data with the motion vector of the surrounding pixel data.
[0235]
The operation of the motion vector identification unit 212 shown in FIG. 32 will be described.
A motion vector MV of a predetermined reference block detected by the motion vector detection unit 211₁~ MV_nIs supplied to the controller 221 and the motion vector temporary specifying unit 224.
[0236]
Correlation calculator 223_-1~ 223_-nThe pixel data (reference pixel data) constituting the predetermined reference block described above is read from the reference frame memory 203 and supplied in common. Further, the correlation calculation unit 223_-1~ 223_-nIncludes a motion vector MV based on the pixel position of the pixel data constituting each reference block.₁~ MV_nThe pixel data (search pixel data) at the pixel position of the search frame corresponding to is read from the memory 222 and supplied. Then, the correlation calculation unit 223_-1~ 223_-nThen, correlation information between the reference pixel data and the search pixel data is obtained.
[0237]
Correlation calculator 223_-1~ 223_-nThe correlation information obtained in step (2) is supplied to the temporary identification unit 224. In the temporary identification unit 224, based on the correlation information, the motion vector when the correlation is highest is identified as the motion vector mv of the reference pixel data. In this case, which motion vector MV₁~ MV_nIf the correlation is not sufficient, information indicating that the motion is indefinite is output instead of the motion vector mv.
[0238]
The above operation is performed on all the pixel data constituting the reference block, whereby the motion vector mv of each pixel data is specified. As described above, the motion vector MV (including motion indefinite information) of each pixel data constituting the reference block specified by the provisional specification unit 224 is used to remove an isolated motion vector (isolation point removal) by the motion vector correction unit 225. Are output sequentially or simultaneously.
[0239]
In the motion vector specifying unit 212 shown in FIG. 32, the motion vector mv is obtained for each pixel data._-1~ 223_-nIn addition, a plurality of sets of the motion vector temporary specifying unit 224 may be provided, and the motion vector mv may be obtained in parallel for a plurality of pixel data. Thereby, for example, all the pixel data constituting the reference block can be obtained in parallel.
[0240]
In the motion vector detection circuit 200 shown in FIG. 30, the system controller 201, the count value generation unit 205, the semiconductor memory 206, the adder 209_-1~ 209_-N, 210..., A semiconductor memory, the motion vector detection unit 211 constitutes a motion vector detection processing unit.
[0241]
The operation of the motion vector detection circuit 200 shown in FIG. 30 will be described.
Pixel data constituting the image data Di input to the input terminal 202 is a plurality of difference absolute value calculators 204 as pixel data Dc of a search frame (input frame)._-1~ 204_-NAre input in common. The image data Di is supplied to the frame memory 203 and stored as image data of a reference frame used in the next frame.
[0242]
In addition, a plurality of computing units 204_-1~ 204_-NIncludes, from the frame memory 203, pixel data Dr of a predetermined reference block of the reference frame including the pixel data Dc in the search range._-1~ Dr_-NAre entered respectively. A plurality of arithmetic units 204_-1~ 204_-NThen, the pixel data Dc and the pixel data Dr_-1~ Dr_-NThe difference absolute value is calculated. In this case, a plurality of arithmetic units 204_-1~ 204_-NThen, for each reference block, an operation for obtaining a difference absolute value corresponding to one candidate block is performed.
[0243]
Multiple computing units 204_-1~ 204_-NThe absolute difference values obtained in the above are respectively supplied to the count value generation unit 205. The count value generation unit 205 generates a predetermined value other than 0 when the difference absolute value is smaller than the threshold value, and generates 0 when the difference absolute value is equal to or greater than the threshold value, corresponding to each of the absolute difference values. (See Table 1).
[0244]
Multiple computing units 204_-1~ 204_-NThe count value generated by the count value generation unit 205 corresponding to the absolute difference value obtained in the above is stored in the storage area 206 of the semiconductor memory 206 for generating the count value table._-1~ 206_-NIs supplied as write data.
[0245]
As described above, each storage area 206_-1~ 206_-NEach has a number of block storage areas corresponding to the number of reference blocks in one horizontal row of the reference frame. Further, each block storage area has a count value storage area for the number of pixel data constituting the reference block.
[0246]
Multiple computing units 204_-1~ 204_-NThe count values generated by the count value generation unit 205 corresponding to the absolute difference values obtained in step 1 are written in the storage area of the semiconductor memory 206 corresponding to the computing unit related to the count value and the pixel position of the reference block. It is. Thereby, a count value table is obtained in which count values are arranged in each block area of the semiconductor memory 206 corresponding to each pixel position in the search range corresponding to each pixel data constituting the reference block.
[0247]
In the correction coefficient acquisition unit 207, the activity A in the surroundings is obtained for each pixel data constituting the reference block, and a larger value as the ratio of the activity A to the maximum activity A_max is higher as the correction coefficient k for each pixel data. Obtained (see FIG. 29, Table 2).
[0248]
The count values (N) of the count value table corresponding to each pixel data constituting the reference block obtained in the semiconductor memory 206 are sequentially read out, and a plurality of adders 209 are passed through the count value correction unit 208._-1~ 209_-NTo be supplied. In the count value correction unit 208, the count value of the count value table corresponding to each pixel data constituting the reference block is multiplied by the correction coefficient k corresponding to each pixel data acquired by the correction coefficient acquisition unit 207, and corrected. Is done.
[0249]
Multiple adders 209_-1~ 209_-NThe count values in the count value table corresponding to the predetermined pixel data constituting the reference block, read from the semiconductor memory 206 and corrected by the count value correction unit 208, are respectively input as frequencies. Multiple storage areas 210 of_-1~ 210_-NEach of the stored data stored in is input.
[0250]
Then, a plurality of adders 209_-1~ 209_-NThen, the frequency is added to the stored data. Multiple adders 209_-1~ 209_-NEach of the addition data obtained in the above is stored in a plurality of storage areas 210 of the semiconductor memory 210_-1~ 210_-NIs written back as stored data.
[0251]
Reading the count value of the count value table from the semiconductor memory 206, a plurality of adders 209_-1~ 209_-NOf addition in the plurality of storage areas 210 of the semiconductor memory 210_-1~ 210_-NThe writing back of the addition data is repeatedly performed by the number of the plurality of count value tables corresponding to each pixel data constituting the reference block. Thereby, a histogram table corresponding to the reference block in which the cumulative value of the frequency is arranged corresponding to each pixel position in the search range is obtained in the semiconductor memory 210.
[0252]
In the motion vector detection unit 211, based on the maximum value in the histogram corresponding to each reference block obtained in the semiconductor memory 210, the motion vector MV of each reference block₁~ MV_nIs detected. As described above, the maximum value of the frequency in the histogram table represents a motion vector corresponding to the motion existing in the reference block. Therefore, when a plurality of different motions are mixed in the reference block, a plurality of maximum values are shown in the histogram table, and thus the motion vector detecting unit 211 detects a plurality of motion vectors.
[0253]
The motion vector MV of the reference block detected by the motion vector detection unit 211 in this way.₁~ MV_nIs supplied to the motion vector identification unit 212. In the motion vector specifying unit 212, the motion vector MV₁~ MV_nBased on the above, the motion vector mv of each pixel data constituting the reference block is specified. The motion vector mv of each pixel data is output to the output terminal 213.
[0254]
As described above, a count value table corresponding to each pixel data composing each reference block for one horizontal row can be obtained based on 15 lines of pixel data. In this case, the pixel data of the latter half of the 15-line pixel data is also used for the arithmetic processing for the reference block for the next horizontal row of the reference frame. For this reason, when the pixel data of the latter half of the line is input, it is necessary to perform the arithmetic processing for the reference block for the next horizontal line in parallel. Therefore, actually, the difference absolute value calculator 204 in the motion vector detection circuit 200 shown in FIG._-1~ 204_-N, Count value generation unit 205, semiconductor memory 206, count value correction unit 208, adder 209_-1~ 209_-NThus, at least two systems of the semiconductor memory 210 are provided.
[0255]
Next, the absolute difference calculator 204_-1~ 204_-NWill be further described. FIG. 33A shows an input pixel and computing unit 204._-1~ 204_-NThe arrangement of the operation symmetry range ((0, 0) to (7, 7)) is shown. FIG. 33B shows 8 × 8 pixel data (a, a) to (h, h) constituting the reference block.
[0256]
The range (calculation target range) where the pixel data of the reference block on which the difference absolute value calculation is to be performed with the input pixel is divided into ranges in which the respective calculators (0, 0) to (7, 7) are in charge. The assigned range of each computing unit (0, 0) to (7, 7) is one pixel.
[0257]
As shown in FIG. 34, when the input pixel is on the first line of the search range of the reference block and the calculation target range is applied to the pixel data (a, a) of the reference block, the 8 × 8 constituting the reference block An operation for obtaining a count value table corresponding to each piece of pixel data is started. At this time, the pixel data (a, a) is input from the frame memory 203 (shown in FIG. 30) to the calculator (7, 7). Then, the arithmetic unit (7, 7) calculates the absolute difference between the input pixel and the pixel data (a, a).
[0258]
Next, as shown in FIG. 35, after one pixel period, the input pixel moves to the right by one pixel, and the calculation target range of the input pixel is applied to the pixel data (b, a) of the reference block. At this time, the pixel data (b, a) is input from the frame memory 203 to the calculator (7, 7). Then, the calculator (7, 7) obtains the input pixel, the pixel data (b, a), and the absolute difference value. At the same time, pixel data (a, a) is input from the frame memory 203 to the calculator (6, 7). Then, the arithmetic unit (6, 7) obtains the absolute difference between the input pixel and the pixel data (a, a).
[0259]
In the following, for the first line, the input pixels are sequentially shifted to the one on the right, and in the arithmetic unit including the pixel data of the reference block in the assigned range, the calculation of the input pixel and the pixel data of the reference block is performed in parallel. Done.
[0260]
FIG. 36 shows a state after seven pixel periods. In this state, the input pixel shifts to the right by 7 pixels, and the calculation target range of the input pixel extends to the pixel data (h, a) of the reference block. At this time, pixel data (h, a) to (a, a) are input from the frame memory 203 to the computing units (7, 7) to (0, 7), respectively. Then, the arithmetic units (7, 7) to (0, 7) obtain absolute differences between the input pixel and the pixel data (h, a) to (a, a), respectively.
[0261]
As shown in FIG. 37, when the input pixel is in the second line of the search range for the reference block and the calculation target range is applied to the pixel data (a, a), (a, b) of the reference block, the calculation is performed. The pixel data (a, b) is input from the frame memory 203 to the unit (7, 7). Then, the arithmetic unit (7, 7) calculates the absolute difference between the input pixel and the pixel data (a, b). At the same time, the pixel data (a, a) is input from the frame memory 203 to the calculator (7, 6). Then, the arithmetic unit (7, 6) calculates the absolute difference between the input pixel and the pixel data (a, a).
[0262]
Hereinafter, for the second line, the input pixels are sequentially shifted to the one on the right, and in the arithmetic unit including the pixel data of the reference block in the assigned range, the calculation of the input pixel and the pixel data of the reference block is performed in parallel. Done.
[0263]
The same applies to the following third to fifteenth lines, and the input pixels sequentially move to the one on the right side, and in the arithmetic unit including the reference block pixel data in the assigned range, the input pixels and the reference block pixels respectively. Operations with data are performed in parallel.
[0264]
In FIG. 38, the input pixel is on the 8th line of the search range for the reference block, and the calculation target range is 8 pixel data from the reference block pixel data (a, a) to (a, h). Indicates the state. In this state, the pixel data (a, h) to (a, a) are input from the frame memory 203 to the calculators (7, 7) to (7, 0). Then, the arithmetic units (7, 7) to (7, 0) obtain the absolute difference between the input pixel and the pixel data (a, h) to (a, a).
[0265]
FIG. 39 shows a state in which the input pixel is on the 15th line of the search range for the reference block, and the calculation target range depends on the pixel data (a, h) on the lower left of the reference block. In this state, pixel data (a, h) is input from the frame memory 203 to the calculator (7, 0). Then, the arithmetic unit (7, 0) obtains the absolute difference between the input pixel and the pixel data (a, h).
[0266]
FIG. 40 shows each of the arithmetic units 204 described above._-1~ 204_-NThe process of calculating the absolute difference of each line in ((0, 0) to (7, 7)) is shown. In FIG. 40, numerals 1 to 64 indicate operations of input pixels and pixel data (a, a) to (h, h) of reference blocks, respectively.
[0267]
In each of the arithmetic units (0, 0) to (7, 7), the input pixel data and the 64 pixel data (a, a) to (h, h) constituting the reference block are related to a certain reference block, respectively. ) Is calculated. That is, in each of the arithmetic units (0, 0) to (7, 7), 64 corresponding pixel data between a certain reference block and one candidate block existing in the search range for the reference block are used. Difference absolute value calculation is performed. FIG. 41 shows a calculation process in the calculator (7, 7) as an example.
[0268]
FIG. 42 shows a motion vector (coordinates of a search range with respect to one reference pixel). In the reference block search range, there are 64 candidate blocks corresponding to the respective motion vectors (x, y). The count value table corresponding to each pixel data constituting the reference block is composed of 64 count values corresponding to the respective motion vectors (x, y).
[0269]
FIG. 43 shows a count value table corresponding to each pixel data ((a, a) to (h, h)) constituting the reference block in an area corresponding to one reference block of the semiconductor memory 206. 64 count values (corresponding to motion vectors (+4, +4) to (-3, -3), respectively) are recorded in which count value storage area (address) is recorded.
[0270]
Further, FIG. 43 shows which absolute value of difference for generating a count value corresponding to which motion vector is obtained by calculation in each of the calculators (0, 0) to (7, 7). . That is, the arithmetic unit (0, 0) obtains an absolute difference value for generating a count value corresponding to the motion vector of (+4, +4). Similarly, in the computing units (1, 0) to (7, 7), absolute difference values for generating count values corresponding to the motion vectors of (+3, +4) to (-3, -3), respectively. Is required.
[0271]
Note that each computing unit 204 corresponds to a certain reference block._-1~ 204_-NIn ((0, 0) to (7, 7)), the calculation is performed as described above. In parallel with the calculation related to a certain reference block, the calculation is performed in the horizontal direction with respect to the certain reference block (reference block P). An operation relating to a reference block adjacent to is also performed. That is, as is clear from FIG. 40, it can be seen that the calculation for the reference block P and the calculation for the reference blocks P-1 and P + 1 before and after the calculation are performed in time.
[0272]
For example, the calculation regarding the reference block P is performed using 15 pixels of each line. When the 1st to 7th pixels are used, the calculation for the reference block P is performed, and the calculation for the reference block P-1 is performed in parallel with the calculation. Similarly, when the ninth to fifteenth pixels are used, calculation related to the reference block P is performed, and calculation related to the reference block P + 1 is performed in parallel with the calculation. Note that when the eighth pixel is used, only the calculation for the reference block P is performed.
[0273]
For example, when the first pixel is used in the first line, the arithmetic unit (7, 7) performs an operation related to the reference block P, while the arithmetic units (6, 7) to (0, 7) perform the reference block P. An operation relating to −1 is performed. Also, for example, when the ninth pixel is used in the first line, the arithmetic units (6, 7) to (0, 7) perform arithmetic operations on the reference block P, but the arithmetic units (7, 7) refer to them. An operation relating to block P + 1 is performed.
[0274]
As described above, the plurality of storage areas 206 of the semiconductor memory 206._-1~ 206_-NEach has a number of block storage areas corresponding to the number of reference blocks in one horizontal row of the reference frame. Further, each block storage area has a count value storage area for the number of pixel data constituting the reference block. A plurality of arithmetic units 204_-1~ 204_-NThe count values generated by the count value generation unit 205 corresponding to the absolute difference values obtained in the above are stored in the count value storage area of the semiconductor memory 206 corresponding to the arithmetic unit and the pixel position of the reference block related to the count value. Written. Therefore, the semiconductor memory 206 has a plurality of arithmetic units 204 in the column direction._-1~ 204_-NAre configured to be independently accessible in units of predetermined memory cells.
[0275]
Next, a detailed configuration of the semiconductor memory 206 will be described. FIG. 44 shows the overall configuration of the semiconductor memory 206. The semiconductor memory 206 includes eight memory units 250._-1~ 250_-8It is composed of Each memory unit 250_-1~ 250_-8Are each composed of a row decoder 251 for reading, eight storage areas, a main row decoder 253 for writing, and a sub-row decoder 254 for writing.
[0276]
Memory unit 250_-1, 250_-2, 250_-3, 250_-Four, 250_-Five, 250_-6, 250_-7, 250_-8Each of the eight storage areas is an arithmetic unit 204._-1~ 204_-8, 204_-9~ 204_-16, 204_-17~ 204_{-twenty four}, 204_{-twenty five}~ 204_-32, 204_-33~ 204_-40, 204_-41~ 204_-48, 204_-49~ 204_-56, 204_-57~ 204_-64Storage areas 206 respectively corresponding to_-1~ 206_-8, 206_-9~ 206_-16, 206_-17~ 206_{-twenty four}, 206_{-twenty five}~ 206_-32, 206_-33~ 206_-40, 206_-41~ 206_-48, 206_-49~ 206_-56, 206_-57~ 206_-64(N = 64).
[0277]
In addition, as described above, the 64 storage areas 206_-1~ 206_-64Each has a number of block storage areas BM corresponding to the number of reference blocks in one horizontal row of the reference frame. Further, each block storage area BM has 64 count value storage areas in the present embodiment corresponding to the number of pixel data constituting the reference block.
[0278]
FIG. 45 shows the 64 storage areas 206 described above._-1~ 206_-64Is shown in more detail. Each memory unit 250_-1~ 250_-88 storage areas (e.g., 206_-1~ 206_-8) Are arranged in a matrix of 64m memory cells in the row direction (m is the number of reference blocks in one horizontal row) and 8n (n is the number of output bits of the count value from the count value generation unit 205) in the column direction. Has been configured.
[0279]
As described above, the difference absolute value calculation regarding a certain reference block (reference block P) is performed using the pixel data of the first line to the 15th line. For example, when the calculation is performed using the pixel data of the first line, the storage area 206_-57~ 206_-64Writing to the storage location is performed. When the calculation using the pixel data of the fourth pixel is performed in the first line, the calculations performed in the calculators (7, 7) to (4, 7) are calculations related to the reference block P, and the calculator (3, The operations performed in 7) to (0, 7) are operations related to the reference block P-1. Therefore, the storage area 206_-57~ 206_-64For example, the count value is written in the storage position indicated by the checkered pattern in FIG. 45 (first line).
[0280]
For example, when the calculation is performed using the pixel data of the eighth line, the storage area 206_-1~ 206_-64Writing to the storage location is performed. When the calculation using the pixel data of the sixth pixel is performed on the eighth line, the calculators (7, 7) to (2, 7), (7, 6) to (2, 6), (7, 5) ~ (2,5), (7,4) ~ (2,4), (7,3) ~ (2,3), (7,2) ~ (2,2), (7,1) ~ ( 2, 1), (7, 0) to (2, 0) are operations relating to the reference block P, and the arithmetic units (1, 7) to (0, 7), (1, 6) to ( 0,6), (1,5)-(0,5), (1,4)-(0,4), (1,3)-(0,3), (1,2)-(0, 2) Operations performed in (1,1) to (0,1) and (1,0) to (0,0) are operations related to the reference block P-1. Therefore, the storage area 206_-1~ 206_-64For example, the count value is written in the storage position indicated by the checkered pattern in FIG. 45 (eighth line).
[0281]
Although detailed description is omitted, the memory unit 250_-1~ 250_-8The main row decoder 253 and the sub row decoder 254 for writing in FIG. 3 are the configurations of the main row decoder 153 and the sub row decoder 154 for addition described with reference to the semiconductor memory 126 of the motion vector detection circuit 111 of FIG. The same applies. That is, for example, the memory unit 150_-124, the decoders 153 and 154 are replaced by decoders 253 and 254, and the recording area 126_-1~ 126_-3Recording area 206_-1~ 206_-3It becomes that. Thereby, the semiconductor memory 206 has a plurality of arithmetic units 204 in the column direction._-1~ 204_-NCan be accessed independently in predetermined memory cell units corresponding to each of the above.
[0282]
Next, a plurality of adders 209_-1~ 209_-NDetails of the semiconductor memory 210 for generating the histogram table will be described. Multiple adders 209_-1~ 209_-NAnd the semiconductor memory 210 are integrated, and a plurality of adders 209 are integrated._-1~ 209_-NA plurality of addition units in bit units constituting the same are arranged in alignment with the column pitch of the semiconductor memory 210.
[0283]
46 shows an adder 209._-1And the corresponding storage area 210 of the semiconductor memory 210_-1The detailed structure of the part is shown. Although explanation is omitted, adder 209_-2~ 209_-NAnd the corresponding storage area 210 of the semiconductor memory 210_-2~ 210_-NThis part is similarly configured.
[0284]
In FIG. 46, the storage area 210_-1The memory cell 130 includes n memory cells 130 in the column direction and one memory cell 130 in the row direction. In this case, one frequency storage area is constituted by n memory cells 130 arranged in the column direction. As described above with reference to FIG. 23, the memory cell 130 has a two-port configuration having a first port for writing and reading and a second port dedicated for reading.
[0285]
A word line WL and a read-only word line WRL are arranged along the memory cells 130 arranged in the column direction. The word line WL is connected to the terminal 13 of the memory cell 130, and the read-only word line WRL is connected to the terminal 17 of the memory cell 130.
[0286]
The bit lines BL are connected to n memory cells 130 arranged in the column direction.₀~ BL_n-1, / BL₀~ / BL_n-1, And read-only bit line BRL₀~ BRL_n-1Is connected. As described above, the bit line BL₀~ BL_n-1Is connected to the terminal 14 of the memory cell 130 and the bit line / BL₀~ / BL_n-1Are connected to the terminal 15 of the memory cell 130 and read-only bit line BRL.₀~ BRL_n-1Is connected to the terminal 16 of the memory cell 130.
[0287]
46 is the same as that of the adder 125 in FIG._-1And storage area 126_-1It is the same as that of the configuration.
Adder 209 shown in FIG._-1And storage area 210_-1The operation of this part will be described.
First, one frequency storage area is configured by n memory cells 130 arranged in the column direction. The operation of clearing the storage data of the n memory cells 130 will be described.
[0288]
When clearing the storage data of the n memory cells 130 constituting the frequency storage area, the write control signal φ_WAnd clear control signal φ_CLRIs active, that is, “1”, and the read control signal φ_RAnd equalize control signal φ_EQIs inactive, that is, “0”, and the word line WL is activated.
[0289]
In this case, the clear control signal φ_CLRIs activated and the transistor Q51 is turned on. Therefore, data “0” is generated, and this data is stored in the bit line BL.₀~ BL_n-1Is output. Therefore, by activating the word line WL, data “0” is written in the n memory cells 130 constituting the frequency storage area, and the stored data is cleared.
[0290]
Next, storage data MD stored in the frequency storage area (n memory cells 130)₀~ MD_n-1And an 8-bit count value D₀~ D₇, Adder 209_-1(Adder 140₁~ 140_n-1) And adder 209_-1Addition data AD obtained in₀~ AD_n-1The operation of writing back to the frequency storage area will be described.
[0291]
Storage data MD stored in a predetermined frequency storage area₀~ MD_n-1And an 8-bit count value D₀~ D₇First, equalize control signal φ_EQIs active, that is, “1”, and the write control signal φ_WRead control signal φ_RAnd clear control signal φ_CLRIs inactive, ie, “0”, and the bit line pair BL₀, / BL₀~ BL_n-1, / BL_n-1Is equalized (precharged).
[0292]
In this case, the bit line pair BL₀, / BL₀Is equalized control signal φ_EQIs activated, all of the transistors Q31 to Q33 are turned on, and the bit line BL₀And bit line / BL₀The power supply potential is applied to the bit lines BL.₀And bit line / BL₀Are at the same potential. Other bit line pairs BL₁, / BL₁~ BL_n-1, / BL_n-1The same applies to.
[0293]
In this way, the bit line pair BL₀, / BL₀~ BL_n-1, / BL_n-1In the state where equalization is performed, the read control signal φ_RIs active, that is, “1”, and the write control signal φ_W, Equalize control signal φ_EQAnd clear control signal φ_CLRIs inactive, ie, “0”, and the word line WL is further activated.
[0294]
Thereby, the storage data MD of the n memory cells 130 constituting the frequency storage area₀~ MD_n-1Are bit line pairs BL₀, / BL₀~ BL_n-1, / BL_n-1And sense amplifier SA₀~ SA_n-1And the adder 140₀~ 140_n-1Are respectively input to the B side input terminals. Therefore, the storage data MD stored in the frequency storage area₀~ MD_n-1And an 8-bit count value D₀~ D₇Is added.
[0295]
Then, the adding unit 140₀~ 140_n-1Addition output at, that is, addition data AD₀~ AD_n-1When becomes effective, write control signal φ_WIs active, that is, “1”, and the read control signal φ_R, Equalize control signal φ_EQAnd clear control signal φ_CLRIs inactive, ie, “0”, and the word line WL is further activated.
[0296]
In this case, the adding unit 140₀The additional data S for the part₀Is "1", the transistor Q11 is on, the transistor Q12 is off, and the bit line / BL₀Since “0” is output to the memory cell 130, the adder 140 out of the n memory cells 130 constituting the frequency storage area.₀Data “1” is stored in the memory cell 130 corresponding to. Meanwhile, the addition unit 140₀The additional data S for the part₀Is "0", the transistor Q11 is off, the transistor Q12 is on, and the bit line BL₀Since “0” is output to the memory cell 130, the adder 140 out of the n memory cells 130 constituting the frequency storage area.₀Data “0” is stored in the memory cell 130 corresponding to.
[0297]
Other adder 140₁~ 140_n-1The same applies to the portion of. Thus, the adder 209_-1Addition data AD obtained in₀~ AD_n-1Is written back to n memory cells 130 constituting the frequency storage area.
[0298]
In addition, in the case of overflow in the adding operation, the adding unit 140_n-1Carry output terminal C_OUTMSB carry output C obtained_MSBBecomes “1”, the transistor Q13 is turned off, and the additional data AD₀~ AD_n-1However, it is not written in the n memory cells 130 constituting the frequency storage area.
[0299]
Instead, in this case, in addition to the transistor Q61 being turned on, the transistor Q62 is also turned on, so that the bit line / BL₀~ / BL_n-1In this case, a signal of “0” is output. Therefore, data “1” is written in each of the n memory cells 130 constituting the frequency storage area. That is, the maximum value is stored in this frequency storage area.
[0300]
Next, the operation when reading the cumulative value (count value) stored in the frequency storage area will be described.
First, precharge control signal / φ_RPCIs active, ie, “1”, and the read-only bit line BRL₀~ BRL_n-1Is precharged. In this case, the transistor Q41 is turned on, and the read-only bit line BRL₀~ BRL_n-1The potential of the power supply is applied to each of the above.
[0301]
In this way, the read-only bit line BRL₀~ BRL_n-1The read-only word line WRL is activated in a state where the precharge is performed. Thereby, the storage data Σ of the n memory cells 130 constituting the frequency storage area₀~ Σ_n-1Are read-only bit lines BRL, respectively.₀~ BRL_n-1Is obtained. Here, the stored data Σ₀~ Σ_n-1Constitutes the cumulative value of the frequency of n bits.
[0302]
As described above, in the motion vector detection circuit 200 shown in FIG. 30, the pixel data constituting the predetermined reference block of the reference frame and the plurality of pixel data existing in the search range of the search frame corresponding to this pixel data For each pixel data constituting the reference block, when the difference absolute value is smaller than the threshold value, a value other than 0 is used as the count value. When the difference absolute value is equal to or greater than the threshold value, a count value table is generated in which 0 is assigned as the count value, and each count value in the count value table corresponding to each pixel data constituting the reference block is set as the frequency. A histogram table is generated by adding the frequency for each pixel position in the search range, and the motion vector of the reference block is based on the maximum value of the frequency in the histogram table. MV₁~ MV_nIs detected.
[0303]
In this case, the maximum value of the frequency in the histogram table represents a motion vector corresponding to the motion existing in the reference block. Only when the degree of matching is high and the difference absolute value is smaller than the threshold value, the count value table is generated by assigning a value other than 0 as the count value, and the histogram table is generated only by the high matching degree. Thus, the frequency distribution becomes sharper. For this reason, when a plurality of different motions are mixed in the reference block, a plurality of maximum values are easily clearly separated and shown in the histogram table. Accordingly, one or more motion vectors MV of the reference block₁~ MV_nCan be detected correctly.
[0304]
In addition, although the count value distribute | arranged when a difference absolute value is smaller than the threshold value is made into the positive value (refer Table 1), it is good also as a negative value. In this case, the histogram table shows the minimum value of the frequency representing the motion vector corresponding to the motion existing in the reference block. Even in this case, the motion vector of the reference block can be correctly detected based on the histogram table as in the above-described embodiment.
[0305]
Also, the count value distributed when the degree of matching is high and the difference absolute value is smaller than the threshold value is not a constant value, but the smaller the absolute difference value, that is, the higher the degree of matching, the larger the absolute value. Therefore, there is an advantage that the frequency distribution of the histogram table can be further sharpened.
[0306]
The correction coefficient acquisition unit 207 obtains an activity A for each pixel data constituting the reference block, and obtains a larger value as the correction coefficient k for each pixel data as the ratio of the activity A to the maximum activity A_max is higher. The correction value k is corrected by multiplying the count value of the count value table corresponding to each pixel data constituting the reference block by the correction coefficient k corresponding to each pixel data. It is possible to reduce problems caused by changes in absolute values.
[0307]
The correction coefficient acquisition unit 207 calculates the correction coefficient k, and the count value correction unit 208 multiplies the correction coefficient k by the count value. The threshold value used when generating the count value corresponding to the value may be changed so as to increase as the activity increases. In this case, as in the case where the count value is corrected by the correction coefficient k, the absolute value of the count value in the count value table corresponding to the pixel data of the reference block having a large activity in the surrounding area becomes large. As a result, the degree of matching due to the activity, that is, the inconvenience due to the change in the absolute difference value can be reduced.
[0308]
Further, a reference frame memory 203 for storing an input frame as a search frame as a reference frame of the next frame is provided, and a plurality of absolute difference calculators 204 are provided._-1~ 204_-NThus, every time pixel data of the input frame is input, an absolute difference between the pixel data and the pixel data of a predetermined reference block of the reference frame that is read from the frame memory 203 and includes the pixel data in the search range is calculated. To do. Therefore, it is possible to eliminate useless operations such as temporarily storing the search frame in the frame memory and then reading it again for processing, and the motion vector can be detected efficiently.
[0309]
Each word line extending in the column direction of the semiconductor memory 206 is connected to a plurality of storage areas 206._-1~ 206_-NThe semiconductor memory 206 is a row decode for selectively activating an arbitrary section word line among the plurality of section word lines constituting the arbitrary word line. It has a main row decoder 253 and a sub-row decoder 254 as means, and the semiconductor memory 206 can be accessed independently in section word line units in the column direction.
[0310]
In addition, a plurality of storage areas 206 of the semiconductor memory 206_-1~ 206_-NIs composed of a plurality of block storage areas BM for storing count values related to a plurality of reference blocks arranged in the row direction. The main row decoder 253 is a global word line corresponding to two consecutive block storage areas BM. The sub-row decoder 254 uses section word lines activated corresponding to the two global word lines as section word lines corresponding to different storage areas.
[0311]
Therefore, the plurality of absolute difference calculators 204_-1~ 204_-NEven when the absolute difference calculation related to the two reference blocks is performed in parallel, the count value generated by the count value generation unit 205 can be distributed and written to different word line positions in the row direction for each reference block. Thus, a count value table can be obtained for each reference block in the semiconductor memory 206.
[0312]
Also, adder 209_-1~ 209_-NAnd the semiconductor memory 210 are integrated, and a plurality of adders 140 in bit units constituting an adder.₀~ 140_n-1Are arranged in alignment with the column pitch of the semiconductor memory 210 (see FIG. 46). Therefore, the adder 209_-1~ 209_-NFrom the semiconductor memory 210 to the adder 209_-1~ 209_-NThe storage data can be efficiently supplied to the storage device.
[0313]
Further, the semiconductor memory 210 has a first port for writing and reading provided in association with a plurality of adders, and a second port dedicated for reading for reading the cumulative value of the frequency. (See FIG. 46). Therefore, the reading of the storage data of the semiconductor memory 210 is performed by the adder 209._-1~ 209_-NIt can be performed independently of the calculation according to.
[0314]
In addition, the motion vector MV of the reference block detected by the motion vector detection unit 211₁~ MV_nBased on the above, the motion vector identification unit 212 can identify the motion vector mv of each pixel data constituting the reference block. As described above, since the motion vector of the reference block can be correctly detected, the motion vector of each pixel data specified based on the motion vector also has higher accuracy.
[0315]
Further, since the motion vector specifying unit 212 performs correction processing such as removing an isolated motion vector from the motion vector mv of each pixel data constituting the reference block specified in this way, the motion vector of each pixel data Accuracy can be further increased.
[0316]
In the motion vector detection circuit 200 of FIG. 30, the semiconductor memory 206 activates two row position global word lines (section word lines) existing in a storage area corresponding to two reference blocks. However, with the same configuration, it is also possible to activate the global word lines (section word lines) at three or more row positions existing in the storage area corresponding to two or more reference blocks. Depending on the search range for one reference pixel in the reference block, it is also assumed that a plurality of absolute difference calculators perform operations related to three or more reference blocks. In this case, it is necessary to activate three or more row position global word lines (section word lines).
[0317]
In the motion vector detection circuit 200 of FIG. 30, the memory cell 130 constituting the semiconductor memory 210 has a 2-port configuration (see FIG. 23), but the memory cell may not have a 2-port configuration. The semiconductor memory 210 as a whole may have a 2-port configuration. Furthermore, even if the semiconductor memory 210 does not have a two-port configuration, for example, the frequency (table data) is read out during the blanking period in the video signal, or a plurality of identical functional blocks are interleaved between fields or frames. For example, the addition and the frequency reading may be performed in different periods in the same port.
[0318]
【The invention's effect】
The motion vector detection circuit according to the present invention provides a difference between pixel data of a predetermined reference block of a reference frame including the pixel data in a search range by a plurality of difference absolute value calculators each time pixel data of the search frame is input. An absolute value is obtained, and a motion vector of the predetermined reference block is detected based on the difference absolute value. When the search frame is an input frame, the search frame is temporarily stored in the frame memory and then processed again. For this reason, it is possible to eliminate useless operations such as reading for the purpose, and to efficiently detect the motion vector of the reference block.
[Brief description of the drawings]
FIG. 1 is a block diagram showing a configuration of a motion compensated prediction encoding apparatus as an embodiment.
FIG. 2 is a diagram for explaining a block matching method for motion vector detection when an input frame is a search frame and a past frame is a reference frame.
FIG. 3 is a block diagram showing a configuration of a motion vector detection circuit.
FIG. 4 is a diagram for explaining a matching operation for motion vector detection when an input frame is a search frame and a past frame is a reference frame.
FIG. 5 is a diagram illustrating a relationship between a reference block and a search range.
FIG. 6 is a diagram illustrating a relationship among input pixels, representative points of reference blocks, and arithmetic units.
FIG. 7 is a diagram illustrating a relative positional relationship between a representative point and an input pixel in one computing unit.
FIG. 8 is a diagram illustrating a positional relationship between a calculation target range of an input pixel and a reference block.
FIG. 9 is a diagram illustrating a positional relationship between a calculation target range of an input pixel and a reference block.
FIG. 10 is a diagram illustrating a positional relationship between a calculation target range of an input pixel and a reference block.
FIG. 11 is a diagram illustrating a positional relationship between a calculation target range of an input pixel and a reference block.
FIG. 12 is a diagram illustrating a positional relationship between a calculation target range of an input pixel and a reference block.
FIG. 13 is a diagram illustrating a positional relationship between a calculation target range of an input pixel and a reference block.
FIG. 14 is a diagram illustrating a positional relationship between a calculation target range of an input pixel and a reference block.
FIG. 15 is a diagram illustrating a calculation process in a plurality of difference absolute value calculators when obtaining correlation values of a plurality of candidate blocks corresponding to a predetermined reference block.
FIG. 16 is a diagram illustrating a representative point for every 4 × 4 pixels of a reference block;
FIG. 17 is a diagram showing a calculation process in a calculator (7, 7).
FIG. 18 is a diagram illustrating a motion vector (coordinates of a search range of one reference pixel).
FIG. 19 is a diagram illustrating a correspondence relationship between a motion vector and a storage position in a table generation memory.
FIG. 20 is a diagram showing an overall configuration of a semiconductor memory.
FIG. 21 is a diagram illustrating a configuration of a table generation memory.
FIG. 22 is a diagram showing a configuration in which a semiconductor memory and an adder are integrated.
FIG. 23 is a diagram showing a configuration of a memory cell.
FIG. 24 is a diagram showing a configuration of main / sub row decoders and word lines of a memory unit;
FIG. 25 is a diagram for explaining a problem (when there are a plurality of movements) of the block matching method.
FIG. 26 is a diagram for explaining an outline of a motion vector detection method;
FIG. 27 is a diagram illustrating an example of a correlation value table (when there are two movements).
FIG. 28 is a diagram illustrating an example of a histogram table (when there are two movements).
FIG. 29 is a diagram illustrating an example of pixel data for obtaining an activity.
FIG. 30 is a block diagram showing a configuration of a motion vector detection circuit.
FIG. 31 is a diagram illustrating a relationship between a reference block and a search range.
FIG. 32 is a block diagram illustrating a configuration of a motion vector specifying unit.
FIG. 33 is a diagram illustrating a relationship among input pixel data, a reference block, and a calculator.
FIG. 34 is a diagram illustrating a positional relationship between a calculation target range of input pixel data and a reference block.
FIG. 35 is a diagram illustrating a positional relationship between a calculation target range of input pixel data and a reference block.
FIG. 36 is a diagram illustrating a positional relationship between a calculation target range of input pixel data and a reference block.
FIG. 37 is a diagram illustrating a positional relationship between a calculation target range of input pixel data and a reference block.
FIG. 38 is a diagram illustrating a positional relationship between a calculation target range of input pixel data and a reference block.
FIG. 39 is a diagram illustrating a positional relationship between a calculation target range of input pixel data and a reference block.
FIG. 40 is a diagram showing a calculation process in a plurality of absolute difference calculators when obtaining a count value table corresponding to each pixel data constituting a predetermined reference block.
FIG. 41 is a diagram showing a calculation process in a calculator (7, 7).
FIG. 42 is a diagram illustrating a motion vector (coordinates of a search range of one reference pixel).
FIG. 43 is a diagram illustrating a correspondence relationship between a motion vector and a storage position in a count value table generation memory.
FIG. 44 is a diagram showing an overall configuration of a semiconductor memory.
FIG. 45 is a diagram showing a configuration of a storage area of a semiconductor memory.
FIG. 46 is a diagram showing a configuration in which a semiconductor memory and an adder are integrated.
FIG. 47 is a diagram for describing a block matching method for motion vector detection when an input frame is a reference frame and a past frame is a search frame.
FIG. 48 is a diagram for explaining a matching operation for motion vector detection when an input frame is a reference frame and a past frame is a search frame.
[Explanation of symbols]
DESCRIPTION OF SYMBOLS 100 ... Motion compensation prediction encoding apparatus, 101 ... Input terminal, 102 ... Subtractor, 103 ... DCT circuit, 104 ... Quantization circuit, 105 ... Output terminal, 106 ... Inverse quantization circuit, 107: Inverse DCT circuit, 108: Adder, 109: Frame memory, 110: Motion compensation circuit, 111, 200: Motion vector detection circuit, 121, 201 ... System controller, 122, 202 ... Input terminal, 123, 203 ... Reference frame memory, 124_-1~ 124_-N, 204_-1~ 204_-N... Difference absolute value calculator, 125_-1~ 125_-N209_-1~ 209_-N... Adder, 126 ... Semiconductor memory for correlation value table, 126_-1~ 126_-N... Storage area, 127 ... Correlation value table evaluator, 128, 213 ... Output terminal, 130 ... Memory cell, 140₀~ 140_n-1... Adding unit, 150_-1~ 150_-8... Memory unit 151, 251 ... Read row decoder, 153 ... Main row decoder for addition, 154 ... Sub row decoder for addition, 205 ... Count value generation unit, 206: Semiconductor memory for generating a count value table, 206_-1~ 206_-N... Storage area, 207 ... Correction coefficient acquisition unit, 208 ... Count value correction unit, 210 ... Semiconductor memory for generating a histogram table, 211 ... Motion vector detection unit, 212 ... Motion Vector specifying unit, 221... Controller, 222... Memory for search pixel, 223_-1~ 223_-n... Correlation calculation unit, 224 ... Motion vector temporary identification unit, 225 ... Motion vector correction unit, 253 ... Main row decoder for writing, 254 ... Sub-row decoder for writing

Claims (2)

A frame memory for storing an input frame as a probe search frame as a reference frame temporally before and after the next frame,
The pixel data of the input frame is input in common, and the pixel data of the predetermined reference block of the reference frame that is read from the frame memory and includes the pixel data of the input frame to be input included in the search range is input. A plurality of absolute difference calculators for calculating an absolute difference between the pixel data of the input frame and the pixel data of the predetermined reference block;
A motion vector detection processing unit that detects a motion vector of the predetermined reference block based on the difference absolute value obtained by being calculated by the plurality of difference absolute value calculators ;
The motion vector detection processing unit
Corresponding to each of the plurality of difference absolute values calculated by the plurality of difference absolute value calculators, when the difference absolute value is smaller than the threshold value, a predetermined value other than 0 is set, and the difference absolute value is A count value generating means for generating a count value to be 0 when the threshold value is exceeded;
First storage means for generating a count value table having a plurality of storage areas respectively corresponding to the plurality of difference absolute value calculators;
The count value generated by the count value generation unit corresponding to each of the absolute difference values calculated by the plurality of difference absolute value calculators is related to the count value of the first storage unit. The search range corresponding to each pixel data constituting the reference block is written in the first absolute value calculator and the count value storage area in the storage area corresponding to the pixel position of the reference block. Write control means for controlling so as to obtain a count value table in which count values are arranged corresponding to each pixel position;
Each count value of the count value table corresponding to each pixel data constituting the reference block obtained in the first storage means is a frequency, and the frequency is added for each pixel position of the search range, Histogram table generating means for generating a histogram table in which cumulative values of frequencies are arranged corresponding to each pixel position in the search range;
A motion vector detection circuit comprising: motion vector detection means for detecting a motion vector of the reference block based on the maximum or minimum value of the frequency in the histogram table . The histogram table generating means includes
A plurality of adders corresponding to the number of pixels in the search range;
Second storage means having a plurality of storage areas respectively corresponding to the plurality of adders;
Each of the plurality of count values in the count value table obtained in the first storage means is a frequency, and each of the plurality of frequencies is stored in a plurality of storage areas of the second storage means. Adding to each of the plurality of adders, and storing each of the addition data obtained by the plurality of adders in a plurality of storage areas of the second storage means, It repeats by the number of a plurality of count value tables corresponding to each pixel data constituting the reference block obtained in the storage means, and the second storage means stores the frequency corresponding to each pixel position in the search range. motion vector detecting circuit according to claim 1 that have a control means for controlling such a histogram table cumulative value was arranged is obtained.

Images