JP4348906B2 - Method for manufacturing substrate for electro-optical device - Google Patents

Description

[0001]
BACKGROUND OF THE INVENTION
The present invention relates to a substrate for an electro-optical device, a method for manufacturing the same, a liquid crystal device, and an electronic device. The present invention relates to a substrate, a method for manufacturing the same, a liquid crystal device using the substrate for an electro-optical device, and an electronic apparatus including the liquid crystal device.
[0002]
[Prior art]
Conventionally, liquid crystal is sandwiched between a pair of substrates having a conductive layer (transparent electrode) on the surface, and the alignment state of the liquid crystal is changed based on the voltage application state between the conductive layers, thereby modulating the light and displaying the gradation. A liquid crystal device that enables this is used. As a substrate in a liquid crystal device, a substrate in which a conductive layer made of a metal oxide such as ITO (Indium Tin Oxide) in which indium oxide is doped with tin oxide is widely used.
[0003]
As a method of forming the conductive layer, there is a method of increasing the crystallinity of the conductive layer by heat treatment for the purpose of improving optical characteristics and electrical characteristics after the conductive layer is once formed. For example, Japanese Patent Laid-Open No. 63-454 discloses a method in which a transparent conductive layer made of a metal oxide is formed on a substrate by vapor deposition or the like, and this transparent conductive layer is heated to increase its crystallinity. It is disclosed. Japanese Patent Application Laid-Open No. 8-64034 discloses a method in which an ITO film is formed on a base material by sputtering or the like, and this is converted into crystalline by heat treatment. In addition, Japanese Patent Application Laid-Open No. 2000-265259 discloses a method of forming a transparent conductive layer having high crystallinity on a substrate by an ion plating method using a pressure gradient type plasma gun.
[0004]
[Problems to be solved by the invention]
When a conductive layer of a substrate for an electro-optical device used in a liquid crystal device or the like has good optical characteristics (such as light transmittance) and electrical characteristics (such as resistivity), an electro-optical device including the substrate, for example, a liquid crystal device The display characteristics are excellent. Therefore, there is a demand for a substrate for an electro-optical device that is superior in terms of optical characteristics (light transmittance, etc.) and electrical characteristics (resistance, etc.). Further, in the conventional substrate for an electro-optical device, when a base material on which a conductive layer is to be formed is made of an organic material having a low bending elasticity such as plastic, the base material and the conductive layer are used when cooling after heat treatment. The substrate may be deformed (warped) due to the stress in the conductive layer caused by the difference in thermal expansion coefficient.
[0005]
The present invention has been made in view of the above circumstances, and the substrate for an electro-optical device, which is less likely to be deformed in the base material and has excellent optical characteristics and electrical characteristics, a method for manufacturing the same, and the substrate for an electro-optical device are used. An object is to provide a liquid crystal device and an electronic apparatus using the liquid crystal device.
[0006]
[Means for Solving the Problems]
The method for manufacturing a substrate for an electro-optical device according to the present invention includes a conductive layer forming step of forming a conductive layer on a base material, and the conductive layer forming step includes a step of forming an amorphous layer on the base material. A crystalline layer forming step, a heat treatment at 140 to 160 ° C. to generate crystal nuclei in an amorphous layer, and a heat treatment at 70 to 90 ° C. to grow the generated crystal nuclei And a crystal growth step of obtaining a conductive layer.
[0007]
Since the manufacturing method of the present invention includes a crystal nucleation process for generating crystal nuclei in an amorphous layer and a crystal growth process for growing crystal nuclei, by adjusting processing conditions in each process, Both nucleation and crystal growth can be performed under optimum conditions. For this reason, the crystal grain size and crystallinity of the conductive layer can be precisely adjusted with a high degree of freedom.
[0008]
Therefore, by performing heat treatment at a high temperature of 140 to 160 ° C. in the crystal nucleus generation step, it is possible to generate crystal nuclei with high crystallinity in the amorphous layer at a high density. By performing the heat treatment at a low temperature of 70 to 90 ° C. in the growth process, it is possible to suppress the formation of coarse crystals and to sufficiently grow crystal nuclei, with a small particle size, uniform particle size, and crystallinity. A conductive layer having an excellent crystal (or crystal structure) can be formed.
[0009]
Especially because the particle size is small and the particle size is uniform, when the conductive layer and the base material are cooled after the crystal growth process, the stress generated in the conductive layer due to the difference in thermal expansion coefficient between the conductive layer and the base material is relieved. it can. Therefore, it can suppress that a deformation | transformation (warp) arises in a base material. Therefore, it is possible to manufacture an electro-optical device substrate in which the base material is hardly deformed (warped). In addition, since the stress generated in the conductive layer due to the difference in coefficient of thermal expansion can be relieved, when processing the substrate for an electro-optical device obtained by the manufacturing method of the present invention, deformation (warping) occurs almost even when heated and cooled. Absent. Further, since the conductive layer is excellent in crystallinity, an electro-optical device substrate excellent in optical characteristics (light transmittance, etc.) and electrical characteristics (resistance, etc.) can be obtained.
[0010]
Furthermore, by performing heat treatment at a high temperature in the crystal nucleation step, crystal nuclei having sufficient crystallinity can be generated, so even if the heat treatment temperature in the crystal growth step is lowered, good crystal growth Is possible. For this reason, the heat treatment temperature in the crystal growth step can be set low, and stress generated in the conductive layer can be reduced when the conductive layer and the substrate are cooled after the crystal growth step. Therefore, it is possible to further prevent the substrate from being deformed (warped).
[0011]
In the manufacturing method of the present invention, the heat treatment in the crystal nucleation step can be performed using the first heat treatment furnace, and the heat treatment in the crystal growth step can be performed using the second heat treatment furnace. According to this manufacturing method, it is not necessary to change the set temperature in the heat treatment furnace according to the process, the transition from the crystal nucleation process to the crystal growth process can be performed quickly, and the manufacturing efficiency can be increased. .
[0012]
In the manufacturing method of the present invention, the heat treatment in the crystal nucleation step can be performed using a heat treatment furnace capable of arbitrarily setting the internal temperature, and the heat treatment in the crystal growth step can be performed using the heat treatment furnace. According to this manufacturing method, since the crystal nucleation step and the crystal growth step can be performed in a common heat treatment furnace, the space for the processing apparatus can be saved. Further, since it is not necessary to carry the substrate between the two steps, the manufacturing efficiency can be improved and the manufacturing cost can be reduced.
[0013]
In the manufacturing method of the present invention, the heat treatment in the crystal nucleation step and the crystal growth step is performed using a heat treatment furnace having first and second temperature adjustment regions that can be independently set to arbitrary temperatures. A method can be employed in which the heat treatment in the crystal nucleation step is performed in the first temperature adjustment region, and the heat treatment in the crystal growth step is performed in the second temperature adjustment region. According to this manufacturing method, it is not necessary to change the set temperature in the heat treatment furnace according to the process, the transition from the crystal nucleation process to the crystal growth process can be performed quickly, and the manufacturing efficiency can be increased. .
[0014]
In the manufacturing method of the present invention, the heat treatment in the crystal nucleation step and the crystal growth step can be performed by sequentially passing the first and second temperature adjustment regions while transporting the substrate in a predetermined direction in a heat treatment furnace. . According to this manufacturing method, the crystal nucleation step and the crystal growth step can be performed by a series of operations. Therefore, manufacturing efficiency can be increased.
[0015]
In the production method of the present invention, the heat treatment in the crystal growth step is performed by gradually lowering the heat treatment temperature, and the temperature lowering rate at this time can be 160 ° C./h or less. Thereby, crystal growth can be performed sufficiently and uniformly. Accordingly, a conductive layer having a crystal (or crystal structure) with uniform grain size and excellent crystallinity can be obtained, stress due to a difference in thermal expansion during cooling can be further relaxed, and deformation (warping) of the base material can be achieved. It can be suppressed from occurring.
[0016]
In the crystal nucleation step, the average heat treatment temperature is preferably 140 to 160 ° C. Thereby, crystal nuclei with high crystallinity can be generated in the amorphous layer at a high density. As a result, even when the heat treatment temperature in the crystal growth step is lowered, good crystal growth is possible. For this reason, the heat treatment temperature in the crystal growth step can be set low, and stress generated in the conductive layer can be reduced when the conductive layer and the substrate are cooled after the crystal growth step. Therefore, it is possible to suppress the deformation (warpage) of the base material. In addition, since a conductive layer having excellent crystallinity can be formed, an electro-optical device substrate having excellent electrical characteristics (such as resistivity) and optical characteristics (such as light transmittance) can be obtained.
[0017]
In the crystal growth step, it is preferable that the average value of the heat treatment temperature is 70 to 90 ° C. Accordingly, generation of coarse crystals can be suppressed, crystal nuclei can be sufficiently grown, and a conductive layer having a crystal (or crystal structure) having a small particle size, a uniform particle size, and excellent crystallinity can be formed. Therefore, after the completion of this step, stress due to the difference in thermal expansion coefficient between the conductive layer and the substrate can be relieved during cooling, and deformation (warping) of the substrate can be suppressed. In addition, an electro-optical device substrate having excellent electrical characteristics (such as resistivity) and optical characteristics (such as light transmittance) can be obtained.
[0018]
The conductive layer is preferably composed mainly of ITO (indium tin oxide). By using ITO excellent in light transmittance and resistivity, a transparent electrode having excellent electrical characteristics and optical characteristics can be formed. For example, an electro-optical device substrate suitable for an electro-optical device such as a liquid crystal device Can be obtained. In the present specification, the “mainly” element refers to the element that is contained most in the target element group, and the main component refers to the component that has the highest content among the constituent components. Say.
[0019]
The electro-optical device substrate of the present invention is manufactured by the above-described manufacturing method. The liquid crystal device of the present invention is a liquid crystal device in which a liquid crystal layer is formed between a pair of substrates, wherein the electro-optical device substrate is used as at least one of the pair of substrates. In this liquid crystal device, since the substrate for an electro-optical device having excellent electrical characteristics (such as resistivity) and optical properties (such as light transmittance) is used, display with excellent visibility is possible. An electronic apparatus according to the present invention includes the above-described liquid crystal device.
[0020]
DETAILED DESCRIPTION OF THE INVENTION
[Electro-optical device substrate]
Hereinafter, a first embodiment of a method for manufacturing a substrate for an electro-optical device according to the present invention will be described with reference to FIG. The manufacturing method of the present embodiment includes a conductive layer forming step of forming the transparent conductive layer 9 that is a conductive layer on the substrate 101. This conductive layer forming step has the following three steps.
(1) Amorphous layer forming step As shown in FIG. 1A, a substrate 101 is prepared. As the base material 101, a material made of an organic material may be used, or a material made of an inorganic material may be used. Examples of organic materials include methacrylate-based, polyester-based, polyolefin-based, polyamide-based, polycarbonate-based, polyamide-imide-based, and polysulfone-based synthetic resins (plastics). Examples of the inorganic material include quartz glass and soda glass.
[0021]
As shown in FIG. 1B, an amorphous layer 9a is formed on the substrate 101. Hereinafter, the base material 101 having the amorphous layer 9a is referred to as an amorphous layer forming substrate 100a. As a material of the amorphous layer 9a, indium tin oxide (ITO), indium oxide (In2O3), tin oxide (SnO2), or zinc oxide (ZnO) can be used. In particular, it is preferable to use ITO from the viewpoint of optical characteristics (light transmittance), electrical characteristics (resistivity), and the like. The amorphous layer 9a can be formed by a physical vapor deposition method such as an ion plating method, a sputtering method, a vapor deposition method, or a PLD method.
[0022]
Hereinafter, an example of a method for forming the amorphous layer 9a made of ITO by an ion plating method will be described with reference to FIG. FIG. 2 shows an example of an ion plating apparatus. The ion plating apparatus shown here includes a chamber 200, a vapor deposition source 201, a plasma generation unit 202, and an oxygen supply device 203. In this ion plating apparatus, the plasma discharge current value in the plasma generation unit 202, the oxygen supply amount in the oxygen supply apparatus 203, the temperature in the chamber 200, and the like can be arbitrarily set.
[0023]
In order to form the amorphous layer 9a, the vapor deposition source 201 is heated by an electron beam in the chamber 200 to generate vapor deposition particles made of ITO, and the generated vapor deposition particles are converted into plasma from the plasma generator 202. To be ionized and supplied to the surface of the substrate 101. At this time, the formed amorphous layer 9a is made amorphous by adjusting the plasma discharge current value, the amount of oxygen supplied into the chamber 200, the temperature in the chamber 200, and the like.
[0024]
In the manufacturing method of the present embodiment, the amorphous layer 9a is crystallized by performing an annealing process in the following crystal nucleation process and crystal growth process.
(2) Crystal Nucleation Step As shown in FIGS. 1B and 1C, a base material 101 (amorphous layer forming substrate 100a) having an amorphous layer 9a is formed in a first heat treatment furnace. It puts in a certain high temperature heat treatment furnace 102 and heat-processes.
[0025]
The heat treatment temperature is 140 to 160 ° C. If the treatment temperature is less than this range, crystal nuclei cannot be formed in the amorphous layer 9a at a high density, which is not preferable. When the treatment temperature exceeds the above range, the crystal growth reaction proceeds together with the crystal nucleation reaction, and the adjacent crystal nuclei are sintered to locally produce crystals having a large particle size. For this reason, crystals (or crystal structures) with uniform particle sizes cannot be formed even if the crystal growth step is subsequently performed. This is not preferable because the stress due to the difference in thermal expansion coefficient between the conductive layer and the substrate cannot be relieved during cooling, and the substrate is deformed (warped). Therefore, according to the present invention, by setting the heat treatment temperature in the crystal nucleus generation step within the above range, crystal nuclei with high crystallinity can be generated in the amorphous layer with high density. As a result, even when the heat treatment temperature in the crystal growth step is lowered, good crystal growth is possible. For this reason, the heat processing temperature in a crystal growth process can be set low, and the stress which arises in a conductive layer when cooling after a crystal growth process can be reduced. Therefore, it is possible to suppress the deformation (warpage) of the base material. In addition, since a conductive layer having excellent crystallinity can be formed, the transparent conductive layer 9 having excellent electrical characteristics (such as resistivity) and optical characteristics (such as light transmittance) can be obtained.
[0026]
The heat treatment time is preferably 30 to 40 minutes. When this treatment time is less than this range, it becomes difficult to generate stable crystal nuclei in the amorphous layer 9a. Further, if the treatment time exceeds the above range, the production efficiency is lowered, which is not preferable. For this reason, this invention can produce | generate a crystal nucleus with high crystallinity efficiently by making the heat processing time of a crystal nucleus production | generation process into the said range. By heat treatment using the high-temperature heat treatment furnace 102, crystal nuclei (fine seed crystals) with high crystallinity can be generated in the amorphous layer 9a with high density. As a result, the amorphous layer 9a becomes a crystal nucleation layer 9b having crystal nuclei inside. Hereinafter, the base material 101 having the crystal nucleation layer 9b is referred to as a crystal nucleation layer forming substrate 100b.
[0027]
(3) Crystal Growth Step As shown in FIGS. 1 (c) and 1 (d), the base material 101 (crystal nucleation layer forming substrate 100b) having the crystal nucleation layer 9b is a second heat treatment furnace. It puts in the low temperature heat processing furnace 103, and heat-processes. The heat treatment temperature in this step is 70 to 90 ° C. If the heat treatment temperature is less than this range, crystal growth tends to be insufficient. On the other hand, when the treatment temperature exceeds the above range, coarse crystals are formed, and crystals (or crystal structures) with uniform particle sizes cannot be formed. For this reason, when the transparent conductive layer 9 and the base material 101 are cooled after the crystal growth step, the stress generated in the transparent conductive layer 9 due to the difference in thermal expansion coefficient between the transparent conductive layer 9 and the base material 101 cannot be relaxed. The base material 101 is likely to be deformed (warped), which is not preferable. For this reason, by setting the heat treatment temperature within the above range, it is possible to obtain a transparent conductive layer 9 having a crystal having a small particle size, uniform particle size, and excellent crystallinity (or crystal structure). Deformation (warping) can be prevented from occurring.
[0028]
The heat treatment time is preferably 60 to 90 minutes. If this treatment time is less than this range, crystal growth tends to be insufficient. If the treatment time exceeds the above range, the production efficiency is lowered, which is not preferable. For this reason, this invention can produce | generate the crystal | crystallization (or crystal structure) excellent in crystallinity efficiently by making the heat processing time of a crystal growth process into the said range.
[0029]
By the heat treatment using the low-temperature heat treatment furnace 103, the crystal nuclei in the crystal nucleation layer 9b are crystal-grown to form crystals (or crystal structures) with small grain sizes, uniform grain sizes, and excellent crystallinity. The electro-optical device substrate 100 in which the transparent conductive layer 9 is formed on the base 101 is obtained by the transparent conductive layer forming step having the above three steps. By patterning the transparent conductive layer 9 by a known technique, a transparent electrode or the like can be formed.
[0030]
Since the manufacturing method of the present embodiment includes a crystal nucleation process for generating crystal nuclei in the amorphous layer 9a and a crystal growth process for growing crystal nuclei, by adjusting the processing conditions in the crystal nucleation process The density of crystal nuclei can be adjusted, and the crystal growth can be adjusted by adjusting the processing conditions in the crystal growth process. Thus, in this manufacturing method, since crystal nucleation and crystal growth are performed in separate steps, the crystal nucleation and crystal growth are both performed under optimum conditions by adjusting the processing conditions in each step. Can be made. For this reason, the crystal grain size and crystallinity of the transparent conductive layer 9 can be adjusted with a high degree of freedom and strictly compared to the conventional method in which the conductive layer is crystallized by a one-step heat treatment.
[0031]
Therefore, it is possible to form the transparent conductive layer 9 having a small particle size, a uniform particle size, and a crystal (or crystal structure) excellent in crystallinity. As a result, the stress generated in the conductive layer during cooling can be relieved, and the electro-optical device substrate 100 can be obtained in which the base material 101 hardly deforms (warps). Furthermore, the transparent conductive layer 9 is excellent in crystallinity, and excellent optical characteristics (light transmittance, etc.) and electrical characteristics (resistance, etc.) are obtained. Specifically, since the resistivity of the formed transparent conductive layer 9 is low, the wiring using the transparent conductive layer 9 can be miniaturized. In addition, the circuit speed can be increased.
[0032]
In addition, since crystal nucleation and crystal growth are performed in separate steps, crystal nuclei with high crystallinity can be generated in the crystal nucleation step, so even when the heat treatment temperature in the crystal growth step is low, it is satisfactory. Crystal growth is possible. For this reason, the heat processing temperature of a crystal growth process can be set low. For example, this processing temperature can be set to around 80 ° C. Therefore, when the transparent conductive layer 9 and the base material 101 are cooled after the crystal growth step, the stress generated in the transparent conductive layer 9 due to the difference in thermal expansion coefficient between the transparent conductive layer 9 and the base material 101 can be reduced.
[0033]
Therefore, even when the base material 101 made of a low-bending elastic organic material (plastic or the like) is used, it is possible to prevent the base material 101 from being deformed (warped). Therefore, the substrate 100 can be reduced in size and weight by using the base material 101 made of an organic material (plastic or the like). Further, it is possible to prevent the hue change (colored) of the transmitted light due to the deformation of the base material 101 and further improve the optical characteristics. Furthermore, since the processing temperature in the crystal growth process can be lowered, the heating cost can be reduced. In addition, the time required for the heat treatment can be shortened and the manufacturing efficiency can be increased.
[0034]
Further, since the heat treatment in the crystal nucleation process is performed using the high-temperature heat treatment furnace 102 and the heat treatment in the crystal growth process is performed using the low-temperature heat treatment furnace 103, the set temperature in the heat treatment furnace is changed according to the process. Therefore, the transition from the crystal nucleation process to the crystal growth process can be performed quickly, and the production efficiency can be increased.
[0035]
Next, a second embodiment of the manufacturing method of the present invention will be described with reference to FIG. In the manufacturing method of the present embodiment, the following (2) crystal nucleation step and (3) crystal growth step are performed following the (1) amorphous layer forming step, which is the same as the method of the first embodiment. .
(2) Crystal Nucleation Step The amorphous layer forming substrate 100a (see FIG. 1B) is placed in a heat treatment furnace (not shown) and heat-treated. As this heat treatment furnace, a furnace capable of arbitrarily setting the internal temperature is used. The solid line in FIG. 3 shows the change with time of the treatment temperature during the heat treatment. As shown in FIG. 3, in the manufacturing method of the second embodiment, the heat treatment temperature is increased to the maximum temperature tmax.
[0036]
In the example shown in FIG. 3, the heat treatment temperature is increased at a substantially constant rate of temperature increase. The heat treatment temperature in the crystal nucleation step is preferably set higher than the heat treatment temperature in the next crystal growth step. Specifically, the average value (the maximum temperature tmax in this example) is 140 to 160 ° C. It is preferable that When the heat treatment temperature is less than the above range, crystal nuclei are hardly generated in the amorphous layer 9a. If the heat treatment temperature exceeds the above range, crystals having a large particle size are locally generated, and crystals (or crystal structures) having a uniform particle size cannot be formed. For this reason, the stress due to the difference in thermal expansion cannot be relieved at the time of cooling, and deformation (warping) occurs in the substrate, which is not preferable.
[0037]
The heat treatment time (in this example, the time kept at the maximum temperature tmax) is preferably 30 to 40 minutes. When this treatment time is less than this range, it becomes difficult to generate stable crystal nuclei in the amorphous layer 9a. Further, if the treatment time exceeds the above range, the production efficiency is lowered, which is not preferable. For this reason, this invention can produce | generate efficiently the crystal nucleus with high crystallinity efficiently by making the heat processing time of a crystal nucleus production | generation process into the said range. By this heat treatment, crystal nuclei with high crystallinity are generated at a high density in the amorphous layer 9a, and the crystal nucleation layer forming substrate 100b having the crystal nucleation layer 9b is obtained.
[0038]
(3) Crystal growth step The crystal nucleation layer forming substrate 100b (see FIG. 1C) is heat-treated in a heat treatment furnace. As this heat treatment furnace, the one used in the crystal nucleation step can be used as it is. In the example shown by the solid line in FIG. 3, the heat treatment temperature is lowered at a substantially constant rate of temperature decrease. The temperature lowering rate is preferably 160 ° C./h or less. If the temperature lowering rate exceeds this range, the crystal growth cannot be sufficiently performed, and the grain size is not uniform. Therefore, the stress due to the difference in thermal expansion during cooling cannot be relaxed, and the base material is deformed (warped). Absent. Further, the temperature lowering rate is preferably 60 ° C./h or more. If the rate of temperature rise is less than this range, the production efficiency is lowered, which is not preferable. The end temperature tend can be room temperature, for example, 0 to 30 ° C.
[0039]
The heat treatment temperature in this step is preferably set to be lower than the heat treatment temperature in the crystal nucleation step. Specifically, the heat treatment temperature is an average temperature tave (the highest value in the example shown in FIG. 3). The average value of the temperature tmax and the end temperature tend is preferably 70 to 90 ° C. If the treatment temperature is below this range, crystal growth tends to be insufficient. If the treatment temperature exceeds the above range, it is not preferable because the base material 101 is likely to be deformed (warped) when the transparent conductive layer 9 and the base material 101 are cooled after the completion of this step.
[0040]
The heat treatment time (the time from reaching the maximum temperature tmax to the final temperature tend) is preferably 60 to 90 minutes. If this treatment time is less than this range, crystal growth tends to be insufficient. If the treatment time exceeds the above range, the production efficiency is lowered. For this reason, this invention can produce | generate the crystal | crystallization (or crystal structure) excellent in crystallinity efficiently by making the heat processing time of a crystal growth process into the said range.
[0041]
Crystal nuclei in the crystal nucleation layer 9b are grown by the heat treatment in this crystal growth step, and the crystal nucleation layer 9b is a transparent conductive layer having a crystal having a small particle size and excellent crystallinity (crystal structure). 9 By the transparent conductive layer forming step having the above three steps, an electro-optical device substrate 100 (see FIG. 1D) in which the transparent conductive layer 9 is formed on the base material 101 is obtained.
[0042]
Similar to the manufacturing method of the first embodiment, the manufacturing method of the second embodiment described above performs crystal nucleation and crystal growth in separate steps, thereby reducing the crystal grain size and crystallinity of the transparent conductive layer 9. It is highly flexible and can be adjusted precisely. Therefore, the stress generated in the conductive layer during cooling can be alleviated, and the substrate 100 for an electro-optical device can be obtained in which the base material 101 is hardly deformed (warped). Furthermore, since the transparent conductive layer 9 is excellent in crystallinity, excellent optical characteristics (light transmittance, etc.) and electrical characteristics (resistance, etc.) can be obtained. Further, since the heat treatment temperature in the crystal growth step can be set low, the deformation (warpage) of the base material 101 can be further reduced. Therefore, the base material 101 made of an organic material (plastic or the like) can be used, and the substrate 100 can be reduced in size and weight.
[0043]
In addition to this effect, the manufacturing method of this embodiment can obtain the following effects. Since the crystal nucleation step and the crystal growth step can be performed in a common heat treatment furnace, space can be saved in the processing apparatus as compared with the method of the first embodiment in which separate heat treatment furnaces are used for each step. it can. Further, since it is not necessary to carry the substrate between the two steps, the manufacturing efficiency can be improved and the manufacturing cost can be reduced.
[0044]
In the present invention, the temperature in the heat treatment furnace can be changed as indicated by a broken line in FIG. That is, in the crystal nucleus generation step, the heat treatment temperature is increased to a temperature tmax at which crystal nuclei can be generated in the amorphous layer 9a, and is maintained for a predetermined time. The processing conditions in the crystal nucleation step can be the same as in the method of the second embodiment. Next, the crystal nucleation layer forming substrate 100b is subjected to a crystal growth step. The heat treatment temperature is raised to a temperature tn at which crystal growth is possible, and this temperature tn is maintained for a predetermined time.
[0045]
The temperature tn is preferably 70 to 90 ° C. If the temperature tn is less than this range, crystal growth is difficult. On the other hand, when the temperature tn exceeds the above range, coarse crystals are formed, and crystals (or crystal structures) with uniform particle sizes cannot be formed. For this reason, the stress generated at the time of cooling cannot be relieved, and deformation (warping) occurs in the substrate, which is not preferable. The heat treatment time (time for maintaining the temperature tn) is preferably 60 to 90 minutes. When this treatment time is less than this range, the crystallinity becomes insufficient. Further, if the treatment time exceeds the above range, the production efficiency is lowered, which is not preferable.
[0046]
Therefore, by setting the heat treatment temperature and time within the above ranges, the transparent conductive layer 9 having a crystal having a small particle size, uniform particle size, and excellent crystallinity (or crystal structure) can be obtained. It is possible to prevent deformation (warpage) from occurring.
[0047]
Next, a third embodiment of the manufacturing method of the present invention will be described with reference to FIG. In the manufacturing method according to the present embodiment, the following (2) crystal nucleation step and (3) crystal growth step are performed following the (1) amorphous layer forming step similar to the method according to the first embodiment described above. I do.
(2) Crystal Nucleation Step FIG. 4 shows a heat treatment furnace that can be used in the present embodiment. The heat treatment furnace 51 shown here is a tubular heat treatment furnace main body 52 and a substrate transport for transporting a substrate therein. And a conveyer 53 as means. The heat treatment furnace body 52 is a tubular body having a carry-in port 52a on one end side and a carry-out port 52b on the other end side. The inside of the heat treatment furnace main body 52 is divided into two temperature adjustment regions 54 and 55 in the substrate transfer direction. The first temperature adjustment region 54 is closer to the carry-in port 52a and the second temperature adjustment region 54 is closer to the carry-out port 52b. The temperature adjustment region 55 can be set to an arbitrary temperature independently. The transfer conveyor 53 is provided along the longitudinal direction of the heat treatment furnace main body 52 so that the substrate placed on the upper surface thereof can be transferred from the carry-in port 52a toward the carry-out port 52b in the heat treatment furnace main body 52. It has become.
[0048]
In this step, the amorphous layer forming substrate 100a is placed on the transport conveyor 53 and transported through the heat treatment furnace main body 52 from the carry-in port 52a toward the carry-out port 52b. In this conveyance process, the amorphous layer forming substrate 100 a is introduced into the first temperature adjustment region 54. The furnace temperature (heat treatment temperature) in the first temperature adjustment region 54 is preferably set to 140 to 160 ° C. If the treatment temperature is less than this range, crystal nuclei cannot be formed at high density, which is not preferable. When the treatment temperature exceeds the above range, the crystal growth reaction proceeds together with the crystal nucleation reaction, and a crystal having a large particle size is locally generated. Even if the crystal growth process is subsequently performed, crystals with uniform particle sizes (or crystal structures) cannot be formed, and stress due to the difference in thermal expansion coefficient between the conductive layer and the substrate cannot be relieved during cooling. ) Is not preferable.
[0049]
In this step, it is preferable that the heat treatment time (the time for the amorphous layer forming substrate 100a to pass through the first temperature adjustment region 54) be 30 to 40 minutes. If the treatment time is less than this range, stable crystal nuclei are hardly generated. Further, if the treatment time exceeds the above range, the production efficiency is lowered, which is not preferable. For this reason, this invention can produce | generate efficiently the crystal nucleus with high crystallinity efficiently by making the heat processing time of a crystal nucleus production | generation process into the said range. In the process in which the amorphous layer forming substrate 100a passes through the first temperature adjustment region 54, crystal nuclei are generated in the amorphous layer 9a with high density, and the crystal nucleation layer forming substrate 100b having the crystal nucleation layer 9b is formed. Get.
[0050]
(3) Crystal Growth Step The crystal nucleation layer forming substrate 100 b is transported toward the transport outlet 52 b by the transport conveyor 53 and is introduced into the second temperature adjustment region 55. The furnace temperature (heat treatment temperature) in the second temperature adjustment region 55 is preferably 70 to 90 ° C. If the furnace temperature is below this range, crystal growth tends to be insufficient. When the furnace temperature exceeds the above range, coarse crystals are formed, and crystals (or crystal structures) with uniform grain sizes cannot be formed. For this reason, when it cools after a crystal growth process, it becomes easy to produce a deformation | transformation (warp) in the base material 101 by the stress by a thermal expansion coefficient difference, and is not preferable. For this reason, by setting the heat treatment temperature within the above range, it is possible to obtain a transparent conductive layer 9 having a crystal having a small particle size, uniform particle size, and excellent crystallinity (or crystal structure). Deformation (warping) can be prevented from occurring.
[0051]
In this step, it is preferable that the heat treatment time (the time for the crystal nucleation layer forming substrate 100b to pass through the second temperature adjustment region 55) be 60 to 90 minutes. If this treatment time is less than this range, crystal growth tends to be insufficient. If the treatment time exceeds the above range, the production efficiency is lowered. For this reason, this invention can produce | generate the crystal | crystallization (or crystal structure) excellent in crystallinity efficiently by making the heat processing time of a crystal growth process into the said range.
[0052]
In the process in which the crystal nucleation layer forming substrate 100b passes through the second temperature adjustment region 55, the crystal nuclei in the crystal nucleation layer 9b grow, and the crystal having a small grain size, uniform grain size, and excellent crystallinity ( Alternatively, the electro-optical device substrate 100 having the transparent conductive layer 9 having a crystal structure) can be obtained.
[0053]
As in the manufacturing method of the first embodiment, the manufacturing method performs crystal nucleation and crystal growth in separate steps, thereby allowing the transparent conductive layer 9 to have a crystal grain size and crystallinity with a high degree of freedom, and Can be adjusted strictly. Therefore, the stress generated in the conductive layer during cooling can be alleviated, and the substrate 100 for an electro-optical device can be obtained in which the base material 101 is hardly deformed (warped). Further, the transparent conductive layer 9 is excellent in crystallinity, whereby excellent optical characteristics (light transmittance, etc.) and electrical characteristics (resistance, etc.) are obtained. Moreover, since the heat treatment temperature in the crystal growth step can be set low, it is possible to further suppress the deformation (warpage) of the base material 101. Therefore, an organic material or the like can be used for the substrate 100, and the base material can be reduced in size and weight.
[0054]
In addition to this effect, the manufacturing method of this embodiment can obtain the following effects. Since the heat treatment in the crystal nucleation step and the crystal growth step is performed using a heat treatment furnace 51 having two temperature adjustment regions 54 and 55 that can be independently set to arbitrary temperatures, the method of the second embodiment (FIG. 3), it is not necessary to change the set temperature in the heat treatment furnace 51 according to the process. For this reason, the transition from the crystal nucleation step to the crystal growth step can be performed quickly, and the production efficiency can be increased.
[0055]
Further, the heat treatment in the crystal nucleation step and the crystal growth step is sequentially passed through the first and second temperature adjustment regions 54 and 55 while the substrate is being transported from the carry-in port 52a toward the carry-out port 52b in the heat treatment furnace 51. Therefore, the crystal nucleation process and the crystal growth process can be performed in a series of operations. Therefore, the substrate 100 can be continuously manufactured, and the manufacturing efficiency can be increased.
[0056]
[Liquid Crystal Device]
Next, an embodiment of the liquid crystal device of the present invention will be described. The liquid crystal device described below is an active matrix transmissive liquid crystal device using a TFT (Thin-Film Transistor) element as a switching element. In addition, the liquid crystal device of the present embodiment includes the electro-optical device substrate according to the present invention.
[0057]
FIG. 5 is an equivalent circuit diagram of switching elements, signal lines, and the like in a plurality of pixels arranged in a matrix constituting the image display region of the liquid crystal device of this embodiment. FIG. 6 is a plan view showing the structure of a plurality of pixel groups adjacent to each other on a TFT array substrate on which data lines, scanning lines, pixel electrodes and the like are formed. FIG. 7 is a cross-sectional view showing the structure of the liquid crystal device of this embodiment, and is a cross-sectional view taken along the line AA ′ of FIG. FIG. 7 illustrates the case where the upper side in the drawing is the light incident side and the lower side in the drawing is the viewing side (observer side).
[0058]
As shown in FIG. 5, in the liquid crystal device of the present embodiment, a plurality of pixels arranged in a matrix that forms an image display area include a pixel electrode 9 as a transparent conductive layer and energization control to the pixel electrode 9. TFT elements 30 that are switching elements for performing the above are formed, and a data line 6 a to which an image signal is supplied is electrically connected to the source of the TFT element 30. Image signals S1, S2,..., Sn to be written to the data line 6a are supplied line-sequentially in this order, or are supplied for each group to a plurality of adjacent data lines 6a.
[0059]
Further, the scanning line 3a is electrically connected to the gate of the TFT element 30, and the scanning signals G1, G2,..., Gm are pulse-sequentially line-sequentially arranged at a predetermined timing with respect to the plurality of scanning lines 3a. . Further, the pixel electrode 9 is electrically connected to the drain of the TFT element 30, and the image signal S1, S2,... Supplied from the data line 6a is turned on by turning on the TFT element 30 as a switching element for a certain period. , Sn is written at a predetermined timing.
[0060]
A predetermined level of image signals S1, S2,..., Sn written to the liquid crystal via the pixel electrode 9 is held for a certain period with the common electrode described later. The liquid crystal modulates light by changing the orientation and order of the molecular assembly according to the applied voltage level, thereby enabling gradation display. Here, in order to prevent the held image signal from leaking, a storage capacitor 70 is added in parallel with the liquid crystal capacitor formed between the pixel electrode 9 and the common electrode.
[0061]
Next, the planar structure of the liquid crystal device of this embodiment will be described with reference to FIG. As shown in FIG. 6, a plurality of pixel electrodes 9 (contours are indicated by dotted line portions 9A) are provided in a matrix on the TFT array substrate, and data lines 6a are provided along the vertical and horizontal boundaries of the pixel electrodes 9, respectively. A scanning line 3a and a capacitor line 3b are provided. In the present embodiment, each pixel electrode 9 and the area where the data line 6a, the scanning line 3a, the capacitor line 3b, etc. are arranged so as to surround each pixel electrode 9 are pixels, and are arranged in a matrix. The display can be displayed for each pixel.
[0062]
The data line 6a is electrically connected to a source region (described later) through a contact hole 5 in the semiconductor layer 1a made of, for example, a polysilicon film constituting the TFT element 30, and the pixel electrode 9 is connected to the semiconductor layer 1a. Among these, it is electrically connected to a drain region described later via a contact hole 8. In addition, the scanning line 3a is disposed so as to face a channel region (a region with a diagonal line rising to the left in the figure), which will be described later, of the semiconductor layer 1a. Function.
[0063]
The capacitor line 3b is formed from a main line portion extending in a substantially straight line along the scanning line 3a (that is, a first region formed along the scanning line 3a in a plan view) and a portion intersecting the data line 6a. And a protruding portion (that is, a second region extending along the data line 6 a when viewed in a plan view) protruding toward the previous stage (upward in the drawing) along the data line 6 a. In the drawing, a plurality of first light shielding films 11a are provided in a region indicated by oblique lines rising to the right.
[0064]
Next, a cross-sectional structure of the liquid crystal device of the present embodiment will be described based on FIG. As shown in FIG. 7, in the liquid crystal device of this embodiment, a liquid crystal layer 50 is sandwiched between the TFT array substrate 10 and the counter substrate 20 disposed to face the TFT array substrate 10. The TFT array substrate 10 is mainly composed of a substrate body 10A made of a light-transmitting material such as quartz, a TFT element 30, a pixel electrode 9, and an alignment film 40 formed on the surface of the liquid crystal layer 50 side. Reference numeral 20 is mainly composed of a substrate body 20A made of a translucent material such as glass or quartz, a common electrode 21 formed on the surface of the liquid crystal layer 50, and an alignment film 60.
[0065]
In the TFT array substrate 10, pixel electrodes 9 are provided on the surface of the substrate body 10 </ b> A on the liquid crystal layer 50 side, and pixel switching TFT elements 30 that perform switching control of the pixel electrodes 9 are provided at positions adjacent to the pixel electrodes 9. It has been. The pixel switching TFT element 30 has an LDD (Lightly Doped Drain) structure, and includes a scanning line 3a, a channel region 1a ′ of the semiconductor layer 1a in which a channel is formed by an electric field from the scanning line 3a, and the scanning line 3a. A gate insulating film 2 that insulates the semiconductor layer 1a, a data line 6a, a low concentration source region 1b and a low concentration drain region 1c of the semiconductor layer 1a, and a high concentration source region 1d and a high concentration drain region 1e of the semiconductor layer 1a. ing.
[0066]
Further, a second contact hole 5 leading to the high concentration source region 1d and a contact hole 8 leading to the high concentration drain region 1e are formed on the substrate main body 10A including the scanning line 3a and the gate insulating film 2. An interlayer insulating film 4 is formed. That is, the data line 6 a is electrically connected to the high concentration source region 1 d through the contact hole 5 that penetrates the second interlayer insulating film 4. Further, on the data line 6a and the second interlayer insulating film 4, a third interlayer insulating film 7 having a contact hole 8 leading to the high concentration drain region 1e is formed. That is, the high concentration drain region 1 e is electrically connected to the pixel electrode 9 through the contact hole 8 that penetrates the second interlayer insulating film 4 and the third interlayer insulating film 7.
[0067]
In the present embodiment, the gate insulating film 2 is extended from a position facing the scanning line 3a and used as a dielectric film, the semiconductor film 1a is extended to form the first storage capacitor electrode 1f, and further opposed thereto. The storage capacitor 70 is configured by using a part of the capacitor line 3b to be a second storage capacitor electrode.
[0068]
Further, on the surface of the TFT array substrate 10 on the liquid crystal layer 50 side of the substrate main body 10A, the TFT array substrate 10 is transmitted to the region where the pixel switching TFT elements 30 are formed, and the lower surface (TFT) of the TFT array substrate 10 is illustrated. The return light reflected by the interface between the array substrate 10 and air and returning to the liquid crystal layer 50 side is prevented from entering at least the channel region 1a ′ and the low concentration source / drain regions 1b and 1c of the semiconductor layer 1a. For this purpose, a first light shielding film 11a is provided.
[0069]
Further, a first interlayer insulation for electrically insulating the semiconductor layer 1a constituting the pixel switching TFT element 30 from the first light shielding film 11a is provided between the first light shielding film 11a and the pixel switching TFT element 30. A film 12 is formed. Further, as shown in FIG. 6, in addition to providing the first light shielding film 11 a on the TFT array substrate 10, the first light shielding film 11 a is electrically connected to the capacitor line 3 b at the preceding stage or the subsequent stage through the contact hole 13. Configured to connect to.
[0070]
An alignment film 40 for controlling the alignment of the liquid crystal molecules in the liquid crystal layer 50 when no voltage is applied is provided on the outermost surface of the TFT array substrate 10 on the liquid crystal layer 50 side, that is, on the pixel electrode 9 and the third interlayer insulating film 7. Is formed. In the liquid crystal device of the present embodiment, the pixel switching TFT element 30 through the third interlayer insulating film 7 from the substrate body 10A correspond to the base material 101 shown in FIG. 1, and the pixel electrode 9 formed on the upper layer thereof is transparent. This corresponds to the conductive layer 9. That is, the TFT array substrate 10 has the configuration of the electro-optical device substrate 100 shown in FIG.
[0071]
On the other hand, the counter substrate 20 has a surface on the liquid crystal layer 50 side of the substrate body 20A, which is a region facing the formation region of the data line 6a, the scanning line 3a, and the pixel switching TFT element 30, that is, an opening region of each pixel unit. The second light-shielding film 23 for preventing incident light from entering the channel region 1a ′, the low-concentration source region 1b, and the low-concentration drain region 1c of the semiconductor layer 1a of the pixel switching TFT element 30 in the other regions. Is provided. Further, the common electrode 21 made of ITO is formed on almost the entire surface of the substrate body 20A on which the second light-shielding film 23 is formed, and the liquid crystal layer 50 has a common electrode 21 when no voltage is applied. An alignment film 60 that controls the alignment of the liquid crystal molecules in the liquid crystal layer 50 is formed.
[0072]
In the liquid crystal device of this embodiment, the TFT array substrate (element substrate) 10 of the pair of substrates 10 and 20 that sandwich the liquid crystal layer 50 has the configuration of the electro-optical device substrate 100 shown in FIG. Since it is adopted, it is excellent in terms of optical characteristics (light transmittance, etc.) and electrical characteristics (resistance, etc.). Therefore, it is possible to display with excellent characteristics such as visibility.
[0073]
In the above-described embodiment, an example in which the configuration of the electro-optical device substrate 100 illustrated in FIG. 1 is adopted as the TFT array substrate (element substrate) 10 out of the pair of substrates 10 and 20 that sandwich the liquid crystal layer 50 is shown. However, in the present invention, at least one of the pair of substrates 10 and 20 only needs to have the configuration illustrated in FIG. For example, the configuration of the substrate 100 shown in FIG. 1 may be adopted for the counter substrate 20 having the common electrode 21. In this case, the common electrode 21 corresponds to the transparent conductive layer 9.
[0074]
Although the liquid crystal device as one embodiment of the present invention has been described above, the present invention is not limited to this. For example, in the present embodiment, only an active matrix type liquid crystal device using TFT elements has been described. However, the present invention is an active matrix type using TFD (Thin-Film Diode) elements that require electrode patterning for each pixel. The present invention can also be applied to a liquid crystal device, a passive matrix liquid crystal device that requires striped patterning, and the like.
[0075]
In the present embodiment, only the transmissive liquid crystal device has been described. However, the present invention is not limited to this, and can be applied to a reflective or transflective liquid crystal device. Thus, the present invention can be applied to a liquid crystal device having any structure. The substrate for an electro-optical device of the present invention can also be applied to an electro-optical device other than a liquid crystal device, for example, an organic electroluminescence device.
[0076]
[Electronics]
An example of an electronic device including the liquid crystal device according to the above embodiment will be described. FIG. 8A is a perspective view showing an example of a mobile phone. Reference numeral 500 denotes a mobile phone body, and reference numeral 501 denotes a liquid crystal display unit using the liquid crystal device of the above embodiment.
[0077]
FIG. 8B is a perspective view showing an example of a portable information processing apparatus such as a word processor or a personal computer. Reference numeral 600 denotes an information processing apparatus, reference numeral 601 denotes an input unit such as a keyboard, reference numeral 603 denotes an information processing apparatus body, and reference numeral 602 denotes a liquid crystal display unit using the liquid crystal device of the above embodiment.
[0078]
FIG. 8C is a perspective view showing an example of a wristwatch type electronic device. Reference numeral 700 denotes a watch body, and reference numeral 701 denotes a liquid crystal display unit using the liquid crystal device of the above embodiment. As described above, since the electronic device shown in FIG. 8 is obtained by applying the liquid crystal device of the above embodiment to the display portion, display with excellent visibility can be performed on the display portion.
[0079]
【The invention's effect】
As described above, the method for manufacturing a substrate for an electro-optical device according to the present invention includes a crystal nucleus generation step for generating crystal nuclei in an amorphous layer and a crystal growth step for growing crystal nuclei. By adjusting the processing conditions in this step, crystal nucleation and crystal growth can both be performed under optimum conditions. For this reason, the crystal grain size and crystallinity of the conductive layer can be precisely adjusted with a high degree of freedom.
[0080]
Therefore, a conductive layer having a crystal (or crystal structure) with a small particle size, uniform particle size, and excellent crystallinity can be formed. For this reason, during cooling, the stress generated in the conductive layer due to the difference in thermal expansion coefficient between the base material and the conductive layer can be relieved, the base material has almost no deformation (warping), and optical characteristics (light transmittance, etc.) and An electro-optical device substrate that is excellent in terms of electrical characteristics (such as resistivity) can be obtained.
[0081]
In addition, since crystal nucleation and crystal growth are performed in separate steps, sufficient crystal nucleation is possible in the crystal nucleation step, so that even when the heat treatment temperature in the crystal growth step is lowered, good crystal growth is achieved. It becomes possible. For this reason, the heat processing temperature in a crystal growth process can be set low. Therefore, when the conductive layer and the substrate are cooled after the crystal growth step, the stress caused by the difference in coefficient of thermal expansion can be further reduced. For this reason, for example, an organic material having low bending elasticity can be used as the base material, and the substrate can be reduced in size and weight.
[Brief description of the drawings]
FIG. 1 is an explanatory diagram illustrating a first embodiment of a method for manufacturing a substrate for an electro-optical device according to the invention.
2 is a schematic configuration diagram showing an ion plating apparatus that can be used in the manufacturing method shown in FIG.
FIG. 3 is an explanatory view showing a second embodiment of a method for manufacturing a substrate for an electro-optical device according to the invention.
FIG. 4 is a schematic configuration diagram showing a heat treatment furnace used in a third embodiment of a method for manufacturing a substrate for an electro-optical device according to the invention.
FIG. 5 is an equivalent circuit diagram of switching elements, signal lines and the like in one embodiment of the liquid crystal device of the present invention.
6 is a plan view showing a structure of a plurality of pixel groups adjacent to each other on a TFT array substrate of the liquid crystal device shown in FIG.
7 is a cross-sectional view illustrating a structure of the liquid crystal device illustrated in FIG.
FIGS. 8A and 8B are diagrams illustrating examples of the electronic apparatus of the present invention, in which FIG. 8A illustrates a mobile phone, FIG. 8B illustrates a portable information processing apparatus, and FIG. 8C illustrates a wristwatch type electronic apparatus.
[Explanation of symbols]
9 ... Transparent conductive layer (conductive layer), pixel electrode 9a ... amorphous layer 9b ... crystal nucleation layer 10 ... TFT array substrate 10A, 20A ... substrate body 20 ... opposite Substrate 30 ... TFT element 50 ... Liquid crystal layer 51 ... Heat treatment furnace 52 ... Heat treatment furnace body 54 ... First temperature adjustment region 55 ... Second temperature adjustment region 100 ... Electrooptic device substrate 100a ... amorphous layer forming substrate 100b ... crystal nucleation layer forming substrate 101 ... base material 102 ... high temperature heat treatment furnace (first heat treatment furnace)
103 ... Low temperature heat treatment furnace (second heat treatment furnace)
500... Mobile phone 600... Information processing device 700.

Claims (8)

Having a conductive layer forming step of forming a conductive layer on a substrate;
The conductive layer forming step includes an amorphous layer forming step of forming an amorphous layer on the substrate,
A crystal nucleation step in which heat treatment is performed at 140 to 160 ° C. to generate crystal nuclei in the amorphous layer;
A method of manufacturing a substrate for an electro-optical device, comprising: a crystal growth step in which heat treatment is performed at 70 to 90 ° C. to grow a generated crystal nucleus to obtain a conductive layer.   2. The electro-optical device according to claim 1, wherein the heat treatment in the crystal nucleation step is performed using a first heat treatment furnace, and the heat treatment in the crystal growth step is performed using a second heat treatment furnace. A method for manufacturing a substrate.   2. The electro-optic according to claim 1, wherein the heat treatment in the crystal nucleation step is performed using a heat treatment furnace capable of arbitrarily setting the internal temperature, and the heat treatment in the crystal growth step is performed using the heat treatment furnace. A method for manufacturing a substrate for an apparatus. The heat treatment in the crystal nucleation step and the crystal growth step is performed using a heat treatment furnace having first and second temperature adjustment regions that can be independently set to arbitrary temperatures,
2. The method for manufacturing a substrate for an electro-optical device according to claim 1, wherein the heat treatment in the crystal nucleation step is performed in the first temperature adjustment region, and the heat treatment in the crystal growth step is performed in the second temperature adjustment region.   5. The heat treatment in the crystal nucleation step and the crystal growth step is performed by sequentially passing the first and second temperature adjustment regions while transporting the substrate in a predetermined direction in a heat treatment furnace. A method for manufacturing a substrate for an electro-optical device.   4. The substrate for an electro-optical device according to claim 3, wherein the heat treatment in the crystal growth step is performed by gradually lowering the heat treatment temperature, and the temperature lowering rate at this time is set to 160 ° C./h or less. Method. In the crystal nucleation step, the average heat treatment temperature is 140 to 160 ° C.,
The method for manufacturing a substrate for an electro-optical device according to claim 6, wherein an average value of the heat treatment temperature is set to 70 to 90 ° C in the crystal growth step.   The method for manufacturing a substrate for an electro-optical device according to claim 1, wherein the conductive layer is mainly composed of ITO (indium tin oxide).

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