JP4354876B2 - Semiconductor device - Google Patents

Description

  The present invention relates to a semiconductor device, and more particularly to a high voltage MOSFET (Metal Oxide Semiconductor Field Effect Transistor) that reduces power loss when a parasitic diode operates.

  For isolation between elements of a semiconductor device, a junction isolation technique using a PN junction has been used for many years. However, in recent years, an SOI (silicon on insulator) substrate having a buried insulating film is formed with dielectric isolation in which a trench reaching from the surface of the SOI substrate to the buried insulating film is formed, and an insulating film is formed inside the trench. It is coming. In particular, in a semiconductor device in the field of high withstand voltage power that generally requires deep isolation, there is a disadvantage that the area of the isolation region becomes large when PN junction isolation is used, but isolation by using SOI-trench isolation. There is an advantage that the area of the region can be reduced and the chip can be reduced in size. In addition, there is an advantage that crosstalk between elements is eliminated, and it is easy to form a plurality of high withstand voltage power elements as output parts and a plurality of low withstand voltage elements as drive circuit parts in the same chip. is there. Because of the advantages as described above, development of products using SOI-trench isolation is active in high voltage power ICs for driving plasma displays and the like that particularly require a multi-output function.

FIG. 8 is a circuit diagram showing an example of an output circuit of a scan driver IC for driving a plasma display.
The output circuit includes high voltage power devices HP1 and HN1, parasitic diodes D1 and D2 formed in HP1 and HN1, a power supply terminal VDDH, a ground terminal VGND, a low voltage input terminal Vin, and an output terminal VOUT. The level shifter is configured to apply a voltage to the discharge cells of the plasma display panel through the output terminal VOUT. Here, HP1 is a high breakdown voltage P-channel MOSFET, and HN1 is a high breakdown voltage N-channel MOSFET.

Next, a high withstand voltage power element used in the scan driver IC will be described.
FIG. 9 is a diagram showing an example of the structure of a conventional high voltage N-channel MOSFET which is a high voltage power element, and all corresponds to HN1 in FIG. FIG. 9A is a top view of the high breakdown voltage N-channel MOSFET, and FIG. 9B is a cross-sectional view of the high breakdown voltage N-channel MOSFET (cross-sectional view taken along YO in FIG. 9A).

  The high breakdown voltage N-channel MOSFET includes an SOI substrate 101, a gate oxide film 111 formed on the SOI substrate 101, a thick LOCOS (local oxidation of silicon) oxide film 112, a LOCOS oxide film 112, and a gate oxide film 111. A part of the LOCOS oxide film 112 and a gate electrode 113 formed on the gate oxide film 111 are formed.

The SOI substrate 101 includes a silicon substrate 102, a buried oxide film 103, and a p-type active layer 104. A p-type body region 105 and an n-type drain offset region 106 are formed in the p-type active layer 104 so as to be exposed on the surface of the SOI substrate 101. An n ⁺ type source region 107 and a p ⁺ type body contact region 108 are formed in the p type body region 105, and an n type drain buffer region 109 and an n ⁺ type drain region 110 are formed in the n type drain offset region 106. Is formed. In this structure, a parasitic diode is formed between the p-type body region 105 and the n-type drain offset region 106. This parasitic diode is particularly relevant to the present invention.

The gate oxide film 111 is formed above the region serving as a channel in the surface of the SOI substrate 101. On the other hand, the LOCOS oxide film 112 is above the surface of the SOI substrate 101 where the n ⁺ -type source region 107, the p ⁺ -type body contact region 108 and the n ⁺ -type drain region 110 are not formed, and the gate oxide film 111. Is formed in a portion where no is formed.

On the upper surface of the SOI substrate 101, as shown in FIG. 9A, an n ⁺ type source region 107, a p ⁺ type body contact region 108, and a gate electrode 113 are formed outside the n ⁺ type drain region 110 as a center. A racetrack-shaped top surface pattern is formed. In other words, the linear portion formed by the n ⁺ -type source region 107, the p ⁺ -type body contact region 108, and the gate electrode 113 and the arc portions at both ends of the linear portion completely surround the central n ⁺ -type drain region 110. A top pattern is formed. This is because current capacity is required when charging / discharging the discharge cells of the plasma display panel. Therefore, by increasing the facing length between the source and drain, the channel width is limited even within a limited device area. This is because it is common to design a device so as to be large.

In addition, there exists a technique of patent document 1 as a prior art which shows another upper surface pattern. The purpose of this is to prevent current concentration occurring in the arc portion during device operation and to improve the withstand voltage when turned on. As shown in the top view of FIG. 10, as shown in FIG. The above object is achieved by deleting the n ⁺ -type source region 107 of the arc portion existing at both ends of the element from the upper surface pattern.

Next, an example of the operation of the scan driver IC will be briefly described.
There are three main steps for driving a plasma display. That is, there are three steps: an initialization period for making the charge information of all the discharge cells uniform, an address period for writing data in the discharge cells, and a discharge maintenance period for maintaining the discharge. An image is displayed by sequentially repeating these steps. In driving, in addition to the scan driver IC, a data driver IC and a sustain driver IC are simultaneously used. In the discharge sustain period of the three steps, in the output circuit shown in FIG. 8, current is drawn from the ground terminal VGND to the output terminal VOUT through HN1. At this time, HN1 is in an ON state, and the output terminal VOUT is LOW. That is, HN1 is in an on state, and the potential of the drain is kept low with respect to the source. This state will be described with reference to the cross-sectional view of FIG.

The current flowing through HN1 during the discharge sustain period basically flows as a forward current of the parasitic diode. This parasitic diode is a parasitic diode formed between the p-type body region 105 and the n-type drain offset region 106 in FIG. However, since HN1 is on, there is current through the channel at the same time. Therefore, a current constituted by the channel current component accompanying the ON state and the parasitic diode current component flows as a total current. In general, when a forward bias applied between the anode and the cathode exceeds a built-in voltage, the diode starts to operate and a diode current flows in the forward direction. Therefore, even if a bias is applied between the source and drain of HN1, only the channel current flows if the voltage applied across the parasitic diode is less than the built-in voltage. This is because if the channel is formed while HN1 is on, current flows through the channel even in a relatively low bias state where the parasitic diode does not start forward operation. When the voltage applied to both ends of the parasitic diode exceeds the built-in voltage, a current obtained by adding the parasitic diode current to the channel current component flows.
Japanese Patent No. 3473460 (Section 7, FIG. 3)

  However, if a conventional high breakdown voltage MOSFET is used for the high breakdown voltage power element of the scan driver IC and the parasitic diode is operated during the discharge sustain period, the diode does not operate even if the built-in voltage is exceeded, and the voltage for starting the diode operation is The problem of rising significantly arises. This point will be described with reference to FIGS. 11, 12, and 13. FIG.

  FIG. 11 is a diagram showing an example of a bias state during the discharge sustaining period when the conventional high voltage MOSFET shown in FIGS. 9A and 9B is used as a high voltage power element of the scan driver IC. .

  From FIG. 11, since HN1 is in the on state during the discharge sustain period and the potential of the drain with respect to the source is kept low, the output circuit has a channel current component (IA) associated with HN1 being in the on state. It can be seen that there is a current constituted by the current component (IB) of the parasitic diode D1. The channel current component (IA) and the current component (IB) of the parasitic diode D1 will be further described with reference to FIG.

  FIG. 12 is a diagram showing the relationship between the source-drain potential difference and the source-drain current of HN1 in the bias state shown in FIG. In FIG. 12, the solid line is when HN1 is in the on state, and the broken line is when HN1 is in the off state.

  From FIG. 12, when HN1 is in the off state, the channel current component (IA) does not exist, and only the current component (IB) of the parasitic diode D1 contributes. You can see that That is, it can be seen that a rapid increase in current is observed from about 0.7 V corresponding to the built-in voltage. On the other hand, when HN1 is in the ON state, it can be seen that the characteristics are greatly different from those of a normal diode. That is, when the voltage corresponding to the built-in voltage exceeds about 0.7V, the channel current component (IA) continues to increase monotonously and reaches the forward diode voltage (VF) as shown by the dotted line in the figure. It can be seen that the parasitic diode D1 finally starts to operate and the diode current component (IB) flows. This operation principle will be further described with reference to FIG.

  FIG. 13A is a top view of a conventional high voltage MOSFET, and FIGS. 13B and 13C are cross-sectional views of the high voltage MOSFET (a cross-sectional view taken along YO in FIG. 13A). In FIG. 13B, the broken line indicates the current distribution after the forward operation of the parasitic diode D1 is started during the discharge sustain period. In FIG. 13C, the broken line indicates the current distribution before the start of the forward operation of the parasitic diode D1 during the discharge sustain period, and the solid line indicates the potential distribution at that time.

  From FIG. 13 (c), the channel current component (IA) already exists in the source-drain potential difference lower than the forward diode voltage (VF), and is caused by the channel current before the start of the forward operation of the parasitic diode D1. It can be seen that the generated potential distribution occurs in the element. It can be seen that the channel current forms a potential distribution perpendicular to the current between the source and drain. At this time, when the PN junction surface forming the parasitic diode D1 is roughly divided into two, that is, a vertical surface near the gate electrode 113 and a bottom surface extending to the drain side, the potential distribution due to the channel current near the vertical surface is approximately It is held at a value close to the source potential, and no potential difference occurs at the PN junction. Further, regarding the PN junction surface on the bottom surface, the potential distribution is perpendicular to the junction surface, and no potential difference is generated in the PN junction. This is a direct factor that the parasitic diode D1 does not start the forward operation even when a potential difference corresponding to the built-in voltage is applied between the source and the drain. However, when a larger potential difference is applied between the source and the drain, a potential difference capable of forward operation also occurs at the PN junction of the parasitic diode D1, and the current component (IB) of the parasitic diode D1 suddenly increases at this moment. Begins to flow. The voltage at which the current component (IB) of the parasitic diode D1 starts to flow is the forward diode voltage (VF) shown in FIG.

  Here, the structure of another conventional example shown in FIG. 10 will be taken up. In the structure of FIG. 10, since the source of the arc region at both ends of the element is deleted, basically no channel current exists in the arc portion. Therefore, when the built-in voltage is exceeded in the arc portion, the parasitic diode should start operating. However, in actuality, the area occupied by the arc portion is very small compared to the area of the straight line portion, and the channel current wraps around from the straight line portion, so that the voltage for starting the diode operation greatly increases.

  Due to the above mechanism, in the conventional high voltage MOSFET, when the parasitic diode is operated during the discharge sustain period, the voltage for starting the diode operation greatly increases. Therefore, an extra voltage is required to pass a current through the diode, causing a problem that power loss of the parasitic diode increases.

  On the other hand, as a method of avoiding this problem, a method of forming an external diode in parallel with the high voltage MOSFET can be considered. However, if a diode is formed separately, the element area becomes larger compared to the case where a parasitic diode is used because an extra isolation region for separating the diode is required.

  In view of the above problems, an object of the present invention is to provide a semiconductor device that suppresses power loss of a parasitic diode.

In order to achieve the above object, a semiconductor device of the present invention is a semiconductor device in which a transistor including a gate electrode, a source region, and a drain region is formed on a semiconductor substrate, and the semiconductor substrate includes an element isolation region. The element isolation region completely surrounds the transistor on the upper surface of the semiconductor substrate, and the gate electrode is one of the source region and the drain region on the upper surface of the semiconductor substrate. A second region, which is the other of the source region and the drain region, is formed along a part of the linear portion, and includes the other of the linear portion. a structure that is not formed along the section, the other section and length of the arc portion other than a portion of the straight portion, the second region and the first region Characterized in that it is more than four times of the distance between the. Here, the present invention is a semiconductor device in which a transistor including a gate electrode, a LOCOS oxide film, a gate oxide film, a source region, and a drain region is formed on a semiconductor substrate, and the semiconductor substrate includes an element isolation region. The element isolation region completely surrounds the transistor on the upper surface of the semiconductor substrate, and the gate electrode and the first region that is one of the source region and the drain region are An upper surface of the semiconductor substrate has an arc portion and a straight portion formed so as to surround the second region which is the other of the source region and the drain region, and a part of the gate electrode of the straight portion has the LOCOS oxide film formed thereon, the gate electrode of the other portions and the arcuate portions other than the portion of the straight portion, the LOCOS oxide film and the gate In a structure formed on the oxide film, the other portion and the length of the arc portion other than a portion of the straight portion, or 4 times the distance between the first region and the second region The semiconductor device may be a semiconductor device including a transistor including a gate electrode, a source region, and a drain region formed on a semiconductor substrate, and the semiconductor substrate includes an element isolation region. The element isolation region completely surrounds the transistor on the upper surface of the semiconductor substrate, and the first region that is one of the source region and the drain region is the source on the upper surface of the semiconductor substrate. An arc portion and a straight portion formed so as to surround the second region which is the other of the region and the drain region, and the gate electrode extends along a part of the straight portion. Formed Te, wherein a other part and not formed along the arc portion structure other than a portion of the linear portion, the other portion and the length of the arc portion other than a portion of said straight portion, said first The semiconductor device may be characterized in that it is at least four times the distance between the region and the second region . The first region may be a drain region. In addition, a racetrack-shaped top pattern in which the gate electrode is formed outside the first region may be formed on the semiconductor substrate top surface, and the comb-shaped top pattern may be formed on the semiconductor substrate top surface. An upper surface pattern having a shape formed so as to be opposed to each other so that the first region and the finger-like portions of the gate electrode are combined with each other is formed, and the tip portion of the finger-like portion and the valley portion between the finger-like portions have a curvature. You may have. The transistor may further include a drain offset region surrounding the drain region, the semiconductor substrate is an SOI substrate having an element isolation region, and the element isolation region is formed on an upper surface of the semiconductor substrate. The transistor may be completely surrounded.

  As a result, a portion functioning as a diode can be formed over a wide range, and current flow from a portion functioning as a transistor can be suppressed. Therefore, even when the parasitic diode is operated in the on state, the potential distribution due to the channel current is not formed in the parasitic diode, so that a semiconductor device in which the diode characteristics of the parasitic diode are equivalent to those of a normal diode is realized. Can do. That is, a semiconductor device that suppresses power loss of the parasitic diode can be realized.

Further, the length of the other part of the linear part and the arc part may be four times or more the distance between the first area and the second area.
As a result, the forward diode voltage of the parasitic diode can be made equal to that of a normal diode, that is, almost the same as the voltage equivalent to the built-in voltage, so that a semiconductor device that further suppresses the power loss of the parasitic diode is realized. Can do.

The gate electrode of the arc portion may be formed on the LOCOS oxide film.
As a result, a semiconductor device that suppresses power loss of the parasitic diode can be realized.

  Further, the gate electrode is not formed along the arc portion, and is formed by the LOCOS oxide film between the first region and the second region of the arc portion, and the first region and the second region of the arc portion are formed. The distance between the regions may be shorter than the distance between the first region and the second region in the other part of the linear portion.

  As a result, it is possible to realize a semiconductor device that improves the current capability of the parasitic diode and reduces the element area.

  According to the semiconductor device of the present invention, it is possible to suppress the power loss of the parasitic diode while reducing the sacrifice of the current capability as the output element. Further, the current capability of the parasitic diode can be improved, and the element area can be reduced.

  Therefore, according to the present invention, it is possible to provide a semiconductor device that suppresses power loss of a parasitic diode, and its practical value is extremely high.

Hereinafter, semiconductor devices according to embodiments of the present invention will be described with reference to the drawings.
(First embodiment)
FIG. 1A is a top view of the high breakdown voltage MOSFET in the first embodiment, and FIG. 1B is a cross-sectional view of the high breakdown voltage MOSFET (a cross-sectional view taken along YO in FIG. 1A). FIG. 1C is a cross-sectional view of the high breakdown voltage MOSFET (cross-sectional view taken along Y1-X1 in FIG. 1A).

  The high voltage MOSFET includes an SOI substrate 1, a gate oxide film 11 and a thick LOCOS oxide film 12 formed on the SOI substrate 1, and a LOCOS oxide film 12 over the LOCOS oxide film 12 and the gate oxide film 11. And a gate electrode 13 formed on the gate oxide film 11. At this time, the outer periphery of the high voltage MOSFET is surrounded by a trench element isolation region 14 in which an insulating film is formed inside the trench.

The SOI substrate 1 includes a silicon substrate 2, a buried oxide film 3, and a p-type active layer 4. Within the p-type active layer 4, a p-type body region 5 and an n-type drain offset are exposed to the surface of the SOI substrate 1. Region 6 is formed. An n-type drain buffer region 9 and an n ⁺ -type drain region 10 are formed in the n-type drain offset region 6. In this structure, a parasitic diode is formed between the p-type body region 5 and the n-type drain offset region 6.

Here, the SOI substrate 1 includes a first portion that functions as a transistor ((A) in FIG. 1A) and a second portion that functions as a diode ((B) in FIG. 1A). The p-type body region 5 has a different structure. That is, the SOI substrate 1 of the first portion has a p-type body region 5 in which an n ⁺ -type source region 7 and a p ⁺ -type body contact region 8 are formed, as shown in FIG. 1B. . The SOI substrate 1 of the second part has a p-type body region 5 in which only a p ⁺ -type body contact region 8 is formed, as shown in FIG.

Gate oxide film 11 is formed above the surface of SOI substrate 1 above the region that becomes the channel including p-type body region 5.
The LOCOS oxide film 12 is above the region of the SOI substrate 1 where the n ⁺ -type source region 7, the p ⁺ -type body contact region 8 and the n ⁺ -type drain region 10 are not formed, and the gate oxide film 11. It is formed in the part where is not formed.

On the top surface of the SOI substrate 1, as shown in FIG. 1A, a racetrack-shaped top surface pattern is formed in which a p-type body region 5 and a gate electrode 13 are formed outside the n ⁺ -type drain region 10. Is done. That is, an upper surface pattern is formed in such a shape that the linear portion formed by the p-type body region 5 and the gate electrode 13 and the arc portions at both ends of the linear portion completely surround the central n ⁺ -type drain region 10. At this time, the p-type body region 5 of the first portion forms a part of the racetrack-shaped straight portion on the upper surface of the SOI substrate 1. On the other hand, the p-type body region 5 of the second part forms the other part of the racetrack-shaped straight part and the arc part. Therefore, the n ⁺ -type source region 7 exists only in a part of the straight part of the racetrack shape, and does not exist in the other part of the straight part and the arc part.

Here, the length of the other part of the straight line portion where the n ⁺ -type source region 7 does not exist and the length of the arc portion ((C) in FIG. 1 (a)) are the values of the n ⁺ -type source region 7 and the n ⁺ -type drain region 10. It is 4 times or more of the distance ((D) in Fig.1 (a)).

Next, a quantitative relationship between the forward diode voltage (VF) of the parasitic diode and the length of the other part of the linear part where the n ⁺ type source region 7 does not exist and the length of the arc part will be described.
FIG. 2 is a diagram illustrating a change in the forward diode voltage (VF) of the parasitic diode when the numerical value (X) is changed. The numerical value (X) is a value calculated by dividing the length of the other part of the straight line part and the arc part by the distance between the n ⁺ type source region 7 and the n ⁺ type drain region 10.

As shown in FIG. 2, the forward diode voltage (VF) increases when the length of the other part of the linear portion and the arc portion is short, and conversely, the forward diode voltage (VF) increases as the length increases. It turns out that it becomes low. Further, it can be seen that when the numerical value (X) is about 4, the forward diode voltage (VF) is almost the same as the forward diode voltage in the off state, and is almost constant beyond that. That is, when the length of the other part of the straight part and the arc part is four times the distance between the n ⁺ -type source region 7 and the n ⁺ -type drain region 10, the diode characteristics of the parasitic diode are usually It can be seen that this is equivalent to the diode.

As described above, according to the high breakdown voltage MOSFET of the present embodiment, the n ⁺ type source region 7 is sufficiently deleted from the arc portion of the racetrack shape to the other portion of the linear portion . Therefore, a portion specialized as a diode can be formed over a wide range on the SOI substrate 1, and current wraparound from a straight portion where the n ⁺ -type source region 7 exists can be suppressed. Therefore, even when the parasitic diode is operated in the ON state, the potential distribution due to the channel current is not formed in the parasitic diode, and the rise of the voltage for starting the diode operation can be prevented. MOSFET can make the diode characteristic of a parasitic diode equivalent to a normal diode. That is, the power loss of the parasitic diode can be suppressed.

Further, in the high voltage MOSFET of the present embodiment, a portion functioning as a diode is formed on the SOI substrate 1 using the p-type body region 5 that forms the arc portion. However, when the p-type body region 5 that forms the arc portion is used to form a portion that functions as a transistor on the SOI substrate 1, the electric field strength is increased in the arc portion. It is necessary to set a long distance between the n ⁺ type source region 7 and the n ⁺ type drain region 10 in the arc portion. Therefore, the high voltage MOSFET according to the present embodiment secures a portion that functions as a diode at the expense of a transistor having a large resistance component and a low current capability. The power loss of the diode can be suppressed.

In the high breakdown voltage MOSFET of the present embodiment, a shape in which the gate electrode 13 completely surrounds the n ⁺ -type drain region 10, that is, a racetrack-shaped top pattern is formed on the top surface of the SOI substrate 1. However, as shown in the top view of the high breakdown voltage MOSFET of FIG. 3, the n ⁺ -type drain region 10 and the gate electrode 13 surround the other, that is, the comb-shaped n ⁺ -type drain region on the top surface of the SOI substrate 1. An upper surface pattern having a shape formed so as to face each other so that the finger portions of the gate electrode 10 and the gate electrode 13 are combined may be formed. At this time, the p-type body region 5 of the first portion ((A) in FIG. 3) is formed along the comb-shaped linear portion on the upper surface of the SOI substrate 1, and the second portion ((B in FIG. 3) The p-type body region 5)) is formed along the other part of the comb-shaped linear part, the tip part and the valley part of the finger-like part having curvature. Here, the length of the other part of the straight part where the n ⁺ type source region 7 does not exist, the tip part of the finger-like part, and the valley part ((C) in FIG. 3) is the same as the n ⁺ type source region 7 and the n ⁺ type. The distance between the drain region 10 and the drain region 10 ((D) in FIG. 3) is four times or more. As a result, as in the case where the racetrack-shaped top surface pattern is formed, the channel length is increased by increasing the opposing length between the n ⁺ -type source region 7 and the n ⁺ -type drain region 10, and the current capability as a MOSFET is increased. Can be improved.

In the high breakdown voltage MOSFET of the present embodiment, the first portion of the p-type body region 5 forms part of the racetrack-shaped straight portion on the upper surface of the SOI substrate 1 and the second portion of the p-type body region 5. The region 5 is assumed to form the other part of the racetrack-shaped straight part and the arc part. That is, the portion of the first portion p-type body region 5 facing the n ⁺ -type drain region 10 has only a linear outer periphery on the upper surface of the SOI substrate 1, and the second portion of the p-type body region 5 The portion facing the n ⁺ -type drain region 10 has an arcuate outer periphery and a linear outer periphery. However, as shown in the top view of the high breakdown voltage MOSFET in FIG. 4, the p-type body region 5 in the first portion ((A) in FIG. 4) is one of the racetrack-shaped linear portions on the top surface of the SOI substrate 1. The p-type body region 5 of the second portion ((B) in FIG. 4) may form the other portion of the racetrack-shaped linear portion. That is, the portion of the first portion p-type body region 5 facing the n ⁺ -type drain region 10 has an arcuate outer periphery and a linear outer periphery on the upper surface of the SOI substrate 1, and the second portion p-type. The part of the body region 5 facing the n ⁺ -type drain region 10 may have only a linear outer periphery. At this time, the length of the other part of the straight line portion where the n ⁺ type source region 7 does not exist ((C) in FIG. 4) is the distance between the n ⁺ type source region 7 and the n ⁺ type drain region 10 (see FIG. 4 (D)) is 4 times or more.

  Similarly, in the high breakdown voltage MOSFET shown in FIG. 3, the p-type body region 5 of the first portion is along a part of the comb-shaped linear portion, the tip portion of the finger-like portion, and the trough portion on the upper surface of the SOI substrate 1. The p-type body region 5 of the second part may be formed along the other part of the comb-shaped linear part.

(Second Embodiment)
FIG. 5A is a top view of the high voltage MOSFET in the second embodiment, and FIG. 5B is a cross-sectional view of the high voltage MOSFET (a cross-sectional view taken along YO in FIG. 5A). FIG. 5C is a cross-sectional view of the high voltage MOSFET (cross-sectional view taken along Y1-X1 in FIG. 5A). The following description will focus on differences from the first embodiment.

  The high voltage MOSFET includes an SOI substrate 21, a gate oxide film 24 and a LOCOS oxide film 22, and a gate electrode 23. At this time, the outer periphery of the high voltage MOSFET is surrounded by the trench element isolation region 14.

The SOI substrate 21 includes a silicon substrate 2, a buried oxide film 3, and a p-type active layer 4, and a p-type body region 25 and an n-type drain offset region 6 are formed in the p-type active layer 4. An n-type drain buffer region 9 and an n ⁺ -type drain region 10 are formed in the n-type drain offset region 6, and an n ⁺ -type source region 7 and a p ⁺ -type body contact region 8 are formed in the p-type body region 25. Is formed. In this structure, a parasitic diode is formed between the p-type body region 25 and the n-type drain offset region 6.

  Here, as shown in FIG. 5B, the SOI substrate 21 is a portion where the gate electrode 23 is formed on the upper surface via the gate oxide film 24 and the LOCOS oxide film 22, that is, a first that functions as a transistor. A part ((A) in FIG. 5A) and a part in which the gate electrode 23 is formed on the upper surface through the LOCOS oxide film 22, as shown in FIG. 5C, that is, a second functioning as a diode. (B in FIG. 5A).

  The gate oxide film 24 is formed on the surface of the first portion of the SOI substrate 21 above the region serving as a channel including the p-type body region 25 and is not formed on the second portion of the SOI substrate 21.

The LOCOS oxide film 22 on the SOI substrate 21 in the first portion is a region in which the n ⁺ type source region 7, the p ⁺ type body contact region 8 and the n ⁺ type drain region 10 are not formed on the surface of the SOI substrate 21. And a portion where the gate oxide film 24 is not formed. On the other hand, in the LOCOS oxide film 22 on the SOI substrate 21 of the second portion, the n ⁺ type source region 7, the p ⁺ type body contact region 8 and the n ⁺ type drain region 10 in the surface of the SOI substrate 21 are formed. It is formed above the non-region.

  The gate electrode 23 on the first portion of the SOI substrate 21 is formed on a part of the LOCOS oxide film 22 and the gate oxide film 24 across the LOCOS oxide film 22 and the gate oxide film 24. On the other hand, the gate electrode 23 on the SOI substrate 21 of the second portion is formed only on the LOCOS oxide film 22.

On the upper surface of the SOI substrate 21, as shown in FIG. 5A, a racetrack-shaped upper surface pattern in which a p-type body region 25 and a gate electrode 23 are formed outside the n ⁺ -type drain region 10 is formed. Is done. At this time, the gate electrode 23 on the first portion of the SOI substrate 21 forms part of the racetrack-shaped linear portion on the upper surface of the SOI substrate 21. On the other hand, the gate electrode 23 on the SOI substrate 21 in the second part forms the other part of the racetrack-shaped linear part and the arc part. Therefore, the gate electrode 23 is formed on the SOI substrate 21 via the LOCOS oxide film 22 in the other part and the arc part of the racetrack-shaped straight part , and the gate electrode 23 is formed in the gate oxide film 24 in a part of the straight part. And formed on the SOI substrate 21 via the LOCOS oxide film 22.

Here, the length of the other part of the racetrack-shaped linear part and the arc part ((C) in FIG. 5A) is the distance between the n ⁺ -type source region 7 and the n ⁺ -type drain region 10 ( The length is at least four times as long as (D) in FIG.

As described above, according to the high breakdown voltage MOSFET of the present embodiment, the gate electrode 23 is connected to the SOI substrate through the LOCOS oxide film 22 in a sufficient region from the arc portion of the racetrack shape to the other portion of the linear portion. 21 is formed. Therefore, the high breakdown voltage MOSFET of the present embodiment can make the diode characteristics of the parasitic diode equivalent to that of a normal diode based on the same principle as that of the first embodiment. That is, the power loss of the parasitic diode can be suppressed. This is because when the gate oxide film 24 having a thickness of several nanometers to several tens of nanometers is replaced with a LOCOS oxide film 22 having a thickness of several hundred nanometers, the gate threshold voltage increases, and a potential is applied to the gate electrode 23. This is because the channel current does not flow even if it is applied.

  In addition, the high voltage MOSFET according to the present embodiment can suppress the power loss of the parasitic diode while reducing the sacrifice of the current capability as the output element based on the same principle as the first embodiment.

(Third embodiment)
FIG. 6A is a top view of the high voltage MOSFET in the third embodiment, and FIG. 6B is a cross-sectional view of the high voltage MOSFET (a cross-sectional view taken along YO in FIG. 6A). FIG. 6C is a cross-sectional view of the high voltage MOSFET (cross-sectional view at Y1-X1 in FIG. 6A). The following description will focus on differences from the first embodiment.

  The high breakdown voltage N-channel MOSFET includes an SOI substrate 31, a gate oxide film 34 and a LOCOS oxide film 12, and a gate electrode 33. At this time, the outer periphery of the high voltage MOSFET is surrounded by the trench element isolation region 14.

The SOI substrate 31 includes a silicon substrate 2, a buried oxide film 3 and a p-type active layer 4, and a p-type body region 35 and an n-type drain offset region 6 are formed in the p-type active layer 4. An n-type drain buffer region 9 and an n ⁺ -type drain region 10 are formed in the n-type drain offset region 6, and an n ⁺ -type source region 7 and a p ⁺ -type body contact region 8 are formed in the p-type body region 35. Is formed. In this structure, a parasitic diode is formed between the p-type body region 35 and the n-type drain offset region 6.

  Here, as shown in FIG. 6B, the SOI substrate 31 is a portion in which the gate electrode 33 is formed on the upper surface, that is, a first portion that functions as a transistor ((A) in FIG. 6A). 6C, the gate electrode 33 is not formed on the upper surface, that is, a second portion that functions as a diode (B in FIG. 6A).

  The gate oxide film 34 is formed on the surface of the first portion of the SOI substrate 31 above the region serving as a channel including the p-type body region 35, and is not formed on the second portion of the SOI substrate 31.

  The gate electrode 33 is formed on a part of the first portion of the LOCOS oxide film 12 and the gate oxide film 34 across the LOCOS oxide film 12 and the gate oxide film 34, and on the second portion of the SOI substrate 31. Not formed.

On the upper surface of the SOI substrate 31, as shown in FIG. 6A, a racetrack-shaped upper surface pattern in which a p-type body region 35 and a gate electrode 33 are formed on the outer side with the n ⁺ -type drain region 10 as a center is formed. Is done. At this time, the gate electrode 33 forms only a part of the racetrack-shaped linear part on the upper surface of the SOI substrate 31 and does not form the other part of the linear part and the arc part.

Here, the length of the other part of the racetrack-shaped linear part and the arc part ((C) in FIG. 6A) not formed by the gate electrode 33 is the n ⁺ -type source region 7 and the n ⁺ -type drain region 10. Is at least four times the distance ((D) in FIG. 6A).

As described above, according to the high breakdown voltage MOSFET of the present embodiment, the gate electrode 33 is not formed on the SOI substrate 31 in a sufficient region from the racetrack-shaped arc portion to the other portion of the linear portion . Therefore, the high breakdown voltage MOSFET of the present embodiment can make the diode characteristics of the parasitic diode equivalent to that of a normal diode based on the same principle as that of the first embodiment. That is, the power loss of the parasitic diode can be suppressed.

  In addition, the high voltage MOSFET according to the present embodiment can suppress the power loss of the parasitic diode while reducing the sacrifice of the current capability as the output element based on the same principle as the first embodiment.

(Fourth embodiment)
FIG. 7A is a top view of the high voltage MOSFET in the fourth embodiment, and FIG. 7B is a cross-sectional view of the high voltage MOSFET (a cross-sectional view taken along YO in FIG. 7A). FIG. 7C is a cross-sectional view of the high voltage MOSFET (cross-sectional view at Y1-X1 in FIG. 7A). In the following, a description will be given focusing on differences from the third embodiment.

The high breakdown voltage N-channel MOSFET includes an SOI substrate 41, a gate oxide film 34 and a LOCOS oxide film 42, a gate electrode 33, an n ⁺ type source region 7, a p ⁺ type body contact region 8 and an n ⁺ type drain region 10. It is comprised from the metal wiring 45 connected. At this time, the outer periphery of the high voltage MOSFET is surrounded by the trench element isolation region 14.

The SOI substrate 41 includes a silicon substrate 2, a buried oxide film 3, and a p-type active layer 4, and a p-type body region 35 and an n-type drain offset region 6 are formed in the p-type active layer 4. An n-type drain buffer region 9 and an n ⁺ -type drain region 10 are formed in the n-type drain offset region 6, and an n ⁺ -type source region 7 and a p ⁺ -type body contact region 8 are formed in the p-type body region 35. Is formed. In this structure, a parasitic diode is formed between the p-type body region 35 and the n-type drain offset region 6.

Here, the SOI substrate 41 is different between a first portion functioning as a transistor ((A) in FIG. 7A) and a second portion functioning as a diode ((B) in FIG. 7A). It has a structure. That is, the distance between the first n ⁺ -type source region 7 of the second portion and the n ⁺ -type drain region 10 shown in FIG. 7 (c), the first portion shown in FIG. 7 (b) n ⁺ It is shorter than the distance between the type source region 7 and the n ⁺ type drain region 10. This is because the electric field strength under the gate electrode 33, particularly the electric field strength at the end of the LOCOS bird's peak, is one of the factors that determine the off-breakdown voltage as a high withstand voltage device. Therefore, when the gate electrode 33 is present, the breakdown voltage can be maintained even if the distance between the n ⁺ -type source region 7 and the n ⁺ -type drain region 10 required for maintaining the breakdown voltage is shortened. It is.

The LOCOS oxide film 42 on the SOI substrate 41 of the first portion is a region in which the n ⁺ type source region 7, the p ⁺ type body contact region 8 and the n ⁺ type drain region 10 are not formed on the surface of the SOI substrate 41. And a portion where the gate oxide film 34 is not formed. On the other hand, the LOCOS oxide film 42 on the SOI substrate 41 in the second portion is a region between the n ⁺ type source region 7, the p ⁺ type body contact region 8 and the n ⁺ type drain region 10 on the surface of the SOI substrate 41. It is formed so as to cover. Further, the LOCOS oxide film 42 on the SOI substrate 41 of the second portion may be formed up to the n ⁺ type source region 7 on the surface of the SOI substrate 41. That is, a structure in which the p ⁺ type body contact region 8 and the n ⁺ type drain region 10 are not formed may be employed.

  The metal wiring 45 is formed on the LOCOS oxide film 42 in the second portion. As a result, the metal wiring 45 can be used in combination as a field plate, so that an effective breakdown voltage can be maintained.

On the upper surface of the SOI substrate 41, as shown in FIG. 7A, a racetrack-shaped upper surface pattern in which a p-type body region 35 and a gate electrode 33 are formed outside the n ⁺ -type drain region 10 is formed. Is done. At this time, the gate electrode 33 forms only a part of the racetrack-shaped linear part on the upper surface of the SOI substrate 41 and does not form the other part of the linear part and the arc part.

Here, the length of the other part of the racetrack-shaped linear part and the arc part ((C) in FIG. 7A) not formed by the gate electrode 33 is the n ⁺ -type source region 7 and the n ⁺ -type drain region 10. Is at least four times the distance ((D) in FIG. 7A).

  As described above, the high-breakdown-voltage MOSFET according to the present embodiment can make the diode characteristics of the parasitic diode equivalent to that of a normal diode based on the same principle as that of the third embodiment. That is, the power loss of the parasitic diode can be suppressed.

  Further, the high voltage MOSFET of the present embodiment can suppress the power loss of the parasitic diode while reducing the sacrifice of the current capability as the output element based on the same principle as that of the third embodiment.

Further, according to the high breakdown voltage MOSFET of the present embodiment, the distance between the n ⁺ -type source region 7 and the n ⁺ -type drain region 10 of the second portion that functions as a diode is the first distance that functions as a transistor. It is shorter than the distance between the n ⁺ -type source region 7 and the n ⁺ -type drain region 10. Therefore, the high voltage MOSFET of the present embodiment can improve the current capability of the diode. Further, since the distance between the n ⁺ -type source region 7 and the n ⁺ -type drain region 10 in the arc portion where a long source-drain distance is set for the purpose of securing a breakdown voltage can be shortened, the element area can be reduced. Can be reduced.

  As described above, the high voltage MOSFET according to the present invention has been described based on the embodiment. However, the present invention is not limited to this embodiment, and various modifications or corrections can be made without departing from the scope of the present invention. Needless to say, this is possible.

For example, in the above embodiment, the upper surface of the SOI substrate is formed with the racetrack-shaped upper surface pattern in which the p-type body region is formed outside the n ⁺ -type drain region. A racetrack-shaped upper surface pattern in which an n ⁺ -type drain region is formed on the outer side with respect to may be formed, and the same effect can be obtained. That is, the same effect can be obtained even when the p-type body region and the n ⁺ -type drain region are interchanged.

  The present invention can be used for a semiconductor device, and in particular, can be used for a high voltage MOSFET used for a high voltage power element of a scan driver IC for driving a plasma display.

(A) It is a top view of the high voltage | pressure-resistant MOSFET of the 1st Embodiment of this invention. (B) It is sectional drawing (sectional drawing in YO of FIG. 1 (a)) of the high voltage | pressure-resistant MOSFET of the embodiment. (C) It is sectional drawing (sectional drawing in Y1-X1 of Fig.1 (a)) of the high voltage | pressure-resistant MOSFET of the embodiment. It is a figure which shows the relationship between the forward direction diode voltage (VF) of a parasitic diode, and the length of the other part and circular arc part of a linear part . It is a top view of the modification of the high voltage | pressure-resistant MOSFET of the embodiment. It is a top view of the modification of the high voltage | pressure-resistant MOSFET of the embodiment. (A) It is a top view of the high voltage | pressure-resistant MOSFET of the 2nd Embodiment of this invention. (B) It is sectional drawing (sectional drawing in YO of Fig.5 (a)) of the high voltage | pressure-resistant MOSFET of the embodiment. (C) It is sectional drawing (sectional drawing in Y1-X1 of Fig.5 (a)) of the high voltage | pressure-resistant MOSFET of the embodiment. (A) It is a top view of the high voltage | pressure-resistant MOSFET of the 3rd Embodiment of this invention. (B) It is sectional drawing (sectional drawing in YO of FIG. 6 (a)) of the high voltage | pressure-resistant MOSFET of the embodiment. (C) It is sectional drawing (sectional drawing in Y1-X1 of Fig.6 (a)) of the high voltage | pressure-resistant MOSFET of the embodiment. (A) It is a top view of the high voltage | pressure-resistant MOSFET of the 4th Embodiment of this invention. (B) It is sectional drawing (sectional drawing in YO of FIG. 7 (a)) of the high voltage | pressure-resistant MOSFET of the embodiment. (C) It is sectional drawing (sectional drawing in Y1-X1 of Fig.7 (a)) of the high voltage | pressure-resistant MOSFET of the embodiment. It is a circuit diagram which shows an example of the output circuit of plasma display scan driver IC. (A) It is a top view of the conventional high voltage | pressure-resistant MOSFET. (B) It is sectional drawing (sectional drawing in YO of Fig.9 (a)) of the conventional high voltage | pressure-resistant MOSFET. 10 is a top view of a conventional high voltage MOSFET described in Patent Document 1. FIG. It is a figure which shows an example of the bias state at the time of a discharge maintenance period at the time of using the conventional high voltage MOSFET as a high voltage power element of a scan driver IC. It is a figure which shows the diode characteristic of the parasitic diode of the high voltage | pressure-resistant power element at the time of a discharge maintenance period. (A) It is a top view of the conventional high voltage | pressure-resistant MOSFET. (B) It is sectional drawing (sectional drawing in YO of Fig.13 (a)) of the conventional high voltage | pressure-resistant MOSFET. (C) It is sectional drawing (sectional drawing in YO of Fig.13 (a)) of the conventional high voltage | pressure-resistant MOSFET.

Explanation of symbols

1, 21, 31, 41, 101 SOI substrate 2, 102 Silicon substrate 3, 103 buried oxide film 4, 104 p-type active layer 5, 25, 35, 105 p-type body region 6, 106 n-type drain offset region 7, 107 n ⁺ type source region 8, 108 p ⁺ type body contact region 9, 109 n type drain buffer region 10, 110 n ⁺ type drain region 11, 24, 34, 111 Gate oxide film 12, 22, 42, 112 LOCOS oxidation Films 13, 23, 33, 113 Gate electrode 14 Trench element isolation region 45 Metal wiring

Claims (14)

A semiconductor device in which a transistor including a gate electrode, a source region, and a drain region is formed on a semiconductor substrate,
The semiconductor substrate is an SOI substrate having an element isolation region;
The element isolation region completely surrounds the transistor on the upper surface of the semiconductor substrate,
The gate electrode has an arc part and a straight part formed so as to surround the first region which is one of the source region and the drain region on the upper surface of the semiconductor substrate,
The second region, which is the other of the source region and the drain region, is formed along a part of the straight part and is not formed along any part other than a part of the straight part,
The length of the other part than the part of the straight part and the arc part is four times or more the distance between the first region and the second region. The semiconductor device according to claim 1, wherein the first region is a drain region. 3. The semiconductor device according to claim 1, wherein a racetrack-shaped upper surface pattern in which the gate electrode is formed outside the first region as a center is formed on the upper surface of the semiconductor substrate. On the upper surface of the semiconductor substrate, an upper surface pattern having a shape formed so as to face each other so that the comb-shaped first region and the finger-like portions of the gate electrode are combined with each other is formed.
The semiconductor device according to claim 1, wherein a tip portion of the finger-like portion and a valley portion between the finger-like portions have a curvature. A semiconductor device in which a transistor comprising a gate electrode, a LOCOS oxide film, a gate oxide film, a source region and a drain region is formed on a semiconductor substrate,
The semiconductor substrate is an SOI substrate having an element isolation region;
The element isolation region completely surrounds the transistor on the upper surface of the semiconductor substrate,
The gate electrode and the first region which is one of the source region and the drain region are arcs formed so as to surround the second region which is the other of the source region and the drain region on the upper surface of the semiconductor substrate. Part and straight part,
A part of the gate electrode of the linear portion is formed on the LOCOS oxide film and the gate oxide film;
The gate electrode of the arc part other than the part of the linear part is formed on the LOCOS oxide film,
The length of the other part than the part of the straight part and the arc part is four times or more the distance between the first region and the second region. The semiconductor device according to claim 5 , wherein the second region is a drain region. The semiconductor substrate on the upper surface, the semiconductor device according to claim 5 or 6, characterized in that the upper surface pattern racetrack shape in which the gate electrode to the outside is formed around the second region. On the upper surface of the semiconductor substrate, an upper surface pattern having a shape formed so as to be opposed to each other so that the comb-shaped second region and the finger-shaped portions of the gate electrode are combined with each other is formed.
Valleys between the tip of the fingers and the fingers A semiconductor device according to claim 5 or 6, characterized in that it has a curvature. A semiconductor device in which a transistor including a gate electrode, a source region, and a drain region is formed on a semiconductor substrate,
The semiconductor substrate is an SOI substrate having an element isolation region;
The element isolation region completely surrounds the transistor on the upper surface of the semiconductor substrate,
The first region that is one of the source region and the drain region has an arc portion and a straight line portion that are formed so as to surround the second region that is the other of the source region and the drain region on the upper surface of the semiconductor substrate. ,
The gate electrode is formed along a part of the linear part and is not formed along the arc part other than the part of the linear part,
The length of the other part than the part of the straight part and the arc part is four times or more the distance between the first region and the second region. The gate electrode is not formed along the arc portion, and the LOCOS oxide film is formed between the first region and the second region of the arc portion,
The distance between the first region and the second region of the arcuate portion, according to claim 9, characterized in that less than the distance between the portion of the first region and the second region of the straight portion Semiconductor device. The semiconductor device according to claim 9 , wherein the second region is a drain region. Wherein the semiconductor substrate upper surface, to any one of claims 9 to 11, characterized in that the upper surface pattern of the racetrack-shaped first area is formed outside around the second region is formed The semiconductor device described. On the upper surface of the semiconductor substrate, an upper surface pattern having a shape formed so as to oppose each other so that the finger-shaped portions of the first region and the second region of the comb shape are combined with each other,
The semiconductor device according to claim 9, wherein a tip portion of the finger-like portion and a valley portion between the finger-like portions have a curvature. The transistor further semiconductor device according to any one of claims 1 to 13, characterized in that a drain offset region surrounding said drain region.

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