JP4357564B2 - Charging / discharging device, display device, plasma display panel, and charging / discharging method - Google Patents

Description

  The present invention relates to driving of a plasma display panel (PDP), and more particularly to a circuit that applies a voltage to display electrodes of a PDP and recovers electrical energy stored in a capacitance between the display electrodes.

  By applying a sustain pulse voltage between the display electrodes forming a pair of PDPs, electric charge, that is, electric energy is accumulated in the capacitance (capacitance) between the display electrodes. A technique for recovering the electrical energy using a recovery capacitor is known. The electric energy recovered by the capacitor is used for applying a sustain pulse voltage between the next display electrodes.

Japanese Laid-Open Patent Publication No. 2004-287466 (A) published on October 14, 2004, which is a divisional application of Japanese Patent Laid-Open No. 10-149135 (A) published on June 2, 1998, shows The drive circuit of the device is described. In this drive circuit, each of the X electrode group and the Y electrode group is provided with 24 power recovery circuits including a reactor, a pair of diodes, a pair of sixth switches, and a capacitor.・ Before the negative voltage rises, one of the pair of sixth switches is turned on to store the current energy from the capacitor in the reactor, and the current energy stored in the reactor is added when the voltage rises to charge from the capacitor. To do.
JP 2004-287466 A

Japanese Unexamined Patent Publication No. 11-15426 (A) published on January 22, 1999 describes a capacitive load driving circuit. In this drive circuit, one end of the capacitive load is grounded, and the other end is connected to an inductor. A series circuit of a switch element and a diode and a parallel circuit of a series circuit of a switch element and a diode are connected to the inductor, and a capacitor for power recovery is connected to the parallel circuit. Two switch elements are connected to the capacitive load, and one switch element is connected to a switch element for switching between a positive power source and a negative power source. A switch element for switching between a positive power source and a negative power source is connected to the capacitor.
Japanese Patent Laid-Open No. 11-15426

  When the sustain pulse is applied to the display electrode of the PDP through the inductor by the recovery capacitor that stores the recovered electrical energy, the rise time of the sustain pulse tends to be long. The inductor requires an inductance having a required magnitude in order to resonately supply electric energy to the display electrode. If the inductance of the inductor is reduced, the electrical energy recovery efficiency is lowered.

  The inventors have recognized that it is desirable to increase the recovery efficiency of electrical energy without increasing the rise time of the pulse applied to the display electrode in driving the PDP.

  An object of the present invention is to increase the recovery efficiency of electrical energy accumulated in a capacitive load known in a PDP or the like.

  Another object of the present invention is to implement a circuit that applies a short rise time pulse to the capacitance.

  Yet another object of the present invention is to shorten the delay from the start of pulse application to the capacitive load known in PDP or the like to discharge.

  Yet another object of the present invention is to reduce the width of a pulse applied to a capacitive load known in a PDP or the like.

  According to the features of the present invention, the charging / discharging device charges / discharges a charge / discharge target capacitance (capacitive load) by applying a voltage, and is for electrical energy recovery in which one terminal is coupled to a common conductor. Recovery capacitor, compensation capacitor having one terminal coupled to the other terminal of the recovery capacitor, one terminal coupled to the other terminal of the compensation capacitor, and other terminal coupled to the charge / discharge target capacitance The first path forming means for charging the charge / discharge target capacitance via the resonant inductor and the other terminal of the recovery capacitor are coupled to one terminal, and the other terminal is coupled to the charge / discharge target capacitance. A second path forming device that discharges the charge / discharge target capacitance through the inductor and recovers the electrical energy to the recovery capacitor. And, and it includes a.

  The present invention also relates to a display device and a plasma display panel including the above-described device configuration.

  The present invention also relates to a charge / discharge method for realizing the functions of the above-described apparatus.

  According to the present invention, electrical energy recovery efficiency can be increased.

  Embodiments of the present invention will be described with reference to the drawings. In the drawings, similar components are given the same reference numerals.

  FIG. 1 shows a configuration of a typical display device 60 according to an embodiment of the present invention. The display device 60 includes a three-electrode surface discharge type PDP 10 having a display surface composed of n × m cells, and a drive unit 50 for selectively emitting light from the cells, for example, a television receiver. Used for computer system monitors.

  In the PDP 10, display electrodes X and Y (X1, Y1,... Xj, Yj,... Xm, Ym) constituting an electrode pair for generating display discharge are arranged in parallel. Address electrodes A (A1,... Ai,... Am) are arranged so as to be orthogonal to Y. The display electrode X is a sustain electrode, and the display electrode Y is a scan electrode. The display electrodes X and Y typically extend in the row direction or the horizontal direction of the screen, and the address electrodes A extend in the column direction or the vertical direction.

  The drive unit 50 includes a driver control circuit 51, a data conversion circuit 52, a power supply circuit 53, an X electrode driver circuit or X driver circuit 61, a Y electrode driver circuit or Y driver circuit 64, and an address electrode driver circuit or A driver circuit 68. And is optionally implemented in the form of an integrated circuit that may include a ROM. The drive unit 50 is supplied with field data Df indicating the light emission intensities of the three primary colors of R, G, and B, together with various synchronization signals, from an external device such as a TV tuner or a computer. Field data Df is temporarily stored in a field memory in data conversion circuit 52. The data conversion circuit 52 converts the field data Df into subfield data Dsf for gradation display and supplies it to the A driver circuit 68. The subfield data Dsf is a set of 1-bit display data per cell, and the value of each bit represents whether or not each cell needs to emit light in the corresponding subfield SF.

  The X driver circuit 61 includes a reset circuit 62 that applies a voltage for initialization to the display electrode X in order to equalize the wall voltages of a plurality of cells constituting the PDP display surface, and a display discharge in the cells. And a sustain circuit 63 for applying a sustain pulse to the display electrode X. The Y driver circuit 64 includes a reset circuit 65 that applies a voltage for initialization to the display electrode Y, a scan circuit 66 that applies a scan pulse to the display electrode Y in addressing, and a display for generating a display discharge in the cell. And a sustain circuit 67 for applying a sustain pulse to the electrode Y. The A driver circuit 68 applies an address pulse to the address electrode A designated by the subfield data Dsf according to the display data.

  The driver control circuit 51 controls the application of the pulse voltage and the transfer of the subfield data Dsf. The power supply circuit 53 supplies driving power to a required part in the unit.

One picture (screen) is typically composed of one frame period. In interlaced scanning, one frame is composed of two fields, and in progressive scanning, one frame is composed of one field. In the display by the PDP 10, in order to perform color reproduction by binary light emission control, typically one field F in the time series of the input image in such one field period is divided into a predetermined number q of subfields SF. . Typically, each field F is replaced with a set of q subfields SF. Often, these subfields SF are in turn 2 ⁰ , 2 ¹ , 2 ² ,. . . 2 Set the number of display discharges in each subfield SF with different weights such as ^q-1 . Brightness setting in N (= 1 + 2 ¹ +2 ² + ... + 2 ^q-1 ) steps can be performed for each color of R, G, and B by a combination of light emission / non-light emission in units of subfields. A field period Tf, which is a field transfer period, is divided into q subfield periods Tsf in accordance with such a field configuration, and one subfield period Tsf is assigned to each subfield SF. Further, the subfield period Tsf is divided into a reset period TR for initialization, an address period TA for addressing, and a display period TS for light emission. Typically, the length of the reset period TR and the address period TA is constant in any subfield, whereas the number of pulses in the display period TS increases as the luminance weight increases, and the length of the display period TS increases in luminance. The greater the weight, the longer. In this case, the length of the subfield period Tsf is longer as the luminance weight of the corresponding subfield SF is larger.

  FIG. 2 illustrates a schematic drive sequence of output drive voltage waveforms of the X driver circuit 61, the Y driver circuit 64, and the A driver circuit 68 according to an embodiment of the present invention. The illustrated waveform is an example, and the amplitude, polarity, and timing can be changed variously.

  The order of the reset period TR, the address period TA, and the sustain period TS is the same in the q subfields SF, and the driving sequence is repeated for each subfield SF. In the reset period TR of each subfield SF, a negative pulse Prx1 and a positive pulse Prx2 are sequentially applied to all the display electrodes X, and a positive pulse Pry1 is applied to all the display electrodes Y. A negative pulse Pry2 is applied in order. The pulses Prx1, Pry1, and Pry2 are obtuse pulses or ramp waveforms that gradually increase in amplitude at the rate of change at which minute discharge occurs. The first applied pulses Prx1 and Pry1 are applied to generate appropriate wall voltages of the same polarity in all cells regardless of light emission / non-light emission in the previous subfield SF. By applying the pulses Prx2 and Pry2 to a cell having an appropriate wall charge, the wall voltage can be adjusted to a value corresponding to the difference between the discharge start voltage and the pulse amplitude. The drive voltage applied to the cell is a combined voltage representing the difference in the amplitude of the pulses applied to the display electrodes X and Y.

  In the address period TA, wall charges necessary for maintaining light emission are formed only in the cells that emit light. With all the display electrodes X and all the display electrodes Y biased to a predetermined potential, a negative scan pulse -Vy is applied to the display electrodes Y corresponding to the selected row for each row selection period (scanning time for one row). Apply. Simultaneously with this row selection, the address pulse Vad is applied only to the address electrode A corresponding to the selected cell in which the address discharge is to be generated. That is, the potentials of the address electrodes A1 to Am are subjected to binary control based on the subfield data Dsf for m columns of the selected row j. In the selected cell, a discharge occurs between the display electrode Y and the address electrode A. The address discharge is a trigger, and subsequent surface discharge between the display electrodes XY occurs.

  In the sustain period TS, first, a sustain pulse Ps having a predetermined polarity (positive polarity in the illustrated example) is applied to all the display electrodes Y. Thereafter, the sustain pulse Ps is alternately applied to the display electrode X and the display electrode Y. The amplitude of the sustain pulse Ps is the sustain voltage Vs. By applying the sustain pulse Ps, a surface discharge occurs in a cell in which a predetermined wall charge remains. The number of times the sustain pulse Ps is applied corresponds to the weight of the subfield SF as described above. Note that the address electrode A is biased to the voltage Vas having the same polarity as the sustain pulse Ps in order to prevent unnecessary counter discharge throughout the sustain period TS.

  In FIG. 1, the capacitor formed by each pair of display electrodes Xj and Yj has a capacitance C. The sustain circuits 67 and 68 in FIG. 1 apply the voltages Vs of the two series of sustain pulses Ps in FIG. 2 between the pair of display electrodes Xj and Yj, respectively.

FIG. 3A shows a typical pulsed power supply and recovery circuit 11 having electrical energy recovery or power recovery function and a clamp circuit 14 used for the sustain circuits 67 and 68. 3B shows the states of the switches SW1 to SW4 of the pulse power supply and recovery circuit 11 and the clamp circuit 14 of FIG. 3A, and the voltages V _Cp and V _Cr across the panel capacitance Cp and the recovery capacitor Cr at the time of pulse application. Shows changes. The panel capacitance Cp is formed between one or more pairs of display electrodes X and Y, and has a capacitance Cp on the order of 100 nF, for example.

  In FIG. 3A, the pulse power supply and recovery circuit 11 has a capacity Cr (for example, 100 times or more of Cp) sufficiently larger than the capacity Cp between the plurality of pairs of display electrodes X and Y, and one terminal is grounded. Connection point between recovery capacitor Cr, diodes D1 and D2 connected in parallel with each other in reverse polarity via switches SW1 and SW3 in series with capacitor Cr, and other terminals of diodes D1 and D2 A resonant inductor L having one terminal connected to each other and an other terminal connected via an electrode resistance R inherent in one (X or Y) of one or more pairs of display electrodes of a capacitance Cp. Yes. The clamp circuit 14 includes a constant voltage source Vs of a predetermined voltage Vs connected via a switch SW2 to a connection point between the other terminal of the resonance inductor L and the electrode resistance R, and the connection point is connected via a switch SW4. Connect to ground GND.

Referring to FIGS. 3A and 3B, it is assumed that charges of voltage Vs / 2 are first accumulated in capacitor Cr, and no charges are accumulated in panel capacitance Cp, which is a capacitance between a plurality of display electrodes. Therefore, the value of the voltage V _{Cp at} the panel capacitance Cp is zero (0). When the switch SW1 is turned on at the start of the rise of the pulse Ps, a supply current flows from the capacitor Cr to the panel capacitor Cp via the switch SW1, the diode D1, and the resonant inductor L, and charges q to CVs are accumulated in the panel capacitor Cp. voltage V _Cp of the panel capacitance Cp is increased, the rise of the pulse Ps is formed. When the voltage V _Cp of the panel capacitance Cp reaches a peak voltage Vpmax, the switch SW2 of the clamp circuit 14 is turned on. The peak voltage Vpmax is slightly lower than the voltage Vs. The voltage source Vs of the clamp circuit 14 clamps the voltage of the panel capacitance Cp to the voltage Vs, and maintains the panel capacitance Cp at the voltage Vs. The clamp circuit 14 compensates the voltage V _Cp of the panel capacitance Cp so as to become a predetermined voltage Vs. Thereafter, a sustain discharge occurs, and the switches SW1 and SW2 are turned off.

When the switch SW3 is turned on at the start of the fall of the pulse Ps, a return current flows from the panel capacitance Cp to the recovery capacitor Cr via the resonant inductor L, the diode D2, and the switch SW2, and the charges q to CVs are recovered. In addition, the voltage is accumulated in the capacitor Cr, the voltage of the panel capacitance Cp is lowered, and the falling of the pulse Ps is formed. When the voltage V _Cp of the panel capacitance Cp reaches a peak voltage Vpmin, switch SW4 is turned on, the ground point GND of the clamp circuit 14 is clamped to the ground potential GND or 0V voltage V _Cp of the panel capacitance Cp. The peak voltage Vrmin is slightly higher than the ground potential GND or 0V. In this way, most of the electric charge supplied from the recovery capacitor Cr to the panel capacitance Cp, that is, the electric power is recovered.

FIG. 4 shows a more detailed normal waveform of the voltage V _Cp of the pulse Ps across the panel capacitance Cp. In this waveform, during the effective pulse rise time Ter, the voltage V _Cp of the panel capacitance Cp between the display electrodes X and Y is changed from the ground potential GND = 0V by the power recovery capacitor Cr at the rise time Trm of the first pulse Ps. The peak voltage Vpmax rises somewhat lower than the clamp potential Vs, and is clamped to the clamp potential Vs by the clamp circuit 14 at the clamp rise time Trc and maintained at the potential Vs.

Next, the power consumption or the work amount per unit time for one pulse Ps by the pulse power supply and recovery circuit 11 and the clamp circuit 14 is obtained. The power consumption W ₀ for the pulse Ps by the clamp voltage Vs when the power is not recovered is W ₀ = CpVs ² , and the power consumption Ws for the pulse Ps by the clamp voltage Vs when the power is recovered is Ws = Cp (Vs−Vpmax ) Vs, and the power consumption Wr for the pulse Ps by the power recovery capacitor Cr when recovering the power is Wr = CpVpmaxVs. In this case, the power recovery efficiency η is expressed by the following equation.

The voltage V _Cp of the panel capacitance Cp is expressed by the following formula.

  The stable voltage Vo of the recovery capacitor Cr is Vo = Vs / 2.

The effective rise time Ter of the pulse Ps is expressed by Ter = Trm + Trc = Trm + 2.2CpR when the clamp rise time Trc = 2.2 CpR by the constant voltage source Vs is added. For example, when Vs = 200 V, R = 0.5Ω, L = 200 nH, Cp = 100 nF, recovery efficiency η = 78.4%, rise time Trm = about 450 ns due to voltage V _Cr of the recovery capacitor Cr, clamp rise time Trc = about 110 ns and effective rise time Ter = about 560 ns.

FIG. 5A shows a pulse voltage application circuit 602 that applies a voltage Vs of a pulse Ps to one or more pairs of display electrodes X and Y having a capacitance Cp according to the first embodiment of the present invention. The pulse voltage application circuit 602 supplies a voltage V _Cp between the display electrodes X and Y to a predetermined voltage Vs and a pulse power supply and recovery circuit 12 that supplies power at the rising edge of the pulse Ps and collects power at the falling edge. A clamp circuit 14 that clamps to 0 V, and a control signal generation circuit 16 that generates a signal for controlling the on / off operation of the switches SW1 to SW4 in the pulse power supply and recovery circuit 12 and the clamp circuit 14 are included. The switches SW1 to SW4 may be transistors.

  In FIG. 5A, the pulse power supply and recovery circuit 12 includes a power recovery capacitor Cr having one terminal coupled to the ground point GND, that is, a common conductor potential, and a negative electrode connected to one terminal of the capacitor Cr in series with the capacitor Cr. A voltage source Vcm for compensation of a constant voltage Va / 2 having a terminal coupled thereto, a compensation capacitor Ca coupled in series with the capacitor Cr and in parallel with the voltage source Vcm, and the other terminal of the voltage source Vcm are coupled in series. A diode D1 having an anode (anode) terminal coupled to the other terminal of the voltage source Vcm via a switch SW1 so as to form a path 1, and a capacitor Ca and a diode D1 coupled in series to the capacitor Cr A switch SW is connected to a connection point between the other terminal of the capacitor Cr and one terminal of the compensation capacitor Ca so as to form the path 2 in parallel. One terminal is coupled to a connection point between the diode D2 having a cathode (cathode) terminal coupled thereto and the other terminals of the diodes D1 and D2, and the other terminal is a pair or a plurality of pairs of display electrodes X and Y of the panel capacitance Cp. And a resonant inductor L coupled via an electrode resistance R inherent in one of each pair (X or Y). The power recovery capacitor Cr has a capacitance Cr sufficiently larger than the panel capacitance Cp between one or more pairs of display electrodes X and Y. The recovery capacitor Cr is typically a combination of an electrolytic capacitor and a film capacitor. The arrangement of the switch SW1 and the diode D1 may be switched. Similarly, the arrangement of the switch SW3 and the diode D2 may be switched.

  The clamp circuit 14 includes a constant voltage source Vs of a predetermined voltage Vs coupled via a switch SW2 to a connection point between the other terminal of the resonance inductor L and the electrode resistance R, and the connection point is connected via the switch SW4. Connect to ground GND.

FIG. 5B shows the on / off states of the control signals C _{SW1 to} C _SW4 of the control signal generation circuit 16 of FIG. 5A for controlling the switches _SW1 to _SW4 and the display electrodes at the time of pulse application according to the embodiment of the present invention. The schematic waveforms of the voltages V _Cp and V _Cr across the capacitor Cp and the recovery capacitor Cr are shown.

FIG. 6 shows a waveform of the voltage V _Cp of the pulse Ps across the panel capacitance capacitor Cp of the pulse voltage application circuit 604 of FIG. 5A. In this case, the waveform of the voltage V _Cp of the pulse Ps is such that the constant voltage Va of the compensation voltage source Vcm is set so that the rising peak voltage V′pmax becomes equal to the clamp voltage Vs at the effective rise time Ter = Trm. Thus, a smooth pulse waveform without a step at the rising portion is formed.

Referring to FIGS. 5A and 5B, in the pulse voltage application circuit 602, in the steady operation state after the power of the display device 60 of FIG. 1 is turned on and the capacitor Cr is repeatedly charged and discharged, the recovery capacitor Cr is approximately at the voltage Vs. The compensation capacitor Ca is charged by the compensation voltage source Vcm to have the voltage Va, and no charge is accumulated in the panel capacitance or the panel capacitance Cp. Therefore, the value of the voltage V _{Cp at} the panel capacitance Cp is zero (0).

Figure 5A, with reference to 5B and 6, at the timing t1 of the start of the rise of the pulse Ps, the switch SW1 in accordance with the control signal C _SW1 is turned on, compensation capacitor Ca from the capacitor Cr, switches SW1, the diode D1 and the resonant inductor L The supply current flows through the panel capacitor Cp, the charge q≈CpVs is accumulated in the panel capacitor Cp, the voltage V _Cp of the panel capacitor Cp rises, and the rise of the pulse Ps is formed. When the voltage V _Cp of the panel capacitance Cp reaches a peak voltage V'pmax, the switch SW2 of the clamp circuit 14 is turned on at timing t2 in accordance with the control signal C _SW2. The peak voltage Vpmax is substantially equal to the voltage Vs (V′pmax = Vs). By applying the voltage Va of the constant voltage source Vcm and the compensation capacitor Ca, the voltage difference Vs−Vpmax in FIG. 4 corresponding to the voltage drop due to the electrode resistance R is compensated, and the peak voltage V′pmax = Vs in FIG. There is no delay time from when the voltage V _Cp in FIG. 4 reaches the peak voltage Vpmax to when it further reaches the voltage Vs. The voltage source Vs of the clamp circuit 14 clamps the voltage V _Cp of the panel capacitance _Cp to the voltage Vs and maintains the voltage V _Cp of the panel capacitance Cp at the voltage Vs between the timings t2 and t3 when the sustain discharge occurs. After the sustain discharge, the switches SW1 and SW2 are turned off according to the control signal C _SW1 and C _SW2.

In the timing t3 of the start of the fall of the pulse Ps, the control when the switch SW3 in accordance with the signal C _SW3 is turned on, the resonant inductor L from the panel capacitor Cp, the return current to the recovery capacitor Cr through diode D2 and the switch SW3 flows , Charges q to CpVs are accumulated in the recovery capacitor Cr, the voltage of the panel capacitance Cp drops, and the falling of the pulse Ps is formed. When the voltage V _Cp of the panel capacitance Cp reaches a peak voltage V'pmin, switch SW4 is turned on according to the control signal C _SW4 at the timing t4. The peak voltage V′pmin is slightly higher than the ground potential GND or 0V. The ground point GND of the clamp circuit 14 clamps the voltage V _Cp of the panel capacitance _Cp to the ground potential GND or 0V. In this way, most of the electric charge accumulated in the panel capacitance Cp, that is, the electric power is recovered by the capacitor Cr. Thereafter, the same operation is repeated.

Next, the power consumption for one pulse Ps is obtained. The power consumption W ₀ due to the clamp voltage Vs when power is not recovered is W ₀ = CpVs ² , and the power consumption Ws due to the clamp voltage Vs when power is recovered is Ws = Cp (Vs−V′pmax) Vs. The power consumption Wa by the voltage source Vcm when recovering the power is expressed by Wa = CpV′pmaxVa. The recovery efficiency η ′ in this case is expressed by the following formula.

Since the supply amount and the reception amount of electrical energy at the connection point between the recovery capacitor Cr and the compensation capacitor Ca are equal to each other, the stable potential V _{1 at} the connection point between the recovery capacitor Cr and the compensation capacitor Ca, and the compensation capacitor Ca. And the stable potential V _{2 at} the connection point of the switch SW1 is expressed by the following equation.

  Here, the falling magnitude Vpmax of the falling peak voltage V′pmin during power recovery is expressed by the following equation.

  Therefore, the ratio between the recovery efficiency η 'of the circuit 12 of FIG. 5A and the recovery efficiency η of the prior art circuit 11 of FIG. 3A is expressed by the following equation.

  Therefore, the recovery efficiency η ′ due to the pulse power supply and recovery circuit 12 and conditions is slightly lower than the recovery efficiency η of the conventional pulse power supply and recovery circuit 11, but the effective rise time Ter is the same.

  Next, consider the recovery efficiency η ′ with respect to the constant voltage Va / 2 of the compensation power supply Vcm determined so that the rising peak voltage V′pmax and the clamp voltage Vs are equal. For example, for Vs = 200 V, L = 200 nH, R = 0.5Ω, and Cp = 100 nF, the constant voltage Va that satisfies the rising peak voltage V′pmax = Vs is Va = about 27.5 V from Equation 6 above. At this time, the recovery efficiency η ′ = about 72.5% and the effective rise time Ter = Trm + 0 = about 450 ns. On the other hand, when L = 450 ns in the conventional pulse power supply and recovery circuit 11 of FIG. 3A, L = about 110 nH and recovery efficiency η = 73.1%.

  FIG. 7 shows the pulse power supply and recovery circuit 11 of the prior art and the pulse power supply and power supply circuit of FIG. 5A when the constant voltage Va of the power source Vcm is set so that the rising peak voltage Vp′max and the clamp voltage Vs are equal. A comparison of the recovery efficiencies η and η ′ with respect to the effective rise time Ter by the recovery circuit 12 is shown.

  Therefore, in FIG. 5A, by setting the compensation power supply Vcm to the constant voltage Va so that the rising peak voltage V′pmax = Vs, the recovery efficiency η ′ and the effective rising time Trm are equal to those of the conventional one. Nevertheless, it is possible to generate a pulse Ps having a smooth drive waveform without a step.

  In the pulse power supply / recovery circuit 12, when the pulse Ps has a smooth waveform with no step at the rising portion, there is no switching loss (turn-on resistance) in the switch SW2, so the pulse power supply and recovery of the prior art of FIG. The effective recovery efficiency η ′ is higher than the recovery efficiency η of the circuit 11.

  8 applies the voltage Vs of the pulse Ps to one or more pairs of display electrodes X and Y having the panel capacitance Cp according to the second embodiment of the present invention, which is a modification of the pulse voltage application circuit 602 of FIG. 5A. A pulse voltage application circuit 604 is shown. In FIG. 8, the inductor L in FIG. 5A is replaced with inductors L1 and L2 for paths 1 and 2, respectively, having different inductances. The inductor L1 has the same inductance as the inductor L of FIG. 5A, and the inductor L2 has an inductance larger than the inductor L1 (L1 <L2). Inductor L1 has one terminal coupled to the cathode of diode D1 to form part of path 1 and inductor L2 has one terminal coupled to the anode of diode D2 to form part of path 2 and inductor L1. And the other terminal of L2 are coupled to one of the display electrodes X and Y, that is, the panel capacitance Cp. Other configurations of the pulse voltage application circuit 604 are the same as those of the pulse voltage application circuit 602 in FIG. 5A.

  In FIG. 8, a pulse power supply and recovery circuit 13 includes a power recovery capacitor Cr, a compensation voltage source Vcm for a constant voltage Va, and a compensation capacitor Ca, similar to the pulse power supply and recovery circuit 12 of FIG. 5A. A diode D1 having an anode terminal coupled to the other terminal of the voltage source Vcm via a switch SW1 so as to form a path 1, and a path coupled in series with the capacitor Cr and in parallel with the compensation capacitor Ca and the diode D1. A diode D2 having a cathode terminal coupled via a switch SW2 to a connection point between the other terminal of the capacitor Cr and one terminal of the compensation capacitor Ca so as to form a diode 2, and a diode D1 so as to form a path 1 One terminal is coupled to the cathode terminal of the other and the other terminal is connected to one or more pairs of display electrodes X and Y of the panel capacitance Cp. One terminal is coupled to the anode terminal of the diode D2 and the other terminal is connected to the panel capacitance Cp so as to form the path 2 and the resonant inductor L1 coupled via the electrode resistance R inherent in one of the pair (X or Y). A resonant inductor L2 coupled via an electrode resistance R inherent in one of the pair of display electrodes X and Y. The inductance of the resonant inductor L2 is larger than the inductance of the resonant inductor L1 (L2> L1). The inductance of the resonant inductor L2 is selected such that the falling peak voltage V'pmax = Vs. Other configurations of the pulse power supply and recovery circuit 13 are the same as those of the pulse power supply and recovery circuit 12 of FIG. 5A.

  FIG. 9 shows the electric energy in the pulse voltage application circuit 604 of FIG. 8 so that the falling peak voltage magnitude V′pmax is equal to the clamp voltage Vs and the falling peak potential V ″ min is equal to the common conductor potential GND. A pulse Ps having a smooth waveform with no step at the rising and falling portions when the inductance of the resonant inductor L2 of the recovery path 2 is set is shown.

  In the pulse voltage application circuit 604, since the inductor L2 of the path 2 has an inductance larger than the inductor L1, the fall time from the timing t3 to the peak voltage V′pmin is somewhat longer, but the magnitude of the peak voltage is large. Thus, the peak voltage V′pmin reaches 0 V of the ground potential GND, and there is no delay time from reaching the peak voltage V′pmin to reaching the ground potential GND. In this case, the effective fall time Tef is longer than the effective rise time Ter.

Next, the power consumption for one pulse Ps is obtained. The power consumption W ₀ by the clamp voltage Vs when the power is not recovered is W ₀ = CpVs ² , and the power consumption Ws by the clamp voltage Vs when the power is recovered is Ws = 0, and compensation is made when the power is recovered The power consumption Wa by the capacitor Ca is Wa = CpV "pmaxVa = CpVsVa. In this case, the recovery efficiency η" is expressed by the following equation.

The stable potential V _{1 at} the connection point between the compensation capacitor Ca and the switch SW1 is expressed by the following equation.

The stable potential V _{2 at} the connection point between the recovery capacitor Cr and the compensation capacitor Ca is expressed by the following equation because the energy input and output at the point V2 are equal.

  The stable voltage Va between both ends of the compensation capacitor Ca is expressed by the following equation.

  FIG. 10 shows the pulse voltage application circuit 11 of the prior art, the constant voltage Va of the compensation power source Vcm is set so that the rising peak voltage V′pmax and the clamp voltage Vs are equal, and the falling peak potential V′min is 8 shows a comparison of the recovery efficiencies η and η ″ with respect to the effective rise time Ter by the pulse voltage application circuit 13 of FIG. 8 when set to be equal to the ground potential GND. In the pulse voltage application circuit 13 of FIG. The recovery efficiency η ″ is higher than the efficiency η of the conventional pulse voltage application circuit 11.

  Therefore, according to the second embodiment of FIG. 8, the recovery efficiency of electrical energy can be increased, and the rise time of the pulse Ps applied to the display electrodes X and Y can be shortened. As a result, the delay from the start of pulse application to the display electrodes X and Y to the discharge can be shortened, and thus the generation of the discharge can be stabilized. Further, the width of the pulse Ps applied to the display electrodes X and Y can be reduced, and therefore the display quality of the display device 60 can be improved by securing the positions of a larger number of pulses Ps within a predetermined period.

  FIG. 11A is a modification of the pulse Ps of FIG. 6 and shows another pulse Ps having a stepped waveform. FIG. 11B is a modification of the pulse Ps in FIG. 9 and shows another pulse Ps having a stepped waveform.

  FIG. 12 shows an alternate application of the voltage Vs of the pulse Ps to each of the two blocks of display electrode pairs X and Y having the panel capacitance Cp according to another embodiment of the present invention, which is a modification of the pulse voltage application circuit 602 of FIG. 5A. A pulse voltage application circuit 606 is shown.

In FIG. 12, a pulse voltage application circuit 606 supplies a voltage V _Cp between the display electrodes X and Y, and a pulse power supply and recovery circuit 120 that supplies power at the rising edge of the pulse Ps and recovers power at the falling edge. And a switch SW1, SW2,... In the pulse power supply and recovery circuit 120 and the clamp circuit 140. . . And a control signal generation circuit 160 for generating a signal for controlling the on / off operation of SW4 ′. The pulse power supply and recovery circuit 120 and the clamp circuit 140 are symmetric with respect to the compensation power sources Vm and Vm ′ and the compensation capacitors Ca and Ca ′.

  In the pulse power supply and recovery circuit 120, the panel capacitance Cp ′ functions as the recovery capacitor Cr in FIG. 5A with respect to the panel capacitance Cp, and the panel capacitance Cp as the recovery capacitor Cr in FIG. 5A with respect to the panel capacitance Cp ′. Function. An inductor L ′ coupled to the panel capacitor Cp ′, a diode D2 ′, a compensation voltage source Vcm coupled in parallel and a compensation so as to form a path 1 for supplying electrical energy to the panel capacitor Cp. Capacitor Ca, switch SW1, and diode D1 coupled to panel capacitance Cp are coupled in series. Also, an inductor L coupled to the panel capacitor Cp, a diode D2, and a compensation voltage source Vcm ′ coupled in parallel to form a path 2 for supplying electrical energy to the panel capacitor Cp ′. Compensation capacitor Ca ′, switch SW1 ′, and diode D1 ′ coupled to panel capacitance Cp ′ are coupled in series.

  The clamp circuit 140 includes two sets of clamp circuits, that is, a constant voltage source Vs coupled to the panel capacitor Cp via the switch SW2, a ground potential GND coupled to the panel capacitor Cp via the switch SW4, and a switch SW2 ′. A constant voltage source Vs coupled to the panel capacitor Cp ′ through the switch SW4 ′ and a ground potential GND coupled to the panel capacitor Cp ′ through the switch SW4 ′.

  Although the PDP has been described above, the present invention is not limited to this, and can be applied to, for example, organic and inorganic EL, and electronic paper that displays characters by storing charges by applying voltage. is there.

  The embodiments described above are merely given as typical examples, and it is obvious to those skilled in the art to combine the components of each embodiment, and variations and variations thereof will be apparent to those skilled in the art. Obviously, various modifications may be made to the above-described embodiments without departing from the scope of the invention as set forth in the scope.

FIG. 1 shows the configuration of a typical display device according to an embodiment of the present invention. FIG. 2 illustrates a schematic drive sequence of output drive voltage waveforms of an X driver circuit, a Y driver circuit, and an A driver circuit according to an embodiment of the present invention. FIG. 3A shows a normal pulse power supply and recovery circuit having an electrical energy recovery or power recovery function and a clamp circuit used in the sustain circuit. FIG. 3B shows the state of the switches of the pulse power supply / recovery circuit and the clamp circuit of FIG. 3A and the change in voltage between both ends of the display electrode capacitor and the recovery capacitor at the time of pulse application. FIG. 4 shows a more detailed normal waveform of the voltage of the pulse across the panel capacitance Cp. FIG. 5A shows a pulse voltage application circuit that applies a pulse voltage to one or more pairs of display electrodes X and Y having a panel capacitance Cp according to an embodiment of the present invention. FIG. 5B illustrates an ON / OFF state of the control signal of the control signal generation circuit of FIG. 5A for controlling the switch and between both ends of the display electrode capacitor and the recovery capacitor when a pulse is applied according to an embodiment of the present invention. Voltage and schematic waveforms are shown. FIG. 6 shows the waveform of the voltage of the pulse across the display electrode capacitor of the pulse voltage application circuit of FIG. 5A. FIG. 7 shows the pulse power supply and recovery circuit of the prior art and the pulse power supply and recovery circuit of FIG. 5A when the constant voltage of the compensation power supply is set so that the rising peak voltage and the clamp voltage are equal. A comparison of recovery efficiency versus effective rise time is shown. FIG. 8 shows a pulse voltage application circuit for applying a pulse voltage to one or more pairs of display electrodes having a panel capacitance Cp according to another embodiment of the present invention, which is a modification of the pulse voltage application circuit of FIG. 5A. Yes. FIG. 9 shows a pulse having a smooth waveform with no step at the rising portion when the inductance of the resonant inductor of the electrical energy recovery path is set so that the falling peak potential becomes equal to the common conductor potential. FIG. 10 shows a conventional pulse voltage application circuit, the constant voltage of the compensation power supply is set so that the rising peak voltage and the clamp voltage are equal, and the falling peak potential is set equal to the common conductor potential. FIG. 9 shows a comparison of recovery efficiency with respect to effective rise time by the pulse voltage application circuit of FIG. FIG. 11A is a modification of the pulse of FIG. 6 and shows another pulse having a stepped waveform. FIG. 11B is a modification of the pulse of FIG. 9 and shows yet another pulse having a stepped waveform. FIG. 12 shows a pulse voltage application circuit for alternately applying a pulse voltage to two blocks of display electrode pairs according to another embodiment of the present invention, which is a modification of the pulse voltage application circuit of FIG. 5A.

Claims (5)

A charge / discharge device for charging / discharging a capacitance to be charged / discharged by applying a voltage,
A recovery capacitor for electrical energy recovery in which one terminal is coupled to a common conductor;
A compensation capacitor having one terminal coupled to the other terminal of the recovery capacitor;
A first switch connected between the other terminal of the compensation capacitor and the charge / discharge capacitance;
A second switch connected between the one terminal of the compensation capacitor and the charge / discharge capacitance;
A first constant voltage source connected in parallel with the compensation capacitor between the other terminal of the recovery capacitor and the first switch;
A second constant voltage source connected to the charge / discharge capacitance via a third switch;
One terminal is coupled to the other terminal of the compensation capacitor, the other terminal is coupled to the charge / discharge capacitance, and the charge / discharge is performed via the first switch and the resonant inductor by turning on the first switch. First path forming means for charging a target capacitance;
One terminal is coupled to the other terminal of the recovery capacitor, the other terminal is coupled to the charge / discharge capacitance, and the charging / discharging capacitor is turned on by turning on the second switch. A second path forming means for discharging the capacitance to be discharged and recovering electrical energy in the recovery capacitor;
The third switch is turned on at a timing when the voltage value supplied to the charge / discharge target capacitance by the first path forming means rises to the voltage value supplied by the second constant voltage source. Charging / discharging device.   2. The inductor according to claim 1, wherein the inductor provided in association with the second path forming means has a larger inductance than the inductor provided in relation to the first path forming means. Charging / discharging device.   The display device including the charge / discharge device according to claim 1, wherein the charge / discharge target capacitance is formed of one or more cells constituting a display screen. A plasma display panel that performs charge transfer to transfer a charge from a recovery capacitor for recovering electrical energy to a cell constituting a screen and power recovery to transfer a charge from the cell to the recovery capacitor,
A recovery capacitor for electrical energy recovery in which one terminal is coupled to a common conductor;
A compensation capacitor having one terminal coupled to the other terminal of the recovery capacitor;
A first switch connected between the other terminal of the compensation capacitor and the charge / discharge capacitance;
A second switch connected between the one terminal of the compensation capacitor and the charge / discharge capacitance;
A first constant voltage source connected in parallel with the compensation capacitor between the other terminal of the recovery capacitor and the first switch;
A second constant voltage source connected to the charge / discharge capacitance via a third switch;
One terminal is coupled to the other terminal of the compensation capacitor, the other terminal is coupled to the charge / discharge capacitance, and the first switch and the resonant inductor are used to turn on the cell by turning on the first switch. First path forming means for charging;
One terminal is coupled to the other terminal of the recovery capacitor, the other terminal is coupled to the cell, and the second switch is turned on to discharge the cell through the second switch and a resonant inductor. And a second path forming means for recovering electrical energy in the recovery capacitor.
The third switch is turned on at a timing when the voltage value supplied to the charge / discharge target capacitance by the first path forming means rises to the voltage value supplied by the second constant voltage source. A plasma display panel.   5. The inductor according to claim 4, wherein the inductor provided in association with the second path forming means has a larger inductance than the inductor provided in relation to the first path forming means. Plasma display panel.

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