JP4359584B2 - Driving circuit - Google Patents
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- JP4359584B2 JP4359584B2 JP2005257585A JP2005257585A JP4359584B2 JP 4359584 B2 JP4359584 B2 JP 4359584B2 JP 2005257585 A JP2005257585 A JP 2005257585A JP 2005257585 A JP2005257585 A JP 2005257585A JP 4359584 B2 JP4359584 B2 JP 4359584B2
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Description
本発明は、発光ダイオード等の駆動に適した駆動回路の改良に関する。 The present invention relates to an improvement of a driving circuit suitable for driving a light emitting diode or the like.
発光ダイオードはそれ自体を文字表示等に用いるほか、特許文献１にも見られるように照明用の光源としても用いられつつある。看板等の大型照明光源では数十個もの素子からなる発光ダイオード列が用いられる。このような大規模な発光ダイオード列に対しては、輝度を安定させかつ電力消費量を最小限とするためにも安定した電流供給を図る必要がある。特に、電源として商用電源を用いる場合には、その電圧変動が大きいため定電流化の必要度が高い。
The light-emitting diode itself is used for character display and the like, and as seen in
このような目的に適う発光ダイオードの駆動回路としては、例えば特許文献２に開示されているように、トランジスタおよび抵抗を負荷となるダイオードに対して直列接続した定電流回路が知られている。図１は、このような定電流回路の基本的な構成を示している。図中のＶ１は交流電源、Ｄ１〜Ｄ４は前記交流電源の出力を直流化する整流用のダイオード、Ｄ５〜Ｄ３４は直列接続された発光ダイオード、Ｑ１はトランジスタ、Ｒ１とＲ２は抵抗、Ｄ０はＲ１に流れる電流を一定値に保つツェナーダイオード、Ｃ１は平滑用コンデンサである。
この駆動回路では、受電後の電源電圧の変動に伴う直流電圧Ｖｉｎの変化を、トランジスタＱ１のコレクタ−エミッタ間の電圧降下のみによって吸収している。このため、電源電圧の変動が大きい工場、交通機関、建物内などに適用した場合、トランジスタＱ１として許容コレクタ損失の大きなものを用いなければならず、回路が高価なものとなってしまう。また、その発熱量も大きいことから大型のヒートシンクを使用しなければならず、それだけ大きな設置スペースが必要になるという問題もある。 In this drive circuit, changes in the DC voltage Vin accompanying fluctuations in the power supply voltage after receiving power are absorbed only by the voltage drop between the collector and emitter of the transistor Q1. For this reason, when applied to factories, transportation facilities, buildings, etc. where the fluctuation of the power supply voltage is large, a transistor having a large allowable collector loss must be used as the transistor Q1, and the circuit becomes expensive. Moreover, since the calorific value is also large, a large heat sink must be used, and there is a problem that a large installation space is required.
本発明はこのような従来の問題点を解消することを目的としている。 The object of the present invention is to eliminate such conventional problems.
本発明は、発光ダイオードからなる負荷に直流電源からの出力を供給する駆動回路であって、ベース端子に接続されたツェナーダイオードの電圧によって、前記負荷側に接続されたコレクタ端子と接地側に接続されたエミッタ端子との間の電圧降下によって前記負荷の回路電流を制御する第１のトランジスタを備えた駆動回路において、前記第１のトランジスタのコレクタ端子の電圧をベース電圧として作動し、エミッタ端子と前記第１のトランジスタのエミッタ端子との間に第１の抵抗が介装される第２のトランジスタと、前記直流電源の電圧をコレクタ端子の電圧とし、エミッタ端子から出力される電流を前記負荷に供給し、前記直流電源と前記ベース端子との間に第２の抵抗が介装され、前記第２のトランジスタのコレクタ端子の電流によって前記ベース端子から接地側に流れる電流が制御される第３のトランジスタと、を備え、前記第１の抵抗の抵抗値と前記第２の抵抗の抵抗値とは、それぞれ、前記第１の抵抗の端子間電圧と前記第２の抵抗の端子間電圧とが等しくなるように設定される。 The present invention is a drive circuit for supplying an output from a DC power supply to a load composed of a light emitting diode, and is connected to a collector terminal connected to the load side and a ground side by a voltage of a Zener diode connected to a base terminal. In a drive circuit including a first transistor that controls a circuit current of the load by a voltage drop between the emitter terminal and the emitter terminal, the voltage at the collector terminal of the first transistor operates as a base voltage, A second transistor having a first resistor interposed between the emitter terminal of the first transistor and the voltage of the DC power source as the voltage of the collector terminal, and the current output from the emitter terminal to the load A second resistor is interposed between the DC power source and the base terminal, and a current of the collector terminal of the second transistor is supplied. Therefore, a third transistor in which a current flowing from the base terminal to the ground side is controlled, and a resistance value of the first resistor and a resistance value of the second resistor are respectively the first resistor The terminal voltage of the second resistor and the terminal voltage of the second resistor are set to be equal .
本発明によれば、電源電圧の変動に伴う電圧降下を、第１のトランジスタに加えて、第３のトランジスタにも分担させられるので、トランジスタ１個当たりのコレクタ損失を小さくできる。すなわち、コレクタ損失の小さい低発熱のトランジスタを用いて発光ダイオード等の負荷を安定駆動することができる。また、低発熱のトランジスタが分散配置され、放熱上も有利になることから、装置の小型化が可能である。 According to the present invention, since the voltage drop caused by the fluctuation of the power supply voltage is shared by the third transistor in addition to the first transistor, the collector loss per transistor can be reduced. That is, a load such as a light emitting diode can be stably driven using a low heat generation transistor with a small collector loss. In addition, since low heat generation transistors are distributed and advantageous in terms of heat dissipation, the size of the device can be reduced.
以下、本発明のいくつかの実施形態を図２以下の各図に基づいて説明する。なお、図１を含めて各図につき共通する部分には互いに同一の符号を付して示してある。 Hereinafter, several embodiments of the present invention will be described with reference to FIG. In addition, the same code | symbol is attached | subjected and shown to the part which is common in each figure including FIG.
図２において、Ｄ５〜Ｄ３４は直列接続された発光ダイオード、Ｑ１は第１のトランジスタ、Ｒ１とＲ２は抵抗、Ｄ０はツェナーダイオード、Ｃ１はコンデンサであり、これらによる回路構成は図１と同一である。本実施形態では、前記構成に加えて、利得１のオペアンプＸ１および第２のトランジスタＱ２と第３のトランジスタＱ３とを設ける。第２のトランジスタＱ２は、第１のトランジスタＱ１のコレクタ電圧Ｖｃ（Ｑ１）をベース電圧Ｖｂ（Ｑ２）として作動し、第３のトランジスタＱ３は、直流電源出力（電圧Ｖｉｎ）をコレクタ電圧Ｖｃ（Ｑ３）として用いて、前記直流出力から負荷であるダイオード列（Ｄ５〜Ｄ３４）への供給電流を制御する。前記第２のトランジスタＱ２は、第３のトランジスタＱ３のベース端子から接地側（この場合、第１のトランジスタＱ１のエミッタ端子）に流れる電流Ｉｃ（Ｑ２）を制御する構成となっている。 In FIG. 2, D5 to D34 are light-emitting diodes connected in series, Q1 is a first transistor, R1 and R2 are resistors, D0 is a Zener diode, and C1 is a capacitor, and their circuit configuration is the same as FIG. . In the present embodiment, in addition to the above configuration, an operational amplifier X1 having a gain of 1, a second transistor Q2, and a third transistor Q3 are provided. The second transistor Q2 operates using the collector voltage Vc (Q1) of the first transistor Q1 as the base voltage Vb (Q2), and the third transistor Q3 uses the DC power supply output (voltage Vin) as the collector voltage Vc (Q3). ) To control the supply current from the DC output to the diode array (D5 to D34) as a load. The second transistor Q2 is configured to control a current Ic (Q2) flowing from the base terminal of the third transistor Q3 to the ground side (in this case, the emitter terminal of the first transistor Q1).
また、前記第２のトランジスタＱ２のエミッタ端子とオペアンプＸ１の出力端子との間に抵抗Ｒ３を、第３のトランジスタＱ３のベース端子と直流電源との間に抵抗Ｒ４を、それぞれ介装してある。この場合、第１のトランジスタＱ１のエミッタ端子電圧とオペアンプＸ１の出力電圧は等しい。トランジスタＱ２のエミッタ電流Ｉｅ（Ｑ２）に対してトランジスタＱ１のエミッタ電流Ｉｅ（Ｑ１）が十分に大きいときには、前記オペアンプＸ１は必ずしも設けなくともよい。 A resistor R3 is interposed between the emitter terminal of the second transistor Q2 and the output terminal of the operational amplifier X1, and a resistor R4 is interposed between the base terminal of the third transistor Q3 and the DC power source. . In this case, the emitter terminal voltage of the first transistor Q1 is equal to the output voltage of the operational amplifier X1. When the emitter current Ie (Q1) of the transistor Q1 is sufficiently larger than the emitter current Ie (Q2) of the transistor Q2, the operational amplifier X1 is not necessarily provided.
次に、前記回路の動作について説明する。なお、以下の説明において抵抗を示す符号Ｒ１〜Ｒ４については抵抗値を示す符号としても用いる。また、電圧Ｖまたは電流Ｉに対する添え字として、ｅ，ｂ，ｃはそれぞれトランジスタのエミッタ、ベース、コレクタの電圧または電流を、ｂｅ，ｃｅはそれぞれベース−エミッタ間、コレクタ−エミッタ間の電圧または電流を示すものとし、その後ろの括弧内に素子符号を付して何れの素子の電圧または電流値であるかを示すこととする。 Next, the operation of the circuit will be described. In the following description, symbols R1 to R4 indicating resistance are also used as symbols indicating resistance values. As subscripts for the voltage V or current I, e, b, and c are the voltage or current of the emitter, base, and collector of the transistor, respectively, and be and ce are the voltage or current between the base and emitter, and between the collector and emitter, respectively. An element code is attached in parentheses after that to indicate which element voltage or current value is.
図２に示した回路において、オペアンプＸ１の出力電圧をＶｏｕｔ（Ｘ１）とすると、次の式（１）〜（４）の関係が成り立つ。 In the circuit shown in FIG. 2, when the output voltage of the operational amplifier X1 is Vout (X1), the following relationships (1) to (4) are established.
Ｖｏｕｔ（Ｘ１）＝Ｖｅ（Ｑ１） …（１）
Ｖｂ（Ｑ２）＝Ｖｃ（Ｑ１） …（２）
Ｖｂ（Ｑ２）−Ｖｏｕｔ（Ｘ１）
＝Ｖｃ（Ｑ１）−Ｖｅ（Ｑ１）
＝Ｖｂｅ（Ｑ２）＋Ｉｅ（Ｑ２）Ｒ３ …（３）
Ｖｃ（Ｑ３）−Ｖｂ（Ｑ３）＝Ｒ４（Ｉｂ（Ｑ３）＋Ｉｃ（Ｑ２）） …（４）
ここで、Ｖｂｅ（Ｑ３）≒Ｖｂｅ（Ｑ２）とすれば、次式（５）の関係が成り立つ。
Vout (X1) = Ve (Q1) (1)
Vb (Q2) = Vc (Q1) (2)
Vb (Q2) -Vout (X1)
= Vc (Q1) -Ve (Q1)
= Vbe (Q2) + Ie (Q2) R3 (3)
Vc (Q3) -Vb (Q3) = R4 (Ib (Q3) + Ic (Q2)) (4)
Here, if Vbe (Q3) ≈Vbe (Q2), the relationship of the following equation (5) is established.
Ｖｃ（Ｑ３）−Ｖｅ（Ｑ３）≒Ｖｂｅ（Ｑ２）＋Ｒ４（Ｉｂ（Ｑ３）＋Ｉｃ（Ｑ２）） …（５）
さらに、Ｒ４（Ｉｂ（Ｑ３）＋Ｉｃ（Ｑ２））＝Ｉｅ（Ｑ２）Ｒ３となるようにＲ３，Ｒ４を設定すれば、次式（６）の関係が成り立つ。
Vc (Q3) -Ve (Q3) ≈Vbe (Q2) + R4 (Ib (Q3) + Ic (Q2)) (5)
Furthermore, if R3 and R4 are set so that R4 (Ib (Q3) + Ic (Q2)) = Ie (Q2) R3, the relationship of the following equation (6) is established.
Ｖｃ（Ｑ３）−Ｖｅ（Ｑ３）≒Ｖｃ（Ｑ１）−Ｖｅ（Ｑ１） …（６）
また、Ｉｅ（Ｑ３）≒Ｉｃ（Ｑ１）であるから、第１のトランジスタＱ１のコレクタ損失Ｐｃ（Ｑ１）と第３のトランジスタＱ３のコレクタ損失Ｐｃ（Ｑ３）とは等しくなる。
Vc (Q3) −Ve (Q3) ≈Vc (Q1) −Ve (Q1) (6)
Since Ie (Q3) ≈Ic (Q1), the collector loss Pc (Q1) of the first transistor Q1 is equal to the collector loss Pc (Q3) of the third transistor Q3.
すなわち、図３に示したように、電源電圧Ｖｉｎの変動に伴うトランジスタのコレクタ−エミッタ間の電圧降下Ｖｃｅは、第１のトランジスタＱ１と第３のトランジスタＱ３とで略等分に分担されることになり、したがって各々はコレクタ損失の小さいトランジスタを適用することが可能となる。 That is, as shown in FIG. 3, the voltage drop Vce between the collector and the emitter of the transistor due to the fluctuation of the power supply voltage Vin is equally divided between the first transistor Q1 and the third transistor Q3. Therefore, it is possible to apply a transistor with a small collector loss.
図４に本発明の第２の実施形態を示す。これは、既述したようにＩｅ（Ｑ２）に対してＩｅ（Ｑ１）を十分に大きく取ってオペアンプＸ１を省略すると共に、図２のトランジスタＱ１〜Ｑ３に代えて電界効果型トランジスタ（ＦＥＴ）Ｍ１〜Ｍ３を適用したものである。ＦＥＴでは第１の実施形態におけるようなベース−エミッタ間の電流は生じないが、同様にして定電流制御を行い得ることは言うまでもない。 FIG. 4 shows a second embodiment of the present invention. As described above, Ie (Q1) is made sufficiently large with respect to Ie (Q2) to omit the operational amplifier X1, and a field effect transistor (FET) M1 is used instead of the transistors Q1 to Q3 in FIG. -M3 is applied. The FET does not generate a base-emitter current as in the first embodiment, but it goes without saying that constant current control can be performed in the same manner.
なお、前記実施形態において、図５にも示したように、第２のトランジスタＱ２によってベース電流を制御する第３のトランジスタをＱ３およびＱ４からなる多段のトランジスタ群で構成してもよく、これにより個々のトランジスタの負担をさらに減じることができる。 In the above embodiment, as shown in FIG. 5, the third transistor that controls the base current by the second transistor Q2 may be formed of a multi-stage transistor group including Q3 and Q4. The burden on individual transistors can be further reduced.
Ｄ５〜Ｄ２８ 発光ダイオード
Ｑ１〜Ｑ３ トランジスタ
Ｍ１〜Ｍ３ ＦＥＴ
Ｃ１〜Ｃ３ コンデンサ
Ｒ１〜Ｒ４ 抵抗（抵抗値）
D5-D28 Light-emitting diode Q1-Q3 Transistor M1-M3 FET
C1 to C3 capacitors R1 to R4 Resistance (resistance value)
Claims (4)
前記第１のトランジスタのコレクタ端子の電圧をベース電圧として作動し、エミッタ端子と前記第１のトランジスタのエミッタ端子との間に第１の抵抗が介装される第２のトランジスタと、
前記直流電源の電圧をコレクタ端子の電圧とし、エミッタ端子から出力される電流を前記負荷に供給し、前記直流電源と前記ベース端子との間に第２の抵抗が介装され、前記第２のトランジスタのコレクタ端子の電流によって前記ベース端子から接地側に流れる電流が制御される第３のトランジスタと、
を備え、
前記第１の抵抗の抵抗値と前記第２の抵抗の抵抗値とは、それぞれ、前記第１の抵抗の端子間電圧と前記第２の抵抗の端子間電圧とが等しくなるように設定されることを特徴とする駆動回路。 A drive circuit for supplying an output from a DC power supply to a load composed of a light emitting diode, and a collector terminal connected to the load side and an emitter terminal connected to the ground side by a voltage of a Zener diode connected to a base terminal A drive circuit comprising a first transistor for controlling the circuit current of the load by a voltage drop between
A second transistor that operates using the voltage at the collector terminal of the first transistor as a base voltage, and a first resistor is interposed between the emitter terminal and the emitter terminal of the first transistor;
The voltage of the DC power supply is set to the voltage of the collector terminal, the current output from the emitter terminal is supplied to the load, and a second resistor is interposed between the DC power supply and the base terminal, A third transistor in which a current flowing from the base terminal to the ground side is controlled by a current of a collector terminal of the transistor;
With
The resistance value of the first resistor and the resistance value of the second resistor are set so that the voltage across the first resistor and the voltage across the second resistor are equal. A drive circuit characterized by that.
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| JP5138424B2 (en) * | 2008-03-04 | 2013-02-06 | シャープ株式会社 | Control method and control apparatus for organic EL device |
| JPWO2015128986A1 (en) * | 2014-02-27 | 2017-03-30 | 有限会社トップス | LED light emitting device |
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Free format text: JAPANESE INTERMEDIATE CODE: R250 |
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| R250 | Receipt of annual fees |
Free format text: JAPANESE INTERMEDIATE CODE: R250 |
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| EXPY | Cancellation because of completion of term |