JP4360439B2 - Memory management device and memory management method - Google Patents

Description

  The present invention uses the link list memory to write the data requested to be written to the data memory, and to read the data requested to be read from the data memory and output the data memory. It is related with the apparatus and method which manage.

For example, in an application such as communication, when a data input request or output request by a plurality of packets is issued to one data memory and the data memory is divided into a plurality of areas corresponding to each packet, the link is used. There is a management method in which area management is performed using a list memory and an empty area of a data memory is used as efficiently as possible (see, for example, Patent Document 1).
JP 2000-200210 A

However, in the management method using the link list as described above, when data input from a plurality of input sources is written in the data memory in time series, the result that the specific input source uses most of the memory area. There is a problem that there is no room for other input sources to use the data memory.
The present invention has been made in view of the above circumstances, and an object of the present invention is to provide a memory management device that can reliably prepare a use area of each unit when a plurality of access units use one data memory. And a memory management method.

  According to the memory management device of the first aspect, when the used area and the free area of the data memory are managed by using the link list memory, a restriction is provided on an area where each of the plurality of access units uses the data memory. Since the use area of each access unit is always ensured, unlike a conventional case, it is avoided that a specific unit exclusively uses the data memory.

In addition , a lower limit value is set in the queue counter of each access unit, and a virtual value obtained by subtracting the sum of all differences between the counter values when the queue counter value is less than the lower limit value from the Idle counter indicating the number of free areas. By managing the free space using the Idle counter, at least the lower limit value is secured in the used space of each unit.
When a write request is issued by any of a plurality of access units (write unit), the write control means has a queue counter of the unit equal to or greater than the upper limit value, or the queue counter is less than the upper limit value and equal to or greater than the lower limit value. When the value of the virtual idle counter is “0”, writing to the data memory is prohibited. That is, even if the queue counter is less than the upper limit value, if the virtual idle counter value is “0”, the free area at that time is substantially free if the lower limit of the used area of other units is secured. It is in. Therefore, also in this case, writing to the data memory is prohibited.

  Also, when the queue counter of the writing unit is less than the lower limit value, or when the counter is less than the upper limit value and greater than or equal to the lower limit value and the virtual Idle counter is not “0”, the counter is decremented and then the Idle head Write data to the address indicated by the register. That is, if the queue counter is less than the lower limit value, it indicates that there is a vacant space in the used area of the writing unit, so that unconditional writing is possible. Even if the queue counter is equal to or greater than the lower limit value, if the virtual idle counter is not “0”, it indicates that a free area exists after ensuring the lower limit used by other units. Therefore, the virtual Idle counter can be decremented (because one area is used) and data can be written to the address indicated by the Idle head register.

  After the above write processing, if the queue counter of the writing unit is not “0”, the address value of the Idle head register is written to the address of the link list memory indicated by the queue tail register of the unit. That is, as a result of performing the above-described writing process, the head of the empty area becomes the end of the used area of the writing unit. In addition, when the write unit queue counter is “0”, it indicates that there is no used area of the unit, so the start address of the free area is written to the queue start register of the unit, and the start of the used area is set. Set.

Furthermore, the contents of the Idle head register (the head address of the empty area) are written to the queue end register of the writing unit, the queue counter of the unit is incremented (because one area is used), and the link list indicated by the Idle head register When data is read from the memory address (that is, the start address of the current empty area), the data is written to the Idle start register and the Idle counter is decremented (because the empty area has been decreased by one).
As described above, write control to the data memory can be performed while securing the use area of each unit. Since the data memory is managed by setting the upper limit value and the lower limit value in the usage area of each unit, the upper limit value can be flexibly set (i.e., the upper limit value after securing the minimum number of units used by the lower limit value). Can be set to exceed the capacity of the data memory).
In addition, a plurality of access units are divided into a plurality of access groups so that each unit belongs to a plurality of groups, and a queue counter is provided for each group, and only the upper limit value of the queue is set for these queue counters. Then, the write control means performs determination processing similar to the upper limit value of the queue counter for each access unit for the upper limit value, and performs the same counting operation as the queue counter for each access unit for the queue counter for each group. Do. With such a configuration, by setting the upper limit of the use area for each group, the upper limit can be set more variously according to the application.

According to the memory management device of claim 2 , when a write request by the writing unit is generated, the write control means is configured such that the queue counter of the unit is greater than or equal to the upper limit value or the queue counter is less than the upper limit value and the lower limit value. When the above is true and the value of the virtual idle counter is “0”, data is written to the head address of the used area of the unit. That is, in claim 1 , writing to the data memory is prohibited in the same case, but in claim 2 , new data is overwritten on the top address of the use area, that is, the oldest data, and the queue top register Is written to the link list memory address indicated by the queue tail register and the queue tail register, data is read from the link list memory address indicated by the queue head register address value, and the data is written to the queue head address. Manage as data. Therefore, the latest data can be stored in the data memory without loss.
A plurality of access units are divided into a plurality of access groups so that each unit belongs to a plurality of groups, and a queue counter is provided for each group, and only the upper limit value of the queue is set for these queue counters. The write control means performs determination processing similar to the upper limit value of the queue counter for each access unit for the upper limit value, and performs the same counting operation as the queue counter for each access unit for the queue counter for each group. . With such a configuration, by setting the upper limit of the use area for each group, the upper limit can be set more variously according to the application.

  According to the memory management device of the fourth aspect, when the read request is issued by any one of the plurality of access units (read unit), the read control means performs data when the queue counter of the unit is “0”. Prohibits reading data from memory. That is, in this case, there is no data to be read. On the other hand, when the queue counter is not "0", data is read from the address of the data memory indicated by the queue head register of the reading unit (that is, the head address of the used area). It is assumed that once read data does not need to be stored in the data memory at that time, and overwriting is permitted.

After the above processing, if the value of the Idle counter is not “0”, the contents of the queue head register of the reading unit are written into the address of the link list memory indicated by the Idle tail register and the Idle tail register. Further, since one used area is released, the Idle counter is incremented.
On the other hand, when the value of the Idle counter is “0”, there is no available area, so the contents of the queue start register of the reading unit are written in the Idle start register and the Idle end register (the start of the free area is (Initializing again) Increment the Idle counter.

Further, data is read from the address of the link list memory indicated by the queue head register of the reading unit, and the data is written to the queue head register. Since one used area is released, the queue counter of the unit is decremented. In addition, if the queue counter of the reading unit is equal to or greater than the lower limit value, the virtual empty area is incremented by one, so the virtual idle counter is incremented.
By controlling as described above, data can be appropriately read from the use area of each unit.

(First embodiment)
Hereinafter, a first embodiment of the present invention will be described with reference to FIGS. FIG. 1 shows a configuration of a data input / output system including a memory management device according to the present invention. Such a system is used, for example, for an apparatus that transmits and receives communication data. The data input / output system 1 includes a data memory 2, and the data memory 2 is shared by three ports P0 to P2 (access units) to write and read data. For the data memory 2, a link list memory 3 is prepared in order to manage the used area and the free area by the link list method.

The ports P0 to P2 access the data memory 2 via the request arbitration unit 4 and the control unit (read control unit, write control unit) 5. When the ports P0 to P2 output a write request (write request) and a read request (read request) to the request arbitration unit 4, the request arbitration unit 4 arbitrates the request and permits the request. Then, any of the ports P0 to P2 to which the request is permitted outputs the Write port and the Read port, and executes the Write access and the Read access.
The request arbitration unit 4 outputs a start signal, an R / W control signal, and a port signal indicating a port for executing access to the control unit 5. The control unit 5 includes a sequencer (state machine) and an arithmetic unit, and performs address, select control, and data control.

The use area management unit (read control means, write control means) 6 includes a register group and a counter for managing each use area when the ports P0 to P2 use the data memory 2. Hereinafter, management parameters in the use area management unit 6 will be described.
-Queue start address: Start address of the used area-Queue end address: End address of the used area-Queue counter: Size in which the used area is actually used (data is written)-Maximum number of queues: Number of used areas Maximum number (fixed value by user setting)
-Queue lower limit number: Lower limit number of used area (fixed value set by user)
That is, by setting the lower limit number (lower limit value) for each used area, the minimum number of used areas is secured for each port P0 to P2. In addition to the lower limit number, an upper limit number (upper limit value) is set to limit the maximum number of used areas. Here, “queue” is synonymous with “use area”.

The following flags are automatically set by the use area management unit 6 according to the state of the queue counter.
• Queue FULL flag: Set when the queue counter exceeds the upper limit • Queue OV_MIN flag: Set when the queue counter exceeds the lower limit • Queue EMPTY flag: Set when the queue counter reaches “0”

On the other hand, the unused area management unit (read control means, write control means) 7 is a register group for managing unused areas (free areas) of the data memory 2. Hereinafter, management parameters in the unused area management unit 7 will be described.
-Idle start address: Start address of unused area-Idle end address: End address of unused area-Idle counter: Size of unused area In addition to the Idle counter, a virtual Idle counter is provided. The virtual Idle counter summed the difference between all the ports when the counter value of the queue counter is less than the queue lower limit number for each port P0 to P2, and subtracted the total value from the counter value of the Idle counter. This is a counter whose value is set by the unused area management unit 7. Here, “Idle” is synonymous with “unused area”.

  That is, as described above, by setting the lower limit number for each used area, the used area of each port P0-P2 is secured, so when any port writes to the data memory 2, its own use Even if there is an apparent free area for the area, if the virtual Idle counter is “0” (the virtual Idle_EMPTY flag is set), writing is prohibited in order to secure the lower limit for the used area of other ports. .

Then, the control unit 5 refers to the statuses of the registers, counters, and flags of the used area management unit 6 and the unused area management unit 7, and stores the link list addresses of the used area and the unused area in the link list memory 3. , The data memory 2 is managed by the link list method. Further, when the writing process and the reading process with respect to the data memory 2 are completed, the control unit 5 outputs a Write acknowledge signal and a Read acknowledge signal to the outside.
In the above configuration, the memory management device 8 is configured by removing the request arbitration unit 4 from the data input / output system 1. The basic part of the management method using the link list is the same as the well-known technique as disclosed in Patent Document 1.

Next, the operation of this embodiment will be described with reference to FIGS.
<Overall processing>
FIG. 3 is a flowchart showing the entire processing executed mainly by the control unit 5. The control unit 5 performs the initial setting shown in FIG. 4 for the link list memory 3, the used area management unit 6, and the unused area management unit 7 (step M1). Then, it waits (Step M2, Idle state) until either a Write request or a Read request is issued by any of the ports P0 to P2 (Step M3, M6).
When there is a write request (step M3, "YES"), it is determined whether or not there is an empty space in the use area (buffer) of the data memory 2 (step M4). M5). On the other hand, if there is a read request (step M6, “YES”), it is determined whether or not there is data to be read in the use area of the data memory 2 (step M7). M8).

<Initial setting process>
Next, the “initial setting” process in step M1 will be described with reference to FIG. First, the control unit 5 writes data of “address + 1” to all addresses in the link list memory 3 (step S1). Then, control registers for the ports P0 to P2 are set (step S2). The queue counter is cleared to zero, and the upper and lower queue numbers are set according to user specifications. Note that since the queue head address and tail address are determined in the process execution process, initial setting is not necessary.

  Subsequently, the use area management unit 6 initializes the FULL flag, the OV_MIN flag, and the EMPTY flag according to the state of the queue counter of each port P0 to P2 (step S3). In this case, only the queue EMPTY flag is set. The subsequent steps S4 and S5 are processes executed in the second embodiment, which is an extension of the first embodiment, and are not used in the first embodiment. Therefore, description thereof will be given in the second embodiment.

  Next, the control unit 5 sets the Idle start address and end address of the unused area management unit 7 to the start address and end address of the link list memory (buffer) 3 and sets the Idle counter in the link list memory 3. The size is set (at this time, all the areas are unused, so step S6). Then, the value of the virtual idle counter is initialized as described above (step S7), and the state of the counter is reflected in the virtual idle_EMPTY flag (step S8).

<Write control>
Next, the write control corresponding to steps M4 and M5 will be described with reference to FIG. First, when it is determined which port of P0 to P2 is to be written (step W1), it is determined whether or not the queue FULL flag of that port (referred to as a write port) is “0” (step W2). ). If the queue FULL flag is “1” (NO), all data is written in the used area of the write port, and they are not yet read. Therefore, the data memory 2 is not written and the process is terminated.

  On the other hand, if the queue FULL flag is “0” (YES), since the use area of the write port has not reached the upper limit, it is subsequently determined whether or not the queue OV_MIN flag is “0” (step W3). If the queue OV_MIN flag is “0” (YES), it indicates that the used area of the write port has not yet reached the lower limit, so that writing is possible unconditionally. Therefore, data is written to the address of the link list memory 3 indicated by the Idle head address register at this time (the first write is the head address of the memory 3) (step W4).

  In Step W3, if the queue OV_MIN flag is “1” (NO), the use area of the write port exceeds the lower limit. Therefore, the process proceeds to step W9, and it is determined whether or not the virtual Idle_EMPTY flag is “0”. If the flag is “1” (NO), it indicates that there is no free space in the data memory 2 in a state where the lower limit of the other port is secured, so the processing is terminated without writing. On the other hand, if the flag is “0” (YES), there is an empty area in the data memory 2, so that the process proceeds to step W4 and writing is performed. Note that the processing of steps W2, W3, W9, and W10 corresponds to step M4 in FIG.

When data is written in step W4, it is subsequently determined whether or not the queue counter of the write port is “0” (step W5). If the counter is not “0” (NO), it indicates that all data written in the use area has not been read at that time.
However, since the queue counter is “0” by the initial setting at the time of the first writing, it is determined as “YES”, and the value of the Idle head address register is written in the queue head address register (step W11). ). Then, the value of the register is also written to the queue end address register (when only one piece of data is written, the beginning and end of the used area are the same), and the queue counter is incremented because one area is used at this point. (Step W7).

When the next data is written next time by the same write port, it is judged as NO in step W5. Therefore, the process proceeds to step W6, and the Idle head is added to the address of the link list memory 3 indicated by the queue end address register. Write the value of the address register. Then, the process proceeds to step W7.
In subsequent step W8, the state of the queue counter is reflected in each queue (FULL, OV_MIN, EMPTY) flag. Then, data is read from the address of the link list memory 3 indicated by the Idle head address register, the data is written to the Idle head address register, and the Idle counter is decremented (step W12). Finally, when the state of the virtual idle counter is reflected in the EMPTY flag (step W13), the process is terminated.

  Regarding the above-described write control, the write processing is prohibited based on the determination result of each flag in steps W2, W3, and W9, and the processing portion related to the virtual idle counter in steps W10 and W13 for performing the determination processing has a new configuration. It has become.

<Read control>
Next, Read control corresponding to steps M7 and M8 in FIG. 3 will be described with reference to FIG. First, when it is determined which port of P0 to P2 is to be read (step R1), it is determined whether or not the queue EMPTY flag of that port (referred to as a read port) is “0” (step R2). ). That is, if the queue EMPTY flag is set to “1” (NO), it indicates that no data is written in the use area of the read port and no read target data exists. Therefore, the process is terminated without reading data.

On the other hand, if the queue EMPTY flag is “0” (step R2, YES), there is data to be read, so data is read from the address of the data memory 2 indicated by the queue head address register (step R3). Subsequently, it is determined whether or not the Idle counter is “0” (step R4). If it is not “0” (NO), there is an empty area in the data memory 2. Therefore, the contents of the queue head address register of the read port are written to the address of the link list memory 3 indicated by the Idle end address register (step R5). That is, the end of the free area is updated to the address read in step R3.
If the Idle counter is “0” in step R4 (YES), the data memory 2 has no free space, so the contents of the queue head address register are written into the Idle head address register (step R12). That is, the free area start address is updated to the use area start address.

  Subsequently, the contents of the queue head address register are written into the Idle tail address register. That is, the start address of the used area at this time is the end address of the empty area. Then, since one used area is released by reading the data, the Idle counter is incremented (step R6). Next, when data is read from the address of the link list memory 3 indicated by the queue head address register, the data is written to the queue head address register and the queue counter is decremented (step R7).

  Next, similarly to step W8, when the state of the queue counter is reflected in each queue (FULL, OV_MIN, EMPTY) flag (step R8), it is determined whether or not the queue OV_MIN flag is “0” (step R9). . If the flag is “1” (NO), the read port allocation area is used more than the lower limit when one used area is released. Therefore, when the virtual idle counter is incremented (step R10) and the state of the counter is reflected in the EMPTY flag (step R11), the process is terminated (step R11 may be passed). On the other hand, if the queue OV_MIN flag is “0” in step R9 (YES), the read port allocation area is not used until the lower limit is reached, and the process proceeds to step R11.

Here, FIG. 2 shows an example of the image of the data memory 2 and the link list memory 3 and the change state of each register and flag when the above-described write control and read control are performed. The initial state is (a), and the empty areas of the data memory 2 (assuming the size is 8 frames) are addresses 4 and 7. The data arrangement of port P0 is
Data P0-0 → address 0
Data P0-1 → Address 1
Data P0-2 → Address 5
The start address of the use area is “0”, the end address is “5”, and the value of the queue counter is “3”. The address link in the link list memory 3 is
Address: 0 → 1 → 5 → (6)
It has become. However, the last address (6) does not mean the use area of the port P0.

  In addition, the upper limit of the use area of each port P0, P1, P2 is “4”, and their total exceeds the size of the data memory 2, but the lower limits are “1”, “1”, “2”. And at least those areas are secured for each port. Even if the number of data written does not reach the upper limit, writing may be restricted by control based on the state of the virtual idle counter.

In the state (a) to (b), when the port P0 next writes the data P0-3, the data P2 is written to the free space start address “4” (Idle0). As a result, the address 4 is written to the address 5 of the link list memory 3, and the address link in the link list memory 3 is
Address: 0 → 1 → 5 → 4 → (7)
To change.
Further, the end address of the used area is “4”, the value of the queue counter is “4”, and since the upper limit has been reached, the queue FULL flag is set. Since the Idle start address is decreased to “7”, the value of the Idle counter is decreased to “1”, and the value of the virtual Idle counter is decreased to “0”, the virtual Idle_EMPTY flag is set.

  Next, in the state (b) to (c), when the port P2 reads the data P2-0, the data P2-0 is read from the queue head address 2 of the data memory 2. Then, the address 2 becomes an empty area, and the used area of the port P2 disappears. That is, the value of the queue counter is “0” and the queue EMPTY flag is set. The Idle end address is “2”, and the Idle counter is incremented to “2”. In this case, the queue head address of the port P2 is updated to (4) according to the Read control, but there is no substantial meaning because there is no used area.

As described above, according to the present embodiment, in the data input / output system 1, when the used area and the free area of the data memory 2 are managed using the link list memory 3, the ports P 0 to P 2 are respectively connected to the data memory. 2 is limited, and the memory management device 8 is configured so that the use areas of the ports P0 to P2 are always secured. Unlike conventional systems, specific ports exclusively use the data memory 2. It is avoided to be in a state of use.
Specifically, the lower limit number is set in the queue counter of each port P0 to P2, and the difference between the two when the counter value in each queue counter is larger than the lower limit number is summed from the value of the idle counter indicating the number of free areas. By managing the free space using the reduced virtual idle counter, the used space of each unit is secured at least the lower limit number.

When a write request is generated by any of the ports P0 to P2, the control unit 5 indicates that the queue counter of the write port is greater than or equal to the upper limit number, or less than the upper limit number and greater than or equal to the lower limit number, and the value of the virtual idle counter is In the case of “0”, writing to the data memory 2 is prohibited. In other words, even if the queue counter is less than the upper limit number, writing is prohibited when it is necessary to secure the lower limit of the used area of other ports.
If the queue counter of the write port is less than the lower limit number, or less than the upper limit number and greater than or equal to the lower limit number, and the virtual Idle counter is not “0”, the counter is decremented and data is stored at the address indicated by the Idle head register. Write. That is, if there is a vacant area in the use area of the write port, or if a vacant area exists after ensuring the lower limit used by other ports, data can be written to the start address of the vacant area.

  When the write process is performed as described above, the head of the free area becomes the end of the used area of the write port. Therefore, if the queue counter is not “0”, the address value of the Idle start register is set to the queue end register of the port. Is written in the address of the link list memory 3 indicated by If the queue counter is “0”, there is no head in the used area, so the head address of the free area is written in the queue head register of the write port, and the head of the used area is set as the head of the free area. Data can be overwritten from the beginning of the area.

Furthermore, the contents of the Idle head register are written to the queue end register of the write port, the queue counter is incremented, data is read from the address of the link list memory 3 indicated by the Idle head register, and the Idle counter is decremented when written to the Idle head register. . Therefore, it is possible to perform write control while securing the use area of each port. And about the use area | region of each port, after ensuring the minimum use number by a lower limit number, an upper limit number can be set flexibly.
Further, when a read request is generated by any of the ports P0 to P2, the control unit 5 prohibits data reading when the queue counter of the read port is “0”, and when the queue counter is not “0”. The data is read from the address of the data memory 2 indicated by the queue head register.

  After the above processing, if the value of the Idle counter is not “0”, the contents of the queue head register are written to the address of the link list memory 3 indicated by the Idle tail register and the Idle tail register, and the Idle counter is incremented. To do. When the value of the Idle counter is “0”, the contents of the queue head register are written in the Idle head register and the Idle tail register, and then the Idle counter is incremented. Further, data is read from the address of the link list memory 3 indicated by the queue head register and written to the queue head register to decrement the queue counter. If the queue counter is equal to or greater than the lower limit, the virtual idle counter is incremented. Therefore, data can be appropriately read from the use area of each port.

(Second embodiment)
7 to 12 show a second embodiment of the present invention. The same parts as those in the first embodiment are denoted by the same reference numerals and the description thereof will be omitted. Hereinafter, different parts will be described. The data input / output system 11 of the second embodiment is configured by increasing the number of units that perform writing and reading to the data memory 2, the request arbitration unit 4 being 12, the control unit 5 being 13, and the use area. The management unit 6 is replaced with 14, and the memory management device 8 is replaced with 15.

  There are eight ports P0 to P7, and three priorities (classes) of High, Mid, and Low are set for each port, and the number of access units is “24”. Each unit of priority High, Mid, and Low at the port P0 is referred to as a P0 group. These priorities are not directly related to the memory management system of the present invention, and indicate priorities for reading / writing data in the ports P0 to P7, and adjustment based on the priorities is performed. This is done by another component.

  In the use area management unit 14, a head / end address register, a queue counter, a queue upper / lower limit number, and queue (FULL, OV_MIN, EMPTY) flags are prepared for each unit, and each port P0 to P7 is provided. In addition, a queue counter, an upper limit number of queues, and a queue FULL flag are prepared (port total management unit). In addition, the priority of High, Mid, and Low in each port P0 to P7 is also grouped in a vertical relationship, and a queue counter, an upper limit number of queues, and a queue FULL flag are prepared for each group (priority level). Total Management Department). The counter and the upper limit number for each group are the sum of the counter values and the upper limit numbers of units belonging to the group.

  Next, the operation of the second embodiment will be described with reference to FIGS. In the case of the second embodiment, in the initial setting process shown in FIG. 4, the initial setting of the queue counter (= 0) and the setting of the upper limit number of queues (users) are also set for each port total management unit and each priority total management unit. (Step S4) and the process of reflecting the state of the queue counter in the queue FULL flag (step S5).

8 and 9 are diagrams corresponding to FIGS. 5 and 6 of the first embodiment. The basic processing is the same as in the first embodiment, but for the processing with the step number “'” added, the processing for specifying the accessed unit together with the group to which the unit belongs is added. Show. For example, in step W1 ′ in FIG. 8, the unit that made the write request belongs to any group of P0 to P7 (which belongs to any port total management unit), and any of High, Mid, and Low In step W2 ′, it is determined whether or not all queue FULL flags of the group to which the writing unit belongs, the priority management unit, and the port total management unit are “0”. To do.
In step W8 ′, the counter state of the target group is reflected in each queue flag, and the counter states of the target port total management unit and priority total management unit are also reflected in the queue FULL flag. The same change is made in the Read control shown in FIG.

  10 and 11 conceptually illustrate an example in which each access unit divides and uses the area of the data memory 2 as a result of performing the processing as described above. In order to simplify the description, a case where there are a total of 12 units with four ports P0 to P3 is shown. The size of the data memory 2 is assumed to be 512 frames.

  In FIG. 11A, the upper limit number is set to “512” for any of the queue unit, output port unit, and class unit of each group, and the setting condition for the upper limit number is the most lenient. That is, for each unit, any one of the other units can be used up to the maximum free space value (<512) indicated by the virtual idle counter, except that the lower limit number of queues is secured. . The same setting is applied to each of the ports P0 to P3 and the classes High, Mid, and Low.

  In FIG. 11B, when the upper limit of the queue unit of each group is 42 frames for class High and 43 frames for classes Mid and Low with respect to (a), 512 frames are equally divided for each port. It is. Although the upper limit of the port unit and the class unit is set to 512 frames, the upper limit is substantially (42 + 43 + 43 =) 128 frames.

  FIG. 11C shows the case where the upper limit number is given an inclination between ports. That is, the upper limit of each class is 64 frames for port P0, and the upper limits of ports P1 and P2 are 48 and 32 frames, respectively. For the port P3, there is no upper limit setting for each class, and the upper limit is set to 80 frames for each port.

  In FIG. 11 (d), the upper limit is set to 128 frames for each port P0 to P3 and is equally divided. The upper limit setting for each queue is set to 50 frames, and the upper limit is limited within a range where the total is 128 frames.

  Further, FIG. 12 shows the data input / output system 11 shown in FIG. 7 with the components that perform input / output control of ports P0 to P7 added to the periphery thereof. Configured as an IC chip. The communication data input / output device 21 has an input port 22 and an output port 23 independently for the eight ports P0 to P7. That is, when data input via the input port 22 (0) is written into the data memory 2, the data is read out by the output port 23 (0) and output to the outside.

When the input port 22 outputs request signals to the input control unit 24, the input control unit 24 arbitrates the request signals, outputs a port select signal to the multiplexer 25 and the write group setting unit 26, and outputs data input / output. A write request signal is output to the request arbitration unit 12 of the system 11.
The data of the input port 22 selected by the input control unit 24 is output to the priority determination unit 27 via the multiplexer 25 and further output to the data memory 2 of the data input / output system 11. For each port, there is a group of high priority, mid, low, and when two or more of these output a request in the port, a high priority is selected in the port. When the priority determination unit 27 determines the priority assigned to the data output from the selected port, the priority determination unit 27 outputs the determination result to the write group setting unit 26.

  The write group setting unit 26 sets a write group (one of the access units) based on the given port and priority, and outputs it to the request arbitration unit 12. The write acknowledge signal output from the control unit 13 of the data input / output system 11 is given to the input control unit 24.

On the other hand, when the output port 23 outputs the request signal to the output priority determination unit 28 and the output control unit 29 corresponding to itself, the output priority determination unit 28 determines the priority of the port group assigned to the request signal. And the determination result is output to the output control unit 29. Then, the output control unit 29 sets a Read group (one of the access units) according to the input request signal and priority, and outputs it to the request arbitration unit 12 together with the Read request signal.
The data output from the data memory 2 is output to each output port 23. The Read acknowledge signal output by the control unit 13 is given to the output control unit 29, and the output control unit 29 outputs the acknowledge signal to one of the selected output ports.

  As described above, according to the second embodiment, a plurality of ports P0 to P7 are provided with a group in which priority classes are set in three levels, and the three-level classes are also divided into access groups. A queue counter is provided for each group, and only the upper limit number is set for these queue counters, and the control unit 13 performs the same determination process as the upper limit number of the queue counter for each of the ports P0 to P7. At the same time, the same counting operation as the queue counter of the ports P0 to P7 is performed for the queue counter for each group. Therefore, the upper limit can be set more variously according to the application.

(Third embodiment)
FIG. 13 shows a third embodiment of the present invention, and different portions from the first embodiment will be described. FIG. 13 corresponds to FIG. In the write control of the first embodiment, when “NO” is determined in steps W2 and W9, writing to the data memory 2 is prohibited. However, in the third embodiment, step W14 is executed in the above case, and writing is performed. Input data is written to the address of the data memory 2 indicated by the queue head address register of the port.

  That is, in the case where “NO” is determined in steps W2 and W9, since there is no free area in the data memory 2, writing is prohibited in the first embodiment, but in the third embodiment, the use area of the write port is The latest input data is overwritten on the oldest data not yet read indicated by the head address. Then, the address value of the queue head register is written to the link list memory address indicated by the queue tail register and the queue tail register (steps W15 and W16), and data is read from the link list memory address indicated by the queue head register address value. The data is written to the queue head address (step W17) and managed as the latest data. Therefore, the latest data can be stored in the data memory without loss.

The present invention is not limited to the embodiments described above and shown in the drawings, and the following modifications or expansions are possible.
The number of access units may be appropriately changed according to the individual design.

1 is a diagram showing a configuration of a data input / output system including a memory management device according to a first embodiment of the present invention. Diagram showing an example of data memory, link list memory image, and change status of each register and flag Flowchart showing the entire processing content The flowchart which shows the detail of the initial setting process of step M1 in FIG. Flow chart showing details of Write control Flow chart showing details of Read control FIG. 1 equivalent view showing a second embodiment of the present invention. Figure equivalent to FIG. 6 equivalent diagram FIG. 1 is a diagram for conceptually explaining an example in which each access unit divides and uses a data memory area (part 1). Equivalent to FIG. 10 (part 2) The figure which shows the structural example of the communication data input / output apparatus comprised with a data input / output system FIG. 5 equivalent diagram showing a third embodiment of the present invention.

Explanation of symbols

  In the drawing, 2 is a data memory, 3 is a link list memory, 5 is a control unit (reading control means, writing control means), 6 is a used area management part (reading control means, write control means), and 7 is unused area management. (Read control means, write control means), 8 is a memory management device, 13 is a control section (read control means, write control means), 14 is a use area management section (read control means, write control means), and 15 is a memory. Indicates a management device.

Claims (8)

When the data requested to be written is written to the data memory and the data requested to be read is read from the data memory and output, the used area and free area of the data memory are managed using the link list memory In the memory management device
A plurality of access units that write and read data to and from the data memory are configured so that a use area of the plurality of access units is always secured by providing a restriction on an area in which the data memory is used. ,
A plurality of access units, a queue start register and a queue end register for storing a start address and an end address of an area in which the data memory is used;
A queue counter for counting the size in which each of the plurality of access units is using the area of the data memory, and
Idle start register and Idle end register in which the start address and end address of the empty area are stored, and
An Idle counter for counting the size of the free area;
An upper limit value of the queue and a lower limit value corresponding to the minimum number of queues are set for each of the plurality of queue counters, and the counter value in each queue counter is less than the lower limit value from the value of the Idle counter. And a virtual idle counter in which the value obtained by adding and subtracting all the differences between the two is stored,
When a write request by any of the plurality of access units occurs,
When the queue counter corresponding to the access unit is greater than or equal to the upper limit value, or when the queue counter is less than the upper limit value and greater than or equal to the lower limit value and the value of the virtual idle counter is “0”, writing to the data memory is performed. Ban,
When the queue counter corresponding to the access unit is less than the lower limit value, or when the queue counter is less than the upper limit value and greater than or equal to the lower limit value and the virtual idle counter is not “0”, the counter is decremented. , Write data to the address indicated by the Idle head register,
When the queue counter is not “0”, the address value of the Idle head register is written to the address of the link list memory indicated by the queue end register of the access unit, and when the queue counter is “0”, the Write the address value to the queue head register of the access unit,
Write the contents of the Idle head register to the queue end register of the access unit, increment the queue counter of the access unit,
Read data from the address of the link list memory indicated by the Idle first register, write the data to the Idle first register, and includes a write control means for decrementing the Idle counter,
The plurality of access units are divided into a plurality of access groups so that each unit belongs to a plurality of groups, and a queue counter is provided for each group,
The write control means sets only the upper limit value of the queue for the queue counter for each group, and performs the same determination processing as the upper limit value of the queue counter for each access unit for the upper limit value. A memory management device that performs a counting operation similar to a queue counter for each unit. When the data requested to be written is written to the data memory and the data requested to be read is read from the data memory and output, the used area and free area of the data memory are managed using the link list memory In the memory management device
A plurality of access units that write and read data to and from the data memory are configured so that a use area of the plurality of access units is always secured by providing a restriction on an area in which the data memory is used. ,
A plurality of access units, a queue start register and a queue end register for storing a start address and an end address of an area in which the data memory is used;
A queue counter for counting the size in which each of the plurality of access units is using the area of the data memory, and
Idle start register and Idle end register in which the start address and end address of the empty area are stored, and
An Idle counter for counting the size of the free area;
The upper limit of the respective queue for the plurality of queues counters, and the lower limit corresponding to minimum number reserved for the queue and is set, than the value of the Idle counter, the counter value of each queue counter is smaller than the lower limit value And a virtual idle counter in which the value obtained by adding and subtracting all the differences between the two is stored,
When a write request by any of the plurality of access units occurs,
When the queue counter corresponding to the access unit is greater than or equal to the upper limit value, or when the queue counter is less than the upper limit value and greater than or equal to the lower limit value and the value of the virtual idle counter is “0” , Data is written to the address indicated by the queue head register, the address value of the queue head register is written to the address of the link list memory indicated by the queue tail register and the queue tail register, and data is obtained from the address of the link list memory indicated by the address value. And write the data to the queue head address,
When the queue counter corresponding to the access unit is less than the lower limit value, or when the queue counter is less than the upper limit value and greater than or equal to the lower limit value and the virtual idle counter is not “0”, the counter is decremented. , Write data to the address indicated by the Idle head register,
When the queue counter is not “0”, the address value of the Idle head register is written to the address of the link list memory indicated by the queue end register of the access unit, and when the queue counter is “0”, the Write the address value to the queue head register of the access unit,
Write the contents of the Idle head register to the queue end register of the access unit, increment the queue counter of the access unit,
Read data from the address of the link list memory indicated by the Idle first register, write the data to the Idle first register, and includes a write control means for decrementing the Idle counter ,
The plurality of access units are divided into a plurality of access groups so that each unit belongs to a plurality of groups, and a queue counter is provided for each group,
The write control means, for the queue counter for each group,
Only the upper limit value of the queue is set, and for the upper limit value, a determination process similar to the upper limit value of the queue counter for each access unit is performed,
A memory management device that performs a counting operation similar to a queue counter for each access unit . The plurality of access units belong to both an access group consisting of a plurality of output ports set in the data memory and an access group consisting of a plurality of priority levels set to each of the plurality of output ports. The memory management device according to claim 1 , wherein the memory management device is a memory management device. When a read request is generated by any of the plurality of access units,
When the queue counter corresponding to the access unit is “0”, data reading from the data memory is prohibited,
When the queue counter corresponding to the access unit is not “0”, data is read from the address of the data memory indicated by the queue head register of the access unit;
When the value of the Idle counter is not “0”, the contents of the queue head register of the access unit are written in the address of the link list memory indicated by the Idle tail register and the Idle tail register, and the Idle counter is set. Increment and
When the value of the counter is “0”, the contents of the queue head register of the access unit are written into the Idle head register and the Idle tail register, and the Idle counter is incremented.
Read data from the address of the link list memory indicated by the queue head register of the access unit, write the data to the queue head register, decrement the queue counter of the access unit,
Wherein if the queue counter of the access unit is not less than the lower limit value, a memory management device according to any one of claims 1 to 3, further comprising a read control means for incrementing the virtual Idle counter. When the data requested to be written is written to the data memory and the data requested to be read is read from the data memory and output, the used area and free area of the data memory are managed using the link list memory In the memory management method to
A plurality of access units that perform writing and reading of data to and from the data memory are provided with restrictions on the areas where the data memory is used, respectively, so that the use area of the plurality of access units is always secured,
A plurality of access units, a queue start register and a queue end register for storing a start address and an end address of an area in which the data memory is used;
A queue counter for counting the size in which each of the plurality of access units is using the area of the data memory, and
Idle start register and Idle end register in which the start address and end address of the empty area are stored, and
An Idle counter for counting the size of the free area;
By setting the upper limit value of the queue and the lower limit value corresponding to the minimum number of reserved queues for each of the plurality of queue counters, the counter value in each queue counter is less than the lower limit value than the value of the Idle counter. Use the virtual idle counter that stores the total of the differences between the two cases and stores the subtracted value.
When a write request by any of the plurality of access units occurs,
When the queue counter corresponding to the access unit is greater than or equal to the upper limit value, or when the queue counter is less than the upper limit value and greater than or equal to the lower limit value and the value of the virtual idle counter is “0”, writing to the data memory is performed. Ban,
When the queue counter corresponding to the access unit is less than the lower limit value, or when the queue counter is less than the upper limit value and greater than or equal to the lower limit value and the virtual idle counter is not “0”, the counter is decremented. , Write data to the address indicated by the Idle head register,
When the queue counter is not “0”, the address value of the Idle head register is written to the address of the link list memory indicated by the queue end register of the access unit, and when the queue counter is “0”, the Write the address value to the queue head register of the access unit,
Write the contents of the Idle head register to the queue end register of the access unit, increment the queue counter of the access unit, read data from the address of the link list memory indicated by the Idle head register, and To the Idle head register, decrement the Idle counter,
Dividing the plurality of access units into a plurality of access groups so that each unit belongs to a plurality of groups, and using a queue counter for each group,
For the queue counter for each group, only the upper limit value of the queue is set, and for the upper limit value, a determination process similar to the upper limit value of the queue counter for each access unit is performed. A memory management method comprising performing a similar counting operation . When the data requested to be written is written to the data memory and the data requested to be read is read from the data memory and output, the used area and free area of the data memory are managed using the link list memory In the memory management method to
A plurality of access units that perform writing and reading of data to and from the data memory are provided with restrictions on the areas where the data memory is used, respectively, so that the use area of the plurality of access units is always secured ,
A plurality of access units, a queue start register and a queue end register for storing a start address and an end address of an area in which the data memory is used;
A queue counter for counting the size in which each of the plurality of access units is using the area of the data memory, and
Idle start register and Idle end register in which the start address and end address of the empty area are stored, and
An Idle counter for counting the size of the free area;
By setting the upper limit value of the queue and the lower limit value corresponding to the minimum number of reserved queues for each of the plurality of queue counters, the counter value in each queue counter is less than the lower limit value than the value of the Idle counter. Use the virtual idle counter that stores the total of the differences between the two cases and stores the subtracted value.
When a write request by any of the plurality of access units occurs,
When the queue counter corresponding to the access unit is greater than or equal to the upper limit value, or when the queue counter is less than the upper limit value and greater than or equal to the lower limit value and the value of the virtual idle counter is “0”, Data is written to the address indicated by the queue head register, the address value of the queue head register is written to the address of the link list memory indicated by the queue tail register and the queue tail register, and data is obtained from the address of the link list memory indicated by the address value. And write the data to the queue head address,
When the queue counter corresponding to the access unit is less than the lower limit value, or when the queue counter is less than the upper limit value and greater than or equal to the lower limit value and the virtual idle counter is not “0”, the counter is decremented. , Write data to the address indicated by the Idle head register,
When the queue counter is not “0”, the address value of the Idle head register is written to the address of the link list memory indicated by the queue end register of the access unit, and when the queue counter is “0”, the Write the address value to the queue head register of the access unit,
Write the contents of the Idle head register to the queue end register of the access unit, increment the queue counter of the access unit, read data from the address of the link list memory indicated by the Idle head register, and To the Idle head register, decrement the Idle counter,
Dividing the plurality of access units into a plurality of access groups so that each unit belongs to a plurality of groups, and using a queue counter for each group,
For the queue counter for each group, only the upper limit value of the queue is set, and for the upper limit value, a determination process similar to the upper limit value of the queue counter for each access unit is performed. A memory management method comprising performing a similar counting operation . The plurality of access units belong to both an access group consisting of a plurality of output ports set in the data memory and an access group consisting of a plurality of priority levels set to each of the plurality of output ports. The memory management method according to claim 5 or 6, wherein: When a read request is generated by any of the plurality of access units ,
When the queue counter corresponding to the access unit is “0”, data reading from the data memory is prohibited,
When the queue counter corresponding to the access unit is not “0”, data is read from the address of the data memory indicated by the queue head register of the access unit;
When the value of the Idle counter is not “0”, the contents of the queue head register of the access unit are written in the address of the link list memory indicated by the Idle tail register and the Idle tail register, and the Idle counter is set. Increment and
When the value of the counter is “0”, the contents of the queue head register of the access unit are written into the Idle head register and the Idle tail register, and the Idle counter is incremented.
Read data from the address of the link list memory indicated by the queue head register of the access unit, write the data to the queue head register, decrement the queue counter of the access unit,
Wherein if the queue counter of the access unit is not less than the lower limit value, a memory management method according to any one of claims 5 to 7, characterized in that incrementing the virtual Idle counter.

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