JP4360873B2 - ウエハレベルcspの製造方法 - Google Patents
ウエハレベルcspの製造方法 Download PDFInfo
- Publication number
- JP4360873B2 JP4360873B2 JP2003325938A JP2003325938A JP4360873B2 JP 4360873 B2 JP4360873 B2 JP 4360873B2 JP 2003325938 A JP2003325938 A JP 2003325938A JP 2003325938 A JP2003325938 A JP 2003325938A JP 4360873 B2 JP4360873 B2 JP 4360873B2
- Authority
- JP
- Japan
- Prior art keywords
- thermal stress
- stress relaxation
- post
- wafer level
- solder
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Fee Related
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Classifications
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W74/00—Encapsulations, e.g. protective coatings
- H10W74/10—Encapsulations, e.g. protective coatings characterised by their shape or disposition
- H10W74/111—Encapsulations, e.g. protective coatings characterised by their shape or disposition the semiconductor body being completely enclosed
- H10W74/129—Encapsulations, e.g. protective coatings characterised by their shape or disposition the semiconductor body being completely enclosed forming a chip-scale package [CSP]
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W72/00—Interconnections or connectors in packages
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W42/00—Arrangements for protection of devices
- H10W42/121—Arrangements for protection of devices protecting against mechanical damage
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W74/00—Encapsulations, e.g. protective coatings
- H10W74/10—Encapsulations, e.g. protective coatings characterised by their shape or disposition
- H10W74/131—Encapsulations, e.g. protective coatings characterised by their shape or disposition the semiconductor body being only partially enclosed
- H10W74/147—Encapsulations, e.g. protective coatings characterised by their shape or disposition the semiconductor body being only partially enclosed the encapsulations being multilayered
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W20/00—Interconnections in chips, wafers or substrates
- H10W20/40—Interconnections external to wafers or substrates, e.g. back-end-of-line [BEOL] metallisations or vias connecting to gate electrodes
- H10W20/49—Adaptable interconnections, e.g. fuses or antifuses
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W70/00—Package substrates; Interposers; Redistribution layers [RDL]
- H10W70/60—Insulating or insulated package substrates; Interposers; Redistribution layers
- H10W70/67—Insulating or insulated package substrates; Interposers; Redistribution layers characterised by their insulating layers or insulating parts
- H10W70/68—Shapes or dispositions thereof
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W70/00—Package substrates; Interposers; Redistribution layers [RDL]
- H10W70/60—Insulating or insulated package substrates; Interposers; Redistribution layers
- H10W70/67—Insulating or insulated package substrates; Interposers; Redistribution layers characterised by their insulating layers or insulating parts
- H10W70/69—Insulating materials thereof
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W72/00—Interconnections or connectors in packages
- H10W72/01—Manufacture or treatment
- H10W72/012—Manufacture or treatment of bump connectors, dummy bumps or thermal bumps
- H10W72/01221—Manufacture or treatment of bump connectors, dummy bumps or thermal bumps using local deposition
- H10W72/01223—Manufacture or treatment of bump connectors, dummy bumps or thermal bumps using local deposition in liquid form, e.g. by dispensing droplets or by screen printing
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W72/00—Interconnections or connectors in packages
- H10W72/01—Manufacture or treatment
- H10W72/019—Manufacture or treatment of bond pads
- H10W72/01921—Manufacture or treatment of bond pads using local deposition
- H10W72/01923—Manufacture or treatment of bond pads using local deposition in liquid form, e.g. by dispensing droplets or by screen printing
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W72/00—Interconnections or connectors in packages
- H10W72/20—Bump connectors, e.g. solder bumps or copper pillars; Dummy bumps; Thermal bumps
- H10W72/241—Dispositions, e.g. layouts
- H10W72/242—Dispositions, e.g. layouts relative to the surface, e.g. recessed, protruding
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W72/00—Interconnections or connectors in packages
- H10W72/20—Bump connectors, e.g. solder bumps or copper pillars; Dummy bumps; Thermal bumps
- H10W72/251—Materials
- H10W72/252—Materials comprising solid metals or solid metalloids, e.g. PbSn, Ag or Cu
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W72/00—Interconnections or connectors in packages
- H10W72/20—Bump connectors, e.g. solder bumps or copper pillars; Dummy bumps; Thermal bumps
- H10W72/29—Bond pads specially adapted therefor
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W72/00—Interconnections or connectors in packages
- H10W72/90—Bond pads, in general
- H10W72/941—Dispositions of bond pads
- H10W72/9415—Dispositions of bond pads relative to the surface, e.g. recessed, protruding
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W72/00—Interconnections or connectors in packages
- H10W72/90—Bond pads, in general
- H10W72/941—Dispositions of bond pads
- H10W72/942—Dispositions of bond pads relative to underlying supporting features, e.g. bond pads, RDLs or vias
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W72/00—Interconnections or connectors in packages
- H10W72/90—Bond pads, in general
- H10W72/951—Materials of bond pads
- H10W72/952—Materials of bond pads comprising metals or metalloids, e.g. PbSn, Ag or Cu
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W74/00—Encapsulations, e.g. protective coatings
- H10W74/40—Encapsulations, e.g. protective coatings characterised by their materials
- H10W74/47—Encapsulations, e.g. protective coatings characterised by their materials comprising organic materials, e.g. plastics or resins
Landscapes
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
- Wire Bonding (AREA)
Description
図1は本発明によって製造したウエハレベルCSPの断面を示すものである。
2 接合パッド
3 再配線回路
4 熱応力緩和ポスト
5 絶縁層
6 絶縁層
7 はんだバンプ
8 熱応力サポート層
8a はんだバンプの下部外周の受容部
Claims (3)
- ウエハ上にメッキによる再配線回路を形成すると共に該再配線回路上にはんだ等の導電材による熱応力緩和ポストを形成し、これら再配線回路と熱応力緩和ポストの周囲に、該熱応力緩和ポストの上面を除いてポリイミド等からなる絶縁層を形成し、更に前記熱応力緩和ポスト上にはんだバンプを形成するウエハレベルCSPの製造方法であって、前記再配線回路上にスクリーン印刷により熱応力緩和ポストを形成し、次に前記再配線回路と熱応力緩和ポストの周囲に、該熱応力緩和ポストの上面を除いてスクリーン印刷により絶縁層を形成し、次に前記熱応力緩和ポスト上にスクリーン印刷によりはんだバンプを形成したことを特徴とするウエハレベルCSPの製造方法。
- 熱応力緩和ポストを形成する導電材がはんだである請求項1記載のウエハレベルCSPの製造方法。
- 絶縁層の上面に、熱応力緩和ポストの位置にはんだバンプの下部外周の受容部を設けた絶縁材からなる熱応力サポート層をスクリーン印刷により形成してなる請求項1又は2記載のウエハレベルCSPの製造方法。
Priority Applications (9)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2003325938A JP4360873B2 (ja) | 2003-09-18 | 2003-09-18 | ウエハレベルcspの製造方法 |
| TW093127629A TWI253128B (en) | 2003-09-18 | 2004-09-13 | Method of manufacturing wafer level chip size package |
| US10/939,416 US20050064624A1 (en) | 2003-09-18 | 2004-09-14 | Method of manufacturing wafer level chip size package |
| KR1020040073293A KR100742902B1 (ko) | 2003-09-18 | 2004-09-14 | 웨이퍼 레벨 csp의 제조방법 |
| EP04255574A EP1517369A3 (en) | 2003-09-18 | 2004-09-15 | Method of manufacturing wafer level chip size package |
| CNA2004100781750A CN1604295A (zh) | 2003-09-18 | 2004-09-17 | 晶片级csp的制造方法 |
| SG200407966-1A SG157220A1 (en) | 2003-09-18 | 2004-09-17 | Method of manufacturing wafer level chip size package |
| MYPI20043805A MY139562A (en) | 2003-09-18 | 2004-09-17 | Method of manufacturing wafer level chip size package |
| US12/007,406 US20080145973A1 (en) | 2003-09-18 | 2008-01-10 | Method of manufacturing wafer level chip size package |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2003325938A JP4360873B2 (ja) | 2003-09-18 | 2003-09-18 | ウエハレベルcspの製造方法 |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JP2005093772A JP2005093772A (ja) | 2005-04-07 |
| JP4360873B2 true JP4360873B2 (ja) | 2009-11-11 |
Family
ID=34191342
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP2003325938A Expired - Fee Related JP4360873B2 (ja) | 2003-09-18 | 2003-09-18 | ウエハレベルcspの製造方法 |
Country Status (8)
| Country | Link |
|---|---|
| US (2) | US20050064624A1 (ja) |
| EP (1) | EP1517369A3 (ja) |
| JP (1) | JP4360873B2 (ja) |
| KR (1) | KR100742902B1 (ja) |
| CN (1) | CN1604295A (ja) |
| MY (1) | MY139562A (ja) |
| SG (1) | SG157220A1 (ja) |
| TW (1) | TWI253128B (ja) |
Families Citing this family (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN100452377C (zh) * | 2005-12-01 | 2009-01-14 | 联华电子股份有限公司 | 芯片与封装结构 |
| KR100713932B1 (ko) * | 2006-03-29 | 2007-05-07 | 주식회사 하이닉스반도체 | 플립 칩 본디드 패키지 |
| JP5075611B2 (ja) * | 2007-12-21 | 2012-11-21 | ローム株式会社 | 半導体装置 |
| KR101678054B1 (ko) | 2010-06-28 | 2016-11-22 | 삼성전자 주식회사 | 반도체 패키지 및 그 반도체 패키지 제조방법 |
| US10163828B2 (en) * | 2013-11-18 | 2018-12-25 | Taiwan Semiconductor Manufacturing Company Ltd. | Semiconductor device and fabricating method thereof |
| US9953954B2 (en) * | 2015-12-03 | 2018-04-24 | Mediatek Inc. | Wafer-level chip-scale package with redistribution layer |
| CN110767556A (zh) * | 2019-10-30 | 2020-02-07 | 华虹半导体(无锡)有限公司 | 智能卡芯片的加工方法及智能卡芯片 |
Family Cites Families (22)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6114756A (en) * | 1998-04-01 | 2000-09-05 | Micron Technology, Inc. | Interdigitated capacitor design for integrated circuit leadframes |
| JP3420703B2 (ja) * | 1998-07-16 | 2003-06-30 | 株式会社東芝 | 半導体装置の製造方法 |
| US6103552A (en) * | 1998-08-10 | 2000-08-15 | Lin; Mou-Shiung | Wafer scale packaging scheme |
| KR100269540B1 (ko) * | 1998-08-28 | 2000-10-16 | 윤종용 | 웨이퍼 상태에서의 칩 스케일 패키지 제조 방법 |
| JP4237325B2 (ja) * | 1999-03-11 | 2009-03-11 | 株式会社東芝 | 半導体素子およびその製造方法 |
| JP4024958B2 (ja) * | 1999-03-15 | 2007-12-19 | 株式会社ルネサステクノロジ | 半導体装置および半導体実装構造体 |
| EP1050905B1 (en) * | 1999-05-07 | 2017-06-21 | Shinko Electric Industries Co. Ltd. | Method of producing a semiconductor device with insulating layer |
| DE60022458T2 (de) * | 1999-06-15 | 2006-06-22 | Fujikura Ltd. | Halbleitergehäuse, halbleitervorrichtung, elektronikelement und herstellung eines halbleitergehäuses |
| JP2001144204A (ja) * | 1999-11-16 | 2001-05-25 | Nec Corp | 半導体装置及びその製造方法 |
| JP3386029B2 (ja) * | 2000-02-09 | 2003-03-10 | 日本電気株式会社 | フリップチップ型半導体装置及びその製造方法 |
| US6383858B1 (en) * | 2000-02-16 | 2002-05-07 | Agere Systems Guardian Corp. | Interdigitated capacitor structure for use in an integrated circuit |
| US6847066B2 (en) * | 2000-08-11 | 2005-01-25 | Oki Electric Industry Co., Ltd. | Semiconductor device |
| JP4394266B2 (ja) * | 2000-09-18 | 2010-01-06 | カシオ計算機株式会社 | 半導体装置および半導体装置の製造方法 |
| JP4183375B2 (ja) * | 2000-10-04 | 2008-11-19 | 沖電気工業株式会社 | 半導体装置及びその製造方法 |
| JP3842548B2 (ja) * | 2000-12-12 | 2006-11-08 | 富士通株式会社 | 半導体装置の製造方法及び半導体装置 |
| JP3767398B2 (ja) * | 2001-03-19 | 2006-04-19 | カシオ計算機株式会社 | 半導体装置およびその製造方法 |
| JP3939504B2 (ja) * | 2001-04-17 | 2007-07-04 | カシオ計算機株式会社 | 半導体装置並びにその製造方法および実装構造 |
| US6756184B2 (en) * | 2001-10-12 | 2004-06-29 | Taiwan Semiconductor Manufacturing Co., Ltd | Method of making tall flip chip bumps |
| JP3877150B2 (ja) * | 2002-01-28 | 2007-02-07 | 日本電気株式会社 | ウェーハレベル・チップスケール・パッケージの製造方法 |
| US6803303B1 (en) * | 2002-07-11 | 2004-10-12 | Micron Technology, Inc. | Method of fabricating semiconductor component having encapsulated, bonded, interconnect contacts |
| US6656827B1 (en) * | 2002-10-17 | 2003-12-02 | Taiwan Semiconductor Manufacturing Co., Ltd. | Electrical performance enhanced wafer level chip scale package with ground |
| US6841883B1 (en) * | 2003-03-31 | 2005-01-11 | Micron Technology, Inc. | Multi-dice chip scale semiconductor components and wafer level methods of fabrication |
-
2003
- 2003-09-18 JP JP2003325938A patent/JP4360873B2/ja not_active Expired - Fee Related
-
2004
- 2004-09-13 TW TW093127629A patent/TWI253128B/zh not_active IP Right Cessation
- 2004-09-14 KR KR1020040073293A patent/KR100742902B1/ko not_active Expired - Fee Related
- 2004-09-14 US US10/939,416 patent/US20050064624A1/en not_active Abandoned
- 2004-09-15 EP EP04255574A patent/EP1517369A3/en not_active Withdrawn
- 2004-09-17 MY MYPI20043805A patent/MY139562A/en unknown
- 2004-09-17 CN CNA2004100781750A patent/CN1604295A/zh active Pending
- 2004-09-17 SG SG200407966-1A patent/SG157220A1/en unknown
-
2008
- 2008-01-10 US US12/007,406 patent/US20080145973A1/en not_active Abandoned
Also Published As
| Publication number | Publication date |
|---|---|
| MY139562A (en) | 2009-10-30 |
| CN1604295A (zh) | 2005-04-06 |
| US20080145973A1 (en) | 2008-06-19 |
| SG157220A1 (en) | 2009-12-29 |
| TWI253128B (en) | 2006-04-11 |
| EP1517369A2 (en) | 2005-03-23 |
| KR20050028313A (ko) | 2005-03-22 |
| JP2005093772A (ja) | 2005-04-07 |
| KR100742902B1 (ko) | 2007-07-25 |
| TW200522227A (en) | 2005-07-01 |
| EP1517369A3 (en) | 2010-10-13 |
| US20050064624A1 (en) | 2005-03-24 |
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