JP4362079B2 - Multilayer chip capacitor and manufacturing method thereof - Google Patents

Description

  The present invention relates to a multilayer chip capacitor and a method for manufacturing the same.

  In general, a so-called multilayer chip capacitor is obtained by alternately laminating, for example, a Ni-containing paste constituting an internal electrode layer and a dielectric ceramic green sheet prepared in advance from a dielectric layer forming paste constituting a dielectric layer, Manufactured by firing. At the time of lamination, since the multilayer structure is required to increase the capacitance at the same volume, the internal electrode layer and the dielectric layer are required to be further thinned.

  When firing such a laminate, in general, since the dielectric layer forming material (ceramic material) having different firing temperatures and the internal electrode layer forming material (for example, Ni) are fired simultaneously, the firing temperature is directly set to the dielectric. Raised to the sintering temperature of the layer forming material.

  However, when the internal electrode layer forming material and the dielectric layer forming material are simultaneously fired by such a method, the internal electrode layer forming material having a lower firing temperature than the dielectric layer forming material has a high firing temperature. Sintering proceeds rapidly and excessively, and the internal electrodes are interrupted by so-called spheroidization. That is, a sheet body (internal electrode layer) in a so-called worm-eaten state in which numerous holes are formed everywhere in the layered body to be formed into a sheet shape is formed. Furthermore, it is said that the spheroidization of the internal electrode causes so-called delamination that causes the dielectric layer and the internal electrode layer to peel off.

  When such spheroidization occurs, the effective area (electrode coverage) of the internal electrode is lowered, and the capacitance of the capacitor is lowered. Therefore, at present, it is necessary to design a capacitor in anticipation of a decrease in effective area due to the interruption of the internal electrode. A reduction in the effective area of the internal electrode requires a number of layers sufficient to compensate for this, which hinders downsizing and an increase in capacitance.

  In order to deal with such a problem, Japanese Patent Application Laid-Open No. 11-354374 discloses the specification of the conductive paste when forming the internal electrode, the average of less than 1/2 of the average particle diameter of the metal powder and the metal particles. It has been proposed that the ceramic powder has a particle size of 2 to 40% by weight, and the conductive paste is fired to form an electrode. However, in this proposal, the electrodes and the dielectric layer are fired at normal conditions, that is, at a firing temperature of 1240 ° C. in a non-oxidizing atmosphere. Therefore, ceramic powder cannot remain in the internal electrode layer during firing or after firing, and the effect of sufficiently preventing a reduction in the effective area of the internal electrode cannot be exhibited. That is, in Patent Document 1, the ceramic powder in the internal electrode forming conductive paste is gradually discharged to the ceramic layer (dielectric layer) side during firing (paragraph [0022]).

  Japanese Patent Laid-Open No. 2000-2323202 uses particles for forming an internal electrode as a granular integrated product of nickel and titanate, and causes a difference in shrinkage due to sintering of the dielectric layer and the internal electrode. Proposals have been made. However, in this case as well, it can be said that the reduction of the electrode effective area cannot be sufficiently prevented under the usual firing conditions. In addition, an extra step for stably producing a granular integrated product of nickel and titanate is also required.

  In JP-A-11-124602 and JP-A-2002-348603, a dielectric layer is formed by shifting the sintering start temperature to a high temperature side by coating the periphery of the Ni metal particles with a high sintering temperature. There has been a proposal to suppress the spheroidization of the electrode close to the sintering temperature. However, in these proposals, although the sintering temperature of the internal electrode can be shifted to a high temperature, the material applied or added to the high temperature is transferred to the dielectric layer during the sintering of the dielectric layer. In particular, when the dielectric layer is thin, the composition of the dielectric layer changes and the original characteristics cannot be obtained. Even when the material applied or added to shift to a high temperature has the same composition as the dielectric layer, it diffuses to the dielectric layer side during the sintering of the dielectric, and the internal electrode layer loses its compactness. However, the problem that the internal electrodes are interrupted remains.

JP-A-11-354374 JP 2000-233202 A JP-A-11-124602 JP 2002-348603 A

  The present invention has been created under such circumstances, and its purpose is to prevent spheroidization during the formation of the internal electrode layer to prevent the internal electrode layer from being interrupted, that is, the effective area of the internal electrode. It is an object of the present invention to provide a multilayer chip capacitor that can prevent a decrease in the capacitance and obtain a high capacitance.

  In order to solve the above problems, the present inventors have conducted extensive research on the structure of the internal electrode and the firing conditions of the chip-like laminate in order to prevent spheroidization during the formation of the internal electrode layer. Only when the electrode structure can be realized, it can be confirmed that the spheroidization of the internal electrode layer is suppressed and the electrode coverage is remarkably improved, and the present invention has been achieved. Furthermore, it has been confirmed that the above-mentioned predetermined internal electrode structure is remarkably realized in the case of specific firing conditions, and the present invention has been achieved.

  That is, the present invention is a multilayer chip capacitor having an element body in which dielectric layers and internal electrode layers are alternately stacked, the internal electrode layer comprising a base metal internal electrode main layer and the internal electrode main layer. It is configured to have a composite structure having ceramic particles embedded in the layer.

  Moreover, as a preferable aspect of the present invention, the content ratio of the cross-sectional area display of the ceramic particles embedded in the internal electrode main layer is configured to be 1.0 to 20%.

  As a preferred embodiment of the present invention, the embedded ceramic particles have an average particle diameter of 2/3 or less (excluding zero) of the thickness of the internal electrode layer.

  The present invention also relates to a method of manufacturing a multilayer chip capacitor having an element body in which dielectric layers and internal electrode layers are alternately stacked, the method comprising: a dielectric layer for forming the dielectric layer A step of preparing a forming paste, a step of preparing an internal electrode forming paste for forming an internal electrode, and an intermediate form of an element body using the dielectric layer forming paste and the internal electrode forming paste A step of forming a chip-like laminate, and a firing step of firing the chip-like laminate, wherein the internal electrode forming paste comprises base metal particles for forming an internal electrode main layer acting as an electrode; And the ceramic particle is contained, and the firing step of the chip-shaped laminate is performed after the first firing step and the first firing step at a firing temperature of 200 to 1000 ° C., in the first firing step. Configured such that a second firing step to be fired at a temperature higher than the formation temperature.

  Moreover, as a preferable aspect of the present invention, the content of the ceramic particles in the internal electrode forming paste is configured to be 0.1 to 40 wt% in terms of solid content with respect to the solid content of the base metal.

  As a preferred embodiment of the present invention, the average particle diameter of the base metal particles contained in the internal electrode forming paste is 0.4 μm or less (excluding zero), and the average particle diameter of the ceramic particles is 0.1 μm. It is configured to be as follows (excluding zero).

  Further, as a preferred embodiment of the present invention, the first firing step is mainly performed for firing the internal electrode layer while confining the ceramic particles added to the internal electrode forming paste inside the internal electrode layer, The second firing step is mainly performed for firing the dielectric layer while the ceramic particles are confined in the internal electrode layer.

  As a preferred embodiment of the present invention, the first firing step is performed in a reducing atmosphere.

  The present invention relates to a multilayer chip capacitor having an element body in which dielectric layers and internal electrode layers are alternately stacked. The internal electrode layer includes a base metal internal electrode main layer, and the internal electrode main layer. Since it is configured to have a composite structure with ceramic particles embedded in the internal electrode layer, it prevents the internal electrode layer from being interrupted by spheroidization when forming the internal electrode layer, that is, suppresses a decrease in the effective electrode area And high capacitance can be obtained.

Embodiments of the present invention will be described below.
First, before describing the main part of the present invention, a schematic configuration of a general multilayer chip capacitor which is an object of the present invention will be described with reference to FIGS. FIG. 1 is a perspective view showing an embodiment of a multilayer chip capacitor, FIG. 2 is a cross-sectional view of the multilayer chip capacitor shown in FIG. 1, taken along line AA, and FIG. It is a perspective view for demonstrating clearly the formation process of.

  As shown in FIGS. 1 to 3, the multilayer chip capacitor 1 of the present invention includes an element body in which first internal electrode layers 23 and second internal electrode layers 28 are alternately stacked via dielectric layers 7. 2 and a pair of external electrodes 11 and 15 provided on opposing end surfaces of the element body 2. The element body 2 is usually a rectangular parallelepiped shape, but the shape is not particularly limited. Also, the dimensions of the element body 2 are not particularly limited and can be appropriately set according to the application. For example, (0.6 to 5.6 mm) × (0.3 to 5.0 mm) × (0.3 ˜2.5 mm).

  The internal electrode layers 23 and 28 in the present invention are composed of the first internal electrode layers 23 and the second internal electrode layers 28 that are alternately stacked via the dielectric layer 7 as described above. A preferred example for forming such a structure is shown in FIG. 3, according to which a sheet body 73 having a dielectric layer 7 and a first internal electrode layer 23, a dielectric layer 7 and a first layer. The sheet body 78 having the two internal electrode layers 28 is sequentially and repeatedly laminated in multiple layers.

  As shown in FIG. 3, the laminated first internal electrode layer 23 has a connection portion 23 a exposed to the first external electrode 11 side, and this connection portion 23 a is connected to the first external electrode 11. . As shown in FIG. 3, the first internal electrode layer 23 is exposed to the dielectric layer 7 so that the portion exposed from the outer peripheral frame of the dielectric layer 7 is only the connection portion 23a (more precisely, the end of the connection portion). Part only).

  On the other hand, the laminated second internal electrode layer 28 has a connection portion 28a exposed to the second external electrode 15 side as shown in FIG. 3, and this connection portion 28a is connected to the second external electrode 15. Has been. As shown in FIG. 3, the second internal electrode layer 28 is in a relationship with the dielectric layer 7 so that the portion exposed from the outer peripheral frame of the dielectric layer 7 is only the connection portion 28a (more precisely, the connection portion 28a End only).

  In the present invention, the first internal electrode layer 23 and the second internal electrode layer 28 may be collectively expressed simply as “internal electrode layers 23, 28”.

  The main part of the multilayer chip capacitor 1 of the present invention will be described with reference to the schematic sectional views of the internal electrode layers 23 and 28 in FIG. FIG. 4 is an enlarged schematic view of a part of the internal electrode layer in the cross-sectional view of FIG.

  In FIG. 4, the internal electrode layer 23 (28) of the present invention has a composite structure having a base metal internal electrode main layer 20 and ceramic particles 70 embedded in the internal electrode main layer. The internal electrode main layer 20 of the base metal is a main component that exhibits the essential function of the internal electrode layer, and occupies most of the solid content in the paste to be coated. In the paste, it is usually contained in the form of a base metal particulate.

  The content of the cross-sectional area display of the ceramic particles 70 embedded in the internal electrode main layer 20 is 1.0 to 20%, more preferably 1.5 to 18%, and still more preferably 2.0 to 10%. %. When this value is less than 1.0%, there arises a disadvantage that the effect of suppressing the spheroidization of the internal electrode layer such as Ni by the ceramic particles is not sufficiently exhibited. On the other hand, if this value exceeds 20%, the continuity of the internal electrode layer is lost, and there is a disadvantage that the effective area is reduced similarly to the interruption.

  The “content ratio of cross-sectional area display” as used in the present invention refers to a multilayer chip capacitor that is fractured on a plane perpendicular to the plane of the internal electrode layer, as will be described later, and the fractured surface is shown by a scanning electron microscope (SEM). The ratio of the ceramic particles embedded in the internal electrode layer is calculated as an area ratio from the image to obtain a content ratio (average value). In other words, this is a numerical value indicating what percentage of the total area of the ceramic particles observed in the predetermined cross section occupies the electrode area.

  In the present invention, the embedded ceramic particles have an average particle size of 2/3 or less (excluding zero) of the thickness of the internal electrode layer. If this value exceeds 2/3, the continuity of the internal electrode layer is lost, and there is a disadvantage that the effective area is reduced similarly to the interruption. The lower limit of this value is not zero, but the average particle size of the ceramic particles used may be very fine particles in Å units or nm units, and the numerical display of the lower limit is as close to zero as possible. Become. For example, if the lower limit value is forced, it is about 1/10000.

Hereinafter, the material of each constituent member constituting the multilayer chip capacitor 1 will be described.
[Internal electrode layers 23 and 28]
The internal electrode layers 23 and 28 in the present invention form a composite structure including the base metal internal electrode main layer 20 and the ceramic particles 70 embedded in the internal electrode main layer 20 as described above. Hereinafter, each member will be described.

Internal electrode main layer 20
It is composed of a base metal conductive material that substantially acts as an electrode. Specifically, Ni or Ni alloy is preferable. The Ni alloy is preferably an alloy of Ni and one or more of Mn, Cr, Co, Al, W, etc., and the Ni content in the alloy is preferably 95% by weight or more. Further, in Ni or Ni alloy, various trace components such as P, C, Nb, Fe, Cl, B, Li, Na, K, F, and S may be contained in an amount of 0.1% by weight or less. The average particle size in the state of being contained in the paste before firing is desirably 0.4 μm or less, and particularly 0.01 to 0.2 μm. This is because a more advanced thinning can be realized.

  The thickness of the internal electrode layer (internal electrode main layer) can be appropriately set according to the use of the multilayer chip capacitor, for example, about 0.5 to 5 μm, particularly about 0.5 to 2.5 μm. Can do.

Ceramic particles 70
The ceramic particles 70 are not particularly limited as long as the ceramic particles 70 have the effect of exhibiting the effects of the present invention. However, the ceramic particles 70 move to the dielectric layer side at a certain ratio during firing and are taken in. In view of this, it is preferable that the dielectric layer 7 is composed of the same material as the main material or an additive element.

  Specifically, a dielectric material used for the dielectric layer, for example, a titanium oxide-based, titanic acid-based composite oxide, or a mixture thereof can be used.

Examples of the titanium oxide include TiO ₂ containing NiO, CuO, Mn ₃ O ₄ , Al ₂ O ₃ , MgO, SiO _{2 and the} like in a total amount of about 0.001 to 30% by weight as necessary. .

In addition, examples of titanate-based complex oxides include barium titanate (BaTiO ₃ ). The atomic ratio of Ba / Ti is preferably in the range of 0.95 to 1.20. For barium titanate, MgO, CaO, Mn ₃ O ₄ , Y ₂ O ₃ , V ₂ O ₅ , ZnO, ZrO ₂ , Nb ₂ O ₅ , Cr ₂ O ₃ , Fe ₂ O ₃ , P ₂ O ₅ , SrO, Na ₂ O, K ₂ O, Li ₂ O, SiO ₂ , WO ₃ etc. are 0.001 to 30% by weight in total You may contain in the range of a grade.

  In addition, Ba, Ca, Sr, Ti, Zr, Mg, Mn, V, Y, Cr, Nb, Si, K, Na, Li, B, Sc, Hf, Al, W, lanthanoid series (La, Ce, Pr , Nd, Sm, Eu, Gd, Tb, Dy, Ho, Er, Tm, Yb, Lu) and the like, or ceramic particles made of one or a combination of two or more oxide compounds.

  The particle size of the ceramic particle is not particularly limited as long as it is a particle size that is completely embedded in the electrode layer, but the average particle size is 0.1 μm or less (including zero) so as to cope with thinning. Not). As described above, the average particle size of the ceramic particles used may be extremely fine particles in nm units, and the lower limit numerical value display is a value close to zero (for example, about 20 nm).

[Dielectric layer 7]
The dielectric material used for the dielectric layer constituting the multilayer chip capacitor 1 of the present invention is not particularly limited, and various dielectric materials can be used. For example, titanium oxide-based, titanic acid-based composite oxide, or a mixture thereof can be used.

Examples of the titanium oxide include TiO ₂ containing NiO, CuO, Mn ₃ O ₄ , Al ₂ O ₃ , MgO, SiO _{2 and the} like in a total amount of about 0.001 to 30% by weight as necessary. .

In addition, examples of titanate-based complex oxides include barium titanate (BaTiO ₃ ). The atomic ratio of Ba / Ti is preferably in the range of 0.95 to 1.20. For barium titanate, MgO, CaO, Mn ₃ O ₄ , Y ₂ O ₃ , V ₂ O ₅ , ZnO, ZrO ₂ , Nb ₂ O ₅ , Cr ₂ O ₃ , Fe ₂ O ₃ , P ₂ O ₅ , SrO, Na ₂ O, K ₂ O, Li ₂ O, SiO ₂ , WO ₃ etc. are 0.001 to 30% by weight in total You may contain in the range of a grade.

In addition, Ba, Ca, Sr, Ti, Zr, La, Mg, Mn, V, Y, Cr, Nb, Si, K, Na, Li, B, Sc, Hf, Al, Ce, Pr, Nd, Sm, One or a combination of two or more oxide compounds such as Eu, Gd, Tb, Dy, Ho, Er, Tm, Yb, Lu, and W can also be used as the dielectric material. For example, (Ca, Sr) (Ti, Zr) O ₃ (CaSr / TiZr ratio 0.6 to 1.2) can be mentioned. This may be Ba, La, Mg, Mn, V, Y, Cr, Nb, Si, K, Na, Li, B, Sc, Hf, Al, Ce, Pr, Nd, Sm, Eu, as required. Gd, Tb, Dy, Ho, Er, Tm, Yb, Lu, and W may be contained in a range of about 0.001 to 30% by weight.

For adjusting the firing temperature, linear expansion coefficient, etc., SiO ₂ or Ba, Ca, Sr, Ti, Zr, La, Mg, Mn, V, Y, Cr, Nb, Si, K, Na, Li, B , Sc, Hf, Al and a compound SiO ₂ glass may be contained.

  The thickness per layer of the dielectric layer is not particularly limited, but can be set to about 0.5 to 20 μm, for example. In addition, the number of laminated dielectric layers can usually be about 2 to 300.

[External electrodes 11, 15]
The external electrodes 11 and 15 constituting the composite electronic component of the present invention use at least one metal such as Pd, Ag, Au, Cu, Pt, Rh, Ru, Ir, or an alloy thereof as a conductive material. be able to. The thickness of the external electrode is not particularly limited, and can be, for example, about 1 to 100 μm, particularly about 5 to 50 μm.

  Further, the external electrode may contain glass for the purpose of improving the sinterability of the conductive material and ensuring the adhesion with the laminate.

Method for Manufacturing Multilayer Chip Capacitor Next, a method for manufacturing the multilayer chip capacitor of the present invention will be described.

  First, dielectric layers and internal electrode layers are alternately stacked by a normal printing method or a sheet method using a paste to form an element body prototype (stacked body). Next, external electrodes are formed by printing, transferring, pasting, dipping or the like on both end faces of the laminate on the external electrode side. Thereafter, the multilayer chip capacitor can be manufactured by firing. Details of each manufacturing process will be sequentially described as (1) to (5) below.

(1) Production of chip-like laminate (element body) When a so-called printing method is used, a dielectric layer forming paste and an internal electrode layer forming paste are sequentially laminated and printed on a support such as polyethylene terephthalate. At this time, the first internal electrode layer 11 and the second internal electrode layer 15 have a predetermined form with respect to the outer frame of the dielectric layer forming paste, as shown in FIGS. Printed on. After the dielectric layer and the internal electrode layer are sequentially laminated and printed, this is cut into a predetermined shape to form a chip, and then peeled off from the support to form a chip-shaped laminate (element element prototype). The

  When the so-called sheet method is used, a plurality of dielectric green sheets are formed using a dielectric layer forming paste. The internal electrode layer forming paste is applied on these green sheets to form sheet bodies 73 and 78 as shown in FIG. These are sequentially laminated, subjected to a predetermined heating / pressurizing operation, and then cut into a predetermined shape to form a chip-shaped multilayer body (element body prototype).

  The content of the ceramic particles in the internal electrode forming paste is 0.1 to 40 wt%, preferably 10 to 20 wt% in terms of solid content relative to the solid content of the base metal. If this value is less than 0.1 wt%, the contribution ratio to the composite structure will decrease. On the other hand, if it exceeds 40 wt%, the continuity of the electrode is lost, and there is a disadvantage that the effective electrode area as a capacitor is reduced.

  In the above process, an example of a composition of a paste that is generally used will be described below.

<Dielectric layer forming paste>
As the dielectric layer forming paste, a material obtained by kneading and dispersing a dielectric material and an organic vehicle is used.

  As the average particle size of the dielectric material, a powder having an average particle size of about 0.1 to 5 μm is usually used. The content of the dielectric material in the dielectric layer forming paste is usually about 30 to 80% by weight.

  The organic vehicle used for the dielectric layer forming paste is obtained by dissolving a binder in an organic solvent. As the binder, for example, known resin binders such as ethyl cellulose, a copolymer of polyvinyl butyral and methacrylic acid ester, and an acrylic acid ester-based copolymer are used. Moreover, organic solvents, such as terpineol, a butyl carbitol, acetone, toluene, are used as an organic solvent for melt | dissolving a binder. The content of such a binder or organic solvent in the dielectric layer forming paste is not particularly limited, but is usually about 1 to 5% by weight for the binder and about 10 to 50% by weight for the organic solvent.

<Internal electrode layer forming paste>
The internal electrode layer forming paste is prepared by kneading and dispersing the above-mentioned various conductive metals and alloys, ceramic particles, and the above organic vehicle.

(2) Debinder treatment step The chip-shaped laminate produced as described above is preferably subjected to a debinder treatment before firing. The conditions for this binder removal treatment can be set as appropriate in consideration of the materials used. For example, when a base metal such as Ni or Ni alloy is used for the conductive material of the internal electrode layer, it can be performed under the following conditions: Particularly preferred.

Debinder treatment condition heating rate: 5 to 300 ° C./hour, particularly 10 to 100 ° C./hour Holding temperature: 200 to 400 ° C., particularly 250 to 300 ° C.
Temperature holding time: 0.5-24 hours, especially 5-20 hours Atmosphere: in air

(3) Firing step The firing of the chip-shaped laminate in the present invention is carried out including at least two stages of firing patterns as shown below.

  That is, the chip-shaped laminate is fired at a firing temperature of 200 to 1000 ° C. (preferably 500 to 900 ° C., more preferably 600 to 800 ° C.) and after the first firing step. It has two firing steps. The firing temperature in the second firing step is set to a temperature higher than the firing temperature in the first firing step.

A suitable firing temperature in the second firing step varies depending on the type of the dielectric layer, for example,
(1) In the case where BaTiO ₃ or (Ba, Ca) (Ti, Zr) O ₃ is the main component, the second firing temperature is preferably set to 1100 to 1280 ° C.,
(2) In the case where (Ca, Sr) (Ti, Zr) O ₃ is the main component, the second firing temperature is preferably set to 1100 to 1400 ° C.

  The temperature holding time during firing is preferably 1 to 50 hours, particularly 2 to 24 hours in the first firing step. In the second baking step, 0.5 to 10 hours, particularly 1 to 4 hours are preferable.

  By performing the two-stage firing set in such a predetermined temperature range, a composite structure in which ceramic particles are embedded in the internal electrode (internal electrode main layer) can be formed. Thereby, generation | occurrence | production of the interruption of an internal electrode layer by the spheroidization at the time of internal electrode layer formation can be reduced markedly compared with the past.

The first baking step is preferably performed in a reducing atmosphere. Reducing atmosphere, for example, the N ₂ and 0.5～10Vol% of H ₂ gas mixture may be formed by flowing the water vapor. The oxygen partial pressure is preferably 10 ^-50 to 10 ^-5 Pa.

  If the first baking step and the second baking step are operatively distinguished, the first baking step is mainly added to the internal electrode forming paste in the first baking step. The internal electrode layer is fired and formed while confining the ceramic particles inside the internal electrode layer, and the second firing step is mainly for firing and forming the dielectric layer while confining the ceramic particles inside the internal electrode layer. It can be said that this is done.

(4) Annealing process When firing in a reducing atmosphere, it is preferable to anneal the fired laminate. Annealing is a process for re-oxidizing the dielectric layer, and this can significantly increase the accelerated life of the insulation resistance.

The oxygen partial pressure in the annealing atmosphere, 10 ^-9 Pa or more, it is preferable to particularly 10 ^-9 to 1 Pa. When the oxygen partial pressure is less than the above range, it is difficult to re-oxidize the dielectric layer, and when the oxygen partial pressure exceeds the above range, the internal electrode layer may be oxidized.

  The annealing holding temperature is preferably 1100 ° C. or lower, particularly 500 to 1100 ° C. When the holding temperature is less than 500 ° C., the reoxidation of the dielectric layer becomes insufficient, and the accelerated life of the insulation resistance is shortened. When the holding temperature exceeds 1100 ° C., the oxidation of the internal electrode layer proceeds and the capacitance is reduced. Instead, it reacts with the dielectric substrate and shortens the accelerated life.

Note that the annealing step may be composed of only temperature rise and temperature drop. In this case, it is not necessary to take a temperature holding time, and the holding temperature is synonymous with the maximum temperature. The temperature holding time is preferably 0 to 20 hours, particularly 2 to 10 hours. It is preferable to use N ₂ and humidified H ₂ gas as the atmospheric gas.

Incidentally, the binder removal process described above, firing, and, at each step of annealing, to wet the N _2, H ₂ or a mixed gas such as, for example, it can be used wetter like. In this case, the water temperature is preferably about 0 to 75 ° C.

  The steps of removing the binder, firing, and annealing may be performed continuously or independently. When these steps are carried out continuously, after removing the binder, the atmosphere is changed without cooling, followed by firing by sequentially raising the temperature to the two-stage firing holding temperature, and then cooling and annealing. It is preferable to perform annealing by changing the atmosphere when the holding temperature is reached.

  When these steps are performed independently, in the binder removal processing step, the temperature is raised to a predetermined holding temperature, held for a predetermined time, and then lowered to room temperature. At that time, the binder removal atmosphere is the same as in the case of continuous operation. Further, in the annealing step, the temperature is raised to a predetermined holding temperature, held for a predetermined time, and then lowered to room temperature. The annealing atmosphere at that time is the same as that in the case of performing continuously. Alternatively, the binder removal step and the firing step may be performed continuously and only the annealing step may be performed independently, or only the binder removal step may be performed independently and the firing step and the annealing step performed continuously. You may go.

(5) External electrode forming step The external electrode forming paste is printed or transferred onto the opposite end face sides of the chip-shaped laminate (element body prototype) produced as described above. Thereafter, firing is performed to form external electrode electrodes. Further, it can be formed by dipping and baking.

The firing conditions of the external electrode paste are preferably, for example, about 10 minutes to 1 hour at 600 to 800 ° C. in a reducing atmosphere such as a mixed gas of N ₂ and H ₂ .

<External electrode forming paste>
As the external electrode forming paste, at least one metal such as Pd, Ag, Au, Cu, Pt, Rh, Ru, Ir, or an alloy thereof is used as a conductive material, and the internal electrode layer paste described above is used. It is prepared in the same manner.

  The various pastes described above may contain additives selected from various dispersants, plasticizers, dielectrics, insulators, and the like as necessary. The total content of these is preferably 10% by weight or less.

  The multilayer chip capacitor of the present invention manufactured as described above is provided with a lead wire if necessary, and is mounted and used on a printed circuit board by soldering or the like.

  Hereinafter, the present invention will be described in more detail with reference to specific examples.

Example 1
Preparation of Dielectric Layer Forming Paste As a main material for the dielectric layer, ceramic powder containing BaTiO _{3 as a} main component having an average particle size of 0.2 μm was prepared. 10 wt% of PVB (polyvinyl butyral) resin as an organic binder and 5 wt% of DOP (dioctyl phthalate) as a plasticizer are weighed and added to the main raw material, and then ball milled. Kneaded to obtain slurry (dielectric layer forming paste).

Preparation of internal electrode layer forming paste Ni particles having an average particle diameter of 0.2 μm were prepared. 20 wt% of ceramic powder (ceramic particles having an average particle diameter of 0.05 μm) having the same composition as that used in the dielectric layer forming paste was added to the Ni particles. Further, 5 wt% of ethylcellulose resin and 35 wt% of tervineol were weighed and added to the mixed powder, and then kneaded with a ball mill to obtain an internal electrode layer forming paste.

Fabrication of chip-shaped laminate (element body prototype) Ceramic green sheet (dielectric material) having a thickness of 1.5 μm after drying by the doctor blade method using the dielectric layer forming slurry (paste). Green sheet) was prepared. On the ceramic green sheet, the above internal electrode layer forming paste was applied by screen printing to form an internal electrode layer pattern having a thickness of 1.8 μm.

Next, the ceramic green sheets on which the internal electrode layer pattern is not printed are stacked up to a thickness of 300 μm, and five ceramic sheets prepared by printing the internal electrode layer pattern in the above-described manner are stacked thereon. A ceramic green sheet on which no electrode pattern is printed is stacked to a thickness of 300 μm, heated and pressed under conditions of a temperature of 80 ° C. and a pressure of 1 ton / cm ² , and a size of 3.2 mm × 1.6 mm × 1.0 mm A chip-like laminate was obtained.

Debinding step and firing step Next, for the purpose of so-called debinding, the binder contained in the chip-like laminate was left for 8 hours at 250 ° C.

Thereafter, the two-stage firing (first and second firing steps) of the present invention was performed in a reducing atmosphere to obtain a multilayer chip capacitor having an internal electrode layer having a composite structure. The reducing atmosphere was obtained by passing a mixed gas of N ₂ and 5 vol% H ₂ through saturated steam at 30 ° C. The first firing step, which is mainly performed to confine ceramic particles (dielectric particles: common material) added to the internal electrode forming paste inside the internal electrode layer, has a firing temperature of 600 ° C. and a holding time of 2 hours. I did it. The second baking step performed after the first baking step was performed in the same reducing atmosphere at a baking temperature of 1240 ° C. and a holding time of 2 hours.

After such first and second firing steps, an annealing step for the purpose of reoxidation of the dielectric layer was performed. That is, a heat treatment at 1050 ° C. was performed in a reducing atmosphere obtained by passing N ₂ gas through water vapor.
A sample of Example 1 of the present invention was produced by such a procedure.

(Example 2)
The reducing atmosphere in the first firing step used in Example 1, a mixed gas of N ₂ and 5 vol% H _2, was changed to a mixed gas of N ₂ and 0.5 vol% H _2. Other than that was carried out similarly to the said Example 1, and produced the sample of Example 2 of this invention.

(Example 3)
The firing temperature in the first firing step used in Example 1 was changed from 600 ° C. to 800 ° C. Other than that was carried out similarly to the said Example 1, and produced the sample of Example 3 of this invention.

(Example 4)
The firing temperature in the first firing step used in Example 1 was changed from 600 ° C to 1000 ° C. Other than that was carried out similarly to the said Example 1, and produced the sample of Example 4 of this invention.

(Example 5)
The reducing atmosphere in the first firing step used in Example 1, a mixed gas of N ₂ and 5 vol% H _2, was changed to a mixed gas of N ₂ and 0.5 vol% H _2. Further, the firing temperature in the first firing step used in Example 1 was changed from 600 ° C. to 260 ° C., and the holding time was changed from 2 hours to 8 hours. Other than that was carried out similarly to the said Example 1, and produced the sample of Example 5 of this invention.

(Example 6)
The reducing atmosphere in the first firing step used in Example 1 was changed from a mixed gas of N ₂ and 5 vol% H ₂ to normal air. Further, the firing temperature in the first firing step used in Example 1 was changed from 600 ° C. to 260 ° C., and the holding time was changed from 2 hours to 8 hours. Other than that was carried out similarly to the said Example 1, and produced the sample of Example 6 of this invention.

(Example 7)
The ceramic powder in the internal electrode layer forming paste used in Example 1 was made of ceramic powder containing BaTiO _{3 as a} main component of the dielectric layer as a main component, and ZrO ₂ ceramic particles (average particle size 0.05 μm). Changed to. Other than that was carried out similarly to the said Example 1, and produced the sample of Example 7 of this invention.

(Example 8)
The ceramic powder in the internal electrode layer forming paste used in Example 1 is made of ceramic powder containing BaTiO _{3 as} the main ingredient of the dielectric layer as the main ingredient, and BaSiO ₃ ceramic particles (average particle size 0.05 μm). Changed to. Other than that was carried out similarly to the said Example 1, and produced the sample of Example 8 of this invention.

Example 9
The ceramic powder of the internal electrode layer forming paste used in Example 1, a ceramic powder and BaTiO ₃ main component, the main ingredient of the dielectric layer, Serammikku particles CaTiO ₃ (average particle diameter 0.05 .mu.m) Changed to. Other than that was carried out similarly to the said Example 1, and produced the sample of Example 9 of this invention.

(Example 10)
The content ratio of the ceramic powder in the internal electrode layer forming paste used in Example 1 was changed from 20 wt% to 5 wt%. Other than that was carried out similarly to the said Example 1, and produced the sample of Example 10 of this invention.

Example 11
The content ratio of the ceramic powder in the internal electrode layer forming paste used in Example 1 was changed from 20 wt% to 10 wt%. Other than that was carried out similarly to the said Example 1, and produced the sample of Example 11 of this invention.

Example 12
The content ratio of the ceramic powder in the internal electrode layer forming paste used in Example 1 was changed from 20 wt% to 15 wt%. Other than that was carried out similarly to the said Example 1, and produced the sample of Example 12 of this invention.

(Example 13)
The content ratio of the ceramic powder in the internal electrode layer forming paste used in Example 1 was changed from 20 wt% to 25 wt%. Other than that was carried out similarly to the said Example 1, and produced the sample of Example 13 of this invention.

(Example 14)
The holding time in the first baking step used in Example 1 was changed from 2 hours to 10 hours. Other than that was carried out similarly to the said Example 1, and produced the sample of Example 14 of this invention.

(Example 15)
The firing temperature in the first firing step used in Example 1 was changed from 600 ° C. to 700 ° C., and the holding time was changed from 2 hours to 20 hours. Further, the firing temperature in the second firing step was changed from 1240 ° C. to 1220 ° C. Other than that was carried out similarly to the said Example 1, and produced the sample of Example 15 of this invention.

(Example 16)
The holding time in the first baking step used in Example 1 was changed from 2 hours to 20 hours. Other than that was carried out similarly to the said Example 1, and produced the sample of Example 16 of this invention.

(Comparative Example 1)
The first baking step used in Example 1 was not omitted and only the second baking step was performed. Other than that was carried out similarly to the said Example 1, and produced the sample of the comparative example 1. FIG. This comparative sample is a sample corresponding to the above-mentioned Patent Document 1 (Japanese Patent Laid-Open No. 11-354374).

(Comparative Example 2)
The content ratio of the ceramic powder in the internal electrode layer forming paste used in Example 1 was changed from 20 wt% to 0 wt% (no addition). Other than that was carried out similarly to the said Example 1, and produced the sample of the comparative example 2. FIG.

(Comparative Example 3)
The firing temperature in the second firing step used in Example 1 was changed from 1240 ° C. to 1300 ° C. Other than that was carried out similarly to the said Example 1, and produced the sample of the comparative example 3. FIG.

(Comparative Example 4)
The firing temperature in the first firing step used in Example 1 was changed from 600 ° C. to 1080 ° C. Other than that was carried out similarly to the said Example 1, and produced the sample of the comparative example 4. FIG.

(Example 17)
The ceramic main component for forming the dielectric layer used in Example 1 was changed from a BaTiO ₃ material having an average particle size of 0.2 μm to a Ca _0.7 Sr _0.3 Ti _0.97 Zr _0.03 O ₃ material having an average particle size of 0.3 μm. The ceramic powder contained in the internal electrode layer forming paste was changed from ceramic powder mainly composed of BaTiO ₃ to ceramic particles of Ca _0.7 Sr _0.3 Ti _0.97 Zr _0.03 O ₃ (average particle diameter 0.03 μm). Further, the firing temperature in the second firing step was changed from 1240 ° C. to 1320 ° C. Otherwise, the sample of Example 17 was made in the same manner as in Example 1 above.

(Example 18)
The ceramic main component for forming the dielectric layer used in Example 1 was changed from a BaTiO ₃ material having an average particle size of 0.2 μm to a Ca _0.7 Sr _0.3 Ti _0.97 Zr _0.03 O ₃ material having an average particle size of 0.3 μm. Further, the firing temperature in the second firing step was changed from 1240 ° C. to 1320 ° C. Otherwise, the sample of Example 18 was made in the same manner as Example 1 above.

Example 19
The ceramic main component for forming the dielectric layer used in Example 1 was changed from a BaTiO ₃ material having an average particle size of 0.2 μm to a Ca _0.7 Sr _0.3 Ti _0.97 Zr _0.03 O ₃ material having an average particle size of 0.3 μm. The ceramic powder contained in the internal electrode layer forming paste is changed from ceramic powder mainly containing BaTiO ₃ (content 20 wt%) to MgTiO ₃ ceramic particles (content 10 wt%; average particle diameter 0.05 μm). It was. Further, the firing temperature in the second firing step was changed from 1240 ° C. to 1320 ° C. Otherwise, the sample of Example 19 was made in the same manner as Example 1 above.

(Example 20)
The ceramic main component for forming the dielectric layer used in Example 1 was changed from a BaTiO ₃ material having an average particle diameter of 0.2 μm to a Ba _0.97 Ca _0.03 Ti _0.8 Zr _0.2 O ₃ material having an average particle diameter of 0.3 μm. The ceramic powder contained in the internal electrode layer forming paste was changed from ceramic powder mainly composed of BaTiO ₃ to ceramic particles of Ba _0.97 Car _0.03 Ti _0.8 Zr _0.2 O ₃ (average particle diameter 0.05 μm). Furthermore, the firing conditions in the first firing step are a firing temperature of 600 ° C., a firing time of 2 hours, and a firing atmosphere of 3% H ₂ atmosphere, and the firing conditions in the second firing step are a firing temperature of 1260 ° C., a firing time of 2 hours, and firing. The atmosphere was 3% H ₂ atmosphere. Otherwise, the sample of Example 20 was made in the same manner as Example 1 above.

(Example 21)
The ceramic main component for forming the dielectric layer used in Example 1 was changed from a BaTiO ₃ material having an average particle diameter of 0.2 μm to a Ba _0.97 Ca _0.03 Ti _0.8 Zr _0.2 O ₃ material having an average particle diameter of 0.3 μm. Furthermore, the firing conditions in the first firing step are a firing temperature of 600 ° C., a firing time of 2 hours, and a firing atmosphere of 3% H _2, and the firing conditions in the second firing step are a firing temperature of 1260 ° C., a firing time of 2 hours, and firing. The atmosphere was 3% H ₂ atmosphere. Otherwise, the sample of Example 21 was produced in the same manner as in Example 1 above.

(Example 22)
The ceramic main component for forming the dielectric layer used in Example 1 was changed from a BaTiO ₃ material having an average particle diameter of 0.2 μm to a Ba _0.97 Ca _0.03 Ti _0.8 Zr _0.2 O ₃ material having an average particle diameter of 0.3 μm. The ceramic powder contained in the internal electrode layer forming paste was changed from ceramic powder containing BaTiO _{3 as a} main component to BaSiO ₃ ceramic particles (average particle size 0.05 μm). Furthermore, the firing conditions in the first firing step are a firing temperature of 600 ° C., a firing time of 2 hours, and a firing atmosphere of 3% H ₂ atmosphere, and the firing conditions in the second firing step are a firing temperature of 1260 ° C., a firing time of 2 hours, and firing. The atmosphere was 3% H ₂ atmosphere. Otherwise, the sample of Example 22 was made in the same manner as Example 1 above.

(Comparative Example 5)
In Example 20, the first firing step was omitted and only the second firing step was performed. Other than that was carried out similarly to the said Example 20, and produced the sample of the comparative example 5. FIG.

  About each said sample, (1) Content rate of the cross-sectional area display of the ceramic particle embed | buried in an internal electrode layer (2) Internal electrode coverage and (3) Capacitance were measured in the following way.

(1) The content ratio of the cross-sectional area display of the ceramic particles embedded in the internal electrode layer is broken at three points on a plane perpendicular to the plane of the internal electrode layer (5 layers per location are Each of the fracture surfaces can be magnified with a scanning electron microscope (SEM) at a magnification of 5000 times, and the ratio of the ceramic particles embedded in the internal electrode layer is calculated from the image as an area ratio and contained It was set as a ratio (average value).

(2) Internal electrode coverage ratio The ratio of the internal electrode layer existing on the fracture surface was calculated as the internal electrode coverage ratio X (%) from Equation 1. Ideally, the internal electrode layer should be continuous and have a predetermined set length L. However, in practice, the internal electrodes are interrupted by so-called spheroidization at a plurality of locations, and the total length ΣLi of the divided electrodes excluding the disconnected portions becomes the actual length value. If displayed in an easy-to-understand manner, (ΣLi / L) ² × 100 is the internal electrode coverage X (%).

To understand the application of Equation 1, see for example the model diagram in FIG.
When equation 1 is fitted to the model diagram of FIG. 5, ΣLi = L1 + L2 + L3 + L4 + L5, and N × L = 2L because there are two electrode layers. Therefore, X = ((L1 + L2 + L3 + L4 + L5) / 2L) ² × 100 is calculated.

(3) Capacitance capacitor The capacitance was measured with an LCR meter at 1 kHz and 1 Vrms.

  These results are shown in Table 1 below. The criteria for determining the internal electrode coverage in Table 1 are as follows.

Internal electrode coverage is 70% or more ... very good level far exceeding conventional examples Internal electrode coverage is 60% or more ... good level exceeding conventional examples Internal electrode coverage is less than 60% ... conventional level

  The present invention is applicable to industries related to multilayer chip capacitors and methods for manufacturing the same.

FIG. 1 is a perspective view showing an embodiment of a multilayer chip capacitor. FIG. 2 is a cross-sectional view of the multilayer chip capacitor shown in FIG. FIG. 3 is a perspective view for easily explaining the formation process of the laminated structure. FIG. 4 is an enlarged schematic view of a part of the internal electrode layer in the cross-sectional view of FIG. FIG. 5 is a model diagram for facilitating understanding of the application of Equation 1 for calculating the internal electrode coverage X (%).

Explanation of symbols

DESCRIPTION OF SYMBOLS 1 ... Multilayer chip capacitor 2 ... Element main body 7 ... Dielectric layer 11, 15 ... External electrode 20 ... Main internal electrode layer 23, 28 ... Internal electrode layer 70 ... Ceramic particle

Claims (6)

A multilayer chip capacitor having an element body in which dielectric layers and internal electrode layers are alternately laminated,
The internal electrode layer has a composite structure having a base metal internal electrode main layer and ceramic particles completely embedded in the internal electrode main layer,
The content ratio of the cross-sectional area display of the ceramic particles completely embedded in the internal electrode main layer is 1.13 to 20%,
A multilayer chip capacitor having an internal electrode coverage of 62% or more.   2. The multilayer chip capacitor according to claim 1, wherein an average particle diameter of the ceramic particles completely embedded in the internal electrode main layer is 2/3 or less (excluding zero) of the thickness of the internal electrode layer. . The method for manufacturing a multilayer chip capacitor according to claim 1, comprising an element body in which dielectric layers and internal electrode layers are alternately stacked.
The method
Preparing a dielectric layer forming paste for forming the dielectric layer;
Preparing an internal electrode forming paste for forming internal electrodes;
Using the dielectric layer forming paste and the internal electrode forming paste to form a chip-like laminate that is an intermediate form of the element body;
A firing step of firing the chip-shaped laminate,
The internal electrode forming paste contains base metal particles for forming an internal electrode main layer acting as an electrode, and ceramic particles,
The firing process of the chip-shaped laminated body is performed after the first firing process at a firing temperature of 600 to 800 ° C. performed in a reducing atmosphere and the first firing process, and is higher than the firing temperature in the first firing process. And a second firing step of firing at a firing temperature of 1220 to 1320 ° C., which is a high temperature.   4. The method of manufacturing a multilayer chip capacitor according to claim 3, wherein the content of the ceramic particles in the internal electrode forming paste is 0.1 to 40 wt% in terms of solid content relative to the solid content of the base metal.   The average particle size of the base metal particles contained in the internal electrode forming paste is 0.4 μm or less (excluding zero), and the average particle size of the ceramic particles is 0.1 μm or less (excluding zero). The method for manufacturing a multilayer chip capacitor according to claim 3 or 4.   The first firing step is mainly performed for firing the internal electrode layer while confining the ceramic particles added to the internal electrode forming paste inside the internal electrode layer, and the second firing step is mainly performed. 6. The method of manufacturing a multilayer chip capacitor according to claim 3, wherein the method is performed to form the dielectric layer by firing while confining the ceramic particles inside the internal electrode layer.

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