JP4363776B2 - Semiconductor device and manufacturing method thereof - Google Patents

Description

[0001]
BACKGROUND OF THE INVENTION
The present invention relates to a semiconductor device having connection contacts to a well and an impurity diffusion layer, and more particularly to a highly integrated semiconductor device in which the well and the impurity diffusion layer are set to the same potential and a method for manufacturing the same.
[0002]
[Prior art]
In semiconductor devices that are becoming highly integrated year by year, particularly in semiconductor memory devices, the number of memory cell elements has increased, and the area of the memory cell array has increased.
[0003]
Here, FIG. 14 shows a plan view of a conventional NOR type flash memory capable of electrical batch erasure. In the memory cell array, a large number of cell transistors are formed in a grid pattern. That is, a plurality of memory cell gates 50 are formed in parallel to each other in the left-right direction of FIG. A plurality of element isolation regions 3 are formed orthogonal to the memory cell gate 50.
[0004]
The semiconductor substrate 1 is exposed at a portion where the memory cell gate 50 and the element isolation region 3 are not formed. One of the source and drain is formed in contact with one side of the longitudinal surface of the memory cell gate 50 in FIG. 14, and the other of the source and drain is formed on the other side. Each source / drain is divided by an element isolation region.
[0005]
A drain connection electrode 12 is formed on each drain 11, and a potential is supplied to each drain 11.
[0006]
A source connection electrode 14 is formed on each source 13, and a potential is supplied to each source 13.
[0007]
Note that a cross section taken along the line “I-J” in FIG. 14 corresponds to FIG. Although FIG. 3 shows the structure around the drain 11, the structure around the source 13 on the “KL” line shown in FIG. 14 is the same as the structure shown in FIG. ing.
[0008]
As shown in FIG. 3, the drain 11 is formed between a pair of element isolation regions 3. A drain connection electrode 12 is formed in contact with a part of the drain 11 and above. The drain connection electrode 12 exists only in a part on the drain 11 sandwiched between the pair of element isolation regions.
[0009]
In the NOR type flash memory, in order to arrange the memory cells at high density, the source and drain contacts are shared for each adjacent memory cell, and the cell occupation area is reduced. Further, the well contact for applying a potential to the well is not in the cell array but in the outer periphery of the cell array. Thus, the source connection electrode and the drain connection electrode have the same shape.
[0010]
Next, the operation principle of the NOR type flash memory will be described. First, in the erase method, a positive potential Ve of about 10 V is applied to the drain, source, and well, a negative potential Vge of about −8 V is applied to the gate, and electrons in the floating gate are extracted to the channel side. By this operation, electrons in the floating gate are reduced, positive charges are apparently increased, and the threshold voltage of the cell transistor is lowered.
[0011]
Next, in the writing method, a ground potential Vgnd is applied to the source and well, a potential Vdp of about 5 V is applied to the drain, and a potential Vgp of about 8 V is applied to the gate. A current flows through the channel, and hot electrons generated by the current flow are injected into the floating gate. By this operation, electrons in the floating gate increase, and the threshold voltage of the cell transistor increases.
[0012]
Next, in the reading method, a ground potential Vgnd is applied to the source and the well, a potential Vdr of about 1 V is applied to the drain, and a potential Vgr of about 5 V is applied to the gate. In this state, since the threshold voltage of the cell transistor is lower than the gate voltage Vgr in the erased cell, a current flows from the drain to the source. In the written cell, since the threshold voltage of the cell transistor is higher than the gate voltage Vgr, no current flows from the drain to the source.
[0013]
Thus, the value of the cell can be determined based on the presence or absence of the drain current.
[0014]
[Problems to be solved by the invention]
The conventional method for manufacturing a semiconductor device as described above has the following problems.
[0015]
In a conventional semiconductor memory device, a well contact for applying a potential to a well is not in the memory cell array but on the outer periphery of the memory cell array.
[0016]
Since there is no contact for fixing the potential of the well in the cell array, it takes time until the potential at the center of the cell array is stabilized when the potential is applied to the well during erasing.
[0017]
In addition, since a relatively large current is allowed to flow through the drain at the time of writing, the well current increases, and the well potential at the center of the cell array tends to become unstable.
[0018]
In particular, in a semiconductor memory device that has been increased in scale, the distance from a memory cell array to a contact that supplies a potential to a well increases, and the above-described problem becomes remarkable.
[0019]
On the other hand, when well contacts are created in the cell array, the distance between the memory cells is increased, and a contact region is provided in the enlarged gap, thereby increasing the area of the cell array.
[0020]
An object of the present invention is to solve the above-described problems of the prior art.
[0021]
In particular, an object of the present invention is to provide a highly integrated semiconductor device and a method for manufacturing the same, in which the same potential can be applied to the well in units of applying a potential to the impurity diffusion layer, the well potential is stabilized. is there.
[0022]
[Means for Solving the Problems]
In order to achieve the above object, the present invention provides a semiconductor substrate, a first conductivity type well provided in the semiconductor substrate, a pair of element isolation regions provided in the well, and an upper portion of the well. A second conductivity type impurity diffusion layer provided between the pair of element isolation regions, a side surface of the impurity diffusion layer, a side surface of the well, and a side surface of the element isolation region; The semiconductor device includes a first connection electrode located deeper than a lower surface of the impurity diffusion layer, and a second connection electrode that is in contact with the upper surface of the impurity diffusion layer and separated from the first connection electrode.
[0024]
Furthermore, another feature of the present invention is that a step of forming a first conductive film on a semiconductor substrate having a first conductivity type well, and the first conductive film above a pair of element isolation region formation scheduled regions. Forming a resist on the first conductive film other than the first conductive film, and using the resist as a mask, a portion of the first conductive film where the resist is not formed above and a part of the well immediately below the first conductive film. A step of removing and forming an opening; a step of embedding an insulator in the removed first conductive film and the opening in the well to form an element isolation region; and an impurity diffusion layer forming region. Etching a side surface of the element isolation region to expose the side surface of the well; burying a conductor between the exposed side surface of the well and the side surface of the element isolation region; and forming a first connection electrode; Impurity diffusion A step of removing the first conductive film corresponding to the region to be formed, and a second portion having a bottom shallower than the bottom of the first connection electrode in the well corresponding to the region from which the first conductive film has been removed. Forming a conductive type impurity diffusion layer and connecting to the first connection electrode; and forming a second connection electrode in contact with the upper surface of the impurity diffusion layer and separated from the first connection electrode. A method for manufacturing a semiconductor device is provided.
[0026]
DETAILED DESCRIPTION OF THE INVENTION
Next, embodiments of the present invention will be described with reference to the drawings. In the following description of the drawings, the same or similar parts are denoted by the same or similar reference numerals. However, the drawings are schematic, and the relationship between the thickness and the planar dimensions, the ratio of the thickness of each layer, and the like are different from the actual ones. Accordingly, specific thicknesses and dimensions should be determined in consideration of the following description. Moreover, the part from which the relationship and ratio of a mutual dimension differ also in between drawings is contained.
[0027]
(First embodiment)
This embodiment will be described with reference to FIGS. FIG. 1 shows the structure of the connection electrode to the source and the connection electrode to the well in the present embodiment. As shown in FIG. 1, a well region 2 in which low-concentration impurities are diffused is formed on a semiconductor substrate 1.
[0028]
A source 4 is formed between the well region 2 and a pair of element isolation regions 3. The source 4 is a high-concentration impurity diffusion layer having a conductivity type opposite to that of the well 2.
[0029]
A source connection electrode 5 is formed so as to surround the periphery other than the lower surface of the source 4. An interlayer insulating film 6 is formed above the well 2 and on the element isolation region 3.
[0030]
The source connection electrode 5 is connected by a source line 7 to another source formed between other element isolation regions.
[0031]
In this way, the source connection electrode 5 is opened larger than the diffusion layer width of the source 4 and deeper than the diffusion layer depth of the source 4 so as to cover the element isolation region 3, thereby exposing the diffusion layer of the source 4 and the well 2. Thus, a metal or the like that is a conductor is embedded as a connection electrode, and a potential can be simultaneously applied to the source 4 and the well 2.
[0032]
FIG. 2 shows a top view of a part of the memory cell array region when the present embodiment is applied to a NOR type flash memory.
[0033]
In the memory cell array, a large number of cell transistors are formed in a grid pattern. That is, a plurality of memory cell gates 8 are formed in parallel to each other in the left-right direction of FIG. A plurality of element isolation regions 9 are formed orthogonal to the memory cell gate 8.
[0034]
The semiconductor substrate 10 is exposed at a portion where the memory cell gate 8 and the element isolation region 9 are not formed. One of the source and drain is formed in contact with one side of the longitudinal surface of the memory cell gate 8, and the other of the source and drain is formed on the other side. Each source / drain is divided by an element isolation region.
[0035]
A drain connection electrode 12 is formed on each drain 11, and a potential is supplied to each drain 11.
[0036]
A source connection electrode 14 is formed on each source 13, and a potential is supplied to each source 13.
[0037]
Note that a cross section taken along the line “AB” in FIG. 2 corresponds to FIG. That is, on the “A-B” line, the width of the element isolation region is narrower in the pair of element isolation regions 9 sandwiching the source 13 than the portion where the source connection electrode 14 is not formed. A source connection electrode 14 is formed.
[0038]
A cross section taken along the line “CD” in FIG. 2 corresponds to FIG. The drain 11 is formed between a pair of element isolation regions 3. A drain connection electrode 12 is formed in contact with a part of the drain 11 and above. Unlike the source 13, the shape of the element isolation region 13 in the drain 11 does not change around the drain connection electrode 12. That is, the drain connection electrode 12 exists only in a part on the drain 11 sandwiched between the pair of element isolation regions as shown in FIG.
[0039]
In FIG. 2, a cross section along the line “EF” is shown in FIG. In order to arrange the memory cells at high density, the memory 4 is highly integrated by reducing the area occupied by the memory cell by sharing the source 4 and the drain 11 and the connection electrodes 7 and 12 for each adjacent memory cell. It is a device.
[0040]
That is, the floating gate 18 is formed on the well 2 between the source 4 and the drain 11 via the tunnel oxide film 17. A control gate 20 is formed on the floating gate 18 via an interelectrode insulating film 19. Further, on the source connection electrode 7, a source wiring 21 that is linearly formed on the paper surface in FIG. 4 from the front side to the back side is connected.
[0041]
A drain lead wiring 23 is connected on the drain connection electrode 12 via a drain connection plug 22. On the drain lead wiring 23, a drain wiring 24 is formed linearly from the front to the back in the paper of FIG. 4 using a wiring layer above the source wiring 21.
[0042]
The manufacturing method of this embodiment will be described with reference to FIGS.
[0043]
The cross section shown in FIGS. 5 and 6 shows the manufacturing process in the cross section corresponding to FIG. As shown in FIG. 5, a well 2 is provided on a semiconductor substrate 1 made of silicon, and an element isolation region 3 for isolating each source and drain is formed. A source 4 and a drain 11 are formed in the well 2 between the element isolation regions 3. An interlayer insulating film 6 is formed on the well 2 and the element isolation region 3.
[0044]
Next, a photoresist 25 is applied over the entire surface of the interlayer insulating film 6 and then patterned except for the area above the drain 11 and the source 4 using a photomask. That is, a drain connection electrode opening 26 corresponding to the size of the connection electrode with the drain 11 manufactured in a later step is formed above the drain 11. In addition, a source connection electrode opening 27 corresponding to the size of the connection electrode with the source 4 manufactured in a later process is formed above the source 4.
[0045]
As shown in FIG. 6, using this photoresist 25 as a mask material, the interlayer insulating film 6 is removed by using a RIE (Reactive Ion Etching) method or the like. The interlayer insulating film 6 is selectively etched without etching the semiconductor substrate 1 by increasing the selection ratio at the time of RIE between the silicon which is the material of the semiconductor substrate 1 and the silicon oxide film which is the material of the interlayer insulating film 6. Can be removed.
[0046]
Here, in the source 4, when the element isolation region 3 is deeper than the diffusion layer depth of the source 4 and is etched by the RIE method so that the diffusion layer of the source 4 in the well 2 in the semiconductor substrate 1 is not lost, a semiconductor is obtained. The side surface of the substrate 1 and the surface and side surface of the diffusion layer of the source 4 are exposed.
[0047]
In the drain 11, an opening corresponding to the opening diameter of the drain connection electrode exposes the surface of the drain 11. That is, in the vicinity of the drain 11, the element isolation region 3 is not exposed from the interlayer insulating film 6.
[0048]
By burying metal or the like of the source and drain connection electrode wiring material in the opening in the interlayer insulating film 6 thus formed, connection electrodes connected to the drain 11, the source 4 and the well 2 can be formed. . In other words, a connection electrode to the well 2 below the source 4 that has not been formed conventionally can be formed in contact with the side surface of the well 2.
[0049]
Here, as the connection electrode, a titanium nitride thin film or tungsten can be used.
[0050]
Thereafter, a metal wiring layer, a surface protective layer, and the like are sequentially formed to form a semiconductor memory device.
[0051]
The element isolation region formation and the gate electrode formation in the cross section shown in FIG. 4 are formed in the conventional manner before the process shown in FIG.
[0052]
According to the present embodiment, a structure for fixing the potential of the well of the memory cell array of the flash memory can be produced in a large amount in the memory cell array. Therefore, even when the potential is applied to the well during the erase operation, But it can be stabilized in a short time. Further, the cell operation is stabilized, for example, the well potential is stabilized even when a relatively large current is supplied to the drain during the write operation.
[0053]
Even if a large number of well connection electrodes are formed in the source portion of the cell array, the area of the cell array does not increase because the source connection electrode is also used and only a part of the element isolation region is used.
[0054]
According to the present embodiment, a connection electrode to the well region can be provided for each source region without increasing the area of the source region sandwiched between the element isolation regions.
[0055]
In the NOR type flash memory, the source region is provided by half the number of transistors in the memory cell array of the semiconductor memory device, and if a connection electrode is provided for each source, the contact between the well and the connection electrode is provided. Even when the area is fine, contact with the well can be made by the number of sources.
[0056]
Therefore, a sufficient potential can be applied to the wells in the memory cell array, and the well potential can be stabilized. That is, in the flash memory, since the source and drain are shared by adjacent cell transistors, the number of sources is half the number of cell transistors.
[0057]
As described above, in this embodiment, connection electrodes to the wells are provided by the number of half of the number of cell transistors provided in the memory cell array, so that the well potential in the cell array can be stabilized.
[0058]
In particular, by applying this embodiment to a flash memory, the well potential can be stabilized at the time of writing, and the threshold value of the transistor to which data has been written can be accurately set and an accurate writing operation can be performed. Further, at the time of erasing, the potential of the memory well can be stabilized at an early stage, and the erasing operation can be speeded up.
[0059]
(Modification of the first embodiment)
As shown in the source connection electrode portion of the modification of the present embodiment in FIG. 7, the source connection electrode 30 serving also as the connection electrode with the well 2 is in contact with the source 4 only on one side of the element isolation region 3. Can also be provided. Even if such a configuration is used, the same effects as those of the first embodiment can be obtained.
[0060]
(Second Embodiment)
FIG. 8 shows a cross-sectional view of the source connection electrode of this embodiment. The shape of the drain connection electrode is the same as that of the first embodiment, and the plan view is the same as that of FIG. 14 which is a plan view of the prior art.
[0061]
As shown in FIG. 8, the well 2 is formed on the semiconductor substrate 1, and the source 4 is formed above the well 2. A pair of element isolation regions 31 are formed so as to sandwich the source 4.
[0062]
Here, the width of the upper portion of the element isolation region 31 is smaller than that of the bottom, and the side is formed obliquely with respect to the surface of the semiconductor substrate. A well connection electrode 32 is formed in contact with the side surface of the element isolation region 31.
[0063]
The well connection electrode 32 is formed deeper than the diffusion layer depth of the source 4 and is in contact with the well 2 and the source 4. A source connection electrode 33 is formed on the source 4 and applies a potential to the source 4. The source connection electrode 33 is formed in contact with only a part of the exposed surface of the source 4.
[0064]
Next, the manufacturing method of this embodiment will be described with reference to FIGS.
[0065]
As shown in FIG. 9, the well 2 is formed on the semiconductor substrate 1, and the gate oxide film 34 is formed on the well 2. A floating gate material 35 is formed on the gate oxide film 34. The floating gate material 35 can be made of polysilicon or the like.
[0066]
Next, a hard mask material 36 is formed on the floating gate material 35. As the hard mask material 36, for example, silicon nitride or the like can be used. A photoresist 37 is formed on the hard mask material 36. Note that in the case where the etching process can be performed using only the photoresist, a hard mask material is not particularly required.
[0067]
The formed photoresist 37 is patterned so as to provide an opening in an element isolation region formation scheduled region. At this time, a pattern is formed under the opening that tends to increase the etching rate of the film embedded in the recess formed in a later step.
[0068]
Etching is performed by the RIE method or the like using the patterned photoresist 37 as a mask. Using the photoresist as a mask, the hard mask material is processed by the RIE method or the like, and the resist is peeled off to form a hard mask pattern corresponding to the photoresist pattern.
[0069]
Thus, the hard mask material 36, the floating material 35, and the gate oxide film 34 under the photoresist opening are removed by performing etching by the RIE method or the like using the pattern of the hard mask material as a mask. Further, the well 2 on the semiconductor substrate 1 is also removed to form a recess 38.
[0070]
At this time, due to the characteristics of the HDP-CVD method, a film having a high wet etching rate is deposited on the side surface of the source formation scheduled region. The surface is flattened using a CMP (Chemical Vapor Deposition) method, and the hard mask material 36 is removed using wet etching.
[0071]
For example, silicon oxide is deposited on the entire surface of the semiconductor substrate 1 by using HDP-CVD (High Density Plasma Chemical Vapor Deposition) as a filling material for the element isolation region.
[0072]
Next, as shown in FIG. 11, after forming the element isolation region 39, the semiconductor substrate 1 on the side surface of the element isolation region 39 is exposed until it becomes deeper than the source diffusion layer (not shown). Wet etching is performed in order to remove the natural oxide film and the film having a high etching rate.
[0073]
Next, as shown in FIG. 12, an additional floating gate material 40 made of a polysilicon film doped with phosphorus, which is a gate material, is formed on the entire surface, and the polysilicon film 40 is formed on the exposed side surface of the element isolation region 39. Then, a connection electrode for simultaneously applying a potential to the source and the well is formed.
[0074]
The additional floating gate material 40 other than the memory cell gate formation region is removed, but the polysilicon film 40 buried between the element isolation region 39 and the semiconductor substrate 1 remains.
[0075]
Thereafter, the slit and the memory cell gate are processed to form a source, a drain, an interlayer insulating film, a metal wiring layer, a surface protective layer, and the like.
[0076]
Here, a plan view of the present embodiment is shown in FIG. A plurality of element isolation regions 39 are linearly arranged in parallel to each other. The well 2 on the semiconductor substrate 1 is exposed between the element isolation regions 39. A source 41 and a drain 11 are formed in the exposed well 2.
[0077]
In the source 41, the width of the element isolation region 39 is partially formed and is narrower than other regions. A plurality of memory cell gates 43 are linearly formed so as to be orthogonal to the element isolation region 39. Along the longitudinal surface of the memory cell gate 43, a source 41 is formed on one side, and a drain 11 is formed on the other side.
[0078]
The cross section on the “GH” line in FIG. 13 corresponds to FIG.
[0079]
This embodiment can have the same effects as those of the first embodiment.
[0080]
In the above embodiment, the structure in which the source and the well are set to the same potential has been described. However, the present invention can be applied to a semiconductor device in which the region other than the source and the well are set to the same potential.
[0081]
Although the NOR type flash memory has been described in the above embodiment, the present invention is not limited to the NOR type flash memory, but can be applied to other semiconductor devices in which the same potential as the impurity diffusion layer is applied to the well.
[0082]
【The invention's effect】
According to the present invention, the same potential can be applied to the well in a unit for applying a potential to the impurity diffusion layer, the well potential can be stabilized, and a highly integrated semiconductor device and a manufacturing method thereof can be provided.
[Brief description of the drawings]
1 is a cross-sectional view taken along the line “AB” in FIG. 2 showing the structure of a semiconductor device according to a first embodiment of the present invention;
FIG. 2 is a plan view showing the structure of the semiconductor device according to the first embodiment of the present invention.
3 is a cross-sectional view taken along the line “CD” in FIG. 2 showing the structure of the semiconductor device according to the first embodiment of the present invention;
4 is a cross-sectional view taken along the line “EF” in FIG. 2 showing the structure of the semiconductor device according to the first embodiment of the present invention;
FIG. 5 is a cross-sectional view showing a step of the method of manufacturing a semiconductor device according to the first embodiment of the present invention.
FIG. 6 is a cross-sectional view showing a step of the method of manufacturing a semiconductor device according to the first embodiment of the present invention.
FIG. 7 is a cross-sectional view showing the structure of a semiconductor device which is a modification of the first embodiment of the present invention.
FIG. 8 is a cross-sectional view taken along the line “GH” in FIG. 13 showing a second embodiment of the present invention.
FIG. 9 is a cross-sectional view showing a step of the method of manufacturing a semiconductor device according to the second embodiment of the present invention.
FIG. 10 is a cross-sectional view showing a step of the method of manufacturing a semiconductor device according to the second embodiment of the present invention.
FIG. 11 is a cross-sectional view showing a step of the method of manufacturing a semiconductor device according to the second embodiment of the present invention.
FIG. 12 is a cross-sectional view showing a step of the method of manufacturing a semiconductor device according to the second embodiment of the present invention.
FIG. 13 is a plan view showing a configuration of a semiconductor device according to a second embodiment of the present invention.
FIG. 14 is a plan view showing a structure of a conventional semiconductor device.
[Explanation of symbols]
1, 10, 42 Semiconductor substrate 2 Well 3, 9, 31, 39 Element isolation region 4, 13, 41 Source 5, 14, 33 Source connection electrode 6 Interlayer insulating film 7, 21, 30 Source wiring 8, 43 Memory cell gate 11 Drain 12 Drain connection electrodes 17 and 34 Gate oxide film 18 Floating gate 19 Interelectrode insulating film 20 Control gate 22 Drain connection electrode plug 23 Drain connection electrode connection wiring 24 Drain wiring 25 and 37 Photoresist 26 Drain opening 27 Source opening 32 Well connection electrode 35 Floating gate material 36 Hard mask material 38 Recess 40 Additional floating gate material

Claims (4)

A semiconductor substrate;
A first conductivity type well provided in the semiconductor substrate;
A pair of element isolation regions provided in the well;
An impurity diffusion layer of a second conductivity type provided between the pair of element isolation regions above the well; and
Side surface of the impurity diffusion layer, in contact with the side surface of the side and the isolation region of the well, a first connection electrode base portion is at a position deeper than the lower surface of the impurity diffusion layer,
Wherein the contact with the impurity diffusion layer top surface, and wherein a and a second connection electrode which is separated from the first connection electrode. The semiconductor device according to claim 1 , wherein the impurity diffusion layer is a source. The result impurity diffusion layer and the source, provided with a plurality, further comprising a plurality of drain and gate, forming a transistor, further comprising a memory cell array having a plurality of said transistors, said first and second 2. The semiconductor device according to claim 1 , wherein one connection electrode is provided for each source of each transistor in the memory cell array. Forming a first conductive film on a semiconductor substrate having a first conductivity type well;
Forming a resist on the first conductive film other than the first conductive film above the pair of element isolation region formation planned regions;
Using the resist as a mask, removing a portion of the first conductive film where the resist is not formed above and a part of the well immediately below the first conductive film, and forming an opening;
Embedding an insulator in the removed first conductive film and the opening in the well to form an element isolation region;
The side surface of the isolation region corresponding to the impurity diffusion layer forming region by etching, thereby exposing the sides of the pre Kiu el,
Burying a conductor between the exposed side surface of the well and the side surface of the element isolation region to form a first connection electrode ;
Removing the first conductive film corresponding to the impurity diffusion layer formation planned region;
A second conductivity type impurity diffusion layer having a bottom shallower than the bottom of the first connection electrode is formed in the well corresponding to the region from which the first conductive film has been removed , and is connected to the first connection electrode. a step of,
A method of manufacturing a semiconductor device , comprising the step of forming a second connection electrode in contact with the upper surface of the impurity diffusion layer and separated from the first connection electrode .

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