JP4365740B2 - Bit modeling processor - Google Patents

Description

  The present invention relates to an encoding processing device compliant with JPEG2000, and more particularly to a coefficient bit modeling processing unit in the same device.

  FIG. 9 (1) is a schematic flow diagram of the encoding process in JPEG2000.

  The image data is converted into coefficient data for each subband by the DC level shift / color conversion processing unit 102, the wavelet conversion unit 104, and the quantization unit 106, and is input to the coefficient bit modeling unit 108. The coefficient bit modeling unit 108 is used when the bit data is sequentially encoded by the subsequent MQ encoding unit 110 based on the coefficient data, and is encoded information extracted from the already encoded bit data. (Referred to as context) and bit data (referred to as decision) that is actually encoded is generated. Further, the MQ encoding unit 110 generates code data from the context and the decision, and finally the JPEG 2000 code is generated by the code forming unit 112.

  FIG. 9B is a diagram showing a data flow between the coefficient bit modeling unit 108 and the MQ encoder 110. The coefficient bit modeling unit 108 generates a context (CX) and a decision (D) from the input coefficient data, and the MQ encoder 110 generates code data (C) from them. FIG. 9 (3) is a diagram illustrating a data flow between the coefficient bit modeling unit 108 and the MQ decoder 111 during decoding. At the time of decoding, first, a decision (D) is generated from code data (C) input to the MQ decoder 111, and the coefficient bit modeling unit 108 constructs coefficient data from the decision, and at the same time, the MQ decoder 111 Generate the context (CX) used to generate the next decision.

  Next, a procedure for generating a context from the coefficient data in the coefficient bit modeling unit 108 (bit modeling procedure) will be described.

  The coefficient data in each subband is first divided into rectangular areas called code blocks that are encoded independently of each other. At this time, the coefficient data is represented by an absolute value and a sign (sign bit), and the accuracy of the absolute value is predetermined for each subband so that the quantization result does not overflow. The absolute value is divided into bit planes in the code block, and encoding is performed in order from the upper bit plane. When a bit plane in which all included bit data is 0 continues from the most significant bit, only the continuous bit plane (zero bit plane) is subjected to encoding in another system, and the first bit plane including 1 bit data Lower bit planes are subject to encoding using bit modeling.

  FIG. 6A is a conceptual diagram illustrating an example in which image data is converted into coefficient data for each subband by wavelet conversion. In this example, the image data is converted into coefficient data of 10 subbands from 3LL to 1HH by three-level wavelet transform.

  FIG. 6B is a diagram illustrating an example in which one subband is divided into a plurality of code blocks. In this example, the size of one code block is 32 × 32 (bits), and the subband in the figure is divided into 16 code blocks from 0 to 15. In this subband, the absolute value of the coefficient data is expressed with M-bit accuracy.

  FIG. 6 (3) is a conceptual diagram showing an example in which the coefficient data of the code block is divided into bit planes. In this example, the coefficient data of the code block is divided into M bit planes (from the MSB (Most Significant Bit) side to BP (M−1), BP (M−2),..., BP (0)). Each bit plane is composed of 32 × 32 bit data.

  FIG. 6 (4) is a diagram illustrating a state in which the bit planes in the code block are divided into a zero bit plane that continues from the top and a bit plane that is an encoding target using bit modeling. Here, BP (N−1) is a bit plane including 1 when viewed from the MSB side. Since all bit data of the bit planes from BP (M−1) to BP (N) are 0, the number (M−N) is encoded. Bit planes from BP (N-1) to BP (0) are to be encoded using bit modeling.

  Next, a bit modeling procedure performed for each bit plane will be described with an example of encoding processing.

  All coefficient data included in each code block is given a 1-bit variable called “significance state” which is 0 when encoding is started. In the process of encoding from the upper bit plane, the absolute value of each coefficient data is encoded bit by bit from the upper bits, but when 1 that is significant data is encoded first. Thus, the “significance state” of this coefficient also becomes 1, and thereafter 1 is held. In the following, coefficient data with “significance state” of 1 is expressed as a significant state, and coefficient data that remains 0 is expressed as an insignificant state. In addition, data outside the code block to be encoded is always handled as an insignificant state.

  First, the bit planes are scanned in a predetermined order to search for bits that meet a specific condition. If a bit satisfying the condition is found, a context is generated using the bit as a coding target bit, and encoding is performed. The search for the bit to be encoded, the context generation, and the encoding are repeated under the same conditions until the scanning of the bit plane is completed. Normally, at the time when one scan is finished, there are still uncoded bits in the bit plane. Therefore, the bit plane is scanned again. Next, the search is performed under different conditions. If there is a bit that satisfies the condition, context generation and encoding are performed using that bit as an encoding target bit. The process of one scan and search for the encoding target bit, generation of context, and encoding is called a pass, and encoding of all bits included in the bit plane is completed in a total of three passes.

  FIG. 7 shows the order in which the bit planes are scanned to search for bits to be encoded. The bit planes are divided into groups (columns) of 4 bits in each vertical direction from the upper left bits. The scan is performed from the upper bit to the lower bit in the group (column), and the group from the upper left to the lower right in the bit plane. This order is common to all paths.

  The first coding pass of each bit plane is referred to as a signature propagation pass (hereinafter referred to as an SP pass). In this pass, bits to be encoded are coefficient data bits that are insignificant at the time of search and at least one of the surrounding eight coefficient data is significant. Further, when the value of the target bit is 1, the sign bit of the coefficient data following that bit becomes the encoding target. The second path is called a Magnitude refinement path (hereinafter referred to as an MR path). In this pass, the bits of the coefficient data that are in a significant state and that are not to be encoded in the immediately preceding SP pass are encoded. The last path is called a Clean up path (hereinafter referred to as a CU path). In this pass, all bits that were not encoded in the immediately preceding SP pass and MR pass are encoded. In the CU pass, as in the SP pass, when 1 is encoded as bit data, the sign bit of the coefficient data is encoded.

  The context generated for the searched encoding target bit is different for each pass. In the SP pass, a context is generated based on the significance state of eight coefficient data around the encoding target bits, the sign data of the upper, lower, left, and right coefficient data including the bits to be encoded (neighbor context). FIGS. 10 (1) and 10 (2) show contexts generated by the SP path in coding of code blocks included in the LL subband and the LH subband. When X in FIG. 10 (1) is the bit to be encoded, the context is determined by the significance state of the eight coefficient data around it as shown in FIG. 10 (2). In FIG. 10 (2), ΣHi represents the sum of the significance state of the left and right coefficient data (H0, H1) of X. Similarly, ΣVi and ΣDi are the sum of the significance state of the coefficient data of upper and lower (V0, V1) and diagonal (D0, D1, D2, D3). The decision at this time is the bit data itself.

  FIGS. 11 (1) and 11 (2) show contexts that are generated when sign bits are encoded. In this case, a context is generated from four significance states and sign data of the coefficient data to be encoded. In addition, the decision in the case of encoding the sign bit is an EXOR (exclusive OR) of the XOR bit and the sign bit shown in FIG.

  In the MR pass, the context is determined based on whether or not the bit to be encoded is a bit (First refinement) encoded for the first time with the coefficient and the significance state of the surrounding coefficient data. FIG. 12 shows a context generated by the MR path. The decision in the MR pass is bit data itself.

The context generation in the CU path will be described. In the following cases (a) and (b), a single context called a run-length context is used.
(A) All four bit data included in one column of FIG. 7 are encoded by the CU pass.
(B) The eight significance states around each of the four bits are all zero.
At this time, if all four bit data of this column are 0, 0 is encoded as a decision, and the encoding of these 4 bits is completed. If even one of the four bits in this column is 1, 1 is encoded as a decision. Further, the position of the first bit among the four bits is represented by 2-bit data, and is encoded bit by bit in a single context called UNIFORM context. Thereafter, the sign bit of the first bit becomes 1 with reference to FIG.

  At this point, if there are still bits that are not encoded in this column, they are encoded bit by bit from the top (same as SP path) using the neighbor context. If the above condition (a) or (b) is not satisfied, or if the number of bits in one column is 3 or less, encoding is performed bit by bit using the neighbor context (same as the SP pass).

  A specific example of the coding process of bit modeling will be described with reference to FIGS. 8A, 8A, 8C, and 8D. These drawings show how one bit plane of a 3 × 4 size code block is encoded in three passes. This bit plane has 12 bits from a1 to c4, and the numbers 1 and 0 shown in each bit position represent bit data. In addition, bit data with a hatched background indicates that the coefficient data is already in a significant state. FIG. 8A shows the state of each bit data immediately before starting the encoding of this bit plane, and only a1 is significant at this point. In each pass, the bits to be encoded are searched by scanning in the order of column a, column b, column c, 1, 2, 3, 4 in each column.

  FIG. 8A shows the state of encoding in the SP pass. Since the first bit that is insignificant and at least one of the surrounding eight coefficients is significant is “a2”, this bit is encoded first in the SP pass. A neighbor context is generated from the significance state of the eight coefficient data around a2. Since the bit data of a2 is 1, the sign bit of a2 is next encoded. FIGS. 8A and 8A show the state of this bit plane when the encoding of a2 is completed. At this time, the significance state of a2 becomes 1, and thereafter, the coefficient data at this position is treated as a significant state (the bit data value is erased to indicate that this bit has already been encoded). Next, the bit to be encoded is the bit a3, but since the data is 0, even if this bit is encoded, this position remains insignificant. FIGS. 8A and 8B show the state of the bit plane when the bit a3 is encoded. Furthermore, encoding is performed in the order of b1, b2, and b3. 8 (a), (3), (4), and (5) show the state of the bit plane at the time when encoding of each bit is completed.

  It should be noted here that since only a1 was in a significant state at the time when encoding in the SP pass was started, the condition to be encoded at that time is satisfied. Is only the surrounding a2, b1, and b2, but since this bit became significant when the processing of a2 was completed, a3 and b3 were added to the encoding target in the SP pass, and the following The target bit is a3. That is, in the SP pass, every time a bit is processed, the number of bits to be encoded increases and the processing order may change.

  Next, encoding is performed in the MR pass. At the end of the SP pass (FIGS. 8 (a) and (5)), it is only a1 that is in a significant state and has not been encoded in the immediately preceding SP pass, and only this bit in the MR pass. Are subject to encoding. The state of the bit plane at the end of encoding in the MR pass is shown in FIG.

  Finally, encoding in the CU pass is performed. In this pass, six bits not encoded in the previous SP pass and MR pass are to be encoded. First, a4 is the first bit to be encoded, and the context at this time is generated from the significance state of the surrounding eight coefficient data (neighbor context). Since the bit data is 1, the sign bit a4 is next encoded. The encoding of b4 is also performed using the neighbor context. The state of the bit plane at the time when the encoding of the two bit data a4 and b4 is completed is shown in FIGS. 8 (D), (1), and (2). Since the value of a4 is 1, a4 has changed to a significant state in FIGS. Next, the bits from c1 are encoded, but the c sequence (c1, c2, c3, c4) satisfies the conditions (a) and (b) related to the above-mentioned run length, so that 4 bits are encoded together. A run-length context is generated. If all the c columns are 0, the decision at this time is set to 0 and the encoding of this code block is completed. However, since the c3 bit is 1, the decision is encoded as 1, and subsequently, there is 1 in the 3rd bit. The information “10” is encoded bit by bit using the UNIFORM context. Further, the c3 bit sign bit and the c4 bit are encoded using the neighbor context, and the encoding process of this code block ends.

  Also in the CU pass, as in the SP pass, the context of subsequent bits varies depending on the value of the bit currently being processed. For example, if the value of the b4 bit is 1, this coefficient data is in a significant state after processing, so the c column does not satisfy the condition (b) described above, and is encoded using the neighbor context in order from c1. Will be.

  The bit modeling procedure has been described above by taking the encoding process as an example. Similarly, the decoding process is performed by a procedure of scanning in three passes of a bit plane, searching for a decoding target bit, and generating a context. However, unlike encoding, since the decision is determined from the code data using the context generated by the MQ decoder, the coefficient modeling unit receives the result and constructs the coefficient data. In particular, in the SP pass and CU pass, the next decoding target bit and context change depending on the decoding result, so it is necessary to wait for the MQ decoder to generate a decision before performing the next decoding process.

  Next, a conventional example of a bit modeling apparatus that performs encoding processing and decoding processing will be described.

  As described above, in determining whether a certain bit is a processing target in the path, the significance state of the coefficient of the position and the surrounding eight (the position) is used. By the way, in the MR pass and CU pass, it is necessary to select bits that were not processed in the previous SP pass. For this reason, in the encoding and decoding processes, information on whether or not processing has been performed in the SP pass is required in addition to the signature state.

  In the conventional example described here, a variable “pass bit” is assigned to one coefficient data of a code block in addition to the significance state, and a bit to be encoded or decoded using these two variables. Explore. The meaning of “pass bit” varies depending on the combination with the significance state. That is, when the coefficient is insignificant, if the pass bit is 1, it indicates that the processing target is the previous SP pass. When the coefficient is significant, if the pass bit is 1, it indicates that the coefficient has already been significant at the start of processing of this bit plane, and therefore has not been processed in the immediately preceding SP pass.

  FIGS. 13 (1) and 13 (2) show a combination of a signature state (hereinafter referred to as ss) to be processed in each path and a pass bit (hereinafter referred to as ps), and the bit. The values (new ss, new ps) of the significance state (ss) and the pass bit (ps) that are updated after the update are shown.

  In the SP pass, if (ss, ps) = (1, x), the coefficient is already significant and no processing is performed, but to indicate that it has already become significant in the previous bit plane ( new ss, new ps) = (1, 1). When (ss, ps) = (0, 0), if any of the surrounding eight coefficients has a significance state of 1 (nei = 1), the bit is processed, and the value of the bit is 1 (decision) , D = 1), (new ss, new ps) = (1, 0), and 0 (D = 0), (new ss, new ps) = (0, 1). In the case of (ss, ps) = (0, 1), it indicates that the previous bit plane has already been processed by the SP path, so the processing is unconditional, and the value of the bit is 1 (decision) , D = 1), it is updated to (new ss, new ps) = (1, 0).

  In the MR pass, only the bits of the coefficient (ss, ps) = (1, 1) are processed.

  In the CU pass, if the bit of the coefficient (ss, ps) = (0, 0) is processed and the value of the bit is 1 (decision, D = 1), (new ss, new ps) = (1 Update to 1).

  The entire code block is divided into 4 × 4 rectangular sub-blocks including four coefficients in the vertical direction and processed. FIG. 14A shows a state where a 16 × 16 code block is divided into 4 × 4 sub-blocks. In this case, 0, 1, 2,..., 15 sub-blocks are processed in order. In order to determine which bit data is to be processed by which path and to generate an appropriate context for the bit data included in the sub-block area, the signifi- cant sign and sign of the area larger than the sub-block one by one up, down, left, and right Bit information is required. That is, for the 4 × 4 sub-block, those pieces of information in the 6 × 6 area shown in FIG. 14 (2) are required.

  FIG. 15 shows an example of the coded bit modeling device 108. In this example, it is assumed that the code block is divided into 4 × 4 subcode blocks and processed as shown in FIG.

  At the time of encoding, the coefficient data converted by the wavelet transformer 104 and the quantizer 106 is divided into absolute values and sign bits and stored in the coefficient absolute value storage memory 58 and the sign bit storage memory 56 for each code block. Is done. The ss flag storage memory 52 and the ps flag storage memory 54 store the significance state and pass bit of the coefficient included in the code block.

  At that time, the coefficient absolute value data and the ps flag are stored in one address area in units of 4 × 4 sub-blocks, but the sign bit and the ss flag are stored so that a 6 × 6 area can be read. This can be realized, for example, by storing data separately in the two memories A and B as shown in FIG. In FIG. 16A, A0 is data stored in the address 0 area of the memory A, A1 is data stored in the address 1 area of the memory A,..., B0 is the address 0 of the memory B. Data stored in the area, B1 indicates data stored in the area of address 1 of the memory B,. In this way, by storing the read data from each memory in a three-stage register whose output is the next stage input as shown in FIG. It becomes possible to read out data in a 6 × 6 area using. FIG. 16B shows a state in which 6 × 6 area data necessary for processing the sub-block “5” in FIG. 14B is input to the register.

  Among the data stored in the memory, the corresponding 4 × 4 area bit data and the ps flag are stored in the 4 × 4 area registers 68 and 64, and the 6 × 6 area sign bit and ss flag necessary for the processing are stored. After reading into the 6 × 6 area registers 66 and 62, the bit modeling processing unit 2 determines the bits to be encoded by the SP pass, MR pass, and CU pass, generates the context decision, and updates the ss flag and the ps flag. To code the code block.

  FIG. 17 is a block diagram of the bit modeling processing unit 2.

  The path counter 16 is a ternary counter, and indicates whether the path currently being processed in processing a bit plane is an SP path, an MR path, or a CU path. Increments to indicate the next pass. pass_init is an initialization signal of the counter 16, and pass_increment is an increment signal.

  The address generation unit 14 reads the data in the 4 × 4 area and 6 × 6 area to be processed from the coefficient absolute value storage memory 58, the sign bit storage memory 56, the ss flag storage memory 52, and the ps flag storage memory 54. Is incremented each time processing of the area is completed. add_init is an address initialization signal, and add_increment is an address increment signal.

  The path determination unit 4 determines whether each of the 16 bits in the 4 × 4 sub-block is a processing target bit in the current path or not based on the ss flag and the ps flag and outputs the result.

  The context decision generation unit 10 generates context and decision data as shown in FIGS. 10, 11, and 12 for each of 16 bits of the 4 × 4 sub-block using the ss flag and the sign bit. To do.

  The ss and ps flag updating unit 12 generates the ss flag and the updated value of the ps flag (new ss, new ps) at the bit position (NXT_BIT) that is the processing target based on the logic shown in FIG. 13, and the update signal is input. Then, the value of the 6 × 6 area register 62 and 4 × 4 area register 64 storing the respective data is updated.

  FIG. 18A is a detailed block diagram of the path determination unit 4. The SP path processing extraction unit 72, the MR path processing extraction unit 74, and the CU path processing extraction unit 76 determine whether 16 bits satisfy the condition of FIG. 13 (2) to be processed in each path. As a result, 16-bit data INP_SP, INP_MR, and INP_CU are output. Each output is 1 if each bit satisfies the condition to be processed, and 0 if not.

The bit positions of the 4 × 4 area and the 6 × 6 area are indicated by numbers and symbols shown in FIGS. 18 (2) and 18 (3). In the SP pass, a bit whose significance state is 0 and whose signifi- cant state is one of the eight neighboring coefficients is a processing target.
INP_SP (N) = (SS (N) == 0) && (nei (N)> 0), (0 ≦ N ≦ 15)
It becomes. Here, “nei (N)” is the total value of the significance state of the surrounding 8 data at the bit position N. For example,
nei (0) = SS (c0) + SS (l0) + SS (l1) + SS (t0) +
SS (1) + SS (t1) + SS (4) + SS (5)
nei (5) = SS (0) + SS (1) + SS (2) + SS (4) + SS (6)
+ SS (8) + SS (9) + SS (10)
It becomes.

In the MR pass, the bits for which the signature state and the pass bit are both 1 are processed, and in the CU pass, the bits for which the signature state and the pass bit are both 0 are processed.
INP_MR (N) = (SS (N) == 1) && (PS (N) == 1), (0 ≦ N ≦ 15)
INP_CU (N) = (SS (N) == 0) && (PS (N) == 0), (0 ≦ N ≦ 15)
It becomes. From these three outputs, the data corresponding to the currently processed path is selected by the path count value of the path counter 16 and output as 16-bit INP.

The INP value output from the path determination unit 4 is input to the mask logic unit 6. The mask logic unit 6 calculates the logical sum of each bit of the MSK value and the INP value input from the mask register 8 as follows and outputs the result as an MSK_INP value.
MSK_INP (N) = INP (N) & MSK (N), (0 ≦ N ≦ 15)

The above MSK value is 0 for the data of the bit position searched for in the 4 × 4 area before the bit processed immediately before, and 1 for the other positions. That is,
MSK (N) = 0, (0 ≦ N ≦ M)
MSK (N) = 1, (M <N ≦ 15)
(M is the position of the bit processed immediately before in the same 4 × 4 area)
It becomes. As a result, MSK_INP is searched sequentially from bit position 0 shown in FIG. 18 (2), and the bit that is first becomes the next bit to be processed in the current pass. This is realized by the processing bit determination unit 18 in the next stage.

FIG. 19 is a detailed block diagram of the processing bit determination unit 18. As described above, the input MSK_INP is input to the priority encoder 84 and converted into bit position information to be processed next, NXT_BIT. The logic at this time is
if (MSK_INP [0] == 1) NXT_BIT = 0
else if (MSK_INP [1] == 1) NXT_BIT = 1
else if (MSK_INP [2] == 1) NXT_BIT = 2
else if (MSK_INP [3] == 1) NXT_BIT = 3
・
・
else if (MSK_INP [15] == 1) NXT_BIT = 15
It becomes. When MSK_INP is all 0, this indicates that there is no bit to be processed in the current pass in the 4 × 4 area, and the BLK_END output is 1 at this time.

  The mask register 8 creates MSK data in which the bit position data searched before the position selected by NXT_BIT is 0, and 1 otherwise.

  The selection / control unit 20 is a block that controls the entire bit modeling processing unit 2 and simultaneously selects the final context and decision from the current path (pass count value) and bit position (NXT_BIT).

  FIG. 20 is a schematic flowchart regarding control of selection of context and decision in the selection / control unit 20.

  After starting the coding of the code block (S00), the address and pass count value are initialized (S02), the first 4 × 4 area ps flag, bit data, 6 × 6 area ss flag, sign bit data Are loaded into the registers (S04). If there is a bit to be processed in the 4 × 4 area (BLK_END = 0), an appropriate context and decision are determined based on the pass count value and the value of NXT_BIT from the plurality of contexts and decisions generated by the context decision generation unit 10. Select and output. At the same time, enable (EN) is set to 1 to allow the MQ encoder 110 to perform encoding (S08). Next, (next ss, next ps) shown in FIG. 13B is generated and the ps flag loaded in the 4 × 4 area register 64 and the ss flag loaded in the 6 × 6 area register 62 are updated. (S10). Further, the processing target bit is searched using the updated ps flag and ss flag, and the same flow is repeated. When the processing of the 4 × 4 area ends (BLK_END = 1), the ps flag loaded in the 4 × 4 area register 64 and the ss flag loaded in the 6 × 6 area register 62 are stored in the respective storage memories ( First, the data is written in the same address area where the reading is performed (S12). It is determined whether or not the processed 4 × 4 area is the last sub-block of the code block (S14). If not, the address is incremented (S18) and the next 4 × 4 area is processed. After the ps flag, bit data, ss flag, and sign bit data for loading are loaded into the register (S04), the sub-block is processed. If it is determined in S14 that it is the last sub-block, it is determined whether the processed path is the last path of the code block (S22). If there are still paths to be processed, the pass count value is incremented. The address is initialized (S24) and a new pass is encoded. If it is the last pass, the process is terminated (S34).

  FIG. 21 shows one example of a decoded bit modeling apparatus. A significant difference from the encoded bit modeling apparatus shown in FIG. 15 is that the decision (D) is output as a result of decoding the code by the MQ decoder 111 instead of the bit modeling processing unit 2. After the bit modeling processing unit 2 generates bit data and a sign bit from this decision, writing to each area register / memory is performed and converted into image data through inverse quantization and wavelet inverse transformation. Here, since the sign bit is used to generate a context, the sign bit storage memory 56 loads the 6 × 6 area register 66. FIG. 22 shows a block diagram of the bit modeling processing unit 2 for realizing the above. Compared to FIG. 17, a bit data, a sign bit for generating a sign bit, and a bit data generation unit 46 are added from the decision.

  In the above conventional technology, in the encoding / decoding processing of a subblock divided into units for processing a code block, the ss flag and ps flag of the subblock are once loaded regardless of the presence / absence of the processing target bit in the current pass. After that, since the presence / absence of the processing target bit is determined, there is a problem that it takes extra time.

The invention according to Patent Document 1 provides a method and apparatus for encoding and decoding information. That is, the apparatus of the present invention includes a memory and decoding hardware. The memory maintains run counts and / or skip counts, and decoding hardware decodes the run counts and / or skip counts obtained from the memory during decoding. The invention according to Patent Document 2 is a bit modeling processing method with a high processing speed and a processing circuit using the same. In other words, the processing method and processing circuit according to the present invention simultaneously generate a bit to be processed and a context and a decision that change according to the state of the significant flag and the state of the sign bit of the surrounding bit group through the sig path. The sign bit context and decision are adopted only when the value of the bit to be processed is 1, updates the significance flag, is abolished when the value of the bit to be processed is 0, and the bit to be processed Regardless of whether the value is 1 or 0, a bit modeling processing circuit that updates the processed flag is simultaneously applied to the bits of the same group and processed in parallel.
JP 2003-8445 A JP 2003-8906 JP

  An object of the present invention is to efficiently perform encoding / decoding processing of a sub-block obtained by dividing a code block in a coefficient bit modeling unit of an encoding / decoding processing device compliant with JPEG2000.

The present invention has been made to achieve the above object. The bit modeling processing device according to claim 1 according to the present invention includes:
In a JPEG2000 bit modeling processing apparatus that searches for and encodes or decodes a processing target bit in a pass processed in units of sub-blocks in which a code block is divided into a plurality of blocks
During processing of Shigunifikanto propagation (Significance propagation) paths for one sub-block,
It generates and stores a subsequent magnitude refinement (Magnitude refinement) path or whether the information processed bits cleanup (Clean Stay up-) path exists which is carried out in at its sub-blocks,
When the information indicating whether or not the processing target bit exists is data indicating the presence, when a magnitude refinement (Cleanup) pass process or a cleanup pass process is performed correspondingly, Information indicating whether or not the processing target bit exists in the sub-block is changed to data indicating that it does not exist,
In the magnitude refinement pass or clean up pass processing in one code block, there is no information on whether or not the processing target bit exists for all the sub blocks of the code block. When the data indicates that, the pass processing in the code block is terminated .

The encoding / decoding processing device according to claim 2 according to the present invention includes:
A JPEG2000 encoding / decoding processing apparatus including the bit modeling processing apparatus according to claim 1 .

  By using the present invention, the following effects can be obtained.

  Since only sub-blocks in which bits to be processed exist in the MR pass and CU pass can be selected and processed, JPEG 2000 encoding and decoding processing can be performed at high speed. In addition, if there is no bit to be processed in the MR path and CU path, the next path can be processed without performing the process for that path, so that higher speed processing can be performed.

  The present invention makes use of the fact that the bit to be processed in the immediately following MR pass or CU pass becomes clear when performing processing in the SP pass, so that each sub-block is processed in the MR pass or CU pass. Information indicating whether there is a bit to be processed is generated at the time of the SP pass processing, and only the sub-block including the processing target bit is selected and processed at the time of the MR pass or CU pass processing. This speeds up processing.

  Hereinafter, preferred embodiments of the present invention will be described with reference to the drawings.

  FIG. 1 is a block diagram of a bit modeling processing unit 2 for encoding processing according to a preferred embodiment of the present invention. Compared to the conventional example (see FIG. 17), an MR path address generation unit 22 and a CU path address generation unit 24 are added.

  These blocks use the ss flag and ps flag that are updated during processing in the SP path to determine whether the processing target bit in the next MR path or CU path is included in the sub-block being processed, Information related to the determination is stored. Further, these blocks sequentially use the information during the MR pass and CU pass processing, and generate and output addresses (MR_ADD, CU_ADD) so that only the sub-block including the processing target bit is processed. Furthermore, these blocks also output signals (MR_NOPASS, CU_NOPASS) indicating that there is no bit to be processed in those paths.

  When the MR path or the CU path is processed, the selection / control unit 20 controls to load the MR_ADD or CU_ADD into the address generation unit 14 instead of incrementing the address. Further, when starting the processing of each path, the selection / control unit 20 determines that there is no bit to be processed in the path if MR_NOPASS or CU_NOPASS is output, and does not perform the encoding process. The pass count value of 16 is incremented and the next pass is processed.

  FIG. 2 shows a configuration diagram of the MR path address generation unit 22. In the MR path address generation unit 22, the same number of flip-flops FF0, FF1, FF2,... FF15 as the number of sub-blocks in the code block are provided. Here, for example, when there is a bit to be processed in the next MR pass in a sub-block of the area whose address is “0”, the output of FF0 (MR_FLAG_0) is 1, and there is no target bit. In this case, it becomes 0. Further, when there is no bit to be processed in all the sub-blocks, the outputs of all the flip-flops become 0, and as a result, the MR_NOPASS output becomes 1. The operation of these flip-flops is that when the en input is 1, the output d is set to 1 if the set signal is input, and the output d is cleared to 0 if the clr signal is input. .

  The operation of the apparatus shown in FIG. 2 will be described in detail. At the time when the processing of the code block is started, the outputs of all the flip-flops (FF0, FF1,... FF15) of the MR path address generation unit 22 are zero. During the SP pass process, the address input is input to the address decoder 30 and the en input of the flip-flop corresponding to the currently processed sub-block becomes 1. On the other hand, since the processing target bit in the MR path is a bit in which both the ss flag and the ps flag are 1 (see FIG. 13), the logic for each bit of the ss flag (newSS) and the ps flag (newPS) to be updated. When the logical sum of products (| (newSS & newPS)) is “1”, there is a processing target bit in the MR pass in the sub-block. Therefore, if the above condition is satisfied at the timing (add_increment) when the address of the sub-block is finished and the address is incremented, the output of the flip-flop corresponding to the currently processed sub-block is set to “1”. The If the condition is not satisfied, it remains 0. Since all sub-blocks are processing targets in the SP pass processing, it is possible to determine whether or not there is a processing target bit for all sub-blocks when the SP pass processing ends.

  The outputs of all the flip-flops (FF0, FF1,... FF15) of the MR path address generation unit 22 are input to the priority encoder 28. From the priority encoder 28, among the flip-flops whose output is 1, the one corresponding to the sub-block at the position to be processed first is preferentially decoded and output as an address (MR_ADD). When processing in the MR path is started, the address of the sub-block to be processed first is loaded into the address generator 14 by the add_load signal. On the other hand, the address output (MR_ADD) is an input to the address decoder 30. When add_load is input, the output of the flip-flop corresponding to the address is cleared to zero. As a result, the address of the sub-block to be processed first is loaded into the address generator 14 and at the same time the address of the sub-block to be processed for the second time is output from MR_ADD. When this operation is repeated and the processing of all the sub-blocks including the processing target bit is completed, the outputs of all the flip-flops are cleared to 0 and the MR_NOPASS signal is output. The selection / control unit 20 controls the whole so as to finish the processing of one pass and start the processing of the next pass.

  FIG. 3 is a configuration diagram of the CU path address generation unit 24. The basic operation is the same as that of the MR path address generation unit 22 shown in FIG. 2, but differs in the following two points.

  First, since the first bit plane of each code block needs to be processed in the CU pass, it is necessary to process all sub-blocks in the first CU pass. For this reason, the outputs of all the flip-flops (FF0, FF1,... FF15) of the CU path address generation unit 24 are 1 when the code block processing is started.

  Further, since the ss flag and the ps flag at the position are both 0 bits for the processing target bit in the CU pass, the logical product for each bit of the bit-inverted data of the ss flag (newSS) and the ps flag (newPS) to be updated When the logical OR (| (~ newSS & ~ newPS)) is "1", the output of the flip-flop corresponding to the sub-block being processed is set to "1" at the timing of address increment (add_increment) Is done.

  FIG. 4 is a flowchart of context and decision selection control in the selection / control unit 20 of the bit modeling processing unit 2 according to the preferred embodiment of the present invention.

  After the start (S00), the path counter is reset by the pass_init signal, but since the first path is a CU path, an add_load signal is generated and CU_ADD is loaded into the address generation unit 14 (S02). Next, after the data of the sub-block selected by the address value is loaded into the storage register of each data (S04), the bit modeling processing in the sub-block is performed. (However, since all the flip-flops of the CU path address generation unit 24 are set to 1 as described above, all sub-blocks are processed in this first CU path.)

  When processing of all the bits in this sub-block is completed, BLK_END is set to 1, so the updated values (newSS, newPS) of the ss flag and ps flag are written in the storage memory (S12).

  Next, it is determined whether the processed sub-block is the last sub-block processed in the code block. If the path being processed is an MR path or a CU path (S14, YES), a NO_PASS signal is used for determination (S20). If the path is an SP path (S14, NO), the address is the last sub-block. Judgment is made based on whether it is shown (S16).

  If it is not the last sub-block of the path, in the case of the SP path, the address of the address generator 14 is incremented by an add_incremet signal (S18). In the case of the MR path or the CU path, the address of the next sub-block including the processing target bit is loaded into the address generator 14 by the add_load signal (S20).

  If it is the last sub-block of the path, it is determined whether or not the processing of all the paths has been completed. If it has been completed (YES at S22), the processing of the code block is terminated (S24). If the path to be processed still remains (S22 / NO), the path count value is incremented by the pass_increment signal (S24).

  If the path indicated by the new pass count is an SP path, the address of the address generation unit 14 is initialized by the add_init signal (S28), the data of the first sub-block area is loaded (S04), and the processing of that path is performed. To start.

  If the new path is an MR path or a CU path, first, a NO_PASS signal is confirmed (S30). If NO_PASS is output at this time (YES in S30), it is indicated that there is no processing target bit in the new path, so it is confirmed again whether the path is the last path (S22). After that, if there are still paths to be processed (S22, NO), the path count value is incremented by the pass_increment signal (S24), and the same processing as described above is repeated.

  If NO_PASS is not output (S30, NO), an ADD (address) indicating a sub-block to be processed first is loaded into the address generation unit 14 by an add_load signal (S32), and each sub-block data is stored. The data is loaded into the register (S04), and the processing of the path is started.

  FIG. 5 is a block diagram of the bit modeling processing unit 2 for decoding processing according to a preferred embodiment of the present invention.

  As in the conventional example (see FIG. 22), the difference from the bit modeling processing unit for encoding processing is that the decision (D) is not output by the bit modeling processing unit, but the MQ decoder decodes the code. This is the point that is output as a result. Therefore, as compared with the bit modeling processing unit 2 for encoding processing in FIG. 1, a sign bit / bit data generating unit 46 for generating bit data and sign bit from the decision (D) is added.

It is a block diagram of a bit modeling processing unit for encoding processing according to a preferred embodiment of the present invention. It is a block diagram of a MR path address generation unit. It is a block diagram of a CU path address generation part. 6 is a flowchart of context and decision selection control in a selection / control unit of a bit modeling processing unit according to a preferred embodiment of the present invention. It is a block diagram of a bit modeling processing unit for decoding processing according to a preferred embodiment of the present invention. (1) is a conceptual diagram illustrating an example in which image data is converted into coefficient data for each subband by wavelet conversion. (2) is a diagram illustrating an example in which one subband is divided into a plurality of code blocks. (3) is a conceptual diagram illustrating an example in which coefficient data of a code block is divided into bit planes. (4) is a diagram illustrating a state in which the bit plane in the code block is divided into a zero bit plane that continues from the top and a bit plane that is to be encoded using bit modeling. It is a figure which shows the order which scans the bit plane in order to search the bit used as encoding object. It is a specific example of the encoding process of bit modeling. (1) is a schematic flow diagram of encoding processing in JPEG2000. (2) is a diagram illustrating a data flow between the coefficient bit modeling unit and the MQ encoder. (3) is a diagram illustrating a data flow between the coefficient bit modeling unit and the MQ decoder at the time of decoding. It is a figure which shows the context produced | generated by SP path in the encoding of the code block contained in LL subband and LH subband. It is a figure which shows the context produced | generated when encoding a sign bit. It is a figure which shows the context produced | generated by MR path | pass. The combination of the signature state (ss) and pass bit (ps) to be processed in each pass, and the value of the signature state (ss) and pass bit (ps) updated after processing the bit (new) ss, new ps). (1) is a diagram illustrating a state in which a 16 × 16 code block is divided into 4 × 4 sub-blocks. (2) is a diagram showing a 6 × 6 area necessary for a 4 × 4 sub-block. It is a block diagram of the coding bit modeling apparatus of a prior art example. (1) is an example of data storage related to a code block. (2) is a diagram illustrating a state in which 6 × 6 area data necessary for processing the sub-block “5” in FIG. 14 (2) is input to the register. It is a block diagram of the bit modeling process part of a prior art example. (1) is a detailed block diagram of a conventional path determination unit. (2) and (3) are diagrams of a 4 × 4 area and a 6 × 6 area, respectively, with numbers and symbols indicating the respective bit positions. It is a detailed block diagram of the processing bit determination part of a prior art example. It is a general | schematic flowchart regarding the control of selection of a context and a decision in the selection / control part of a prior art example. An example of a conventional decoding bit modeling apparatus is shown. It is a block diagram of the bit modeling process part of a prior art example.

Explanation of symbols

2 ... Bit modeling processing unit, 14 ... Address generation unit, 16 ... Pass counter, 20 ... Selection / control unit, 22 ... MR path address generation unit, 24 ... CU path address Generation unit, 46... Sign bit / bit data generation unit.

Claims (2)

In a JPEG2000 bit modeling processing apparatus that searches for and encodes or decodes a processing target bit in a pass that is processed in units of subblocks in which a code block is divided into a plurality of blocks,
During processing of Shigunifikanto propagation (Significance propagation) paths for one sub-block,
It generates and stores a subsequent magnitude refinement (Magnitude refinement) path or whether the information processed bits cleanup (Clean Stay up-) path exists which is carried out in at its sub-blocks,
When the information indicating whether or not the processing target bit exists is data indicating the presence, when a magnitude refinement (Cleanup) pass process or a cleanup (Cleanup) pass process is performed correspondingly, Information indicating whether or not the processing target bit exists in the sub-block is changed to data indicating that it does not exist,
In the magnitude refinement pass or clean up pass processing in one code block, there is no information on whether or not the processing target bit exists for all the sub blocks of the code block. The bit modeling processing device, wherein the pass processing in the code block is terminated when the data indicates the data . A JPEG2000 encoding / decoding processing apparatus comprising the bit modeling processing apparatus according to claim 1 .

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