JP4366938B2 - Semiconductor device - Google Patents

Description

[0001]
BACKGROUND OF THE INVENTION
The present invention relates to a semiconductor device, and more particularly to a semiconductor device in which an on voltage is reduced.
[0002]
[Prior art]
An example of a conventional semiconductor device is disclosed in Japanese Patent Laid-Open No. 2001-127286 (Patent Document 1). In this conventional semiconductor device, a region where an n + type emitter region is formed and a region where an n + type emitter region is not formed are provided separately, and an n + type hole is formed in a region where an n + type emitter region is formed. A barrier is provided. This prevents latch-up and lowers the on-voltage. In addition, semiconductor devices shown in Patent Documents 2 to 4 are disclosed.
[0003]
[Patent Document 1]
JP 2001-127286 A [Patent Document 2]
JP-A-10-294461 [Patent Document 3]
Japanese Patent Laid-Open No. 9-331063 [Patent Document 4]
Japanese Patent Laid-Open No. 2001-15747
[Problems to be solved by the invention]
However, the conventional semiconductor device disclosed in Patent Document 1 has a problem that a sufficient on-voltage reduction effect cannot be obtained because holes pass through the region where the n + -type emitter region is not formed and pass through the emitter electrode. It was.
[0005]
The present invention has been made in view of the above problems, and an object of the present invention is to provide a semiconductor device that improves the on-voltage reduction effect.
[0006]
[Means for Solving the Problems]
To achieve the above object, a semiconductor device according to a first aspect of the present invention, a plurality of semiconductor regions which are separated from each other by a first electrode and an insulating film formed in the trench seen including, the first A semiconductor device in which an electrode is connected to a semiconductor region through the insulating film , wherein at least one of the semiconductor regions is capable of supplying carriers of the first conductivity type, and the other semiconductor regions are second conductive A semiconductor region including a barrier region that suppresses the passage of carriers of the type, a first region of the second conductivity type, and a second region of the first conductivity type joined to the first region, Further, the semiconductor region capable of supplying the first conductivity type carrier includes a first conductivity type third region, and a second conductivity type second region joined to the third region and the second region. 4, and the semiconductor region including the barrier region is the second region. A fifth region of the second conductivity type joined to the third region, further comprising a second electrode joined to the third region, the fourth region, and the fifth region, In this region, a second conductivity type region having a higher concentration than the lower surface side is formed on the upper surface side of the barrier region, and the barrier region is a first conductivity type region and is in contact with the insulating film. In this case, the second conductivity type carriers are prevented from passing from the first region . Note that the first conductivity type carrier is preferably a minority carrier for the semiconductor device, and the second conductivity type carrier is preferably a majority carrier. The carrier of the first or second conductivity type is an electron when the conductivity type is n-type, and a hole when it is p-type.
[0009]
The semiconductor device according to a second aspect of the present invention is the apparatus according to the first aspect of the present onset bright, the barrier region is characterized by being intermittently formed.
[0012]
The semiconductor device according to a third aspect of the present invention is the apparatus according to the first or second invention, the second electrode, the semiconductor region including the barrier region, the including pre Symbol barrier region It is characterized by not being joined to a region of one conductivity type.
[0013]
A semiconductor device according to a fourth aspect of the present invention includes a plurality of semiconductor regions separated from each other by a first electrode formed in a trench and an insulating film, and the first electrode is connected to the semiconductor region via the insulating film. In the connected semiconductor device, at least one of the semiconductor regions can supply a carrier of the first conductivity type, and the other semiconductor region has a barrier region that suppresses the passage of the carrier of the second conductivity type. A first conductive type first region; and a first conductive type second region joined to the first region; and supplying a first conductive type carrier. The semiconductor region capable of forming includes a first conductivity type third region, and a second conductivity type fourth region joined to the third region and the second region, and the barrier region The semiconductor region including the second conductive type fifth region joined to the second region And further including a second electrode joined to the third region, the fourth region, and the barrier region, wherein the barrier region is a region of a first conductivity type, and the insulating film And the second conductivity type carrier is prevented from passing from the first region .
[0014]
A semiconductor device according to a fifth aspect of the present invention is the device according to the fourth aspect of the present invention, wherein the barrier region is intermittently joined to the second electrode. A semiconductor device according to a sixth aspect of the present invention is the device according to any one of the first to fifth aspects of the present invention, further comprising a third electrode joined to the first region. To do.
[0015]
DETAILED DESCRIPTION OF THE INVENTION
Hereinafter, embodiments of the present invention (hereinafter referred to as embodiments) will be described with reference to the drawings.
[0016]
(1) First Embodiment FIGS. 1A and 1B are diagrams schematically showing a configuration of a semiconductor device according to a first embodiment of the present invention. FIG. 1A is a plan view and FIG. The figure is shown. However, the emitter electrode and the insulating film are not shown in FIG. 1A, and FIG. 1B is a cross-sectional view taken along the line BB in FIG. This embodiment shows a case where the present invention is applied to an IGBT. The IGBT of this embodiment includes gate electrodes 206a, 206b, 206c, an emitter electrode 209, a collector electrode 210, a p + collector region 201, an n drift region 202, and a p body. It includes regions 203a and 203b, p + emitter regions 203c and 203d, an n + emitter region 204a, a gate insulating film 205, an insulating film 207, and an n hole barrier region 211.
[0017]
The p + collector region 201 is formed on the silicon substrate. An n drift region 202 is joined on the p + collector region 201, and a collector electrode 210 is joined below the p + collector region 201. A p body region is joined on n drift region 202.
[0018]
Gate electrodes 206a, 206 b, 206c are respectively buried in the train Ji. Tren Chi penetrates the p-body region, and reaches the n drift region 202. Between the inner surface and the bottom surface of the gate electrode 206a and the train Ji, between the inner surface and the bottom surface of the gate electrode 206b and the train Ji, between the inner surface and the bottom surface of the gate electrode 206c and the train Ji, the gate insulating film 205 is formed.
[0019]
Here, is prescribed Thus semiconductor regions 213a to train Ji, the train Chi Thus semiconductor region 213b are defined. It is separated by semiconductor regions 213a and the gate electrode 206b and the gate insulating film 205 formed on the train Chi the semiconductor region 213b. Further, the p body region in the semiconductor region 213a is referred to as a p body region 203a, and the p body region in the semiconductor region 213b is referred to as a p body region 203b.
[0020]
An n + emitter region 204a is joined on the p body region 203a in the semiconductor region 213a. A p + emitter region 203c is intermittently formed in the n + emitter region 204a. The p + emitter region 203c is not in contact with the gate insulating film 205, and the n + emitter region 204a is in contact with the gate insulating film 205.
[0021]
On the other hand, the n + emitter region is not formed in the semiconductor region 213b, and the n hole barrier region 211 is joined in the p body region 203b. A p + emitter region 203 d is joined on the n hole barrier region 211. The n hole barrier region 211 is not in contact with the gate insulating film 205, and the p + emitter region 203 d is in contact with the gate insulating film 205.
[0022]
On train Chi, insulating film 207 is formed. An emitter electrode 209 is formed so as to cover the insulating film 207, and the emitter electrode 209 is in contact with the n + emitter region 204a and the p + emitter regions 203c and 203d. Here, the portion of the emitter electrode 209 that is in contact with the n + emitter region 204a and the p + emitter region 203c becomes the contact opening 208.
[0023]
In the above configuration, the p + collector region 201 is an example of the first region, the n drift region 202 is an example of the second region, the n + emitter region 204a is an example of the third region, the p body region 203a and the p + emitter region 203c. Is an example of the fourth region, the p body region 203b and the p + emitter region 203d are an example of the fifth region, and the n hole barrier region 211 is an example of the barrier region. The gate electrodes 206a, 206b, and 206c are examples of the first electrode, the emitter electrode 209 is an example of the second electrode, and the collector electrode 210 is an example of the third electrode. In FIG. 1, only one semiconductor region 213a and 213b is shown, but the number of semiconductor regions 213a and 213b can be arbitrarily set.
[0024]
Next, the manufacturing method of IGBT of this embodiment is demonstrated using FIG.
[0025]
First, an n drift region 202 is epitaxially grown on a silicon substrate to be a p + collector region 201. Next, a thermal oxide film (not shown) having a thickness of about 700 nm is formed on the surface of the n drift region 202 by pyrogenic oxidation at about 1000 ° C. Thereafter, a resist (not shown) is stacked on the surface of the thermal oxide film, and an opening pattern is formed by a photolithography process. Using this resist pattern as a mask, the thermal oxide film is removed by wet etching to form a region for forming an element (not shown). Next, an oxide film 207b having a thickness of about 18 nm is formed on the surface of the n drift region 202 by an oxidation treatment at an ambient temperature of about 900 ° C. Thereafter, a resist is laminated on the surface of the oxide film 207b, and an opening pattern is formed by a photolithography process. Then, boron is applied at an acceleration voltage of about 60 keV and a dose of about 4.7 × 10 ¹³ cm ^{−2 using} the resist pattern as a mask. Ion implantation. Thereafter, diffusion is performed by a heat treatment at an atmospheric temperature of about 1150 ° C. to form a p body region 203 having a depth of about 5 μm. Next, after an opening pattern is formed by a photolithography process, arsenic is ion-implanted with an acceleration voltage of 100 to 300 keV and a dose of about 3 × 10 ¹⁴ cm ^{−2 using} the resist pattern as a mask. Thereafter, the n-hole barrier region 211 is formed by diffusion by heat treatment at an atmospheric temperature of about 1150 ° C. (FIG. 2A).
[0026]
In the above process, an n-silicon substrate may be used as the n drift region 202, and a p-type impurity may be diffused by injecting p-type impurities into one main surface and annealing. Further, instead of implanting p-type impurities, a semiconductor film into which p-type impurities are introduced may be deposited by a CVD method. Manufacturing cost can be reduced by using an n-silicon substrate.
[0027]
Next, after an oxide film 207c having a thickness of about 400 nm is deposited on the oxide film 207b by a CVD method, a resist is laminated on the surface, and a strip-shaped opening pattern is formed by a photolithography process. Thereafter, the oxide films 207b and 207c are removed by etching by the RIE method using the resist pattern as a mask to form a silicon etching mask. Next, etching is performed by the RIE method using this silicon etching mask as a mask, and a trench having a depth of about 6 μm is formed through the p body region 203. Thereafter, the sidewall of the trench is etched by the CDE method, and then an oxide film (not shown) is formed by an oxidation treatment at an atmospheric temperature of about 1100 ° C. to remove the defect on the sidewall. Thereafter, a gate insulating film 205 having a thickness of about 100 nm is formed by oxidation treatment at an ambient temperature of about 1100 ° C. (FIG. 2B).
[0028]
Next, a polycrystalline silicon film having a thickness of about 800 nm is deposited by CVD. Thereafter, heat treatment is performed at an atmospheric temperature of about 950 ° C. to diffuse phosphorus in the polycrystalline silicon film. Thereafter, a resist is stacked, a gate wiring (not shown) pattern is formed by a photolithography process, and then the trench opening is left so as to leave a polycrystalline silicon film embedded in the trench by RIE etching using the resist pattern as a mask. The gate electrode 206 is formed by removing up to the portion. Next, after an oxide film (not shown) having a thickness of about 30 nm is formed on the surface of the p body region 203 and the surface embedded in the trench by an oxidation process at an atmospheric temperature of about 950 ° C., a resist is stacked, and a photolithography step As a result, patterns of the p + emitter regions 203c and 203d are formed. Thereafter, boron is ion-implanted with an acceleration voltage of about 70 keV and a dose of about 4 × 10 ¹⁵ cm ^{−2 using} the resist pattern as a mask. Next, a resist is stacked on the surface of the oxide film, and a pattern of the n + emitter region 204a is formed by a photolithography process. Thereafter, phosphorus is ion-implanted with an acceleration voltage of about 120 keV and a dose of about 5 × 10 ¹⁵ cm ^{−2 using} the resist pattern as a mask. Thereafter, a BPSG film 207 having a thickness of about 1.5 μm is deposited on the surface of the oxide film by a CVD method, and then the BPSG film 207 is planarized by a heat treatment at an atmospheric temperature of about 950 ° C. The region 204a is formed by diffusing. Next, a resist is stacked on the surface of the BPSG film 207, and a pattern of the contact opening 208 is formed so as to expose the surfaces of the p body region 203, the p + emitter regions 203c and 203d, and the n + emitter region 204a by a photolithography process. Then, the BPSG film 207 and the oxide film (not shown) are removed by etching by the RIE method using the resist pattern as a mask (FIG. 2C).
[0029]
Next, the p body region 203, the p + emitter regions 203c and 203d, the n + emitter region 204a, and the trenches are formed so that the p body region 203, the p + emitter regions 203c and 203d, and the n + emitter region 204a exposed by etching are short-circuited. A barrier metal film made of titanium and an Al film are stacked on a gate wiring (not shown) connected to the crystalline silicon film by a sputtering method. Thereafter, a resist is laminated on the surface of the Al film, and a pattern of the emitter electrode 209 and the gate wiring electrode is simultaneously formed by a photolithography process. Thereafter, the emitter electrode 209 and the gate wiring electrode (not shown) are simultaneously formed by wet etching and etching by the RIE method using the resist pattern as a mask (FIG. 2D). Next, a collector electrode 210 (Ti / Ni / Al or the like) is formed on the surface of the p + collector region 201 by sputtering (FIG. 2E). The IGBT of this embodiment is manufactured through the above steps.
[0030]
When the IGBT is turned on in this embodiment, a channel is formed in the vicinity of the gate insulating film 205 on the semiconductor region 213a side, and electrons (minority carriers) supplied from the n + emitter region 204a flow through the channel. On the other hand, electrons are not supplied to the semiconductor region 213b. Here, since the channel formed in the vicinity of the gate insulating film 205 serves as an electron flow path, electrons accumulate in the vicinity of the gate insulating film 205 as shown in FIG. Furthermore, since the n-hole barrier region 211 is provided in the semiconductor region 213b, the flow path of holes (majority carriers) supplied from the p + collector region 201 and passing through the semiconductor region 213b becomes extremely narrow, Outflow to the emitter electrode 209 is suppressed. As a result, it is possible to suppress a decrease in holes in the n drift region 202, so that the effect of reducing the on-voltage of the IGBT can be improved. Furthermore, even if the channel density is lowered, the short circuit current can be reduced without increasing the on-voltage.
[0031]
On the other hand, during the off operation, as shown in FIG. 3B, the electrons accumulated in the vicinity of the gate insulating film 205 disappear, so that the holes pass through the flow path in the vicinity of the gate insulating film 205 and the emitter electrode 209. Spill to As a result, stable switching characteristics can be obtained. Furthermore, since the high-concentration p + emitter region 203d is formed on the upper surface side of the n-hole barrier region 211, holes can be more efficiently discharged to the emitter electrode 209 during the off operation. Further, by forming the low-concentration p body region 203b on the lower surface side of the n hole barrier region 211, an inversion layer can be formed to enhance the hole accumulation effect, and the p body region 203b There is no increase in the electric field at the junction between the n drift region 202 and the n drift region 202, and a high breakdown voltage can be realized.
[0032]
(2) Second Embodiment FIG. 4 is a diagram schematically showing a configuration of a semiconductor device according to a second embodiment of the present invention. FIG. 4 (a) is a plan view, and FIGS. c) shows a cross-sectional view. However, in FIG. 4A, the illustration of the emitter electrode and the insulating film is omitted, and FIG. 4B is a cross-sectional view cut along BB in FIG. 4A. FIG. 4C is a cross-sectional view taken along CC of a). In this embodiment, the n hole barrier region 211 is intermittently formed in the p body region 203b. More specifically, when viewed in a cross-sectional view, a cross section in which an n-hole barrier region 211 is formed as shown in FIG. 4B, and an n-hole barrier as shown in FIG. There is a cross section in which the region 211 is not formed. Since other configurations are the same as those of the first embodiment, description thereof is omitted.
[0033]
Also in the present embodiment, as in the first embodiment, the effect of reducing the on-voltage can be improved, the short-circuit current can be reduced, and a high breakdown voltage can be realized. Further, in this embodiment, the n hole barrier region 211 is formed intermittently, and the amount of holes flowing out to the emitter electrode 209 through the semiconductor region 213b is adjusted by adjusting the interval. it can. Therefore, the current in the semiconductor device can be made uniform, and the heat generation in the semiconductor device during the on operation can be made uniform.
[0034]
(3) Third Embodiment FIG. 5 is a diagram schematically showing the configuration of a semiconductor device according to a third embodiment of the present invention. FIG. 5 (a) is a plan view, and FIGS. c) shows a cross-sectional view. However, in FIG. 5A, illustration of the emitter electrode and the insulating film is omitted, and a cross-sectional view cut along BB in FIG. 5A is FIG. 5B, and FIG. FIG. 5C is a cross-sectional view taken along CC of a). In the present embodiment, the p + emitter region 203d and the n + emitter region 204b are intermittently formed on the n hole barrier region 211. More specifically, when viewed in a cross-sectional view, as shown in FIG. 5B, a cross-section in which the n + emitter region 204b is formed on the n-hole barrier region 211, as shown in FIG. 5C. Thus, there exists a cross section in which the p + emitter region 203 d is formed on the n hole barrier region 211. Here, not only the n hole barrier region 211 but also the n + emitter region 204b is an example of the barrier region. Since other configurations are the same as those of the first embodiment, description thereof is omitted.
[0035]
Also in the present embodiment, as in the first embodiment, the effect of reducing the on-voltage can be improved, the short-circuit current can be reduced, and a high breakdown voltage can be realized. Furthermore, in the present embodiment, the n + emitter region 204b is intermittently formed on the n hole barrier region 211, and the channel density can be adjusted by adjusting the distance between the n + emitter region 204b and the emitter electrode 209. Hole outflow can be further suppressed. Therefore, the on-voltage and the short-circuit current can be adjusted without changing the withstand voltage. Further, by bringing the n + emitter region 204b and the n hole barrier region 211 into contact with each other, the n + emitter region 204b and the n hole barrier region 211 can be set to the same potential, so that the n + emitter region 204b / p body region 203b / n A thyristor operation including the hole barrier region 211 / p body region 203b can be prevented, and a stable switching operation can be realized.
[0036]
(4) Fourth Embodiment FIGS. 6A and 6B are diagrams schematically showing a configuration of a semiconductor device according to a fourth embodiment of the present invention. FIG. 6A is a plan view and FIG. The figure is shown. However, in FIG. 6A, illustration of the emitter electrode and the insulating film is omitted, and FIG. 6B is a cross-sectional view cut along BB in FIG. 6A. In the present embodiment, the p + emitter region 203 d is not formed, and the n hole barrier region 211 is in contact with the emitter electrode 209. Since other configurations are the same as those of the first embodiment, description thereof is omitted.
[0037]
Also in the present embodiment, as in the first embodiment, the effect of reducing the on-voltage can be improved, the short-circuit current can be reduced, and a high breakdown voltage can be realized. Furthermore, in this embodiment, since the n + emitter region 204b and the n hole barrier region 211 in the third embodiment can be used simultaneously and formed, the manufacturing cost can be reduced.
[0038]
In addition, in embodiment, this invention is not limited to the content of said description, A various deformation | transformation is possible within the range in which the technical idea of this invention is reflected. For example, the n-hole barrier region 211 can be applied to the collector short type as shown in FIGS.
[0039]
In the configuration shown in the cross-sectional view of FIG. 7, n drift region 202 is also joined to collector electrode 210, and p + collector region 201 is separated by n drift region 202. The p + collector region 201 in FIG. 7 is formed by forming a pattern with a partial opening by a photolithography process, implanting p-type impurities using this pattern as a mask, and diffusing by annealing.
[0040]
In the configuration shown in the cross-sectional view of FIG. 8, an n drift region 202, a p + collector region 201, and an n buffer region 214 joined to the collector electrode 210 are provided, and the p + collector region 201 is separated by the n buffer region 214. ing. The n buffer region 214 in FIG. 8 is formed by depositing n-type impurities and diffusing them by annealing.
[0041]
In addition, the characteristic portions of the first to fourth embodiments can be used in combination, for example, the second embodiment + third embodiment, the second embodiment + fourth embodiment, or the like. As the semiconductor substrate, SiC, GaN, GaAs or the like can be used in addition to silicon. The planar shape of the gate electrodes 206a, 206b, and 206c can be an arbitrary shape such as a circle, an ellipse, or a polygon. Further, for the gate electrodes 206a, 206b, and 206c, a planar type or concave type gate electrode may be used instead of the trench type. In each embodiment, the case of the non-punch through type has been described. However, the present invention can also be applied to a punch through type having an n + buffer region. The concentration distribution of the n drift region 202 does not need to be uniform. Furthermore, a defect region may be provided near the boundary between the p + collector region 201 and the n drift region 202 or in the n drift region 202 by charged particle or electron beam irradiation. The present invention can also be applied to a semiconductor device in which p-type and n-type are inverted. The semiconductor device to which the present invention can be applied is not limited to the IGBT, and the present invention can also be applied to other semiconductor devices such as a MOS control thyristor.
[0042]
【The invention's effect】
As described above, according to the present invention, the semiconductor region to which the first conductivity type carrier is not supplied includes the barrier region that suppresses the passage of the second conductivity type carrier, thereby reducing the on-voltage. The effect can be improved.
[Brief description of the drawings]
FIG. 1 is a diagram schematically showing a configuration of a semiconductor device according to a first embodiment of the present invention.
FIG. 2 is a diagram for explaining the method for manufacturing the semiconductor device according to the first embodiment of the invention.
FIG. 3 is a diagram for explaining the operation of the semiconductor device according to the first embodiment of the present invention.
FIG. 4 is a diagram schematically showing a configuration of a semiconductor device according to a second embodiment of the present invention.
FIG. 5 is a diagram schematically showing a configuration of a semiconductor device according to a third embodiment of the present invention.
FIG. 6 is a diagram schematically showing a configuration of a semiconductor device according to a fourth embodiment of the present invention.
FIG. 7 is a diagram schematically showing a configuration of a semiconductor device according to another embodiment of the present invention.
FIG. 8 is a diagram schematically showing a configuration of a semiconductor device according to another embodiment of the present invention.
[Explanation of symbols]
201 p + collector region, 202 n drift region, 203a, 203b p body region, 203c, 203d p + emitter region, 204a, 204b n + emitter region, 205 gate insulating film, 206a, 206b, 206c gate electrode, 209 emitter electrode, 210 collector Electrode, 211 n hole barrier region, 213a, 213b Semiconductor region.

Claims (6)

Look including a plurality of semiconductor regions which are separated from each other by a first electrode and an insulating film formed in the trench, the first electrode is a semiconductor device which is connected to the semiconductor region through the insulating film,
At least one of the semiconductor regions can supply a carrier of the first conductivity type,
The other semiconductor region has a semiconductor region including a barrier region that suppresses the passage of carriers of the second conductivity type ,
A first conductivity type first region; and a first conductivity type second region joined to the first region;
The semiconductor region capable of supplying the first conductivity type carrier includes a first conductivity type third region, and a second conductivity type fourth region joined to the third region and the second region. And including
The semiconductor region including the barrier region further includes a second conductivity type fifth region joined to the second region,
A second electrode joined to the third region, the fourth region, and the fifth region;
For the fifth region, a region of the second conductivity type having a higher concentration than the lower surface side is formed on the upper surface side of the barrier region,
The semiconductor device is characterized in that the barrier region is a first conductivity type region, is not in contact with the insulating film, and suppresses the passage of the second conductivity type carrier from the first region . The semiconductor device according to claim 1,
The semiconductor device is characterized in that the barrier region is formed intermittently . The semiconductor device according to claim 1 , wherein
The semiconductor device, wherein the second electrode is not bonded to a first conductivity type region including the barrier region in the semiconductor region including the barrier region . A semiconductor device including a plurality of semiconductor regions separated from each other by a first electrode and an insulating film formed in a trench, wherein the first electrode is connected to the semiconductor region via the insulating film ,
At least one of the semiconductor regions can supply a carrier of the first conductivity type,
The other semiconductor region has a semiconductor region including a barrier region that suppresses the passage of carriers of the second conductivity type,
A first conductivity type first region; and a first conductivity type second region joined to the first region;
The semiconductor region capable of supplying the first conductivity type carrier includes a first conductivity type third region, and a second conductivity type fourth region joined to the third region and the second region. And including
The semiconductor region including the barrier region further includes a second conductivity type fifth region joined to the second region,
A second electrode joined to the third region, the fourth region, and the barrier region;
The semiconductor device is characterized in that the barrier region is a first conductivity type region, is not in contact with the insulating film, and suppresses the passage of the second conductivity type carrier from the first region . The semiconductor device according to claim 4 ,
The semiconductor device , wherein the barrier region is intermittently joined to the second electrode . A semiconductor device according to any one of claims 1 to 5 ,
The semiconductor device further comprising a third electrode joined to the first region .

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