JP4367272B2 - Encoding and decoding apparatus, encoding apparatus, and decoding apparatus - Google Patents

Description

  The present invention relates to an MPEG (Moving Picture Experts Group) standard encoding and decoding device, an encoding device, and a decoding device. Specifically, the present invention relates to a power consumption reduction technique during decoding processing.

Recently, development of an MPEG encoding / decoding device (MPEG CODEC LSI) is in progress (for example, see Patent Document 1). In the MPEG encoding and decoding apparatus, the processing amount is increased in accordance with new standards such as MPEG4-ASP (Advanced Simple Profile) and MPEG4-AVC (Advanced Video Coding), and the resolution is increased (from SD size to HD size). Therefore, power consumption tends to increase.
JP 2001-160968 A

  For example, when an MPEG encoding / decoding device is for a battery-powered portable device, an increase in power consumption of the MPEG encoding / decoding device reduces the operation time of the portable device. It is a serious problem.

  In view of the above, an object of the present invention is to provide an encoding and decoding apparatus, an encoding apparatus, and a decoding apparatus that can reduce power consumption during decoding processing.

  An encoding and decoding apparatus according to the present invention includes an encoding unit that encodes an image signal to generate a code string, and a decoding unit that decodes the code string generated by the encoding unit. The encoding unit includes a pause information generation unit that generates pause information for instructing a function that does not require an operation during a decoding process for each predetermined pixel block, and the decoding unit includes the pause information. Based on the above, a pause control unit that performs pause control of the circuit unit corresponding to the pause information is provided for each predetermined pixel block.

  An encoding apparatus according to the present invention is an encoding apparatus that encodes an image signal to generate a code string, and generates pause information that indicates a function that does not require an operation during decoding processing for each predetermined pixel block. It has a generation part.

  A decoding apparatus according to the present invention is a decoding apparatus that receives an encoded image signal and pause information that indicates a function that does not require operation during signal processing, and decodes the image information. Based on the above, a pause control unit that performs pause control of the circuit unit corresponding to the pause information is provided for each predetermined pixel block.

  According to the encoding and decoding apparatus of the present invention, the decoding unit can perform pause control of the circuit unit corresponding to the pause information for each predetermined pixel block based on the pause information. The power consumption can be reduced.

  According to the encoding apparatus of the present invention, pause information for instructing a function that does not require an operation during decoding processing is generated for each predetermined pixel block. Therefore, the decoding apparatus performs, for each predetermined pixel block, based on the pause information. In addition, by performing pause control of the circuit unit corresponding to the pause information, it is possible to reduce power consumption during the decoding process.

  According to the decoding device of the present invention, it is possible to perform pause control of a circuit unit corresponding to pause information for each predetermined pixel block based on pause information, thereby reducing power consumption during decoding processing. Can do.

  1 to 8, an encoding and decoding apparatus, an encoding apparatus, and a decoding apparatus according to an embodiment of the present invention will be described with reference to the MPEG standard encoding and decoding apparatus and encoding. A case where the present invention is applied to an apparatus and a decoding apparatus will be described as an example.

  FIG. 1 is a schematic configuration diagram of a system including an embodiment of an encoding and decoding apparatus according to the present invention. In FIG. 1, 1 is an embodiment of an encoding and decoding apparatus according to the present invention, and 2 is a DRAM (dynamic random access access) in a device equipped with an embodiment 1 of an encoding and decoding apparatus of the present invention. (Memory) 3 is an external device outside the device on which the first embodiment of the encoding and decoding apparatus of the present invention is mounted.

  In Embodiment 1 of the encoding and decoding apparatus of the present invention, reference numeral 4 denotes an encoding unit, which constitutes an embodiment of the encoding apparatus of the present invention. Reference numeral 5 denotes a decoding unit, which constitutes an embodiment of the decoding device of the present invention. 6 is a memory controller, 7 is a controller such as a CPU (central processing unit) or I / O (input / output) interface, and 8 is an internal bus.

  In the system shown in FIG. 1, the encoding unit 4 encodes a video input signal to generate an MPEG stream that is a code string of the MPEG standard, and the generated MPEG stream is stored in the DRAM 2 via the memory controller 6. The The decoding unit 5 inputs the MPEG stream stored in the DRAM 2 via the memory controller 6 and decodes it by a process compliant with the MPEG standard to generate a video output signal. Further, the MPEG stream stored in the DRAM 2 may be output to the external device 3 via the memory controller 6 and the controller 7.

  FIG. 2 is a schematic configuration diagram of the encoding unit 4. In FIG. 2, 9 is a DCT unit that inputs a video input signal and performs DCT (discrete cosine transform) processing, 10 is a quantization unit that performs quantization processing on the output of the DCT unit 9, and 11 receives a video input signal. An intra prediction unit 12 that performs an intra prediction process, and 12 is an inter prediction unit that inputs an image input signal and performs an inter prediction process.

  Reference numeral 13 denotes a mode determining unit that determines an encoding mode (encoding method) having the highest “image quality / stream size” or the optimum image quality from the characteristics of the input image for each picture that is an encoding unit image. On the basis of the encoding mode determined by the mode determination unit 13, for each macroblock that is a unit pixel block for encoding, in the decoding unit 5, pause information that instructs the pause of the circuit unit that does not require operation during the decoding process is made. A pause flag generation unit (pause information generation unit) 15 that generates a pause flag, 15 is an MPEG stream from the output of the quantization unit 10, the output of the intra prediction unit 11 or the output of the inter prediction unit 12, the output of the pause flag generation unit 14, etc. Is a stream generation unit that generates

  FIG. 3 is a schematic configuration diagram of the decoding unit 5. In FIG. 3, 16 is a stream analysis unit that analyzes an MPEG stream, 17 is an inverse quantization unit that receives a picture and performs inverse quantization processing, and 18 is an inverse DCT process performed on the output of the inverse quantization unit 17. An inverse DCT unit for performing 19, an intra correction unit for performing intra correction processing, 20 an inter correction unit for performing inter correction processing, and a selector for selecting and outputting the output of the intra correction unit 19 or the output of the inter correction unit 20. is there.

  Reference numeral 22 denotes an adder that inputs the output of the inverse DCT unit 18 and the output of the selector 21 to generate a video output signal. Reference numeral 23 denotes an inverse quantization unit 17 for each macroblock based on a pause flag included in the MPEG stream. This is a pause control unit that controls pauses of the inverse DCT unit 18, the intra correction unit 19, and the inter correction unit 20.

  FIG. 4 is a diagram illustrating the operation of the mode determination unit 13. The mode determination unit 13 receives a video input signal, performs a mode determination process using an existing technique, and determines a coding mode candidate for each picture (step S1). If there are a plurality of encoding mode candidates, the decoding unit power consumption table 24 is referenced for each encoding mode candidate, and the power consumption during the decoding process of the pause control target circuit unit of the decoding unit 5 is calculated. Then, the encoding mode candidate with the minimum power consumption during the decoding process of the pause control target circuit unit of the decoding unit 5 is determined as the encoding mode (step S2). When there is one encoding mode candidate, the encoding mode candidate is determined as the encoding mode as it is.

  Here, the coding mode is determined by determining the coding mode for each picture and the coding mode for each macroblock for each picture. For example, in the case of MPEG2, the coding mode for each picture is determined. There are an I picture, a P picture, and a B picture, and coding modes in units of macroblocks include intra, inter, skip, and the like.

  FIG. 5 is a diagram illustrating a configuration example of a picture in which the mode determination unit 13 determines the encoding mode. In this example, for convenience of explanation, it is assumed that a picture is composed of four macroblocks MB00, MB01, MB10, and MB11.

  FIG. 6 is a diagram illustrating an example of a coding mode candidate determined by the mode determination unit 13 for the picture shown in FIG. 5. FIG. 6 (A) is a coding mode candidate 1 and FIG. 6 (B) is a coding. Mode candidate 2 is shown. The encoding mode candidate 1 is the macroblock encoding mode, MB00 is intra, MB01 is inter, MB10 is intra, and MB11 is skip. The encoding mode candidate 2 is the macroblock encoding mode, MB00 is intra, MB01 is intra, MB10 is skip, and MB11 is skip.

  Table 1 shows an example of the decoding unit power consumption table 24. The decoding unit power consumption table 24 can be created based on the actual machine measurement result of each circuit unit of the decoding unit 5 or the result of the power consumption analysis tool. For the sake of convenience, only the inverse quantization unit 17, the inverse DCT unit 18, the intra correction unit 19, and the inter correction unit 20 are included.

  Here, the decoding process of the intra / macroblock requires the operations of the inverse quantization unit 17, the inverse DCT unit 18, and the intra correction unit 19 in the pause control target circuit unit. Is 0.4 μW. Since the inter-macroblock decoding process requires the operations of the inverse quantization unit 17, the inverse DCT unit 18, and the inter correction unit 20 in the pause control target circuit unit, the power consumption of the pause control target circuit unit is 1. 0 μW. The skip / macroblock decoding process requires the operation of the inter correction unit 20 in the pause control target circuit unit, so that the power consumption of the pause control target circuit unit is 0.8 μW.

  Table 2 shows the results of power consumption calculation of the encoding mode candidate 1 shown in FIG. 6A and the encoding mode candidate 2 shown in FIG.

  That is, in the case of encoding mode candidate 1, the power of the pause control target circuit unit necessary for the decoding process of each macroblock is 0.4 μW for MB00 (intra), 1.0 μW for MB01 (inter), and MB10 ( Intra) is 0.4 μW, MB11 (skip) is 0.8 μW, and the entire picture is 2.6 μW.

  On the other hand, in the case of the encoding mode candidate 2, the power of the pause control target circuit unit necessary for the decoding process of each macroblock is 0.4 μW for MB00 (intra) and MB01 (intra), respectively. MB10 (skip) and MB11 (skip) are each 0.8 μW, and the entire picture is 2.4 μW. Therefore, in this example, the mode determination unit 13 determines the encoding mode candidate 2 as the encoding mode.

  FIG. 7 is a diagram showing the configuration of the pause flag generated by the pause flag generator 14. The pause flag is configured to include an inverse quantization unit pause flag 25, an inverse DCT unit pause flag 26, an intra correction unit pause flag 27, and an inter correction unit pause flag 28.

  The inverse quantization unit pause flag 25 is a flag that indicates whether or not the operation of the inverse quantization unit 17 is paused, and the inverse DCT unit pause flag is a flag that indicates whether or not the operation of the inverse DCT unit 18 is paused. The intra correction unit pause flag is a flag for instructing whether or not the operation of the intra correction unit 19 is paused, and the inter correction unit pause flag is a flag for instructing whether or not the operation of the inter correction unit 20 is paused. In this case, “0” is set when the pause is instructed, and “1” is set when the pause is not instructed.

  Table 3 shows the content of the pause flag generated by the pause flag generation unit 14 when the encoding mode candidate 2 shown in FIG. 6B is determined to be the encoding mode.

  FIG. 8 is a diagram showing a part of an MPEG stream generated by the encoding unit 4. The pause flag is transmitted to the stream generation unit 15 and sent as a stream using the user enhancement layer. For example, in the case of the MPEG2 standard, it is transmitted for each “picture_header” in “user_data” in the “extension_and_user_data” layer.

  Here, the pause control unit 23 of the decoding unit 5 performs the quantization unit 17, the inverse DCT unit 18, and the intra correction unit 19 in the pause control target circuit unit for each macro block based on the pause flag included in the MPEG stream. In addition, the pause of the inter correction unit 20 is controlled. The pause control is performed by the supply control of the gated clock to the circuit unit which is paused during the decoding process.

  For example, if the MPEG stream includes the pause flag shown in Table 3, during the decoding process of MB00 and MB01, the inverse quantization unit 17, the inverse DCT unit 18, and the intra correction unit 19 are in the operating state, and the inter correction unit 20 During the decoding process of MB10 and MB11, the dequantization unit 17, the inverse DCT unit 18, and the intra correction unit 19 are set in the dormant state, and the inter correction unit 20 is set in the operation state.

  As described above, according to the first embodiment of the encoding and decoding apparatus of the present invention, the encoding unit 4 includes the pause flag generation unit (pause information generation unit) 14, and the decoding unit is provided for each macroblock. 5, the MPEG stream includes a pause flag (pause information) for instructing pause of the circuit unit that does not require operation during decoding processing, and a pause control unit 23 is provided in the decoding unit 5, so that the pause flag included in the MPEG stream is included. Based on this, the pause control of the circuit unit that does not require operation during the decoding process is performed for each macroblock, so that it is possible to reduce the power consumption during the decoding process.

  In the encoding and decoding apparatus, encoding apparatus, and decoding apparatus of the present invention, the case where the present invention is applied to an MPEG standard encoding and decoding apparatus, encoding apparatus, and decoding apparatus is taken as an example. As described above, the present invention is directed to an encoding / decoding device in which a circuit unit that does not require operation at the time of decoding processing exists depending on the encoding mode, and a decoding device in which a circuit unit that does not need to operate at the time of decoding processing exists. The present invention can be widely applied to the encoding device and the decoding device in which there is a circuit unit that does not require operation during decoding processing.

  Here, to summarize the present invention, the present invention includes at least the following encoding and decoding apparatus, encoding apparatus, and decoding apparatus.

  (Supplementary Note 1) An encoding and decoding apparatus including an encoding unit that encodes an image signal to generate a code string, and a decoding unit that decodes the code string generated by the encoding unit, The converting unit includes a pause information generating unit that generates pause information for instructing a function that does not require an operation during decoding processing for each predetermined pixel block, and the decoding unit is configured to generate a predetermined pixel block based on the pause information. An encoding and decoding apparatus, comprising: a pause control unit that performs pause control of a circuit unit corresponding to the pause information.

  (Supplementary Note 2) When there are a plurality of encoding mode candidates in an image having a plurality of predetermined pixel blocks as a unit, the encoding unit encodes the encoding mode candidate having the minimum power consumption during the decoding process of the image. The encoding and decoding apparatus according to appendix 1, further comprising a mode determination unit that determines a mode.

  (Additional remark 3) The said pause information production | generation part produces | generates the said pause information based on the encoding mode which the said mode determination part determined, The encoding and decoding apparatus of Additional remark 2 characterized by the above-mentioned.

  (Supplementary Note 4) The encoding according to Supplementary Note 3, wherein the suspension control unit performs suspension control of a circuit unit corresponding to the suspension information by supply control of a gated clock to the circuit unit corresponding to the suspension information. Decryption device.

  (Additional remark 5) It is an encoding apparatus which encodes an image signal and produces | generates a code sequence, Comprising: It has the pause information generation part which produces | generates the pause information which instruct | indicates the function which becomes operation | movement unnecessary at the time of a decoding process for every predetermined pixel block An encoding apparatus characterized by that.

  (Additional remark 6) It is the decoding apparatus which receives the pause information which instruct | indicates the function which becomes operation | movement unnecessary at the time of a signal processing with the encoded image signal, Comprising: Based on the said pause information, A decoding apparatus, comprising: a pause control unit that performs pause control of a circuit unit corresponding to the pause information for each predetermined pixel block.

It is a schematic block diagram of the system containing one Embodiment of the encoding and decoding apparatus of this invention. It is a schematic block diagram of the encoding part with which one Embodiment of the encoding and decoding apparatus of this invention is provided. It is a schematic block diagram of the decoding part with which one Embodiment of the encoding and decoding apparatus of this invention is provided. It is a figure which shows operation | movement of the mode determination part in the encoding part with which one Embodiment of the encoding and decoding apparatus of this invention is provided. It is a figure which shows the structural example of the picture from which the mode determination part in the encoding part with which one Embodiment of the encoding and decoding apparatus of this invention is provided determines an encoding mode. It is a figure which shows the example of the encoding mode candidate determined by the mode determination part in the encoding part with which one Embodiment of the encoding and decoding apparatus of this invention is provided. It is a figure which shows the structure of the pause flag which the pause flag production | generation part in the encoding part with which one Embodiment of the encoding and decoding apparatus of this invention is provided. It is a figure which shows a part of MPEG stream produced | generated by the encoding part with which one Embodiment of the encoding and decoding apparatus of this invention is provided.

Explanation of symbols

DESCRIPTION OF SYMBOLS 1 ... Embodiment of the encoding and decoding apparatus of this invention 2 ... DRAM
DESCRIPTION OF SYMBOLS 3 ... External device 4 ... Encoding part 5 ... Decoding part 6 ... Memory controller 7 ... Controller 8 ... Internal bus 9 ... DCT part 10 ... Quantization part 11 ... Intra prediction part 12 ... Inter prediction part 13 ... Mode determination part 14 ... pause flag generation unit 15 ... stream generation unit 16 ... stream analysis unit 17 ... inverse quantization unit 18 ... inverse DCT unit 19 ... intra correction unit 20 ... inter correction unit 21 ... selector 22 ... addition unit 23 ... pause control unit 24 ... Decoding unit power consumption table 25 ... Inverse quantization unit pause flag 26 ... Inverse DCT unit pause flag 27 ... Intra correction unit pause flag 28 ... Inter correction unit pause flag

Claims (5)

An encoding and decoding apparatus comprising: an encoding unit that encodes an image signal to generate a code string; and a decoding unit that decodes the code string generated by the encoding unit,
The encoding unit includes a pause information generation unit that generates pause information for instructing a function that does not require an operation during a decoding process for each predetermined pixel block.
The decoding unit includes a pause control unit that performs pause control of a circuit unit corresponding to the pause information for each predetermined pixel block based on the pause information.   When there are a plurality of encoding mode candidates in an image having a plurality of predetermined pixel blocks as a unit, the encoding unit determines an encoding mode candidate having a minimum power consumption during the decoding process of the image as an encoding mode. The encoding / decoding apparatus according to claim 1, further comprising a mode determination unit.   The encoding / decoding apparatus according to claim 2, wherein the pause information generation unit generates the pause information based on the encoding mode determined by the mode determination unit. An encoding device that encodes an image signal to generate a code string,
An encoding apparatus, comprising: a pause information generation unit that generates pause information for instructing a function that does not require an operation during a decoding process for each predetermined pixel block. A decoding device that receives encoded image signals and pause information that indicates functions that do not require operation during signal processing, and decodes the image information,
A decoding apparatus comprising: a pause control unit that performs pause control of a circuit unit corresponding to the pause information for each predetermined pixel block based on the pause information.

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