JP4375159B2 - Image processing device - Google Patents

Description

  The present invention relates to an image processing apparatus, and more particularly to an apparatus such as a copying machine or a multifunction machine having a function of performing a filtering process on an input image.

  Conventionally, an input image converted into digital data by a scanner or the like is stored in a page memory and a line memory, and the input image is smoothed, enlarged / reduced, edge-enhanced, etc. by performing filter processing using peripheral pixels of the pixel of interest An apparatus for performing various image processing is known.

  FIG. 6 is a block diagram showing the configuration of a conventional image processing apparatus disclosed in the following patent document.

  The page memory 12 stores one page of input image data. The segment reading unit 14 divides the page memory 12 into a plurality of blocks, reads image data in the main scanning direction (A direction), and outputs data (segment data) for one line in the block to the image processing ASIC 18. This is repeated in the sub-scanning direction (B direction) for each segment in the block, and when the reading of one block is completed, the next block is read (image data is read in block units in the order of 1 to 9 in the figure). ). In the image processing ASIC 18, the segment data output from the segment reading unit 14 is subjected to image processing using, for example, a 3 × 3 filter. That is, segment data from the segment reading unit 14 and segment data from the segment memories (line memories) 22 and 24 are supplied to the image processing unit 16 and image processing is performed using these data. The segment data subjected to image processing by the image processing unit 26 is output to the line restoration unit 20.

  The segment readout unit 14 has an overlap readout function, and when there are peripheral pixels to be referred to by the target pixel in the adjacent block, the segment readout unit 14 reads out the pixels present in the adjacent block. Thereby, even if the image data stored in the page memory 12 is divided and read in units of blocks, it is possible to appropriately perform the filtering process at the joint portion of the blocks.

JP 2000-251065 A

  However, in the above prior art, the image size that can be processed is basically determined by the size of the line memories 22 and 24 in the image processing ASIC 18. For example, when the document size to be processed is A4, as shown in FIG. In the case of processing in a block reading order, when the document size to be processed is changed to the document size of A0 which is long horizontally, it becomes difficult to cope with this.

  Further, in the conventional technology, when reading is performed in units of blocks, reading is performed in an overlapping manner, but image data (data outside the document size) that does not exist in the document is stored at the edge of the document, and this processing is complicated. There is a problem.

  Further, in the prior art, a page memory is provided to store data before image processing, and a page memory is also provided to store data after image processing in order to restore data in raster order. Since it is necessary to store image data, there is also a problem that it takes time from inputting image data to outputting processed image data.

  An object of the present invention is to provide an image processing apparatus that can cope with an arbitrary document size such as A0 and can obtain processed image data by promptly filtering.

  The present invention is an image processing apparatus that performs image processing of a pixel of interest with reference to surrounding pixels, and a filter circuit that performs filtering using a pixel of interest stored in the line memory and the surrounding pixels. First and second image processing means, and among the input image data, first and second image data having a data amount that can be processed by the image processing means are sequentially stored and supplied to the image processing unit. Input-side storage means, and first and second output-side storage means for sequentially storing the image data filtered by the image processing unit, the first input-side storage means, first image processing And the first output side storage means are connected in series to form a first processing system, and the second input side storage means, the second image processing means, and the second output side storage means are in series. Connected second processing system Configured, the input image is processed in parallel in the main scanning direction by the first processing system and the second processing system, and the image data stored in the first input side storage means and the second input side storage means The image data stored in the image data is image data partially overlapped in the main scanning direction, and outputs from the first processing system and the second processing system are selectively output and output in raster order. Selecting means.

  In the present invention, input image data is processed by a plurality of processing systems. Each image processing system is provided with an image processing means for performing filter processing, an input side storage means is provided upstream of the image processing means, and an output side storage means is provided downstream of the image processing means. The storage means on the input side and the output side do not need to be page memories, respectively, but may have a data amount that can be processed by the image processing means, and more specifically, may be approximately the same as the capacity of the line memory of the image processing means. The image data of the line in the main scanning direction is sequentially stored in the first input side storage unit and the second input side storage unit, and then supplied to the image processing unit and filtered. The filtered image data is stored in the first output side storage means and the second output side storage means, respectively. By selecting and outputting the first output storage means and the second output side storage means alternately by the selection means, the processed image data is output in raster order without providing a page memory.

  According to the present invention, there is provided an adding unit for adding identification data to the overlapped image data, and the first and second image processing units are configured such that the image data to which the identification data is added is the filter. Although used for processing, the data is not output to the first and second output-side storage means, and the first and second output-side storage means are image data filtered by the first and second image processing means. Among these, image data other than the image data to which the identification data is assigned is stored. The first input side storage means and the second input side storage means have overlapping data that overlap each other in the main scanning direction. This is image data to be referred to for filtering the pixel of interest, and output image data. Is essentially unnecessary image data. Therefore, only effective image data can be easily obtained by adding identification data to the image data and not storing the image data with the identification data in the output side storage means. Is output.

  Hereinafter, embodiments of the present invention will be described with reference to the drawings.

<Basic configuration>
FIG. 1 is a block diagram showing the configuration of the image processing apparatus according to this embodiment. In this embodiment, no page memory is provided, a plurality of FIFO memories 50 and 60 are provided in the preceding stage of image processing, and FIFO memories 54 and 64 are also provided in the subsequent stage of image processing. An image processing ASIC 52 is connected to the FIFO memory 50, and a FIFO memory 54 is connected to the image processing ASIC 52. An image processing ASIC 62 is connected to the FIFO memory 60, and a FIFO memory 64 is connected to the image processing ASIC 62. The FIFO memory 50, the image processing ASIC 52, and the FIFO memory 54 constitute a first processing system, and the FIFO memory 60, the image processing ASIC 62, and the FIFO memory 64 constitute a second processing system. A selector (SEL) 42 is connected to the FIFO memory 54 and the FIFO memory 64 to selectively output any one of the outputs.

  The FIFO memory 50 sequentially stores image data of a capacity that can be processed by the image processing ASIC 52, that is, image data having the same capacity or less as the line memory in the image processing ASIC 52, and supplies the image data to the image processing ASIC 52. The FIFO 60 is the same as the FIFO 50 and sequentially stores image data for a capacity that can be processed by the image processing ASIC 62 and supplies the image data to the image processing ASIC 62. The FIFO memories 50 and 60 store image data of a document to be processed in the main scanning direction, store image data of a line in the main scanning direction in the FIFO memory 50, and the remaining image data of the line. Is stored in the FIFO memory 60. It can be said that image data of a certain line in the main scanning direction is sequentially divided and stored in the FIFO memory 50 and the FIFO memory 60. More specifically, the first half of the first line of the document is stored in the FIFO memory 50, the second half of the first line is stored in the FIFO memory 60, and the first half of the second line is stored in the FIFO memory 50. For example, the second half of the second line is stored in the FIFO memory 60. 1/4 of the first line is stored in the FIFO memory 50, the next 1/4 of the first line is stored in the FIFO memory 60, the next 1/4 of the first line is stored in the FIFO memory 50, and The last quarter of one line can also be stored in the FIFO memory 60. When the document size is horizontally long such as A0, the latter is stored.

  The image data stored in the FIFO memory 50 and the FIFO memory 60 is stored by overlapping a part thereof in the main scanning direction by a necessary amount. The FIFO memories 50 and 60 output image data at a speed corresponding to the processing speed of the image processing ASICs 52 and 62, respectively. For the pixel data to be overlapped, that is, the boundary pixel data in the FIFO memories 50 and 60 in the main scanning direction, the FIFO control unit 40 gives identification data indicating that the pixel data is overlapped pixel data. Which pixel is the overlap pixel is determined by the number of pixels used for the filter processing. For example, the first two pixels and the last two pixels of the FIFO memories 50 and 60 are given the identification data as the overlap pixel data. To do.

  The FIFO control unit 40 creates and assigns identification data to the overlap pixel data as described above, and supplies the identification data to the image processing ASICs 52 and 62. The identification data is, for example, an overlap flag. A flag other than the overlap pixel data is not set (data is set to 0 or L (low)), and a flag is set to overlap image data (data is set to 1 or H). (High). When attention is paid to certain pixel data, the pixel value of the pixel and the over flag value of the pixel are supplied to the image processing ASICs 52 and 62 as a set. When the pixel value is represented by 8 bits, only 1 bit of the overlap flag may be added, and the pixel value of the pixel and the presence or absence of the overlap flag may be represented by a total of 9 bits. Of course, the set state of the overlap flag may be expressed by adding specific data only to the overlap pixel.

  Similar to the image processing ASIC 18 in the prior art, the image processing ASICs 52 and 62 include a necessary number of line memories and an image processing unit that performs filter processing such as 3 × 3. The image processing ASICs 52 and 62 store the image data supplied from the FIFO memories 50 and 60 in the line memory, respectively, and perform 3 × 3 filter processing using the image data stored in the line memory. The image processing ASICs 52 and 62 are supplied not only with the image data from the FIFO memories 50 and 60 but also with the overlap flag created by the FIFO control unit 40. The image processing ASICs 52 and 62 perform filter processing on the overlap flag. Without being performed, it is used as a write prohibition flag for the FIFO memories 54 and 64 in the subsequent stage. That is, the image processing ASICs 52 and 62 process the overlap flag as a write enable signal, write pixel data for which the overlap flag is not set to the FIFO memories 54 and 64, and set the overlap flag. For the existing pixel data, writing to the FIFO memories 54 and 64 is not performed. Overlap flag set = enable signal OFF, overlap flag not set = enable signal ON.

  The FIFO memories 54 and 64 sequentially store the image data filtered by the image processing ASICs 52 and 62, respectively.

  The selector 42 alternately selects and outputs the image data stored in the FIFO memory 54 and the FIFO memory 64, and controls the output image data to be arranged in raster order. Specifically, all the image data stored in the FIFO memory 54 is first read, then all the image data stored in the FIFO memory 64 is read, and then the image data stored in the FIFO memory 54 is read again. Output in raster order by repeating.

  In this embodiment, it is only necessary to provide a FIFO memory that stores image data having a capacity that can be processed by the image processing ASIC in the preceding and subsequent stages of image processing, and the page memory can be eliminated. Then, the processing of the first processing system including the FIFO memory 50, the image processing ASIC 52, and the FIFO memory 54 and the processing of the second processing system including the FIFO memory 60, the image processing ASIC 62, and the FIFO memory 64 are performed in parallel. Processing time can be shortened.

  Although not explicitly shown in the figure, a timing adjustment circuit for storing image data in the FIFO memories 50 and 60 and a timing adjustment circuit for outputting image data from the FIFO memory 54 and the FIFO memory 64 may be provided. Good.

<Processing timing>
FIG. 2 shows a timing chart of the processing of the present embodiment. FIG. 2A shows the timing of input image data sequentially input in the main scanning direction. It is assumed that a certain line (line 1) in the main scanning direction is input and the next line (line 2) is further input at a predetermined speed (for example, 100 MB / S).

  FIG. 2B shows the input timing of the FIFO memories 50 and 60. First, the image data of line 1 is input and stored in the FIFO memory 50, and then the remaining image data of line 1 is stored in the FIFO memory 60. Input and stored. More specifically, the writing of image data to the FIFO memory 60 is started at a timing slightly earlier than the timing of writing all the image data to the FIFO memory 50. This is because the image data at the end of the FIFO memory 50 is overlapped and stored at the head of the FIFO memory 60. The timing for writing to both FIFO memories is adjusted by a timing adjustment circuit. In the figure, FIFO (1) W means writing of image data to the FIFO memory 50, and FIFO (2) W means writing of image data to the FIFO memory 60. A shaded portion indicates overlap pixel data. For the overlap pixel data, the FIFO control unit 40 generates an overlap flag. Next, when the image data of line 2 is input, the image data is sequentially stored in the FIFO memory 50 and the FIFO memory 60 in the same manner. Pixel data existing at the boundary between the FIFO memory 50 and the FIFO memory 60 are overlapped and stored.

  FIG. 2C is a timing chart of the first processing system. The image data of line 1 stored in the FIFO memory 50 is read out and supplied to the image processing ASIC 52, which is already stored and stored in the line memory. 3 × 3 filter processing is executed in combination with the existing image data. In the case of 3 × 3 filter processing, the image data of the previous line and the image data of the previous two lines from the image data of the line input at the current timing are stored in the line memory. Both are supplied to the image processing unit and subjected to filter processing. The filter processing itself is the same as the conventional one, and is a matrix operation using the pixel of interest and its surrounding pixels. The filtered image data is sequentially stored in the FIFO memory 54. Reading of the image data from the FIFO memory 50 is performed at a speed that matches the processing speed of the image processing ASIC 52. Further, the FIFO control unit 40 supplies the overlap flag to the image processing ASIC 52 in association with the overlap pixel. The image processing ASIC 52 performs calculation using the 3 × 3 pixel data supplied from the FIFO memory 50, but the overlap flag itself is not used for the calculation. The image processing ASIC 52 determines whether or not the overlap flag is set in the pixel data when writing the filtered image data into the FIFO memory 54. If the overlap flag is not set, the FIFO 54 Write to memory 54. On the other hand, when the overlap flag is set for the pixel data, the image processing ASIC 52 discards the pixel data without writing it to the FIFO memory 54. As a result, only the filtered effective pixels (target pixels) are stored in the FIFO memory 54. In the figure, FIFO (1) R means reading of image data from the FIFO memory 50, and “processing” stores image data in a plurality of line memories of the image processing ASIC 52, and in the image processing unit using them. Means filtering. FIFO (1) ′ W means writing of image data to the FIFO memory 54. With the above processing, the processing of line 1 in the first processing system is completed.

  FIG. 2D is a timing chart for processing the next line 2 in the first processing system. The filter processing for line 1 is completed, and the image data for the next line 2 is sequentially read from the FIFO memory 50 and supplied to the image processing ASIC 52 in synchronization with the timing at which the processed image data is written to the FIFO memory 54. That is, after all the image data of line 1 stored in the FIFO memory 50 is read and supplied to the image processing ASIC 52, the writing of the line 2 immediately after the completion of the writing of the remaining image data of the line 1 to the FIFO memory 60 is completed. Since the image data has been written, the image data of line 2 can be read from the FIFO memory 50 at the timing of writing the processed image data of line 1 to the FIFO memory 54. The image processing ASIC 52 performs 3 × 3 filter processing using the read image data, and stores the processing result in the FIFO memory 54. At this time, the FIFO control unit 40 generates an overlap flag for the overlap data stored in the FIFO memory 50 and the FIFO memory 60 and supplies the overlap flag to the image processing ASIC 52. The overlap flag is set in the image processing ASIC 52. The image data is discarded without being written in the FIFO memory 54. As described above, the processing of the line 2 in the first processing system is completed.

  FIG. 2E is a timing chart showing processing of line 1 in the second processing system. The image data of line 1 stored in the FIFO memory 60 is sequentially read and supplied to the image processing ASIC 62. Reading from the FIFO memory 60 is executed in parallel with the reading of the image data of line 1 from the FIFO memory 50 and the filter processing in the image processing ASIC 52. In synchronization with the timing at which the image data of line 1 is written into the FIFO memory 60, the image data is sequentially read from the FIFO memory 60 and filtered by the image processing ASIC 62. When supplying image data from the FIFO memory 60 to the image processing ASIC 62, an overlap flag is generated in association with the overlap data from the FIFO control unit 40 and supplied to the image processing ASIC 62. The image data filtered by the image processing ASIC 62 is sequentially written into the FIFO memory 64. However, the image processing ASIC 62 discards the image data for which the overlap flag is set without writing it to the FIFO memory 64. In the figure, FIFO (2) R means reading of image data from the FIFO memory 60, and FIFO (2) 'W means writing of image data into the FIFO memory 64.

  FIG. 2F is a timing chart showing the processing of line 2 in the second processing system. At the timing when writing to the FIFO memory 64 is completed, the image data of line 2 stored in the FIFO 60 is sequentially read and supplied to the image processing ASIC 62. Thereafter, the image processing ASIC 62 performs filtering, and only the image data for which the overlap flag is not set is written in the FIFO memory 64.

  FIG. 2G is a timing chart for selecting and outputting the filtered image data stored in the FIFO memories 54 and 64 by the selector 42. Since the image data of line 1 filtered by the first processing system is stored in the FIFO memory 54, the selector 42 selects the FIFO memory 54, reads out the image data from the FIFO memory 54, and outputs it (output line (1)). ). Next, since the remaining image data of the line 1 filtered by the second processing system is stored in the FIFO memory 64, the selector 42 switches from the FIFO memory 54 to the FIFO memory 54, and reads the image data from the FIFO memory 64. (Output line (2)). As described above, all the filtered effective image data on line 1 are output. Next, since the image data of line 2 filtered by the first processing system is stored in the FIFO memory 54, the selector 42 selects the FIFO memory 54 again, reads out the image data from the FIFO memory 54, and outputs the image data ( Output line (1)). Thereafter, the remaining image data of the line 2 filtered by the second processing system is stored in the FIFO memory 64. Therefore, the selector 42 switches from the FIFO memory 54 to the FIFO memory 64, and reads the image data from the FIFO memory 64. Output (output line (2)). Therefore, the selector 42 outputs image data that has been subjected to filter processing in the order of rasters in order of line 1, line 2, line 3,.

  As described above, the image processing in the main scanning direction is distributed between the first processing system and the second processing system, and the processing is performed in parallel while adjusting the processing timing of the first processing system and the second processing system. It is possible to perform image processing at high speed without providing a memory and output the processing results in raster order.

And even if the document size is a landscape such as A0, it can be easily handled by storing image data in the main scanning direction alternately in the FIFO memories 50 and 60. Of course, not only two FIFO memories but also three or four FIFO memories can be provided as required. When three FIFO memories are provided, there are three third processing systems such as the first processing system and the second processing system as processing systems, and three FIFO memories provided in the preceding stage of the image processing ASIC, respectively. The image data is sequentially stored, and the three FIFO memories respectively provided in the subsequent stage of the image processing ASIC are sequentially switched by the selector and output.

<Overlap processing and edge processing>
FIG. 3 schematically shows the overlap processing and document edge processing when there are three FIFO memories. These three FIFO memories are referred to as FIFO (1), FIFO (2), and FIFO (3) for convenience.

  First, image data of a line in the main scanning direction of the document is stored in the FIFO (1). An overlap flag created by the FIFO control unit 40 is set in the pixel data at the head of the FIFO (1). In the figure, the overlap flag is indicated by an H signal. When the first image data of the line is stored in the FIFO (1), this portion is not inherently overlapping data, but by overlapping the image data outside the main scanning effective pixel width, the overlapping is performed. The set of flags can be used effectively. That is, the image data in which the overlap flag is set is not written in the FIFO memory at the subsequent stage of the image processing ASIC as described above, but the data outside the effective pixel width is not inherently valid image data. By controlling the writing of the image data with the overlap flag, it is possible to prevent unnecessary writing of the image data. The overlap flag created by the FIFO control unit 40 is also set in the pixel data at the end of the FIFO (1). In the figure, as an example, it is assumed that two pixels overlap each other, and H (high) is assigned to the last two pixels. These two pixels are invalid pixels that are not written to the FIFO memory in the subsequent stage (indicated by x in the figure). Note that when 3 × 3 filter processing is performed, one overlap pixel is sufficient.

  Next, the remaining image data in the same line in the main scanning direction is stored in the FIFO (2). An overlap flag created by the FIFO control unit 40 is set in the pixel data of the head part and the terminal part of the FIFO (2). The overlap pixels stored in both FIFO (1) and (2) are a total of four pixels, and the overlap flag is set for each two pixels in FIFO (1) and (2).

  Next, the remaining image data in the same line in the main scanning direction is stored in the FIFO (3). An overlap flag created by the FIFO control unit 40 is set at the head of the FIFO (3). If it is determined that the image data of the document is lost in the middle of the capacity of the FIFO (3) and the document reaches the end of the document, the FIFO control unit 40 similarly sets the overlap flag for the subsequent pixel data. By setting the overlap flag, this portion of the image data is discarded without being filtered.

  As described above, the FIFO control unit 40 sets the overlap flag for the overlap pixel, and similarly sets the overlap flag for image data other than the effective pixel width, thereby simplifying output of unnecessary image data. Can be prevented.

<Other configurations>
FIG. 4 shows a configuration in the case where four FIFO memories are provided in the front stage and the rear stage of the image processing ASIC.

  FIFO memories 50, 60, 70, and 80 are provided in the preceding stage of the image processing ASICs 52, 62, 72, and 82, respectively, and FIFO memories 54, 64, 74, and 84 are provided in the subsequent stages. The FIFO memory 50, the image processing ASIC 52, and the FIFO memory 54 constitute a first processing system, and the FIFO memory 60, the image processing ASIC 62, and the FIFO memory 64 constitute a second processing system. The FIFO memory 70, the image processing ASIC 72, and the FIFO memory 74 constitutes a third processing system, and the FIFO memory 80, the image processing ASIC 82, and the FIFO memory 84 constitute a fourth processing system.

  The input images are sequentially stored in the FIFO memories 50, 60, 70, 80. That is, the image data of a line in the main scanning direction is stored in the FIFO memory 50, the remaining image data of the same line is stored in the FIFO memory 60, and the remaining image data of the same line is stored in the FIFO memory 70. The remaining image data of the line is stored in the FIFO memory 80. It can also be said that image data of one line is divided and stored in the FIFO memories 50, 60, 70, 80. The pixel data at the boundary of each FIFO memory is stored partially overlapping each other. For the overlapped pixel data, the FIFO control unit 40 creates an overlap flag and supplies it to the image processing ASICs 52, 62, 72, and 82. The FIFO control unit 40 also applies an overlap flag to pixel data other than the effective pixel width existing at the head of the input image and pixel data other than the effective pixel width that may exist at the end of the input image as described above. Set. The overlap flag functions as an enable signal for controlling writing to the subsequent FIFO memory, and pixel data for which the overlap flag has been set is prohibited from being written to the subsequent FIFO memory. It should be noted that the overlap flag is not set when the image data of the input image fits the capacity of the FIFO memory 80 without any excess or deficiency.

  The FIFO memories 54, 64, 74, and 84 sequentially store the image data filtered by the image processing ASICs 52, 62, 72, and 82, respectively. The selector 42 sequentially selects and outputs the image data stored in the FIFO memories 54, 64, 74, and 84, and outputs them in raster order. The image processing ASICs 52, 62, 72, and 82 discard the pixel data for which the overlap flag is set, without writing it in the FIFO memories 54, 64, 74, and 84 in the subsequent stage. The overlap flag is supplied from the FIFO control unit 40 to the image processing ASICs 52, 62, 72, and 82. However, the image processing ASICs 52, 62, 72, and 82 do not perform any processing on the overlap flag and perform the FIFO as it is. The pixel data for which the overlap flag is set in the FIFO memories 54, 64, 74, and 84 may be discarded. In the figure, this is indicated by the fact that the overlap flag is supplied to the FIFO memory in the subsequent stage after passing through the image processing ASIC.

<Processing timing>
FIG. 5 shows a timing chart in the configuration of FIG. Assume that the document size is A0, and image data for one line in the main scanning direction of the document is stored in the FIFO memories 50, 60, 70, and 80.

  FIG. 5A is a timing chart of the input image, and shows two lines (line 1 and line 2). The image data of the line 1 is stored in the FIFO memories 50, 60, 70, 80, and the next line is read at the timing when the respective image data is read out and filtered by the image processing ASICs 52, 62, 72, 82. One image data is sequentially stored in the FIFO memories 50, 60, 70, and 80.

  FIG. 5B is an input timing chart of each FIFO memory. The image data of line 1 is sequentially stored in the FIFO memories 50, 60, 70, and 80. In the figure, FIFO (1) W means writing to the FIFO memory 50, and FIFO (2) W means writing to the FIFO memory 60. After the line 1 image data is written, the next line 2 image data is sequentially stored in the FIFO memories 50, 60, 70 and 80.

  FIG. 5C to FIG. 5F are processing timing charts in the first processing system to the fourth processing system. In the first processing system, as shown in FIG. 5C, image data is read from the FIFO memory 50 and supplied to the image processing ASIC 52. The image data is stored in a line memory in the image processing ASIC 52. When image data for the number of lines necessary for the filter processing is stored, the image data is supplied to the image processing unit. Perform filtering. The filtered image data is stored in the FIFO memory 54 at the subsequent stage. However, the pixel data for which the overlap flag is set is discarded by the image processing ASIC 52 without writing to the FIFO memory 54. The image data stored in the FIFO memory 54 is selected by the selector 42 and read out.

  On the other hand, in parallel with the filtering process in the first processing system, the filtering process is also performed in the second processing system. That is, the image data stored in the FIFO memory 60 is read out, supplied to the image processing ASIC 62, stored in the line memory in the image processing ASIC 62, and then subjected to filter processing using the necessary number of lines of image data. The filtered image data is sequentially stored in the FIFO memory 64 at the subsequent stage. The overlap pixel data located at the boundary with the FIFO memory 50 is not written to the FIFO memory 64 because the overlap flag is set. The image data stored in the FIFO memory 64 is selected by the selector 42 and read out.

  Similarly, the filter processing is performed in the third processing system in parallel with the filter processing in the first processing system and the second processing system. That is, the image data stored in the FIFO memory 70 is read out, supplied to the image processing ASIC 72, stored in the line memory in the image processing ASIC 72, and then subjected to filter processing using the image data of the necessary number of lines. The filtered image data is sequentially stored in the FIFO memory 74 at the subsequent stage. The overlap pixel data located at the boundary with the FIFO memory 60 is not written to the FIFO memory 74 because the overlap flag is set. The image data stored in the FIFO memory 74 is read by the selector 42.

  Similarly, the filter processing is performed in the fourth processing system in parallel with the filter processing in the first processing system, the second processing system, and the third processing system. That is, the image data stored in the FIFO memory 80 is read out, supplied to the image processing ASIC 82, stored in the line memory in the image processing ASIC 82, and then subjected to filter processing using the required number of lines of image data. The filtered image data is sequentially stored in the FIFO memory 84 at the subsequent stage. The overlap pixel data located at the boundary with the FIFO memory 70 is not written to the FIFO memory 84 because the overlap flag is set. Also, pixel data outside the effective pixel width stored at the end of the FIFO memory 84 is not written to the FIFO memory 84 because the FIFO control unit 40 sets the overlap flag. The image data stored in the FIFO memory 84 is selected by the selector 42 and read out.

  The first processing system starts the process for line 2 after the process for line 1 is completed. That is, the image data of line 2 stored in the FIFO memory 50 is read out and supplied to the image processing ASIC 52 to perform filter processing. The same applies to other processing systems.

  FIG. 5G shows an output timing chart from the selector 42. After the line 1 image data is filtered in the first processing system and stored in the FIFO memory 54, the selector 42 selects the FIFO memory 54 and outputs the image data. Next, since the image data filtered by the second processing system is stored in the FIFO memory 64, the selector 42 switches from the FIFO memory 54 to the FIFO memory 64 and outputs the image data. Next, since the image data filtered by the third processing system is stored in the FIFO memory 74, the selector 42 selects the FIFO memory 74 and outputs the image data. Next, since the image data filtered by the fourth processing system is stored in the FIFO memory 84, the selector 42 selects the FIFO memory 84 and outputs the image data. As described above, the image data of line 1 is output. The same applies to the image data of line 2. Since the image data of line 2 filtered in parallel in each system is sequentially stored in the FIFO memories 54, 64, 74, 84, the selector 42 switches between these. The image data of line 2 is output sequentially. As described above, the filtered image data is output in raster order.

It is a configuration block diagram of an embodiment. 2 is a processing timing chart in the configuration of FIG. 1. It is processing explanatory drawing of the overlap pixel in the structure of FIG. It is another composition block diagram of an embodiment. 5 is a processing timing chart in the configuration of FIG. 4. It is a block diagram of a conventional apparatus.

Explanation of symbols

  40 FIFO control unit, 42 selector, 50 FIFO memory (input side), 52 image processing ASIC, 54 FIFO memory (output side), 60 FIFO memory (input side), 62 image processing ASIC, 64 FIFO memory (output side).

Claims (3)

An image processing apparatus that performs image processing of a pixel of interest with reference to surrounding pixels,
First and second image processing means including a line memory, and a filter circuit that performs a filter process using the pixel of interest and its peripheral pixels stored in the line memory;
First and second input side storage means for sequentially storing image data of an amount of data that can be processed by the image processing means among the input image data and supplying the image processing section to the image processing section;
First and second output side storage means for sequentially storing the image data filtered by the image processing unit;
Have
The first input side storage means, the first image processing means, and the first output side storage means are connected in series to form a first processing system, and the second input side storage means, the second input side storage means, The image processing means and the second output side storage means are connected in series to form a second processing system, and the input image is processed in parallel in the main scanning direction by the first processing system and the second processing system,
The image data stored in the first input side storage means and the image data stored in the second input side storage means are image data partially overlapped in the main scanning direction,
Selection means for selectively outputting outputs from the first processing system and the second processing system and outputting them in raster order;
An attaching means for giving identification data to the overlapped image data;
And the first and second image processing means do not output the image data to which the identification data is given to the first and second output side storage means although they are used for the filtering process.
The first and second output-side storage means store image data other than the image data to which the identification data is assigned, among the image data filtered by the first and second image processing means. An image processing apparatus. The apparatus of claim 1 .
The image processing apparatus according to claim 1, wherein when the image data outside the document size is stored in the first and second input side storage units, the adding unit adds the identification data to the image data. The apparatus according to claim 1,
The image processing apparatus according to claim 1, wherein the first and second input side storage means and the first and second output side storage means are FIFO memories.

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