JP4376573B2 - Semiconductor memory device - Google Patents

Description

  The present invention relates to a semiconductor memory device, and more particularly to a semiconductor memory device that reduces power consumption.

  Conventionally, a synchronous static random access memory (SRAM) performs an internal operation based on a synchronization signal to perform reading and writing. Based on the synchronization signal, the previously accessed data is initialized internally and the next address is accessed.

  FIG. 12 shows a block diagram of a conventional 1-port SRAM. FIG. 13 shows an example of a memory cell.

  A conventional 1-port SRAM will be described with reference to FIG. The 1-port SRAM 200 includes a memory cell array 10 in which memory cells are arranged in a matrix, a read / write circuit 20 that performs read and write operations on the memory cell array 10, and a row decoder 40 that specifies an address of the memory cell array 10. A column decoder 50, a control circuit 30, and an input / output circuit 70 that transfers data between the read / write circuit 20.

  The control circuit 30 receives the synchronization signal CK, the write enable signal WEB, and the chip enable signal CEB, generates a signal DEN to be given to the row decoder 40 and the column decoder 50, and signals WEN and SEN to be given to the read / write circuit 20, and outputs them. To do.

  The synchronization signal CK is a clock signal for controlling the operation of the SRAM. WEN is a write control signal that is set to L level (L active) when a write operation is instructed, and is set to H level when a read operation is instructed. SEN is a read control signal that is set to L level (L active) when a read operation is instructed, and H level when a write operation is instructed.

  Address signals AAD0 to AADn are applied to address buffer circuit 60, and address signals AAD0 to AADn are applied to row decoder 40 and column decoder 50 from address buffer circuit 60. The row decoder 40 selects a specific word line in order to select a specific memory cell according to an address signal supplied from the address buffer circuit 60. The column decoder 50 supplies a signal for selecting a bit line for selecting a specific memory cell to the read / write circuit 20 based on the address signal supplied from the address buffer circuit 60.

  The read / write circuit 20 transmits / receives read data and write data to / from memory cells through a bit line corresponding to an address signal. The input / output circuit 70 temporarily stores data read from the memory cell and data to be written to the memory cell.

  As shown in FIG. 13, the memory cell array 10 includes, for example, a memory cell 103 composed of CMOS inverters 101 and 102 connected in a cross-shaped manner, and access transistors 105 and 106 provided for the memory cell 103. .

  Corresponding to each row of memory cells 103, a word line WL is provided. Word line WL is selectively activated by row decoder 40 operating in response to address signals AAD0-AADn. When data is written to or read from the memory cell 103, the access transistors 105 and 106 transmit the data to the bit lines BL and BLB according to the activation of the word line WL, and the data is transferred to and from the read / write circuit 20. Will be given and received.

  In the conventional synchronous SRAM described above, when “H” (“L”) is input to the synchronization signal (CK), the designated address is accessed and the read / write operation is performed.

  When “L” (“H”) is input to the synchronization signal, the bit lines BL and BLB are boosted (precharged) to a predetermined voltage in preparation for the next access. In recent years, with the increase in cycle time, the end of the read operation is internally detected, and a precharge operation is performed in which the external clock (CK) changes with the internally generated clock (CK).

  For this reason, even if there is no change in address or data, when the clock (CK) is input, an access operation is performed, and a normal operation is performed on the entire SRAM circuit. This increases current consumption.

  For this reason, even when the same address is accessed, power is similarly consumed when another address is accessed.

By the way, there is a method of precharging only a specific bit line to reduce current consumption (see, for example, Patent Document 1).
JP 2000-195260 A

  In the method described in Patent Document 1 described above, current consumption cannot be reduced because normal operation is performed for access to the same address.

  In view of the above circumstances, the present invention detects an address change or input data change, determines whether or not to perform a normal operation when a clock is input, and performs a read operation to the same address or the same data An object is to reduce current consumption by automatically stopping unnecessary operations such as writing.

The semiconductor memory device according to the present invention detects and detects a change in an address signal in a semiconductor memory device in which a plurality of memory cells are arranged in a matrix and a read operation and a write operation are performed using arbitrary address information and an external synchronization clock. A detection circuit for outputting a signal, a means for controlling propagation of the clock to the read circuit based on a detection signal from the address change detection circuit, and detecting a change from a write operation to a read operation and outputting a detection signal A mode change detection circuit that detects a change from a write operation to a read operation by the mode change detection circuit and detects an address change by a detection signal from the address change detection circuit. Then, prohibits be transferred to the read data output circuit write data And wherein the door.

In addition, in a semiconductor memory device in which a plurality of memory cells are arranged in a matrix and have a plurality of access systems, each performing read and write operations independently using arbitrary address information and an external synchronization clock, address signal changes A detection circuit that detects the signal and outputs a detection signal; means for controlling propagation of the clock to the read circuit based on the detection signal from the address change detection circuit; and detects that the write operation has changed to the read operation. A mode change detection circuit that outputs a detection signal in response to the mode change detection circuit, wherein the control means detects a change from a write operation to a read operation by the mode change detection circuit, and also detects a detection signal from the address change detection circuit. When the address change is detected by, the write data is transferred to the read data output circuit It characterized in that it prohibited the Rukoto.

  According to the above configuration, in the synchronous semiconductor memory device, current consumption can be suppressed by not performing the internal operation even when the clock signal moves without an address change during the read operation.

According to the first aspect of the present invention, in the synchronous semiconductor memory device, when the write mode is changed to the read mode and the address changes, it is prohibited to transfer the write data to the read data output circuit. , Excess current consumption can be suppressed.

According to the second aspect of the present invention, the same effect as described above can be realized for a multi-port semiconductor memory device.

  Embodiments of the present invention will be described below with reference to the drawings. FIG. 1 is a block diagram showing a configuration of a synchronous SRAM according to the first embodiment of the present invention. The same parts as those of the SRAM shown in FIG. 12 are denoted by the same reference numerals, and the description thereof is omitted here in order to avoid duplication of explanation.

  As shown in FIG. 1, an address transition detection circuit (ATD: Address Transition Detector) 80 is a circuit that detects a change in address and generates a high-level signal, receives an address signal from an address buffer 60, and receives an address signal. A change signal is detected and a detection signal is output. This detection signal is given to the control circuit 30 as an internal operation permission signal (SATD).

  As described above, the control circuit 30 receives the synchronization signal CK, the write enable signal WEB, and the chip enable signal CEB, the signal DEN to be supplied to the row decoder 40 and the column decoder 50, and the signals WEN and SEN to be supplied to the read / write circuit 20. Is generated and output. In this embodiment, in the read mode, the write enable signal WEN is “H”, the read sense signal SEN is “H”, and in the write mode, the write enable signal WEN is “L”. The write signal WEN becomes “H”.

  In the read mode of the synchronous SRAM, when the address changes before the synchronization signal CK operates, the ATD circuit 80 sends an internal operation permission signal (SATD) based on the address change detection to the control circuit 30. Based on the detection of the internal operation permission signal (SATD), the control circuit 30 sets the SEN signal to “H” based on the external synchronization signal CK and operates the read / write circuit 20 to perform normal operation.

  After the operation is completed, the control circuit 30 deactivates the internal operation permission signal (SATD) to prohibit the operation. Next, when there is no address change until the synchronization signal CK operates, the internal operation permission signal (SATD) remains in a prohibited state, and even if the external synchronization signal CK operates, the internal operation permission signal (SATD) is prohibited. Since the state remains, the control circuit 30 does not send a signal for internal operation.

If the address does not change during the read operation, the read data also does not change, and the memory does not need to operate. Therefore, the data held in the input / output circuit 70 may be output as it is .

The above operation will be described with reference to the timing chart of FIG. When the address changes before the synchronization signal CK operates, the ATD circuit 80 detects the address change and the internal operation permission signal (SATD) becomes the high level (81). Then, at the rising edge of the synchronization signal CK, the control circuit 30 supplies the signal DEN to the row decoder 40 and the column decoder 50 and the read / write circuit 20 when the internal operation permission signal SATD is at a high level, that is, in the activated state. Generate and output signals WEN and SEN. The internal operation permission signal SATD is deactivated after a predetermined time delay from the rising edge of the clock CK (82). When there is no change in address, the internal operation permission signal SATD maintains the inactive state. DEN, WEN, and SEN become inactive after a predetermined time delay from the fall (32) of the synchronization signal CK. The internal operation period is from the rising edge 31 of the clock CK until DEN, WEN, and SEN become inactive.

  Even if the synchronous clock CK operates (33, 34) while the internal operation permission signal (SATD) remains inactive while there is no change in address, DEN, WEN, and SEN are inactive between the inactive fields. No action is taken. When the address changes, the internal operation permission signal (SATD) becomes high level (83), and DEN, signals WEN and SEN are generated and output at the rising edge of the synchronization signal CK.

  In the first embodiment described above, when the address does not change and the write mode is changed to the read mode, it is necessary to output write data. At this time, the written data is performed as it is by the read operation. For example, in a circuit configured so that the write data can be transferred to the read data output circuit, the write data is not read but output. Write data can be output by the operation of transferring to the circuit.

  Next, a second embodiment of the present invention will be described. FIG. 3 is a block diagram showing a configuration of a synchronous SRAM according to the second embodiment of the present invention. The same parts as those in the conventional example and the first embodiment are denoted by the same reference numerals, and the description thereof is omitted here in order to avoid duplication of explanation.

  In the first embodiment described above, when the address does not change and the write mode is changed to the read mode, it is necessary to output the write data. However, when the address is changed, it is not necessary to output the write data.

  Therefore, in the second embodiment, a mode change detection circuit 90 that detects a change in the read / write mode is provided. This mode change detection circuit 90 determines the state of the write enable signal (WEB) given from the control circuit 30, detects that the mode has changed from the state of this signal, and sends the detection result signal (MTD) to the control circuit. 30. The control circuit 30 changes the write mode to the read mode based on the address change detection signal (SATD) and the read / write mode change detection signal (MTD), and reads the write data in the read / write circuit 20 when the address changes. A signal (DRW) that prohibits transfer to the output circuit is output to reduce excessive current consumption.

  Next explained is the third embodiment of the invention. FIG. 4 is a block diagram showing a configuration of a synchronous SRAM according to the third embodiment of the present invention. The same parts as those in the conventional example and the first embodiment are denoted by the same reference numerals, and the description thereof is omitted here in order to avoid duplication of explanation.

  In the third embodiment, a data change detection circuit 91 is provided, and the data change detection circuit 91 detects whether the write data has changed in the previous write data. In the write mode, the data change detection circuit 91 detects whether or not the write data has changed from the previous write data, and outputs a detection signal (SDTD) to the control circuit 30. Then, the control circuit 30 enables the write data latch signal when the write data is changed, captures the write data, and when the write data does not change, the control circuit 30 keeps the latch signal in the latched state by the data capture prohibition signal (DLA). Keep it. As a result, when the write data is not changed, the signal controlled by the latch does not operate, so that current consumption can be reduced.

  Next explained is the fourth embodiment of the invention. FIG. 5 is a block diagram showing a configuration of a synchronous SRAM according to the fourth embodiment of the present invention. In addition, the same code | symbol is attached | subjected to the same part as said conventional example, 1st, 3rd embodiment, and the description is omitted here in order to avoid duplication of description.

  In the fourth embodiment, the power consumption is reduced when the same address and the same data as in the previous cycle are written in the write mode.

  In the write mode, when writing the same address and the same data as in the previous cycle, the memory does not need to operate, but if the external synchronization signal CK is received, the write operation is performed.

  Therefore, in the fourth embodiment, a change in address and a change in write data are detected and the operation is controlled. When the address changes before the synchronization signal CK operates, the ATD circuit 80 detects an address change, and when the write data change detection circuit 91 detects that the write data changes, the control circuit 30 The internal operation permission signal (DRW) is transmitted, and the normal operation is performed based on the external synchronization signal CK. After the operation is completed, the internal operation permission signal (SATD) is deactivated, the operation is prohibited, and there is no need to operate when there is no change in address and no change in write data until the next synchronization signal CK operates. The operation permission signal is kept inactive and no unnecessary operation is performed, thereby reducing current consumption.

  Each of the above embodiments describes a 1-port SRAM. However, even in a multi-port SRAM, the same effect can be obtained by adding a similar circuit to each port.

  In the third and fourth embodiments described above, the synchronous SRAM has been described. However, the present invention can also be applied to an asynchronous memory. Regarding writing, regardless of whether it is synchronous or asynchronous, power consumption can be reduced by adopting the above-described configuration. In the case of an asynchronous memory, a clock is generated based on address information.

  Next explained is the fifth embodiment of the invention. FIG. 6 is a block diagram showing a configuration of a mask ROM according to the fifth embodiment of the present invention. The fifth embodiment differs from the first embodiment in the circuit configuration associated with the fact that the type of memory is ROM, and since it is a ROM, it has the configuration of a read circuit 20a and an output circuit 7a. However, the configuration is basically the same as that of the first embodiment.

  In the synchronous mask ROM (programming data in the manufacturing process), when the address changes before the synchronous signal CK operates, the ATD circuit 80 detects the address change and sends an internal operation permission signal (SATD). The control circuit 30 performs a normal operation based on the external synchronization signal CK. After the operation is completed, the internal operation enable signal is deactivated to disable the operation, and when there is no address change until the next synchronization signal CK operates, the internal operation enable signal remains disabled and the external synchronization signal CK operates. However, the internal operation is not performed because the internal operation permission signal remains in the prohibited state.

  In the above-described embodiment, the mask ROM is described. However, a similar circuit is added to the reading circuit unit for an EPROM, an EEPROM, or the like which is a writable ROM in which a user can arbitrarily write data. Thus, a similar effect can be realized.

  An example of the change detection circuit in the address change detection circuit 80 and the data change detection circuit 91 is shown in FIG. These detection circuits are different in whether the input is address information data or write data, and the configuration for detecting changes in those data is the same. As shown in FIG. 7, in the change detection circuit in the address change detection circuit 80 or the data change detection circuit 91, address information data or write data is given to the inverter 801. The signal is output from the inverter 801 to one terminal of the NAND circuit 806 and the NOR circuit 807 via the inverter 802. Data obtained by delaying the output of the inverter 802 by the inverters 803 to 805 is given to the other inputs of the NAND circuit 806 and the NOR circuit 807. The output of the NAND circuit 806 is supplied to one input of the NOR circuit 809 via the inverter 808, and the output of the NOR circuit 807 is supplied to the other of the NOR circuit 809. The output of the NOR circuit 809 is supplied to the inverter 810, and a pulse signal is output from the inverter 810. That is, when the address information data or write data signal changes, the rising edge and the falling edge are detected, and a pulse signal is generated from the inverter 810.

  FIG. 8 shows an example of a circuit that collects the signals of the change detection circuits of the address change detection circuit 80 and the data change detection circuit 91. The change detection circuit shown in FIG. 7 detects a change with respect to one data line, and the address change detection circuit 80 and the data change detection circuit 91 are composed of a plurality of change detection circuits. The output of the change detection circuit is given to the gates of the transistors 81-0 to 81-n. The sources of these transistors are grounded, the drains are connected in common, and the output is output from the inverter 84 as a detection signal. The commonly connected drains are supplied with a power supply potential via a transistor 82 and grounded via a capacitor 83. The circuit shown in FIG. 8 combines the pulse-like signals from which changes in the respective signals are detected, and generates and outputs a pulse-like signal (SATD) (SDTD) from the inverter 84.

An example of the read / write mode change detection circuit 90 is shown in FIG. As shown in FIG. 9, in the read / write mode change detection circuit 90, the write enable signal (WEB) given from the control circuit 30 is input to the inverter 901, and is transferred from the inverter 901 to one terminal of the NAND circuit 906 via the inverter 902. Is output. Data obtained by delaying the output of the inverter 902 by the inverters 903 to 905 is applied to the other input of the NAND circuit 906. The output of the NAND circuit 906 is given to the inverter 907, and a mode change detection signal is output from the inverter 907.

  An example of a circuit that generates an internal operation inhibition signal is shown in FIG. After the operation is finished, a prohibition signal is set, a signal in which an address or data change is detected is applied to one of the NOR circuits 910, and an output signal thereof is applied to one of the NOR circuits 911. A synchronization signal CK is given to the other of the NOR circuit 911. Then, the output of the NOR circuit 911 is given to the other of the NOR circuit 910, the output of the NOR circuit 910 is given to the inverter 912, and an internal operation inhibition signal is outputted from the inverter 912. In this way, after the operation is completed, the prohibition signal is set, an address or data change is detected, and the internal operation prohibition signal is output using the signal as a reset signal.

  FIG. 11 shows an example of a circuit that outputs a signal prohibiting transfer of input data to the output circuit. A signal (MTD) changed from the writing mode to the reading mode and the internal prohibition signal are supplied to the NAND circuit 920, an output of the NAND circuit 920 is supplied to the inverter 921, and a signal (DRW) is output from the inverter 921. As described above, when the signal changed from the write mode to the read mode is pulsed, when the input data is transferred to the output circuit, the pulse is not generated by performing a logical operation with the internal operation inhibition signal. Circuit.

1 is a block diagram showing a configuration of a synchronous SRAM according to a first embodiment of the present invention. 3 is a timing chart showing an operation of the synchronous SRAM according to the first embodiment of the present invention. It is a block diagram which shows the structure of the synchronous SRAM concerning 2nd Embodiment of this invention. It is a block diagram which shows the structure of the synchronous SRAM concerning 3rd Embodiment of this invention. It is a block diagram which shows the structure of the synchronous SRAM concerning 4th Embodiment of this invention. It is a block diagram which shows the structure of the synchronous SRAM concerning the 5th Embodiment of this invention. It is a circuit diagram which shows an example of the change detection circuit in an address change detection circuit and a data change detection circuit. It is a circuit diagram which shows an example of the circuit which puts together the signal of a change detection circuit. It is a circuit diagram which shows an example of the reading / writing mode change detection circuit. It is a circuit diagram which shows an example of the circuit which generates an internal operation prohibition signal. It is a circuit diagram which shows an example of the circuit which outputs the signal which prohibits transferring input data to an output circuit. It is a block diagram of the conventional 1 port SRAM. It is a circuit diagram which shows an example of a memory cell.

Explanation of symbols

10 memory cell array 20 read / write circuit 30 control circuit 40 row decoder 50 column decoder 60 input / output circuit 70.

80 Address change detection circuit 90 Mode change detection circuit 91 Data change detection circuit

Claims (2)

In a semiconductor memory device in which a plurality of memory cells are arranged in a matrix and a read operation and a write operation are performed using arbitrary address information and an external synchronization clock, a detection circuit that detects a change in an address signal and outputs a detection signal; Means for controlling propagation of the clock to the read circuit based on a detection signal from the address change detection circuit, and a mode change detection circuit for detecting a change from a write operation to a read operation and outputting a detection signal; And the control means detects the change from the write operation to the read operation by the mode change detection circuit and reads the write data when the address change is detected by the detection signal from the address change detection circuit. the semiconductor memory instrumentation to and inhibits a transfer to the circuit . A plurality of memory cells are arranged in a matrix, and there are multiple access systems, and each address signal and external synchronization clock are independently used to detect address signal changes in a semiconductor memory device that performs read and write operations. Detection circuit for outputting a detection signal, means for controlling propagation of the clock to the read circuit based on the detection signal from the address change detection circuit, and detecting and detecting a change from the write operation to the read operation A mode change detection circuit for outputting a signal, wherein the control means detects a change from a write operation to a read operation by the mode change detection circuit, and also detects an address by a detection signal from the address change detection circuit. When a change is detected, the write data is transferred to the read data output circuit. The semiconductor memory device characterized by prohibiting.

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