JP4388397B2 - MODULE TEMPLATE DATA STRUCTURE AND MULTI-CHIP INTEGRATED DEVICE DESIGN SYSTEM AND DESIGN METHOD - Google Patents

Description

  The present invention relates to a design technique for a multi-chip integrated device, and more particularly, to a design technique for a multi-chip integrated device capable of performing a design in which circuit design and mounting design are consistent.

  In recent years, SiP (System in Package) technology, which can minimize the newly developed parts by effectively utilizing existing LSI chips, has been rapidly developed to complement SoC (System on Chip) technology. ing.

  Further, as an extension of the current SiP technology, research and development aiming at higher performance and higher functionality by integrating dissimilar materials and devices in one package is progressing. SiGe (silicon germanium), InP (indium phosphorus), GaAs (gallium arsenic), which has better speed performance than the silicon semiconductors that currently occupy the majority, GaN (gallium nitride), etc., which has superior pressure resistance By integrating the compound semiconductor integrated chip, it is possible to realize ultrahigh speed performance and ultrahigh withstand voltage performance that cannot be realized with a silicon semiconductor. And the application range of integrated circuits is expected to further expand. Furthermore, the SiP technology enables the integration of light, bio, chemical sensors, etc., which are currently making remarkable progress, beyond the bounds of materials and logic. With these technological developments, the application range of SiP is expected to expand at a stretch.

  Hereinafter, in the present specification, a device in which two or more integrated logic circuit chips, such as the above-mentioned SiP, are integrated via a connection medium is referred to as a “multi-chip integrated device”.

  In a multi-chip integrated device, a plurality of chips are arranged in one package and connected by a connection medium. Therefore, it is important to achieve consistency between a circuit design in which each chip is combined to design one circuit and a mounting design in which chips necessary for the circuit configuration are arranged and connected in the package.

  As a design method for integrating circuit design and mounting design by unifying design data between circuit design and mounting design, those described in Patent Document 1 and Non-Patent Documents 1 to 3 are known. is there.

  FIG. 16 is a block diagram showing the configuration of the design apparatus described in Patent Document 1. The design apparatus includes a component database 101, a circuit design CAD (Computer Aided Design) device 102, a mounting design CAD device 103, a pattern design CAD device 104, and design data 105. The component database 101 stores logical function data and physical shape data of each component used for design.

  The circuit design CAD device 102 performs circuit design using the logical function data of each component stored in the component database 101. The circuit design parameters constructed by the design are transferred as design data 105 to the mounting design CAD device 103. The mounting design CAD device 103 performs mounting design using physical shape data of each component stored in the component database 101. At this time, the mounting design parameters are additionally constructed in the design data 105. The design data 105 to which the mounting design parameters are added is passed to the pattern design CAD device 104. The pattern design CAD device 104 performs mounting design using the physical shape data and design data 105 of each component and board stored in the component database 101.

In this way, by sharing the component database 101 and the design data 105 among the circuit design CAD device 102, the mounting design CAD device 103, and the pattern design CAD device 104, the circuit design and the mounting design are matched. Yes.
JP-A-11-184908 GA Katopis, et al., "MCM technology and design for the S / 390 G5 system", IBM J. RES. DEVELOP., Vol.43, No.5 / 6, pp.621-650, 1999. Azad M. Madni and Carla C. Madni, "An Adaptive Wide-area Design Process Manager for Collaborative Multichip Module Design", IEEE Multi-Chip Module Conference 1997 (MCMC-97), Proc., Pp.63-72, 1997. SJ Yang, et al., "High Speed I / O Buffer Design for MCM", IEEE Multi-Chip Module Conference 1997 (MCMC-97), Proc., Pp.52-57, 1997.

  By the way, in the multi-chip integrated device, the effect of the arrangement and connection of the mounted chips on the electrical characteristics becomes a problem. In particular, in a multi-chip integrated device that operates at a high frequency, a parasitic effect that causes signal degradation associated with the increase in the frequency increases. That is, in the high frequency region, frequency characteristics of circuit parameters, crosstalk (coupling) between transmission lines, signal wraparound noise caused by power supply impedance, and the like become obvious.

  However, in the conventional design system, the circuit design parameters can be referred to in the chip mounting design, but the magnitude of the parasitic effect cannot be evaluated. In addition, the effects of these parasitic effects on the electrical characteristics of a circuit are often clarified by performing electromagnetic simulation based on the physical shape of the circuit. It cannot be easily derived by just looking.

  On the other hand, even if the circuit design of the chip is designed with the electrical characteristic specifications at the high frequency of the chip and given as design data at the packaging design stage, the given design data is seen in the packaging design. Therefore, it is not possible to easily derive physical design parameters that satisfy the specifications. In particular, when the wiring between chips becomes complicated, it is practically difficult to perform a mounting design that fully considers a given high-frequency electrical characteristic specification.

  Therefore, conventionally, in the circuit design of the multi-chip integrated device, the circuit design parameter and the mounting design parameter are independently performed by the circuit design CAD device and the mounting design CAD device, respectively. Accordingly, there is a problem that the influence of the physical shape at the time of mounting on the electrical characteristics is not sufficiently reflected in the mounting design, and the design rule in the mounting design is not reflected in the circuit design.

  Therefore, when designing a multi-chip integrated device that operates at a high frequency, the influence of the parasitic effect is found after the packaging design or after the trial production, and a change in the circuit design or the packaging design is often required. (Turn Around Time).

  On the other hand, in order to shorten the development TAT, it is necessary to design with an extra design margin in the circuit design in consideration of the influence of a parasitic effect that may become a problem after mounting design. This increases the restrictions on circuit design and causes an increase in design effort for realizing a desired circuit.

  As described above, the conventional design method has a drawback that the design efficiency in designing a multi-chip integrated device operating at a high frequency is poor.

  By the way, when designing a multi-chip integrated circuit using a plurality of chips manufactured using different kinds of materials or different kinds of logic, generally, the power supply voltage and logic level used in each chip circuit are different. To do. Therefore, a logic level transformer is used to absorb the difference between the power supply voltage and the logic level. “Logic level transformer (Logic level transform circuit)” refers to a circuit that performs logic level conversion between circuits having two or more logic levels.

  For example, compound semiconductor devices manufactured using the above-described SiGe, InP, GaAs, GaN, and the like are different from Si devices in terms of electrical characteristics unique to each material. Therefore, when these various compound semiconductor devices are combined with Si devices to form an integrated logic circuit, appropriate power supply voltages and logic interfaces differ among the chips.

  Specifically, for example, SiGe compound semiconductor devices use Ge as a base material, which has a lower band gap energy than Si. Therefore, a bipolar transistor made of a SiGe compound has a lower breakdown voltage than that of a Si device. Therefore, the power supply voltage needs to be lower than that of the Si device, and the logic operation requires a lower logic amplitude operation than that of the Si device.

  That is, in Si devices, a wide range of logic levels ranging from 3 V to 350 mV, such as general CMOS logic, low voltage complementary logic (LVCMOS) logic, and low voltage deferential signal (LVDS) logic. Is used. In addition, a positive logic interface that operates at a positive power supply voltage and a logic level interface that operates at a level higher than 0 V is employed. In contrast, SiGe devices generally employ an ECL (Emitter-Coupled Logic) type logic level interface having an amplitude of about 250 mV to 400 mV. In addition, the ECL normally employs a negative logic interface that operates with a negative power supply voltage and the logic level interface also operates at a level lower than 0V.

  Also, in other InP and GaAs, when used for applications that take advantage of high speed, most of them are ECL systems suitable for high speed operation, negative logic interfaces such as SCFL (Source Coupled FET Logic), etc. Is adopted.

  In this way, when a multi-chip integrated circuit is configured using different types of devices and logic circuits, a logic level transformer is connected to connect a negative logic chip such as ECL and a positive logic chip such as CMOS / LVDS. Is needed.

  In designing a multi-chip integrated circuit, various logic level transformers such as ECL to CMOS and ECL to LVDS as described above are registered in the component database in advance as standardized cells and IP (Intellectual Property). It is selected and used according to the chip used for the design. When mounted on a multi-chip integrated circuit, the connection medium between the chip and the logic level transformer is usually a combination of solder bumps and metal wiring formed on a connection substrate called an interposer. That is, the signal pad of the first integrated logic circuit is electrically connected to the signal pad on the connection board via the solder bump, and further from the far-end signal pad via the solder bump via the metal wiring on the connection board. To the signal pad of the second integrated logic circuit.

  In such a multi-chip integrated circuit, impedance matching between each chip and the logic level transformer is a problem when connecting and mounting chips having different logic level interfaces using the logic level transformer. It becomes.

  As described above, in the conventional multi-chip integrated circuit design method, the design of the mounting parameters of the mounting wiring portion including the mounting substrate is performed independently of the design of the circuit parameters of the chip. Therefore, on the circuit design side of the chip, the electrical characteristics of the mounting wiring portion cannot be optimally determined according to the integrated circuit in the chip. In other words, the electrical connection conditions such as characteristic impedance, termination condition, and current load driving force suitable for the logic level transformer and the integrated logic circuit connected to the input side / output side cannot be determined as optimum conditions. For this reason, it is necessary to design a logic level transformer with a sufficient design margin in the fluctuation range of these electrical connection conditions assumed in the mounting portion.

  For example, when the signal wiring length of the mounting portion is extended, a large current load driving force is required for the signal output stage circuit. Therefore, it is necessary to form a circuit with transistors with large current consumption. When the signal wiring length further expands and reaches about one-tenth of the wavelength of the maximum frequency component included in the signal (for example, in the signal wiring running on the surface of the mounting substrate having a frequency of 10 GHz and a relative dielectric constant of 6) For a length of about 12 mm), the signal wiring is regarded as a transmission line. Therefore, the characteristic impedance becomes the load impedance. Therefore, the signal output circuit of the logic level transformer is required to have a current driving capability that can drive the load impedance. Further, if the input impedance of the next-stage integrated logic circuit to be connected does not match the characteristic impedance of the line, signal reflection occurs. For this reason, if the output impedance of the signal output circuit does not match the characteristic impedance of the line, the signal reflection further multi-reflects at the input end and adversely affects the next stage circuit such as malfunction. In order to avoid such problems, the impedance matching function is added to the signal output circuit of the logic level transformer, and then the characteristic impedance of the signal wiring is specified, or the characteristic impedance of the signal wiring and the next stage circuit are specified. It is necessary to define the impedance matching condition when connecting the or the circuit specifications. Thus, in the conventional design method, since the signal wiring environment that affects the high frequency performance cannot be specified, the operation speed performance and the operation frequency band performance of the circuit are limited.

  In addition, a multi-chip in which integrated logic circuits, heterogeneous devices, and heterogeneous logic interfaces are integrated, and logic level transformers must be prepared as standard cells or core IPs for each logic level interface combination. In an integrated device, the number of standard cells or the number of core IPs is extremely large. As a result, there is a problem that the development cost and design time of the multi-chip integrated device increase.

  Accordingly, an object of the present invention is to facilitate design in consideration of the correlation between the electrical characteristics in circuit design of each chip and the mounting design parameters when mounting the chip, thereby improving the design efficiency. Another object of the present invention is to provide a design technology for a multi-chip integrated device capable of designing a circuit having high operation speed performance and high operation frequency band performance.

  Another object of the present invention is to maximize the performance of each semiconductor element even in the design of a multi-chip integrated device in which integrated circuits of many different materials, different devices, and different logic interfaces are integrated. The object is to provide a logic level transformer design technique that can be realized and achieve high performance, ease of design, and reduction of development cost at the same time.

The data structure of the module template according to the present invention includes the following various tables.
(1) Circuit design parameter information including parameters related to circuit characteristics of the module (hereinafter referred to as “circuit design parameters”);
(2) Mounting design parameter information including parameters for mounting the circuit of the module (hereinafter referred to as “mounting design parameters”);
(3) and conversion information including information on a mutual derivation function for deriving one from the other between each circuit design parameter and each mounting design parameter.

  By using a module template having such a data structure, design information in circuit design and packaging design is shared in designing a multi-chip integrated device. Then, when determining the circuit design parameters of the module used by the designer at the time of circuit design, the designer uses the mutual derivation function defined in the correlation table to implement the circuit design parameters to be determined. Parameters can be determined. Therefore, it becomes easy for the designer to proceed with the circuit design while verifying the conformity with the mounting restrictions based on the design rules when designing the circuit of the multi-chip integrated device.

  Further, when the designer determines the mounting design parameters of each module during mounting design, the circuit parameters for the mounting design parameters to be determined can be obtained using the mutual derivation function defined in the correlation table. Therefore, it becomes easy for the designer to proceed with the mounting design while verifying the compatibility with the range of circuit design parameters allowed for the module in the entire circuit during the mounting design of the multi-chip integrated device. .

  Accordingly, the module template used in the design system of the multi-chip integrated device has the data structure of the module template as described above, so that the design information can be obtained by the circuit design and the mounting design of the multi-chip integrated device. It becomes easy to make the design parameters consistent between the two designs.

  Here, the “module” refers to a unit of a standardized circuit that can be physically separated. The “module” mentioned here includes various IP (intellectual property) cores and wiring networks.

  “Circuit design parameters” refer to input / output impedance of the module, circuit parameters (resistance, inductance, capacitance, etc.) of each component in the module, and the like. The “mounting design parameter” refers to a parameter for mounting a module such as a dimension, a physical parameter such as an electrical characteristic of a material used for the module, and the like.

  In the present invention, the module is a wiring network that connects chips, and the circuit design parameter information includes a parameter group that represents a characteristic impedance of a transmission line and a matching termination circuit as circuit design parameters. It can be set as a structure.

  By using a module template having such a data structure, design information in circuit design and packaging design is shared in designing a multi-chip integrated device. Then, at the time of circuit design, it is possible to design by designating electrical characteristics while taking into account the mounting restrictions of the connection wiring portion between the chips at the time of mounting. On the other hand, at the time of mounting design, since the electrical characteristics of the connection wiring portion between the chips are specified, the mounting design parameters can be derived from the circuit design parameters by the mutual derivation function. If mounting design is performed within the range of the given mounting design parameters, it is possible to perform mounting design that is consistent with circuit design even in connection wiring.

A first configuration of a design system for a multi-chip integrated device according to the present invention includes the following configuration.
(1) a. Circuit design parameter information including parameters relating to the circuit characteristics of the module (hereinafter referred to as “circuit design parameters”); b. Mounting design parameter information including parameters for mounting the circuit of the module (hereinafter referred to as “mounting design parameters”); c. And a module library storing a module template having conversion information including information on a mutual derivation function for deriving one from the other between each circuit design parameter and each mounting design parameter;
(2) When one of the circuit design parameters and the mounting design parameters is input to the module selected from the module library, the other parameter is calculated by referring to the conversion information. The parameter derivation means.

  When designing a circuit of a multi-chip integrated device using such a design system, when the designer determines the circuit design parameters of each module used for the design, each circuit design parameter is determined by the parameter deriving means. Implementation design parameters for can be derived and referenced. Therefore, it is possible to proceed with the circuit design while verifying the compatibility with the constraints on the mounting by the design rule or the like.

  On the other hand, at the time of mounting design, when the designer determines the mounting design parameters of each module, the circuit parameter for each mounting design parameter can be obtained by the parameter deriving means. Therefore, it is easy to proceed with the mounting design while verifying whether or not the circuit design parameter range allowed for each module specified in the circuit design is satisfied during the mounting design.

  Therefore, it becomes easy to design a multi-chip integrated device while maintaining consistency of design parameters between circuit design and mounting design.

  According to a second configuration of the design system of the multi-chip integrated device according to the present invention, in the first configuration, the module library includes a module template of a wiring network that connects chips. Features.

  In this way, by registering the module template of the wiring network that connects the chips to the module library, multi-chip integration is possible by specifying the circuit design parameters for the connection wiring between the chips during circuit design. The device can be designed. Then, the mounting design parameter can be derived by the parameter deriving means from the circuit design parameter of the connection wiring between the chips specified in the circuit design. In the mounting design, the mounting design of the wiring network for connecting the chips can be performed using the mounting design parameters. This makes it possible to easily design the electrical connection conditions between the chips.

  According to a third configuration of the design system of the multi-chip integrated device according to the present invention, in the second configuration, the circuit design parameter information in the module template of the wiring network includes a transmission path as a circuit design parameter. A parameter group representing the characteristic impedance and matching termination circuit is included.

  As a result, it is possible to determine the parameter group representing the characteristic impedance of the transmission line and the matching termination circuit in the circuit design, and to design the electric transmission characteristic. In addition, by determining these parameter groups in circuit design, it is possible to impose restrictions on the range of selection of each mounting design parameter of the transmission path in mounting design. In mounting design, when selecting a mounting design parameter, the parameter deriving means derives the circuit design parameter from the mounting design parameter to be selected, and is compatible with the circuit design previously determined in the circuit design. By verifying the above, it is possible to perform mounting design that realizes the transmission characteristics of the wiring network determined in the circuit design.

  The fourth configuration of the multi-chip integrated device design system according to the present invention is that in the second or third configuration, the module library has a logic level of an input signal (hereinafter referred to as “input logic level”). )), And a module template of a logic level conversion core that converts the output logic level to a logic level different from the input logic level and outputs the converted logic level is included.

  In this way, a logic level transformer with various input / output impedances can be designed by combining the logic level conversion core and the wiring network in the module library as separate module templates. Is possible.

  That is, when a wiring network having various input / output impedances is combined with one logic level conversion core, a logic level transformer having various input / output impedances is configured using one logic level conversion core. be able to. Therefore, it is not necessary to prepare a logic level transformer module template having a wide variety of input / output impedances. By preparing a small number of logic level conversion cores and combining wiring networks according to the purpose, the desired input / output can be obtained. A logic level transformer having impedance may be designed.

  Accordingly, the design resources can be effectively utilized and the design freedom of the logic level transformer is improved.

A fifth configuration of the design system for a multi-chip integrated device according to the present invention is any one of the first to fourth configurations,
A circuit design CAD device for referring to the module library and using the module template to design a circuit of a multi-chip integrated device;
A mounting design CAD device for mounting design of a multi-chip integrated device designed by a circuit design CAD device;
Design information storage means for storing design information of the multi-chip integrated device;
The circuit design CAD device and the mounting design CAD device construct common design information stored in the design information storage means, and the parameter derivation means includes circuit design parameters or When any one of the mounting design parameters is input, the other parameter is calculated with reference to the conversion information and added to the design information stored in the design information storage means. Features.

  According to this configuration, when the circuit design parameter of the multi-chip integrated device is input to the circuit design CAD device, the parameter deriving unit refers to the conversion information to calculate the mounting design parameter and stores it in the design information storage unit. Add to the stored design information. When mounting design of a multi-chip integrated device is performed by the mounting design CAD device, the mounting design parameters included in the design information stored in the design information storage means are referred to and the design margin of the circuit design parameters is set. Applicable mounting design can be performed. Thus, by sharing the design information between the circuit design CAD device and the mounting design CAD device, it becomes extremely easy to match the design parameters between the circuit design and the mounting design.

A method for designing a multi-chip integrated device according to the present invention comprises: a. Circuit design parameter information including parameters relating to the circuit characteristics of the module (hereinafter referred to as “circuit design parameters”); b. Mounting design parameter information including parameters for mounting the circuit of the module (hereinafter referred to as “mounting design parameters”), and c. A module template having conversion information including information on a mutual derivation function for deriving one from the other between each parameter included in the circuit design parameter information and each parameter included in the mounting design parameter information is stored. Module library;
A circuit design CAD device for referring to the module library and using the module template to design a circuit of a multi-chip integrated device;
A mounting design CAD device for mounting design of a multi-chip integrated device designed by a circuit design CAD device;
And design information storage means for storing design information of the multi-chip integrated device;
A design method for designing a multi-chip integrated device using a system comprising: the circuit design CAD device and the mounting design CAD device construct common design information stored in the design information storage means In addition, when one of the circuit design parameters and the mounting design parameters is input in the design information, the other parameter is calculated with reference to the conversion information and stored in the design information storage means. The design information is updated.

In the method for designing a multi-chip integrated device according to the present invention, the module library includes
A module template of a logic level conversion core that detects a logic level of an input signal (hereinafter referred to as “input logic level”), converts the logic level to a logic level different from the input logic level, and outputs the logic level;
And module templates for wiring networks that connect chips;
By combining the module template of the logic level conversion core and the module template of the wiring network, design information of the logic level transformer that connects the chips can be constructed.

  As described above, according to the data structure of the module template according to the present invention, a multi-chip integrated device is obtained by adopting a data structure including three of circuit design parameter information, mounting design parameter information, and a correlation table. At the time of designing, it becomes easy to share design information between circuit design and mounting design, and to ensure consistency of design parameters between the two designs.

  In addition, according to the design system for a multi-chip integrated device according to the present invention, it is easy to design a multi-chip integrated device while maintaining consistency of design parameters between circuit design and mounting design. It becomes. Therefore, the circuit design can be performed while taking into consideration that the mismatch of the electrical characteristics between the modules occurring in the mounting design does not occur. This eliminates the need for an excessive circuit design parameter design margin width. In addition, by designing the multi-chip integrated device while verifying the consistency of design parameters in the circuit design process and the mounting design process, the design correction work due to design mismatch between the two is eliminated, and the development TAT is reduced. It can be shortened.

  In addition, by preparing a module template of a wiring network for connecting chips in the module library, it is possible to easily design electrical connection conditions between chips. Therefore, the design accuracy of the multi-chip integrated device can be improved. In particular, when designing a high-frequency circuit, it becomes easy to design desired performance with respect to power consumption, operating speed, operating frequency, and the like.

  Furthermore, by sharing the design information between the circuit design CAD device and the mounting design CAD device, it becomes extremely easy to match the design parameters between the circuit design and the mounting design. Therefore, the design efficiency of the multi-chip integrated device can be further improved.

  The best mode for carrying out the present invention will be described below with reference to the drawings.

  FIG. 1 is a diagram showing the configuration of a design system for a multi-chip integrated device according to Embodiment 1 of the present invention.

  The multi-chip integrated device design system includes a plurality of module libraries 1 in which a plurality of module templates 2 are stored. Each module template 2 has circuit design parameter information including circuit design parameters, mounting design parameter information including mounting design parameters, and conversion information including information on mutual derivation functions.

  As the module template 2, module templates of various core IPs, logic level conversion cores, and input / output wiring networks are stored.

  These module libraries 1 are connected to a circuit design CAD device 4 and a mounting design CAD device 5 via a network 3. The circuit design CAD device 4 is a CAD device that refers to the module library 1 and uses each module template 2 to design a circuit of a multi-chip integrated device. The mounting design CAD device 5 is a CAD device that refers to the module library 1 and uses each module template 2 to perform mounting design of a multi-chip integrated device.

  The design information output from the circuit design CAD device 4 and the mounting design CAD device 5 is stored in a common design information storage unit 6. The circuit design CAD device 4 and the mounting design CAD device 5 can refer to and edit common design information from the design information storage means 6.

  Furthermore, parameter deriving means 7 is connected to the design information storage means 6. The parameter deriving means 7 refers to the conversion information of the module when either the circuit design parameter or the mounting design parameter is input in each module in the design information stored in the design information storage means 6. Then, the other parameter is derived and stored in the design information of the design information storage means 6.

  The circuit design CAD device 4, the mounting design CAD device 5, the design information storage means 6, and the parameter derivation means 7 are constituted by programs, and are realized by reading this program into a computer and executing it.

  FIG. 2 is a diagram illustrating a data structure of the module template 2 according to the first embodiment of the present invention. The module template 2 includes attribute information 2a, a circuit design table 2b, a mounting design table 2c, and a conversion table 2d.

  In the attribute information 2a, information related to module attributes is recorded. Circuit design information, mounting design information, and conversion information are recorded in the circuit design table 2b, the mounting design table 2c, and the conversion table 2d, respectively.

  FIG. 3 shows a specific example of the module template 2. The module template in FIG. 3 is an example of a module template for a wiring network.

  In the attribute information, information related to the cell name, the function classification, and the attribute classification is recorded. The “cell name” is a name for specifying this module. The “function classification” is a classification related to the function of the module. For example, “input wiring network for logic level conversion”. In the “attribute classification”, a parameter group indicating the characteristic impedance of the transmission line and the matching termination is recorded. Specifically, the parameter group indicating the matching end is as shown in (Table 1).

  Circuit design information determined by the circuit design CAD device 4 is recorded in the circuit design table. This is specifically determined by each module. For example, in the case of a module template of a wiring network, parameters such as those described in the “LCRK determination parameter” and “LCRK determination parameter value” fields of FIG. 3 are recorded.

  In the mounting design table, mounting design information determined by the mounting design CAD device 5 is recorded. This is also determined specifically by each module. For example, in the case of a module template of a wiring network, parameters such as those described in the “structural parameters” and “material parameters” fields of FIG. 3 are recorded.

  In the conversion table, information on a mutual derivation function between the circuit design parameter and the mounting design parameter is recorded. For example, in the case of a wiring network module template, formulas for determining the resistance R, inductance L, capacitance C, and mutual inductance K of the transmission path from the values of “structural parameters” and “material parameters” and formulas for determining the characteristic impedance Z Is recorded. These formulas are given in the form of a numerical table (lookup table) obtained by a theoretical formula or simulation based on the unique shape of each module.

  A design method using the multi-chip integrated device design system according to the present embodiment configured as described above will be described below.

  FIG. 4 is a flowchart showing the overall design flow of the multi-chip integrated device. First, when a design request is received (S1), the designer gives an instruction for selecting a job to perform chip design or SiP design to the computer (S2). When a chip design instruction is input, the computer activates the circuit design CAD device 4 and executes a chip design support operation (S3). Since the chip design is not directly related to the present invention, a detailed description is omitted.

  On the other hand, when an instruction for SiP design is input, the computer first activates the circuit design CAD device 4 and starts SiP design (S4). First, the designer inputs to the circuit design CAD device 4 the specifications of the multi-chip integrated device to be designed. When the specifications of the multi-chip integrated device are input, the circuit design CAD device 4 creates a new design information file in the design information storage means 6 and stores the specifications of the multi-chip integrated device in the file. Save (S5).

  Next, the designer inputs an instruction for selecting a module to be used for design to the circuit design CAD device 4. When an instruction for module selection is input, the circuit design CAD device 4 refers to the specifications of the multi-chip integrated device previously stored in the design information file, and determines the module template 2 used for circuit design as the module Search and extract from library 1. The extracted module template 2 is stored in the design information file (S6).

  FIG. 5 is a flowchart showing the module selection operation. First, the circuit design CAD device 4 extracts a module (core IP) used for the design from the specifications of the multi-chip integrated device. Then, the module template 2 of the core IP is searched and extracted from the module library 1 and stored in the design information storage means 6 (S11).

  Next, the circuit design CAD device 4 extracts the coupling relationship of each core IP from the specifications of the multi-chip integrated device. Then, the module template 2 of the core IP connected to each other is referred to inspect the power supply voltage, logic level, etc. of both core IPs. Then, the module template 2 of the logic level conversion core required between the core IPs is searched and extracted as necessary, and stored in the design information file (S12).

  Next, the circuit design CAD device 4 refers to the module template 2 and extracts input / output impedance, matching termination circuit, and output circuit information of the core IP or logic level conversion core connected to each other. Then, the module template 2 of the input / output wiring network required between the core IPs or logic level conversion cores is searched and extracted as necessary, and stored in the design information file (S13, S14). The module selection operation is thus completed.

  Returning to FIG. 4, next, the designer performs circuit design using the circuit design CAD device 4 (S7), and then performs mounting design using the mounting design CAD device 5 (S8).

  FIG. 6 is a flowchart showing the flow of circuit design. First, the designer refers to the module template 2 of the preceding chip for each core IP or logic level conversion core (hereinafter referred to as “core IP” unless otherwise specified) (S21). Then, an output circuit for the preceding chip is described and stored in the design information storage means 6 (S22).

  Next, the module template 2 of the input wiring network between the preceding chip and the core IP is referred to (S23). Then, each circuit design parameter of the module template 2 of this input wiring network is designed and stored in the design information storage means 6 (S24).

  Next, the module template 2 of the core IP is referred to (S25). Then, each circuit design parameter of the module template 2 of the core IP is designed and stored in the design information storage means 6 (S26).

  Next, the module template 2 of the output wiring network between the subsequent chip and the core IP is referred to (S27). Then, each circuit design parameter of the module template 2 of this output wiring network is designed and stored in the design information storage means 6 (S28).

  Finally, the designer refers to the module template 2 of the subsequent chip of each core IP (S29). Then, an input circuit for the subsequent chip is described and stored in the design information storage means 6 (S30).

  The design in steps S21 to S30 is executed for the entire circuit of the multi-chip integrated device, and the entire circuit is synthesized (S31). When the entire circuit synthesis is completed, the designer inputs a circuit simulation instruction to the circuit design CAD device 4. As a result, the circuit design CAD device 4 simulates the entire circuit using a predetermined test pattern (S32). Then, the designer determines the performance of the designed circuit from the result of the circuit simulation (S33). If the desired performance is not obtained, the cause is analyzed, a correction guideline is formulated (S34), and the circuit is redesigned.

  If a desired performance is obtained as a result of the circuit simulation, the process proceeds to the next mounting design (S8).

  FIG. 7 is a flowchart showing the flow of mounting design. First, the designer refers to the module template 2 of the preceding chip for each core IP (S41). Then, the mounting parameters of the output circuit for the preceding chip are described and stored in the design information storage means 6 (S42).

  At this time, when a mounting parameter is input, the parameter deriving means 7 refers to the conversion table of the module template 2 and derives a circuit parameter for the mounting parameter. The calculated value of the circuit design parameter is displayed on the display screen together with the design value recorded in the circuit design table. The designer adjusts the mounting parameters so that the design values of the two match.

  Next, the module template 2 of the input wiring network between the preceding chip and the core IP is referred to (S43). Then, each mounting design parameter of the module template 2 of this input wiring network is designed and stored in the design information storage means 6 (S44).

  At this time, when a mounting parameter is input, the parameter deriving means 7 refers to the conversion table of the module template 2 and derives a circuit parameter for the mounting parameter. For example, in the case of the example of FIG. 3, the structural parameters and material parameters in the mounting design table are input as design values. Then, the parameter deriving means 7 calculates the LCRK parameter value and the characteristic impedance value for these structural parameters and material parameters based on the LCRK parameter derivation formula and the characteristic impedance derivation formula of the conversion table. The calculated LCRK parameter value and characteristic impedance value are substituted into the corresponding portions of the attribute information and the circuit design table, and each parameter value is displayed on the display screen of the mounting design CAD device. At this time, the circuit design parameters stored in the circuit design table are also displayed. The designer looks at this calculated value and confirms whether or not the designed mounting design parameter is within the range of the given circuit design parameter. If it is not within the range of the given circuit design parameter, the mounting design parameter is corrected. If it is within the range of the given circuit design parameter, the design value is determined by the mounting design parameter. In this way, the design values of the mounting design parameters and the circuit design parameters can be matched.

  Next, the module template 2 of the core IP is referred to (S45). Then, each mounting design parameter of the module template 2 of the core IP is designed and stored in the design information storage means 6 (S46). In this case as well, the design is performed while matching the circuit design parameters at the time of designing the mounting design parameters.

  Next, the module template 2 of the output wiring network between the subsequent stage chip and the core IP is referred to (S47). Then, each mounting design parameter of the module template 2 of this output wiring network is designed and stored in the design information storage means 6 (S48). In this case as well, the design is performed while matching the circuit design parameters at the time of designing the mounting design parameters.

  Finally, the designer refers to the module template 2 of the subsequent chip of each core IP (S49). Then, the mounting design parameters of the input circuit for the subsequent chip are described and stored in the design information storage means 6 (S50). In this case as well, the design is performed while matching the circuit design parameters at the time of designing the mounting design parameters.

  The design in steps S41 to S50 is executed for the entire circuit of the multi-chip integrated device. Then, layout synthesis of the entire circuit is performed (S51).

  Next, the mounting design CAD device 5 performs connection verification of each wiring based on the design information stored in the design information storage unit 6 (S52). Then, the mounting design CAD device 5 converts the parasitic components of the circuit calculated by the mutual derivation function stored in the conversion table into an equivalent circuit for the mounting design parameters of each module and imports them into the circuit (S53).

  When the above mounting design is completed, the designer inputs a circuit simulation instruction to the circuit design CAD device 4. As a result, the circuit design CAD device 4 simulates the entire circuit using a predetermined test pattern (S54). Then, the designer determines the performance of the designed circuit from the result of the circuit simulation (S55). If the desired performance is not obtained, the cause is analyzed, a correction guideline is formulated (S56), and the mounting is redesigned.

  When the desired performance is obtained as a result of the circuit simulation, the design is terminated. This completes the design of the multi-chip integrated device.

  As described above, according to the present invention, it is possible to design a multi-chip integrated device while maintaining consistency of design parameters between circuit design and mounting design. Therefore, by designing the multi-chip integrated device while verifying the consistency of the design parameters in the circuit design process and the mounting design process, the design correction work due to the design mismatch between the two is eliminated, and the development TAT is reduced. It can be shortened.

[Design example]
Next, a design example of a logic level transformer using this design system will be specifically described.

  First, the configuration of the logic level transformer to be designed, and the configuration of the logic level conversion core and the input wiring network which are its components will be described.

  FIG. 8 is a block diagram showing the configuration of the logic level transformer. A logic level interface signal is output from the logic output signal terminal a of the first integrated logic circuit chip 11. This logic output signal is guided to the input signal terminal b of the input wiring network 12. Then, it is guided to the output signal terminal c through the transmission line 13 formed in the input wiring network 12. Further, the signal is led to the input signal terminal d of the logic level conversion core 14. The logic level conversion core 14 includes a cascade connection of an input signal detection block 15 and a logic level conversion output block 16. Input signal detection block 15 detects an input signal level that is compatible with at least two or more logic level interfaces. The logic level conversion output block 16 selectively converts to one of signal levels compatible with at least two or more logic level interfaces different from the input signal level and outputs the signal level. A signal converted into a desired logic level interface is output from the output signal terminal e of the logic level conversion core 14. The logic output signal is guided to the input signal terminal f of the output wiring network 17. Then, it is guided to the output signal terminal g through the transmission line 18 formed in the output wiring network 17. Further, it is guided to the logic input signal terminal h of the second integrated logic circuit chip 19. A logic level transformer 20 is configured by integrating the input wiring network 12, the logic level conversion core 14, and the output wiring network 17.

  FIG. 9 is a mounting cross-sectional view of the logic level transformer. In FIG. 9, the first integrated logic circuit chip 11, the transmission line 13, the logic level conversion core 14, the transmission line 18, and the second integrated logic circuit chip 19 are the same as those in FIG.

  Metal transmission lines 13 and 18 are formed on the surface of the mounting substrate 21. The first integrated logic circuit chip 11 is connected to one end of the transmission line 13 via a solder bump 22. A logic level conversion core 14 is connected to the other end of the transmission line 13 and one end of the transmission line 18 via solder bumps 23 and 24. A second integrated logic circuit chip 19 is connected to the other end of the transmission line 18 via a solder bump 25.

  The input wiring network 12 extending from the logic output signal terminal a to the input signal terminal d is realized by a line extending from the solder bump 22 and the transmission line 13 to the solder bump 23. The output wiring network 17 from the output signal terminal e to the logic input signal terminal h is realized by a line from the solder bump 24 to the solder bump 25 through the transmission line 18.

  FIG. 10 is a circuit diagram illustrating a configuration example of the logic level conversion core. Transistors Q1, Q2, and Q3 constitute an input-stage differential pair circuit. Transistors Q4 and Q5 are connected to collector terminals of the differential pair Q1 and Q2 via feedback resistors R1 and R2. The collector terminals of the differential pair Q1, Q2 are simultaneously connected to the input terminals of the differential pair circuit in the output stage composed of the transistors Q6, Q7, Q8. The collector terminals of the output stage differential pair Q6, Q7 are connected to the pull-up power supply voltage Vcc via load resistors R3, R4.

The collector terminals of the output stage differential pair Q6 and Q7 become complementary output terminals V ₃ and V ₄ through the base input terminals of the transistors Q4 and Q5 which perform parallel feedback. Transistors Q3 and Q8 are constant current source transistors of an input stage differential pair and an output stage differential pair, respectively. Current control voltages V ₅ and V ₆ are applied to the base terminals of the transistors Q3 and Q8, respectively. The emitter terminals of the transistors Q3 and Q8 are connected to the pull-down power supply voltage Vee via negative feedback resistors R5 and R6.

Input signal V ₁ of the level is compared with the voltage of the base terminal V ₂ of Q2 is detected as a logic low level / high level. For example, if the pull-up voltage is set to 3.3V and the pull-down voltage is set to about -3V and the transistors Q1 to Q8 are formed of silicon bipolar transistors, an emitter coupled logic circuit (ECL) having an input level of 0V to -0.8V, It is possible to detect the input signal levels of the source coupled FET logic circuit (SCFL), the low level ECL (LECL) of the input level 0V to -0.4V, and the plurality of logic interfaces of the low level SCFL (LSFFL).

The output signal levels of the output signal terminals V ₃ and V ₄ are adjusted by adjusting the current control voltages V ₅ and V ₆ to 0V to + 5V CMOS, 0V to + 3.3V, 0V to + 2.6V, 0V to +1. The signal level of any one of 5V, low voltage CMOS logic (LVCMOS) of 0V to 1.0V and low voltage differential signal logic (LVDS) of + 1.0V to + 1.35V can be output.

  FIG. 11 is a diagram showing an example of the configuration of an input wiring network that is a component of a logic level transformer. This figure shows an electrical equivalent circuit of a configuration example of an input wiring network that conforms to the input logic level interface of the logic level conversion core shown in FIG.

  As an output circuit form of a logic level interface such as ECL, SCFL, LECL, LSCFL assumed in the first integrated logic circuit chip 11, there is an output stage circuit of an emitter follower type or a source follower type. One end of a transmission line 13 having a characteristic impedance matched to the output impedance Zout (generally lower than 50Ω) of the emitter follower or the source follower is connected to the logic output signal terminal a. This is a general-purpose configuration connected to the input signal terminal d of the logic level conversion core 14 via the. In this example, the characteristic impedance of the transmission line matches the output impedance of the logic output signal terminal a of the first integrated logic circuit chip 11. As a result, even if the length of the transmission line becomes as long as the wavelength of the upper limit frequency of the passing signal, high-quality signal transmission and connection without waveform distortion can be achieved.

  FIG. 12 is a diagram showing another example of the configuration of the input wiring network that is a component of the logic level transformer. This input wiring network is compatible with the input logic level interface of the logic level translation core 14. In the first integrated logic circuit chip 11, an open collector form is assumed as an output circuit form of ECL, SCFL, LECL, LSCFL. Therefore, in the input wiring network of FIG. 12, one end of the transmission line 13 having a characteristic impedance of 50Ω is connected to the logic output signal terminal a. Further, the input signal terminal d of the logic level conversion core 14 is connected to the other end of the transmission line 13. A 50Ω termination resistor R7 is connected as a load in the immediate vicinity of the input signal terminal d of the logic level conversion core 14.

  In this case, the input impedance of the input signal terminal d of the logic level conversion core 14 becomes approximately 50Ω due to the 50Ω termination resistor R7. Therefore, the characteristic impedance of the transmission line needs to match the input impedance of the input signal terminal d of the logic level conversion core 14. As a result, even if the length of the transmission line becomes as long as the wavelength of the upper limit frequency of the passing signal, high-quality signal transmission and connection without waveform distortion can be achieved.

  FIG. 13 is a diagram showing an example of the configuration of the output wiring network that is a component of the logic level transformer. This input wiring network is suitable when the output logic level interface of the logic level conversion core 14 is CMOS or LVCMOS.

  This output wiring network assumes an open collector form having a collector load resistance as an output circuit form of the logic level conversion core 14. The output impedance of the output signal terminal e of the logic level conversion core 14 can be approximated as the resistance value of the collector load resistor R3 shown in FIG. 10: Zout (generally on the order of 100Ω). Therefore, one end of a transmission line 18 having a characteristic impedance matched with the output impedance Zout is connected to the output signal terminal e of the logic level conversion core 14. The other end is connected to the logic input signal terminal h of the second integrated logic circuit chip 19 via the transmission line 18.

  In this output wiring network, it is necessary to match the characteristic impedance of the transmission line to the output impedance of the output signal terminal e of the logic level conversion core 14. With this matching, even if the length of the transmission line is as long as the wavelength of the upper limit frequency of the passing signal, high-quality signal transmission and connection without waveform distortion can be achieved.

FIG. 14 is a diagram showing another example of the configuration of the output wiring network that is a component of the logic level transformer. This output wiring network is designed on the assumption that the output logic level interface of the logic level conversion core 14 is LVDS. In this example learn the LVDS standard, complement output signal terminal _e a, _{e b} complementary signal transmission lines connected to 18a, and shunt-connected to the far end of the 18b by the resistance R1 of 100 [Omega, each second integrated logic circuit chip 19 Are connected to the complementary logic signal input terminals h _a and h _b .

In this case, for each of the complementary signal transmission lines, the input impedance at the far end (input terminals c and d) looks almost 50Ω. Therefore, it is necessary to configure each of the complementary signal transmission lines to have a characteristic impedance of 50Ω. In this example, the characteristic impedances of the transmission lines 18 a and 18 _b are designed to match the input impedances of the logic signal input terminals h _a and h _b of the second integrated logic circuit chip 19. As a result, even if the length of the transmission line becomes as long as the wavelength of the upper limit frequency of the passing signal, high-quality signal transmission and connection without waveform distortion can be achieved.

  An example in which the logic level transformer as described above is designed by the design system of this embodiment will be described below.

  FIG. 15 is a diagram showing the design process of the logic level transformer. The module library 1 includes a module template (not shown) of the logic level conversion core 14 and module templates a1 to an, b1 to various input wiring networks 12 and output wiring networks 17 as described above. bm is prepared.

  First, templates of the first integrated logic circuit chip 11 and the second integrated logic circuit chip 19 are selected. Then, a template of the logic level conversion core 14 adapted to these logic levels and output circuits is selected.

  Here, with respect to one logic level conversion core 14 which is a component of a logic level transformer and performs a conversion / connection function of a plurality of logic level interfaces, an input wiring network 12 and an output which are other components The wiring network 17 is assumed to have many forms according to the logic level interface of the integrated logic circuit chip to be connected. Therefore, a unique template including characteristic impedance of the transmission line and termination circuit information suitable for connection with the logical level interface is created in the module library 1 for each logical level interface assumed in advance. Yes.

  15, a1, a2, a3,..., An are prepared in advance as module templates of the input wiring network 12, and b1, b2, b3,.

  For example, assume that the logic level interface of the first integrated logic circuit chip 11 is an SCFL open collector format. A3 is selected as a template that matches this. Based on the characteristic impedance of the transmission line defined in the template a3 and the termination circuit information, the actual mounting design parameters of the input wiring network 12 are designed.

  Similarly, it is assumed that the logic level interface of the second integrated logic circuit chip 19 is LVDS. B3 is selected as a template that matches this. Based on the characteristic impedance of the transmission line defined in the template b3 and the termination circuit information, the actual mounting parameters of the output wiring network 17 are designed. Finally, the input wiring network 12, the logic level conversion core 14, and the output wiring network 17 are integrated to form a logic level transformer 20.

In this way, the designer of the logic level transformer 20 can add appropriate input / output wiring networks 12 and 17 to be combined with the logic level conversion core 14 according to the required connection / conversion specifications of the logic level interface. The template can be obtained quickly and accurately. In addition, it is possible to quickly design a circuit by using a module template.
(End of design example)

It is a figure showing the structure of the design system of the multi-chip integration apparatus which concerns on Example 1 of this invention. It is a figure showing the data structure of the module template which concerns on Example 1 of this invention. It is a figure showing the specific example of a module template. It is a flowchart showing the flow of the whole design of a multichip integrated device. It is a flowchart showing module selection operation. It is a flowchart showing the flow of circuit design. It is a flowchart showing the flow of mounting design. It is a block block diagram showing the structural example of a logic level transformer. It is a mounting sectional view of a logic level transformer. It is a circuit diagram showing the example of 1 structure of a logic level conversion core. It is a figure which shows an example of a structure of the input wiring network which is a component of a logic level transformer. It is a figure which shows another example of a structure of the input wiring network which is a component of a logic level transformer. It is a figure which shows an example of a structure of the output wiring network which is a component of a logic level transformer. It is a figure which shows another example of a structure of the output wiring network which is a component of a logic level transformer. It is a figure showing the design process of a logic level transformer. 10 is a block diagram illustrating a configuration of a design apparatus described in Patent Literature 1. FIG.

Explanation of symbols

DESCRIPTION OF SYMBOLS 1 Module library 2 Module template 2a Attribute information 2b Circuit design table 2c Mounting design table 2d Conversion table 3 Network 4 Circuit design CAD apparatus 5 Mounting design CAD apparatus 6 Design information storage means 7 Parameter derivation means 11 First integrated logic circuit Chip 12 Input wiring network 13, 18, 18a, 18b Transmission line 14 Logic level conversion core 15 Input signal detection block 16 Logic level conversion output block 17 Output wiring network 19 Second integrated logic circuit chip 20 Logic level transformer 21 Mounting board 22, 23, 24, 25 Solder bump

Claims (3)

A multi-chip integrated device design system for designing a desired multi-chip integrated device by combining a plurality of modules ,
Circuit design parameter information including parameters related to the circuit characteristics of the module (hereinafter referred to as “circuit design parameters”);
Implementation design parameter information including parameters on the module circuit implementation (hereinafter referred to as “implementation design parameters”),
Conversion information including information on a lookup table representing a mutual derivation function for deriving one from the other between each circuit design parameter and each mounting design parameter;
Comprises a module library module template is stored with,
The module library includes various core IPs used for designing a multi-chip integrated device, a logic level conversion core for converting a logic level between the core IPs, and between the core IP or the logic level conversion cores. Storing a plurality of the module templates of the input / output wiring network to be connected;
Design information storage means for storing data on specifications of the multi-chip integrated device including information on the core IP used for circuit design of the multi-chip integrated device to be designed, and data of the selected module template When,
(A) When the specifications of the multi-chip integrated device are input, the specifications of the multi-chip integrated device are stored in the design information storage means, and (b) when the module selection instruction is input, the multi-chip integrated device The module template of the core IP included in the specifications of the chip integrated device is extracted from the module library and stored in the design information storage unit, and the extracted module template of each core IP is referred to Then, the module template of the logic level conversion core necessary between the core IPs connected to each other is extracted from the module library and stored in the design information storage means, and the extracted core IP and logic The core IP or the logic connected to each other with reference to the module template of the level conversion core The module template of the input / output wiring network necessary between the bell conversion cores is extracted from the module library and stored in the design information storage means. (C) When a circuit design parameter change instruction is input, A circuit design CAD device that changes and updates the value of the circuit design parameter of each module template stored in the design information storage means;
When a mounting design parameter change instruction is input, a mounting design CAD device that changes and updates the value of the mounting design parameter of each module template stored in the design information storage unit;
To the module templates stored in the design information storage unit, if one of the parameters of the circuit design parameters or implementation design parameters have been updated, by referring to the conversion information of the Module Template a parameter deriving means other parameters calculated, updating the circuit design parameters or the mounting design parameters of the module templates stored in the design information storage unit by the mutual derivation function,
A design system for a multi-chip integrated device. The circuit design parameter information in the module template of the wiring network includes a parameter group representing the characteristic impedance of the transmission line and the matching termination circuit as a circuit design parameter ,
When the module selection instruction is input, the circuit design CAD device is configured to connect the cores connected to each other based on the extracted circuit design parameter information of the module template of the core IP and logic level conversion core. A parameter group representing the characteristic impedance of the transmission path of the IP and logic level conversion core and the matching termination circuit is extracted, and between the core IP or the logic level conversion cores connected to each other based on the extracted parameter group design system multichip integrated device according to claim 1, wherein the extracting said module template of the required input and output wiring network from the module library. Circuit design parameter information including parameters related to the circuit characteristics of the module (hereinafter referred to as “circuit design parameters”);
Implementation design parameter information including parameters on the module circuit implementation (hereinafter referred to as “implementation design parameters”),
And conversion information including information on a lookup table representing a mutual derivation function for deriving one from the other between each parameter included in the circuit design parameter information and each parameter included in the mounting design parameter information,
Comprises a module library module template is stored with,
The module library includes various core IPs used for designing a multi-chip integrated device, a logic level conversion core for converting a logic level between the core IPs, and between the core IP or the logic level conversion cores. Storing a plurality of the module templates of the input / output wiring network to be connected;
Design information storage means for storing data on specifications of the multi-chip integrated device including information on the core IP used for circuit design of the multi-chip integrated device to be designed, and data of the selected module template When,
A circuit design CAD device for referring to the module library and using the module template to design a circuit of a multi-chip integrated device ;
A mounting design CAD device for performing mounting design of a multi-chip integrated device designed by a circuit design CAD device ;
Parameter derivation means;
A design method for designing a multi-chip integrated device by a system comprising:
Storing the specifications of the multi-chip integrated device in the design information storage means when the specifications of the multi-chip integrated device are input to the circuit design CAD device;
When a module selection instruction is input to the circuit design CAD device, the module template of the core IP included in the specifications of the multi-chip integrated device is extracted from the module library and the design information storage means The module template of the logic level conversion core required between the core IPs connected to each other is extracted from the module library with reference to the module template of each core IP stored and extracted. Input / output necessary between the core IP or the logic level conversion cores connected to each other with reference to the module template of each of the core IPs and the logic level conversion cores stored and extracted in the design information storage unit The module template of the wiring network is used as the module live. And storing the design information storage means extracts from Li,
The parameter of each module template stored in the design information storage means when the circuit design parameter or the change instruction of the mounting design parameter is input to the circuit design CAD device or the mounting design CAD device. Building common design information by updating ; and
Have
In the step of constructing the common design information,
When the value of the circuit design parameter of each module template stored in the design information storage unit is updated by the circuit design CAD device, the parameter derivation unit stores the conversion information of the module template. Referring to the mutual derivation function to calculate the mounting design parameters and updating the mounting design parameters of the module template stored in the design information storage means;
When the mounting design CAD device updates the mounting design parameter value of each module template stored in the design information storage unit, the parameter deriving unit stores the conversion information of the module template. Calculating the circuit design parameters by the mutual derivation function with reference and updating the circuit design parameters of the module template stored in the design information storage means;
A design method for a multi-chip integrated device, characterized in that common design information is constructed by repeating .

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