Deprecated: The each() function is deprecated. This message will be suppressed on further calls in /home/zhenxiangba/zhenxiangba.com/public_html/phproxy-improved-master/index.php on line 456
JP4389321B2 - Manufacturing method of inspection jig - Google Patents
[go: Go Back, main page]

JP4389321B2 - Manufacturing method of inspection jig - Google Patents

Manufacturing method of inspection jig Download PDF

Info

Publication number
JP4389321B2
JP4389321B2 JP2000036500A JP2000036500A JP4389321B2 JP 4389321 B2 JP4389321 B2 JP 4389321B2 JP 2000036500 A JP2000036500 A JP 2000036500A JP 2000036500 A JP2000036500 A JP 2000036500A JP 4389321 B2 JP4389321 B2 JP 4389321B2
Authority
JP
Japan
Prior art keywords
inspection
electrode
insulating
wiring layer
layer
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
JP2000036500A
Other languages
Japanese (ja)
Other versions
JP2001228172A (en
Inventor
孝二 今吉
達広 岡野
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Toppan Inc
Original Assignee
Toppan Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Toppan Inc filed Critical Toppan Inc
Priority to JP2000036500A priority Critical patent/JP4389321B2/en
Publication of JP2001228172A publication Critical patent/JP2001228172A/en
Application granted granted Critical
Publication of JP4389321B2 publication Critical patent/JP4389321B2/en
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Images

Landscapes

  • Measuring Leads Or Probes (AREA)
  • Testing Or Measuring Of Semiconductors Or The Like (AREA)

Description

【0001】
【発明の属する技術分野】
本発明は、半導体装置や半導体を搭載する配線回路基板等の導通検査をするために用いられる検査治具に関する。
【0002】
【従来の技術】
従来の半導体装置や配線回路基板等の導通検査は図3(a)〜(c)に示すように、検査治具50と検査用ソケット70を用いて被検査体60の導通検査を行っている。具体的には、検査用ソケット70上のシリコンラバー71上に検査治具50を載置し、検査治具50の検査電極53と被検査体60の電極部61を押圧して、検査電極53と被検査体60の電極部61との電気的な導通を行うことで検査を行っている。
【0003】
検査電極53の構造は図3(b)に示すように、配線層52との接続部から一直線に延びた円錐台形状をしており、検査電極53は絶縁基板51に形成された配線層52との接続部で保持されている。このような検査電極53と被検査体60の電極部61とを押圧して導通を計る検査方法では、押圧した際に検査治具50の検査電極53及び配線層52の一部がシリコンラバー41側に沈み込み、接触抵抗が不均一になったり、接触不良が発生したりして導通検査の信頼性を損なうという問題を有している。
また、検査治具50の検査電極53及び配線層52の一部がシリコンラバー41側に沈み込むことによる、配線層52と検査電極53との断線や配線層52の絶縁基板51からの部分剥離が発生することもある。
【0004】
【発明が解決しようとする課題】
本発明は上記問題点に鑑みなされたもので、検査治具の検査電極を被検査体に押圧して繰り返し導通検査を行っても、検査電極及び配線層の一部が絶縁基板より離脱することなく、信頼性の高い導通検査ができる検査治具製造方法を提供することを目的とする。
【0005】
【課題を解決するための手段】
本発明に於いて上記問題を解決するために請求項1においては、少なくとも下記(a)〜(g)の工程を備えることを特徴とする検査治具の製造方法としたものである。
(a)支持基板13上に2層の絶縁層12及び絶縁層11を形成する工程。
(b)絶縁層11及び絶縁層12の所定位置に開口部14を形成する工程。
(c)開口部14に導電ペーストを充填し導体電極15を形成する工程。
(d)絶縁層11及び導体電極15上の所定位置に配線層16を形成する工程。
(e)絶縁層11及び配線層16上に絶縁基板17を形成し、配線層16上の絶縁基板17の所定位置に開口部18を形成する工程。
(f)開口部18の配線層16上に所定厚の導体層を形成し、導通パッド19を形成する工程。
(g)支持基板13及び絶縁層12を剥離処理して、検査電極15aを形成する工程。
【0008】
【発明の実施の形態】
以下本発明の実施の形態につき説明する。
図1(a)に本発明の検査治具の一実施例を示す部分模式斜視図を、図1(b)に図1(a)に示す検査治具の部分模式斜視図をA−A線で切断した模式構成断面図を示す。
本発明の検査治具10は絶縁基板17の一方の面に検査電極15aが、他方の面に導通パッド19が形成されており、検査電極15aと導通パッド19は配線層16にて電気的に接続されている。ここで、検査電極15aを導電ペーストで形成することにより、検査電極自体にわずかな弾性を持たせ、導通検査時の電気的接触を確実なものにしている。
【0009】
検査電極15aの一部と配線層16は絶縁層11にて被覆されており、配線層16の保護層の役目と、検査電極15aと配線層16が絶縁基板17に強固に固定されるようになっている。
さらに、検査電極15aと配線層16の接続部は絶縁基板17上に形成されており、導通検査の際押圧加重を繰り返しても検査電極15a及び配線層16が絶縁基板17より離脱するようなことは起こらない。
【0010】
絶縁基板17に設けられた導通パッド19は別設の検査治具用ソケットを介して所定の検査装置に接続し導通検査を行う際検査治具用ソケットの検査コンソールのバンプ電極と電気的に接続され、所定の検査機器に接続されるようになっている。導通パッド19の先端部が絶縁基板17の他方の面より低くしてあるのは、検査治具の導通パッド19と検査コンソールのバンプ電極を位置合せする際のわずかなズレに対しては矯正されるような働きをし、導通検査中に導通パッド19と検査コンソールのバンプ電極が位置ズレを起こさないような堰の役目をして、接触不良を起こすのを防止している。
【0011】
以下本発明の検査治具の作製法について図面を用いて説明する。
図2(a)〜(g)に本発明の検査治具の一実施例の製造工程を工程順に示す部分模式断面図を示す。
まず、支持基板13上に絶縁層12及び絶縁層11を形成する(図2(a)参照)。
支持基板13は検査電極の先端部形状を形成するための基板であり、且つ配線層及び導通パッドを形成するためのめっき電極になるもので、導電性を有する金属であれば使用可能であるが、ここでは製造プロセス上ステンレス板が好ましい。
絶縁層11及び絶縁層12は検査電極を形成するための型を形成したり、検査電極の高さを調整するためのもので、絶縁性を有する樹脂であれば使用可能であるが、絶縁層12は最終工程で剥離・除去されるため、電解めっきプロセスには充分な耐性を有し、且つ剥離処理が容易な感光性レジスト又はドライフィルムレジストが好適である。さらに、絶縁層11は最終的に保護層として残るため、支持基板13及び絶縁層12を剥離・除去する溶媒に溶解しない樹脂を選定する必要がある。絶縁層11はポリエステル、エポキシ、アクリル及びポリイミド樹脂等の樹脂が使用可能である
【0012】
次に、レーザ加工にて絶縁層11及び絶縁層12にテーパー形状の開口部14を形成する(図2(b)参照)。
【0013】
次に、開口部14に導電性ペーストを充填し導体電極15を形成する(図2(c)参照)。
導電性ペースとしては、金、銀、銅、ニッケル等の金属を主成分とした導電性材料或いはそれらの化合物からなる導電性材料を使用した導電性ペーストが使用できる。導体電極15の形成法としてはスクリーン印刷法、フォトプロセス法、注入法等を適宜選択して使用する。
【0014】
次に、絶縁層11及び導体電極15上の所定位置にセミアディティブ或いはアディティブプロセスにて配線層16を形成する(図2(d)参照)。
【0015】
次に、絶縁層11及び配線層16上に絶縁フィルムを貼着し絶縁基板17を形成する。さらに、絶縁基板17の所定位置にレーザー加工にて開口部18を形成する(図2(e)参照)。
絶縁基板17は検査治具の支持基板になるもので、絶縁性、耐熱性及び機械的強度が求められ、ポリエステル、エポキシ、アクリル及びポリイミド樹脂等の絶縁樹脂が使用可能であるが、ポリイミド樹脂からなる絶縁基板が耐熱性や物質安定性の点から好適である。
【0016】
次に、支持基板13をカソード電極にして開口部18の配線層16上に導体金属の電解めっきを行い、導通パッド19を形成する(図2(f)参照)。
ここで、導体層を形成する導体金属は導電性及び強度の問題から銅もしくはニッケルが好適である。
【0017】
次に、導体電極15、配線層16及び導通パッド19が形成された積層基板を専用の剥離液に浸漬し、支持基板13及び絶縁層12を剥離・除去することにより、絶縁基板17の一方の面に検査電極15aが、他方の面に導通パッド19が形成され、検査電極15aと導通パッド19が配線層16で電気的に接続された本発明の検査治具10を得ることができる(図2(g)参照)。
【0018】
【実施例】
下実施例により本発明を詳細に説明する。
まず、0.15mm厚のステンレス板からなる支持基板11上に25μm厚のドライフィルムレジスト(DFR:日立化成工業(株)製)及び25μm厚のエポキシ系接着フィルムをラミネートして、絶縁層12及び絶縁層11を形成した。
【0019】
次に、エキシマレーザ加工機を用いて絶縁層11の所定位置にレーザービームを照射し、絶縁層11及び絶縁層12に40μmφのテーパー形状を有する開口部15を形成した。ここで、エキシマレーザの加工条件は、エネルギ密度1.5J/cm2であった。
【0020】
次に、銅金属を主成分とするスーパーソルダー(ハリマ化成(株)製)をスクリーン印刷により開口部14に充填し、乾燥硬化して導体電極15を形成した。
【0021】
次に、絶縁層11及び導体電極15上に銅をスパッタリングして約3000Å膜厚の薄膜導体層を形成し、さらに、ドライフィルムレジスト(RY−3025:日立化成工業(株)製)にて感光層を形成し、露光、現像を行うことでセミアディティブプロセス用のレジストパターンを形成した。
レジストパターンをマスクにして薄膜導体層上に電解銅めっきを行い、10〜15μm厚の導体層を形成した。さらに、レジストパターンを5wt%の苛性ソーダ溶液にて溶解除去し、レジストパターン下部に形成されていた薄膜導体層を20wt%のペルオキソ二硫酸アンモニウム溶液にてフラッシュエッチングすることにより配線層16を形成した。
【0022】
次に、絶縁層11及び配線層16上に50μm厚のポリイミドフィルム(ユーピレックス:宇部興産)を貼り合わせて、絶縁基板17を形成した。さらに、エキシマレーザ加工機を用いて配線層16上の絶縁基板17の所定位置にレーザービームを照射し開口部18を形成した。
【0023】
次に、支持基板13をカソード電極にして開口部18の配線層16上に電解銅めっきを行い、導通パッド19を形成した。さらに、導通パッド19の表面にNi/Auめっき膜を形成した。
【0024】
次に、導体電極15、配線層16及び導通パッド19が形成された積層基板を専用の剥離液に浸漬し、支持基板13及び絶縁層12を剥離・除去することにより、絶縁基板17の一方の面に検査電極15aが、他方の面に導通パッド19が形成され、検査電極15aと導通パッド19が配線層16で電気的に接続された本発明の検査治具10を得た。
【0025】
【発明の効果】
本発明の検査治具を用いることにより、被検査体に押圧して繰り返し導通検査を行っても、絶縁基板からの検査電極と配線層の離脱は見られず、安定した、信頼性の高い導通検査を行うことができる。
【図面の簡単な説明】
【図1】(a)は、本発明の検査治具の一実施例を示す部分模式斜視図である。
(b)は、本発明の検査治具の部分模式斜視図をA−A線で切断した部分模式断面図である。
【図2】(a)〜(g)は、本発明の検査治具の製造方法を工程順に示す部分模式断面図である。
【図3】(a)は、従来の検査治具50を示す部分模式斜視図である。
(b)は、従来の検査治具50の部分模式斜視図をB−B線で切断した部分模式断面図である。
(c)は、従来の検査治具50を検査用ソケット70上のシリコンラバー71上に載置して被検査体60を導通検査している状態を示す部分模式断面図である。
【符号の説明】
10……本発明の検査治具
11、12……絶縁層
13……支持基板
14……開口部
15……導体電極
15a……検査電極
16……配線層
17……絶縁基板
18……開口部
19……導通パッド
50……従来の検査治具
51……絶縁基板
52……配線層
53……検査電極
60……被検査体
61……電極部
70……検査用ソケット
71……シリコンラバー
[0001]
BACKGROUND OF THE INVENTION
The present invention relates to an inspection jig used to inspect a continuity of a semiconductor device, a printed circuit board on which a semiconductor is mounted, and the like.
[0002]
[Prior art]
In a conventional continuity test of a semiconductor device, a printed circuit board, etc., as shown in FIGS. 3A to 3C, a continuity test of the device under test 60 is performed using an inspection jig 50 and an inspection socket 70. . Specifically, the inspection jig 50 is placed on the silicon rubber 71 on the inspection socket 70, and the inspection electrode 53 of the inspection jig 50 and the electrode portion 61 of the inspection object 60 are pressed to inspect the inspection electrode 53. And the electrode part 61 of the object 60 to be inspected for electrical inspection.
[0003]
As shown in FIG. 3B, the structure of the inspection electrode 53 has a truncated cone shape extending straight from the connection portion with the wiring layer 52, and the inspection electrode 53 is formed on the wiring layer 52 formed on the insulating substrate 51. And is held at the connection. In such an inspection method in which the inspection electrode 53 and the electrode portion 61 of the inspected object 60 are pressed to measure continuity, a part of the inspection electrode 53 and the wiring layer 52 of the inspection jig 50 is silicon rubber 41 when pressed. It has a problem that the reliability of the continuity test is impaired due to sinking to the side, non-uniform contact resistance, or poor contact.
In addition, when a part of the inspection electrode 53 and the wiring layer 52 of the inspection jig 50 sinks to the silicon rubber 41 side, the wiring layer 52 and the inspection electrode 53 are disconnected, and the wiring layer 52 is partially separated from the insulating substrate 51. May occur.
[0004]
[Problems to be solved by the invention]
The present invention has been made in view of the above problems, and even when the inspection electrode of the inspection jig is pressed against the object to be inspected and the continuity inspection is repeatedly performed, the inspection electrode and a part of the wiring layer are separated from the insulating substrate. no, it is an object to provide a method of manufacturing a test jig for reliable continuity test.
[0005]
[Means for Solving the Problems]
In order to solve the above problems in the present invention, in claim 1, in which the production method of inspecting jig, characterized in that it comprises at least the following steps (a) ~ (g).
(A) A step of forming two insulating layers 12 and 11 on the support substrate 13.
(B) A step of forming the opening 14 at a predetermined position of the insulating layer 11 and the insulating layer 12.
(C) A step of filling the opening 14 with a conductive paste to form the conductor electrode 15.
(D) A step of forming the wiring layer 16 at predetermined positions on the insulating layer 11 and the conductor electrode 15.
(E) A step of forming an insulating substrate 17 on the insulating layer 11 and the wiring layer 16 and forming an opening 18 at a predetermined position of the insulating substrate 17 on the wiring layer 16.
(F) A step of forming a conductive layer of a predetermined thickness on the wiring layer 16 of the opening 18 and forming the conductive pad 19.
(G) A step of peeling the support substrate 13 and the insulating layer 12 to form the inspection electrode 15a.
[0008]
DETAILED DESCRIPTION OF THE INVENTION
Hereinafter, embodiments of the present invention will be described.
FIG. 1A is a partial schematic perspective view showing an embodiment of the inspection jig of the present invention, and FIG. 1B is a partial schematic perspective view of the inspection jig shown in FIG. The schematic structure sectional drawing cut | disconnected by is shown.
In the inspection jig 10 of the present invention, an inspection electrode 15 a is formed on one surface of an insulating substrate 17, and a conduction pad 19 is formed on the other surface. The inspection electrode 15 a and the conduction pad 19 are electrically connected by a wiring layer 16. It is connected. Here, by forming the test electrode 15a with a conductive paste, the test electrode itself has a slight elasticity, and the electrical contact during the continuity test is ensured.
[0009]
A part of the inspection electrode 15 a and the wiring layer 16 are covered with the insulating layer 11, so that the role of the protective layer of the wiring layer 16 and the inspection electrode 15 a and the wiring layer 16 are firmly fixed to the insulating substrate 17. It has become.
Further, the connection portion between the inspection electrode 15a and the wiring layer 16 is formed on the insulating substrate 17, and the inspection electrode 15a and the wiring layer 16 are separated from the insulating substrate 17 even when the pressure load is repeated during the continuity inspection. Does not happen.
[0010]
The conductive pad 19 provided on the insulating substrate 17 is electrically connected to the bump electrode of the inspection console of the inspection jig socket when connecting to a predetermined inspection device via a separate inspection jig socket and conducting a continuity inspection. And is connected to a predetermined inspection device. The reason why the leading end of the conductive pad 19 is lower than the other surface of the insulating substrate 17 is corrected for slight misalignment when the conductive pad 19 of the inspection jig and the bump electrode of the inspection console are aligned. It acts as a weir to prevent positional displacement between the conductive pad 19 and the bump electrode of the inspection console during the continuity test, thereby preventing contact failure.
[0011]
Hereinafter, a method for producing the inspection jig of the present invention will be described with reference to the drawings.
2A to 2G are partial schematic cross-sectional views showing the manufacturing process of one embodiment of the inspection jig of the present invention in the order of steps.
First, the insulating layer 12 and the insulating layer 11 are formed on the support substrate 13 (see FIG. 2A).
The support substrate 13 is a substrate for forming the tip shape of the inspection electrode and serves as a plating electrode for forming a wiring layer and a conductive pad, and any metal having conductivity can be used. Here, a stainless steel plate is preferable in terms of the manufacturing process.
The insulating layer 11 and the insulating layer 12 are for forming a mold for forming the inspection electrode or adjusting the height of the inspection electrode, and any insulating resin can be used. Since No. 12 is peeled and removed in the final step, a photosensitive resist or dry film resist that has sufficient resistance to the electrolytic plating process and is easy to peel off is suitable. Furthermore, since the insulating layer 11 finally remains as a protective layer, it is necessary to select a resin that does not dissolve in the solvent for peeling and removing the support substrate 13 and the insulating layer 12. Resin such as polyester, epoxy, acrylic and polyimide resin can be used for the insulating layer 11.
Next, a tapered opening 14 is formed in the insulating layer 11 and the insulating layer 12 by laser processing (see FIG. 2B).
[0013]
Next, the conductive electrode 15 is formed by filling the opening 14 with a conductive paste (see FIG. 2C).
As the conductive pace, a conductive paste using a conductive material mainly composed of a metal such as gold, silver, copper, nickel, or a conductive material made of a compound thereof can be used. As a method for forming the conductor electrode 15, a screen printing method, a photo process method, an injection method, or the like is appropriately selected and used.
[0014]
Next, the wiring layer 16 is formed at a predetermined position on the insulating layer 11 and the conductor electrode 15 by a semi-additive or additive process (see FIG. 2D).
[0015]
Next, an insulating film is stuck on the insulating layer 11 and the wiring layer 16 to form the insulating substrate 17. Further, an opening 18 is formed at a predetermined position of the insulating substrate 17 by laser processing (see FIG. 2E).
The insulating substrate 17 serves as a support substrate for the inspection jig, and is required to have insulating properties, heat resistance and mechanical strength. Insulating resins such as polyester, epoxy, acrylic and polyimide resins can be used. An insulating substrate is preferable in terms of heat resistance and material stability.
[0016]
Next, a conductive metal 19 is formed on the wiring layer 16 in the opening 18 by using the support substrate 13 as a cathode electrode to form a conductive pad 19 (see FIG. 2F).
Here, copper or nickel is suitable for the conductive metal forming the conductive layer from the viewpoint of conductivity and strength.
[0017]
Next, the laminated substrate on which the conductor electrode 15, the wiring layer 16, and the conductive pad 19 are formed is dipped in a dedicated stripping solution, and the supporting substrate 13 and the insulating layer 12 are peeled and removed, whereby one of the insulating substrates 17. The inspection electrode 15a is formed on the surface and the conduction pad 19 is formed on the other surface, and the inspection jig 10 of the present invention in which the inspection electrode 15a and the conduction pad 19 are electrically connected by the wiring layer 16 can be obtained (FIG. 2 (g)).
[0018]
【Example】
The following examples illustrate the invention in detail.
First, a 25 μm thick dry film resist (DFR: manufactured by Hitachi Chemical Co., Ltd.) and a 25 μm thick epoxy adhesive film are laminated on a support substrate 11 made of a stainless steel plate having a thickness of 0.15 mm, and an insulating layer 12 and An insulating layer 11 was formed.
[0019]
Next, an excimer laser processing machine was used to irradiate a predetermined position of the insulating layer 11 with a laser beam, thereby forming an opening 15 having a taper shape of 40 μmφ in the insulating layer 11 and the insulating layer 12. Here, the excimer laser processing conditions were an energy density of 1.5 J / cm 2 .
[0020]
Next, a super solder (manufactured by Harima Chemical Co., Ltd.) containing copper metal as a main component was filled in the opening 14 by screen printing, and dried and cured to form a conductor electrode 15.
[0021]
Next, copper is sputtered onto the insulating layer 11 and the conductor electrode 15 to form a thin-film conductor layer having a thickness of about 3000 mm, and further exposed to dry film resist (RY-3025: manufactured by Hitachi Chemical Co., Ltd.). A layer was formed, and a resist pattern for a semi-additive process was formed by performing exposure and development.
Electrolytic copper plating was performed on the thin film conductor layer using the resist pattern as a mask to form a conductor layer having a thickness of 10 to 15 μm. Further, the resist pattern was dissolved and removed with a 5 wt% caustic soda solution, and the thin film conductor layer formed under the resist pattern was flash etched with a 20 wt% ammonium peroxodisulfate solution to form the wiring layer 16.
[0022]
Next, a 50 μm-thick polyimide film (Upilex: Ube Industries) was bonded onto the insulating layer 11 and the wiring layer 16 to form an insulating substrate 17. Further, an opening 18 was formed by irradiating a predetermined position of the insulating substrate 17 on the wiring layer 16 with a laser beam using an excimer laser processing machine.
[0023]
Next, electrolytic copper plating was performed on the wiring layer 16 in the opening 18 using the support substrate 13 as a cathode electrode to form a conductive pad 19. Further, a Ni / Au plating film was formed on the surface of the conductive pad 19.
[0024]
Next, the laminated substrate on which the conductor electrode 15, the wiring layer 16, and the conductive pad 19 are formed is dipped in a dedicated stripping solution, and the supporting substrate 13 and the insulating layer 12 are peeled and removed, whereby one of the insulating substrates 17. The inspection electrode 15a was formed on the surface, the conduction pad 19 was formed on the other surface, and the inspection jig 10 of the present invention in which the inspection electrode 15a and the conduction pad 19 were electrically connected by the wiring layer 16 was obtained.
[0025]
【The invention's effect】
By using the inspection jig of the present invention, the test electrode and the wiring layer are not detached from the insulating substrate even when the test object is repeatedly pressed and tested for continuity, and the continuity is stable and reliable. Inspection can be performed.
[Brief description of the drawings]
FIG. 1 (a) is a partial schematic perspective view showing an embodiment of an inspection jig of the present invention.
(B) is the partial schematic cross section which cut | disconnected the partial schematic perspective view of the inspection jig of this invention by the AA line.
FIGS. 2A to 2G are partial schematic cross-sectional views illustrating a method for manufacturing an inspection jig according to the present invention in the order of steps.
3A is a partial schematic perspective view showing a conventional inspection jig 50. FIG.
(B) is the partial schematic cross section which cut | disconnected the partial model perspective view of the conventional test | inspection jig 50 by the BB line.
FIG. 6C is a partial schematic cross-sectional view showing a state in which the conventional inspection jig 50 is placed on the silicon rubber 71 on the inspection socket 70 and the inspected object 60 is inspected for continuity.
[Explanation of symbols]
DESCRIPTION OF SYMBOLS 10 ... Inspection jig | tool 11, 12 ... Insulating layer 13 ... Supporting substrate 14 ... Opening part 15 ... Conductor electrode 15a ... Inspection electrode 16 ... Wiring layer 17 ... Insulating substrate 18 ... Opening Part 19: Conductive pad 50 ... Conventional inspection jig 51 ... Insulating substrate 52 ... Wiring layer 53 ... Inspection electrode 60 ... Inspected object 61 ... Electrode part 70 ... Inspection socket 71 ... Silicon rubber

Claims (1)

少なくとも下記(a)〜(g)の工程を備えることを特徴とする検査治具の製造方法。
(a)支持基板(13)上に絶縁層(12)及び絶縁層(11)を形成する工程。
(b)絶縁層(11)及び絶縁層(12)の所定位置に開口部(14)を形成する工程。
(c)開口部(14)に導電ペーストを充填し導体電極(15)を形成する工程。
(d)絶縁層(11)及び導体電極(15)上の所定位置に配線層(16)を形成する工程。
(e)絶縁層(11)及び配線層(16)上に絶縁基板(17)を形成し、配線層(16)上の絶縁基板(17)の所定位置に開口部(18)を形成する工程。
(f)開口部(18)の配線層(16)上に所定厚の導体層を形成し、導通パッド(19)を形成する工程。
(g)支持基板(13)及び絶縁層(12)を剥離処理して、検査電極(15a)を形成する工程。
A method for producing an inspection jig, comprising at least the following steps (a) to (g):
(A) The process of forming an insulating layer (12) and an insulating layer (11) on a support substrate (13).
(B) A step of forming the opening (14) at a predetermined position of the insulating layer (11) and the insulating layer (12).
(C) A step of filling the opening (14) with a conductive paste to form a conductor electrode (15).
(D) A step of forming a wiring layer (16) at a predetermined position on the insulating layer (11) and the conductor electrode (15).
(E) A step of forming an insulating substrate (17) on the insulating layer (11) and the wiring layer (16), and forming an opening (18) at a predetermined position of the insulating substrate (17) on the wiring layer (16). .
(F) A step of forming a conductive layer of a predetermined thickness on the wiring layer (16) of the opening (18) to form a conductive pad (19).
(G) A step of peeling the support substrate (13) and the insulating layer (12) to form the inspection electrode (15a).
JP2000036500A 2000-02-15 2000-02-15 Manufacturing method of inspection jig Expired - Fee Related JP4389321B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP2000036500A JP4389321B2 (en) 2000-02-15 2000-02-15 Manufacturing method of inspection jig

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2000036500A JP4389321B2 (en) 2000-02-15 2000-02-15 Manufacturing method of inspection jig

Publications (2)

Publication Number Publication Date
JP2001228172A JP2001228172A (en) 2001-08-24
JP4389321B2 true JP4389321B2 (en) 2009-12-24

Family

ID=18560543

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2000036500A Expired - Fee Related JP4389321B2 (en) 2000-02-15 2000-02-15 Manufacturing method of inspection jig

Country Status (1)

Country Link
JP (1) JP4389321B2 (en)

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP4612605B2 (en) * 2006-10-03 2011-01-12 株式会社みくに工業 Contact probe manufacturing method

Also Published As

Publication number Publication date
JP2001228172A (en) 2001-08-24

Similar Documents

Publication Publication Date Title
US7874066B2 (en) Method of manufacturing a device-incorporated substrate
EP0544305A2 (en) Method of forming a contact bump using a composite film
JP4288814B2 (en) Semiconductor inspection jig and manufacturing method thereof
JP4389321B2 (en) Manufacturing method of inspection jig
EP1942711B1 (en) Method of manufacturing a wiring board including electroplating
JPH10197557A (en) Inspection member and method of manufacturing the same
JPH0727789A (en) Circuit wiring board and manufacturing method thereof
JP2700259B2 (en) Method of forming solder layer having recess in printed wiring board
JP4161463B2 (en) Chip carrier manufacturing method
JP4556327B2 (en) Manufacturing method of inspection jig
JP3896611B2 (en) Wiring circuit board having inspection electrode and method for forming the same
JP3562166B2 (en) Method of forming printed circuit board having inspection electrode
JP4572438B2 (en) Inspection jig manufacturing method and inspection jig
JP2000155132A (en) Inspection jig and its manufacturing method
JP2000162240A (en) Inspection jig and its manufacturing method
JP2001033485A (en) Inspection jig and its manufacturing method
JP4635329B2 (en) Method for manufacturing printed circuit board
JPH09172243A (en) Manufacturing method of electrical inspection jig for wiring board
JP2957747B2 (en) Method of manufacturing circuit board with circuit component mounting terminals
JPH11135907A (en) Printed circuit board structure with test electrodes
JP2000055981A (en) Inspection jig
JP4114235B2 (en) Inspection jig
JP3401891B2 (en) Lead frame manufacturing method
JPH0748583B2 (en) Method for manufacturing electrical inspection jig board for high-density printed wiring board
JPH11295339A (en) Inspection jig

Legal Events

Date Code Title Description
A621 Written request for application examination

Free format text: JAPANESE INTERMEDIATE CODE: A621

Effective date: 20070131

A977 Report on retrieval

Free format text: JAPANESE INTERMEDIATE CODE: A971007

Effective date: 20090406

A131 Notification of reasons for refusal

Free format text: JAPANESE INTERMEDIATE CODE: A131

Effective date: 20090414

A521 Written amendment

Free format text: JAPANESE INTERMEDIATE CODE: A523

Effective date: 20090610

A131 Notification of reasons for refusal

Free format text: JAPANESE INTERMEDIATE CODE: A131

Effective date: 20090630

A521 Written amendment

Free format text: JAPANESE INTERMEDIATE CODE: A523

Effective date: 20090828

TRDD Decision of grant or rejection written
A01 Written decision to grant a patent or to grant a registration (utility model)

Free format text: JAPANESE INTERMEDIATE CODE: A01

Effective date: 20090915

A01 Written decision to grant a patent or to grant a registration (utility model)

Free format text: JAPANESE INTERMEDIATE CODE: A01

A61 First payment of annual fees (during grant procedure)

Free format text: JAPANESE INTERMEDIATE CODE: A61

Effective date: 20090928

FPAY Renewal fee payment (event date is renewal date of database)

Free format text: PAYMENT UNTIL: 20121016

Year of fee payment: 3

R150 Certificate of patent or registration of utility model

Free format text: JAPANESE INTERMEDIATE CODE: R150

FPAY Renewal fee payment (event date is renewal date of database)

Free format text: PAYMENT UNTIL: 20131016

Year of fee payment: 4

LAPS Cancellation because of no payment of annual fees