JP4389580B2 - Image signal processing circuit - Google Patents

Description

  The present invention relates to an image signal processing circuit, and more particularly to an image signal processing circuit that performs enlargement / reduction processing of a digital image signal.

  Conventionally, digital image signals are enlarged or reduced by an image signal processing circuit for aspect ratio conversion or the like. As a conventional image signal processing circuit for performing the enlargement process and the reduction process, the input image data is divided into a plurality of unit block data, stored in a memory, and the unit block data related to the unit image to be processed is read from the memory. After performing the specified enlargement or reduction data processing and writing it back to the memory, all the unit block data including the unit block data after the data processing stored in the memory is read and combined into one output image data An image signal processing circuit configured as described above is known (see, for example, Patent Document 1).

  FIG. 6 is a block diagram showing another example of a conventional image signal processing circuit. This conventional image signal processing circuit includes a synchronous dynamic random access memory (SDRAM) 1 that stores a digital image signal to be processed, and an SDRAM controller that controls write and read operations of the SDRAM 1 (hereinafter referred to as this). (Also referred to as an LS module) 2, a YC module 3 for separating luminance signals and color difference signals and converting them into a predetermined image format, and a PC module 4 for performing reduction / enlargement processing.

  As an example, the line memory (lmem1) 5 and the line memory (lmem2) 7 in the LS module 2 are each 32 bits × 256 words × 2 single-port SRAM (static random access memory), and the SDRAM 1 is the total number of strokes data capacity It is assumed that the 32-bit bus configuration is as described above. In addition, it is assumed that a digital image signal obtained by imaging with a solid-state image sensor, for example, is written in the SDRAM 1 through the line memory 5.

  The memory 10 in the PC module 4 is a single port of 16 bits × 1984 words × 4 when the interpolation circuit 11 interpolates one pixel using two adjacent pixels in the vertical direction (when vertical interpolation is performed by linear interpolation). If the SRAM also interpolates one pixel with a total of 4 pixels, 2 pixels before and after (3rd order spline interpolation), a single-port SRAM of 16 bits × 1984 words × 8 is required at a minimum. The line memory of the YC module 3 also requires a plurality of 1984 word single port SRAMs.

  An outline of the processing operation of this conventional circuit will be described with reference to the timing chart of FIG. When enlarging / reducing processing in the horizontal direction of the screen is performed, first, four bursts of image data of one line are read from the SDRAM 1 with 256 words per burst. The read operation of the SDRAM 1 at this time is indicated by b in FIG. The image data read from the SDRAM 1 is written into the line memory 7 through the buffer 6 as schematically shown in FIG.

  The image data output from the line memory 7 as schematically shown in FIG. 7D is converted from 32 bits to 16 bits by the conversion circuit 8 of 32 → 16 bits, and 32 bits × 256 words × 4 bursts are obtained. As shown schematically in FIG. 7E, 16 bits × 512 words × 4 bursts, that is, a total of 16 bits × 2048 words (of which 1984 words are used for calculation) are continuous data. .

  The continuous data is subjected to enlargement / reduction processing via the YC module 3 and the PC module 4 to obtain continuous data of the maximum effective pixel 1920 words (the number of words depends on the enlargement / reduction ratio), and then the 16 → 32 bit conversion circuit 9. 7 (B), where 32 bits × 960 words (the number of words depends on the enlargement / reduction ratio), and as schematically shown in FIG. 7 (C), the line memory 5 is supplied. As schematically shown in FIG. 7F, the line memory 5 reads out data in units of 256 words and stores them in the SDRAM 1 in 1 burst 256 words × 4 bursts. The number of effective image pixels in the fourth burst is 192 pixels.

  The enlargement / reduction processing in the vertical direction is performed from data of several adjacent lines using a plurality of the line memories. 7A shows the horizontal synchronization pulse, and FIG. 7I shows the address of the SDRAM 1.

Japanese Patent Laid-Open No. 2-96878

  However, in the conventional image signal processing circuit shown in FIG. 6, the YC module 3 and the PC module 4 perform YC processing and enlargement / reduction processing based on pixel data of a plurality of lines. Since a plurality of line memories (consisting of SRAM) each having a capacity of 2 are required, the number of pixels in the horizontal direction of the digital image signal to be processed is increased, and more advanced YC processing and image enlargement / reduction processing are performed. As a result, their memory capacity increases. As a result, the conventional image signal processing circuit has drawbacks such as an increase in chip size and power consumption, and inability to flexibly cope with other system development. Similarly, the conventional image signal processing circuit described in Patent Document 1 has a problem that the chip size and power consumption increase as the number of pixels in the horizontal direction increases and more advanced YC processing and image enlargement / reduction processing are performed. .

  The present invention has been made in view of the above points, and an object thereof is to provide an image signal processing circuit capable of performing image enlargement / reduction processing with a low-cost configuration.

  Another object of the present invention is to provide an image signal processing circuit that can flexibly cope with an increase in the number of pixels of another system without increasing the memory capacity of the enlargement / reduction circuit.

  Another object of the present invention is to provide an image signal processing circuit capable of reducing power consumption.

To achieve the above object, the present invention, when displaying a digital image, in the image signal processing circuit that is condensation small processing on the image size of any magnification, for each predetermined period by imaging a subject at predetermined time intervals imaging means for obtaining digital image data, together with the digital image data is written obtained by the imaging means, the written digital image data is read out, the storage means condensation small processed image data is written to the image size When a first writing means for writing the digital image data obtained by the imaging means in the storage means, the digital image data written in the storage means by the first writing means, horizontal direction and block in the vertical direction The image data divided into units is read out from the storage means by the reading means for reading out the data in block units. A memory in which image data of the issued block is written, the read address to be incremented by the address value corresponding to the magnification, continued to occur for each block, the block from the memory based on the read address on the read image data in the unit, and reduced small processing means for obtaining a reduced image data of a successive row I block the contraction small processing of any size, the reduced image data of the obtained block unit by the reduction processing unit , serial and second writing means for writing to憶means, and writing processing of the digital image data next to a reduction process to the storage means by the first writing means is performed, for each block from the storage means by the reading means Time-division processing includes reading processing of image data and writing processing of reduced image data for each block to the storage unit by the second writing unit. Thus it is obtained a structure in which a control means for controlling so as to execute within a predetermined time period.

According to the present invention, the image data in units of blocks, by sequentially performing the reduced small processing for reducing the image size of any magnification, collectively performing contraction small processing the image data for a plurality of lines because you to significantly reduce the amount of memory in the contraction small processing means as compared with the conventional circuit, it is possible to reduce the memory capacity of the entire circuit, which can constitute a low-cost and low power consumption Can be realized.

Further, according to the present invention, the image data in units of blocks, since the so sequentially perform a reduced small processing for reducing the image size of any magnification, even the digital image signal to be processed is highly pixelated This can be done flexibly to increase the number of pixels without increasing the memory capacity.

  Next, the best mode for carrying out the present invention will be described. FIG. 1 is a block diagram showing an embodiment of an image signal processing circuit according to the present invention. In the figure, the same components as those in FIG. 6 are denoted by the same reference numerals, and the description thereof is omitted. The image signal processing circuit of the present embodiment shown in FIG. 1 includes an SDRAM 1 that stores a digital image signal to be processed, an SDRAM controller (LS module) 20 that controls write and read operations of the SDRAM 1, a luminance signal, and a color difference signal. Is composed of a YC module 21 for separating and converting to a predetermined image format, and a PC module 22 for performing reduction / enlargement processing.

That is, the present embodiment, compared with the conventional circuit, is characterized as the processing method of the Y C module 21 and the PC module 22, the configuration of the LS module 20. The LS module 20 includes a buffer 6 that receives read image data of the SDRAM 1 as an input, a line memory (lmem2) 7, a line memory (lmem3) 25, and a rearrangement circuit (sd_top) 30 that are commonly connected to the output side of the buffer 6. A 32-to-16-bit conversion circuit 8 connected to the output of the line memory 7, a 16-to-32-bit conversion circuit 23 and 29, switches 24, 25, 53 and 54, a line memory (lmem1) 26 and It is composed of a line memory (lmem5) 27.

  Here, the line memory (lmem2) 7, the line memory (lmem3) 25, the line memory (lmem1) 26, and the line memory (lmem5) 27 in the LS module 20 are each a single-port SRAM of 32 bits × 256 words × 2. It is assumed that the SDRAM 1 has a 32-bit bus configuration that exceeds the total image data capacity as in the prior art.

  The memory 12 in the PC module 22 has 16 bits × 576 words × 4 when the interpolation circuit 11 interpolates one pixel using two adjacent pixels in the vertical direction (when vertical interpolation is performed by linear interpolation). When a single port SRAM interpolates one pixel with a total of 4 pixels, 2 pixels before and after (3rd order spline interpolation), a 16-bit × 576-word × 8 single-port SRAM is required. That is, the memory 12 requires a considerably smaller capacity than the memory 10 in the conventional PC module 4. The line memory in the YC module 21 also requires a plurality of 576-word single-port SRAMs, but this also requires a considerably smaller capacity than the memory in the conventional YC module 3.

  As shown in FIG. 2, the rearrangement circuit (sd_top) 30 includes D-type flip-flops (dff) 31, 35 and 36, switches 28, 33, 34 and 37, a rearrangement circuit (PLTRP) 40, and the like. It is made up of. The rearrangement circuit (PLTRP) 40 includes two rearrangers (REARG1, 2) 41 and 42, various controllers 43 to 47, various memories 49 to 52, an address decoder 48, various switches, and the like.

  Next, the outline of the processing operation of the present embodiment will be described with reference to the timing chart of FIG. Now, the enlargement / reduction ratio in the horizontal direction of the screen is defined as X / 255. When X = 80, that is, when the reduction ratio is 0.31 (= 80/255), the original image data is converted into effective pixels in the horizontal direction. The number 1920 and the number of effective pixels 1480 in the vertical direction (that is, the number of effective lines 1480) will be described as an example.

  First, image data (CCD data) having a quantization bit number of 16 bits obtained by digital signal processing of an image signal obtained by imaging with a solid-state imaging device (CCD) is 16 → 32 bits in the LS module 20. After being converted into a quantization bit number of 32 bits by the conversion circuit 23, the signal is supplied to and stored in the SDRAM 1 through the switch 24, the line memory 26 and the switch 53, respectively.

  In this embodiment, the image data having a quantization bit number of 32 stored in the SDRAM 1 is divided into 1024 pixels in the horizontal direction and 80 lines in the vertical direction (512 words × 32 bits × 80 lines) as one block unit. Then, the data are read from the SDRAM 1 in the order indicated by area A, area B, area C, and area D in FIG. The image data read in block units is supplied to the YC module 21 once via the LS module 20 and further supplied to the PC module 22.

The YC module 21 and the PC module 22 use 576 pixels in the horizontal direction and 80 lines in the vertical direction among the 1024 pixels in the horizontal direction and 80 lines in the vertical direction for processing. The PC module 22 the image data input to the block unit via the YC module 21, after having sequentially written into the memory 12 in blocks, the block from the address incremented by a value determined in accordance with the contraction small processing is reduced small processed is supplied to the interpolation circuit 11 reads out the unit.

  The image data enlarged / reduced in block units by the PC module 22 is supplied to the LS module 20. The LS module 20 deletes both the horizontal and vertical edges of the input image data group, and for example, at the time of 1 ×, the horizontal direction 512 pixels and the vertical direction 64 lines are cut out as effective pixels and stored in the SDRAM 1. In the case of the above reduction ratio of 0.31 times (1 / 3.875 times), about 161 pixels in the horizontal effective pixel number and about 20 lines in the vertical direction are generated. The decimal point of the reduction ratio is a fraction generated for each block process, and this fraction must be absorbed by the address generation circuit of the enlargement / reduction PC module 22 and the LS module 20 for the memory controller.

  Further, when the memory (RA1MEM) 51 in FIG. 2 has the above reduction ratio of 0.31 times (1 / 3.1875 times), the LS module 20 reduces each image data read out in a divided manner. The image data after reduction, which is about 161 effective pixels in the horizontal direction, is stored, read, for example, at the time when 512 pixels are stored, and written to the SDRAM 1 at once, and then the reduced image of 595 pixels for one screen. When the reduced image data for the remaining 83 pixels is stored in the memory (RA1MEM) 51, it is read from the memory (RA1MEM) 51 again and written into the SDRAM 1. Here, one pixel is 16 bits, and two pixels are written per one 32-bit address of the SDRAM 1.

  The reduction processing will be further described with reference to FIG. 2. Image data having a quantization bit number of 32 bits is read from SDRAM 1 by dividing it into 2 bursts with 256 words per burst as indicated by L2A and L2B in FIG. So that the output image data of the 32 → 16-bit conversion circuit 8 is continuous data of a total of 16 bits × 1024 pixels (of which 576 pixels are used for YC and PC computation). (Lmem2) 7 is supplied, and once stored for one line, it is converted into a quantization bit number of 16 bits by a 32 → 16 bit conversion circuit 8. FIG. 3A shows a horizontal synchronization pulse.

  The image data DMAIN1 shown in FIG. 3C output from the 32 → 16 bit conversion circuit 8 is then subjected to YC processing by the YC module 21, taken out as shown in FIG. After being input to the memory 12 as shown in FIG. 5E, the interpolation circuit 11 performs reduction processing, and as shown in FIG. 5F, the effective 161 pixels in the horizontal direction (the number of pixels depends on the reduction magnification). ) And is supplied to the LS module 20.

  That is, this continuous data is transferred to a 16 → 32 bit conversion circuit 29 in the LS module 20 and converted into a quantization bit number of 32 bits, and then the memory (PCMEM) shown in FIG. 2 in the rearrangement circuit (sd_top) 30. ) 50. Thereafter, the continuous data is temporarily stored in the temporary areas TA and TB of the SDRAM 1 at the timing of the SRAM operation indicated by L1TA and TB in FIG.

  Subsequently, the image data read from the memory (PCMEM) 50 at the timing shown in FIG. 3G and the timing shown by L3TB, TA, TD, and TC in FIG. 3B are shown in FIG. Thus, the image data RAMRDDT read from the temporary area of the SDRAM 1 is rearranged so that it can be written into the memory (RA1MEM) 51 by the rearranger (REARG1) 41 of FIG. 3 (I) is partially stored by array conversion at the timing indicated by LPAB. The image data stored in the memory (RA1MEM) 51 is read out as indicated by LP in FIG. 3J at the operation timing of the SDRAM indicated by L1TC and TD in FIG. 3B, and the temporary areas TC and TD of the SDRAM 1 are read. Temporarily stored.

  Subsequently, the image data read out from the SDRAM 1 at the timings indicated by L3TD and TC in FIG. 3B is applied to the flip-flop 31 shown in FIG. 2 in the rearrangement circuit (sd_top) 30 and shown in FIG. Then, after the write timing is adjusted by the rearranger (REARG2) 42, a part of the data is written in the memory (RA2MEM) 52 at the timing indicated by LLPCD in FIG. The data read from the memory (RA2MEM) 52 at the timing indicated by L5 in FIG. 3B is stored in the final image area of the SDRAM 1 only when it is a valid pixel.

  This is repeated, and finally image data of a desired size is generated on the SDRAM 1. FIG. 4 shows a memory map of the SDRAM 1. As shown in the figure, the SDRAM 1 includes an original image data storage area 61, a reduced image data storage area 62 obtained by the above processing, and a temporary area 63 used for the above processing. The temporary area 63 has a capacity of 256 words × 32 bits × 4 × 80 lines, and is an area used in the reduction / enlargement processing of the present embodiment.

  According to the present embodiment, the temporary area 63 is increased in the SDRAM 1 and the number of line memories in the LS module 20 is increased by about 2 compared with the conventional image signal processing circuit. In the embodiment, the memory capacities in the YC module 21 and the PC module 22 are significantly smaller than the conventional one and the increase in the capacity of the SDRAM 1 is slight, so that the entire memory capacity may be made considerably smaller than the conventional circuit. it can.

  For this reason, according to the present embodiment, it is possible to configure at a low cost by reducing the memory capacity and to realize low power consumption. Furthermore, in this embodiment, the YC module 21 and the PC module 22 perform processing on image data in units of blocks, so that even if the digital image signal to be processed has a high number of pixels, it can flexibly handle this. You can do it.

  By the way, in the present embodiment, the YC module 21 and the PC module 22 have horizontal 576 pixels × vertical 80 lines as one block unit (in the LS module 20, if the enlargement / reduction ratio α is set, horizontal 512 pixels × α, vertical 64 lines). Xα), it is necessary to pay attention to address generation at the joint for each block. For example, when the reduction ratio is 0.31 times (1 / 3.875 times), the progress of the read address of the memory 12 for one pixel is +3.1875 (= 255/85), compared to +1.00 at the time of 1 time. Become. FIG. 5 is an explanatory diagram of address generation in consideration of these.

  When the reduction process is performed at a reduction ratio of 0.31, the memory 12 first has a write address in which image data of 512 effective pixels in the area A shown in FIG. Are written sequentially from left to right and from top to bottom as schematically shown in FIG. 5A, and then start from 0 as shown in FIG. The image data written in the memory 12 is read based on a read address that advances by 1875, and reading for reduction processing of one block (area A) is completed at the 161st pixel (address 510.0). .

  Subsequently, as shown schematically in FIG. 5A, the image data of 512 effective pixels in the area B shown in FIG. The image data written in the memory 12 is read based on a read address that is incremented by +3.1875 after the pixels are sequentially written in the order of pixels from right to left and from top to bottom. However, the first address among the read addresses at this time is not reset and starts from 0, but +3. To the last read address “51.0” of the first block as shown in FIG. The value obtained by 1875 is “513.1875”.

  As described above, since the first read address “513.1875” starts from 0 as described above, actually, “1.1875” is obtained by subtracting the last write address 512 of the previous block. It is. Thereafter, as shown in FIG. 5B, the image data written in the memory 12 is read based on the read address incremented by +3.1875 from this value, and at the 160th pixel (address 1020.0). Reading for the next one block reduction process is terminated. Thereby, the joints of the reduced images can be stored in the SDRAM 1 without failure. Thereafter, the same processing is performed for the effective 512 pixels in area C. The same applies to effective 384 pixels in area D.

  In the above embodiment, the reduction process has been described. However, the enlargement process in which the number of pixels in the horizontal direction and the vertical direction increases is different only in the address generation method. The image signal can be divided and enlarged by inserting / interpolating each pixel.

It is a block diagram of one embodiment of the present invention. FIG. 2 is a circuit diagram of an embodiment of a rearrangement circuit (sd_top) in FIG. 1. 3 is a timing chart for explaining the operation of FIGS. 1 and 2. It is a figure which shows an example of the memory map of SDRAM in FIG. It is a figure explaining the mode of the address generation of the joint of the block in this invention. It is a block diagram of an example of the prior art. 7 is a timing chart for explaining the operation of FIG. 6.

Explanation of symbols

1 SDRAM (Synchronous Dynamic Random Access Memory)
7, 24-26 Line memory 8 32 → 16 bit conversion circuit 11 Interpolation circuit 12 Memory 20 LS module 21 YC module 22 PC module 23, 29 16 → 32 bit conversion circuit 30 Rearrangement circuit (sd_top)
40 Rearrangement circuit (PLTRP)
41, 42 Rearranger 48 Address decoder 49-52 Memory

Claims (1)

When displaying a digital image, in the image signal processing circuit that is condensation small processing on the image size of any magnification,
Imaging means for imaging a subject every predetermined period to obtain digital image data for each predetermined period;
Together with the digital image data obtained is written by said image pickup means, the written digital image data is read out, and storage means condensation small processed image data is written to the image size,
First writing means for writing the digital image data obtained by the imaging means into the storage means;
The digital image data written in the storage means by the first writing means, the horizontal direction and the image data divided into blocks in the vertical direction, reading means for reading the said block,
A memory in which image data of the block unit read out from said memory means by said reading means is to be written, a read address to be incremented by the address value corresponding to the magnification, ongoing basis for each block occurs, the image data read in blocks from the memory based on the read address, and reduced small processing means for obtaining a reduced image data of a successive row I block the contraction small processing of any size,
The reduced image data of the block unit obtained by said reduction processing means, and second writing means for writing to prior Kiki憶means,
A digital image data writing process in which a reduction process is performed next to the storage means by the first writing means; a reading process of the image data for each block from the storage means by the reading means; And a control means for controlling the writing process of the reduced image data for each block to the storage means by the writing means to be executed within the predetermined period by time-sharing processing. .

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