JP4394077B2 - Cumulative addition device and cumulative addition method - Google Patents

Description

  The present invention relates to a cumulative addition apparatus and a cumulative addition method.

  A high-frequency power amplifier is used at the output stage of a transmission circuit in a cellular phone or the like, and this high-frequency power amplifier is required to have linearity and high power efficiency when amplified with low distortion. However, non-linear distortion inevitably occurs when high power amplification is performed. Therefore, in order to compensate for the nonlinear distortion, distortion compensation by an adaptive predistortion method is performed.

  In general adaptive predistortion type distortion compensation, the output signal of a high-frequency power amplifier is branched and fed back by a directional coupler, and the difference between the original transmission signal and the feedback signal is calculated to remain. The degree of distortion being detected is detected, and the distortion compensation coefficient is adaptively updated so as to reduce the distortion.

  In order to improve the calculation accuracy of the distortion compensation coefficient, it is important to reduce the calculation error. The major factor of the calculation error is the limit of the bit width of the numerical operation circuit and the processor. In general, a least square method is used for a method of calculating a distortion compensation coefficient. Since the least square method is a statistical process, the observation accuracy is improved as the observation period is longer. However, since the processing bit width of the numerical arithmetic processor is narrow relative to the accuracy of the A / D converter, the sampled numerical data becomes invalid and a large arithmetic error may occur. In this case, the original error distribution cannot be accurately grasped, and the solution by the least square method converges to a point different from the original convergence point.

  More specifically, in statistical processing by an arithmetic unit, when the population (sample) distribution is wide with respect to the arithmetic bit width and the number of parameters is large, an error due to information loss occurs during cumulative addition. “Information loss” is because the number of significant digits is limited. Therefore, when a numerical value with a small absolute value is added to (or subtracted from) a numerical value with a large absolute value, the numerical value with a small absolute value is the result of addition or subtraction. This is an error caused by this. When a large number of numerical values are cumulatively added, if the appearance frequency of numerical data with a small absolute value that is not reflected is high, the important numerical data is not reflected in the cumulative addition result, resulting in a large error.

  As described above, in order to adaptively generate a distortion compensation coefficient, it is necessary to sample transmission data and feedback data in a predetermined observation period and perform statistical processing using a least square method or the like. In performing this statistical processing, it is necessary to ensure accurate cumulative addition of numerical data during the observation period.

  FIG. 14 is a diagram for explaining the state of error expansion when there is information loss. FIG. 14A shows the input data 1401, the ideal sum value 1042, and the sum value when there is information loss. FIG. 14B is a diagram illustrating a graph of the input data 1401 and the total values 1042 and 1403.

  Here, the effective digit is assumed to be one decimal digit. As shown in the total value 1402 in FIG. 14A, the total value should be updated every time numerical data is input. However, if there is an information drop, the total value immediately saturates. End up. In other words, it is added smoothly until the 0th to 4th time, but when the carry is increased to a large numerical value at the 4th time, no matter how much a smaller value is input thereafter, it is ignored. As a result, errors accumulate. The change in the total value (with missing information) is seen when a large value of “0.01” is input for the 10th time and the most significant digit changes from “1” to “2”. The total value does not change at all.

  In FIG. 14B, the horizontal axis indicates the number of calculations, and the vertical axis indicates the total value. A scale for input data 1401 is attached to the left side of the vertical axis, and a scale for total values 1402 and 1403 is attached to the right side of the vertical axis. As is apparent from the comparison result of the total values 1402 and 1403, it can be seen that the error 1404 increases as the number of operations increases. The occurrence of such a large error greatly affects the compensation characteristics in predistortion distortion compensation.

  In order to suppress such error expansion due to information loss, the arithmetic unit needs to have a sufficient bit width adapted to the population distribution and the parameter. A system that sorts the population in ascending order and performs floating point arithmetic and a system that performs iterative arithmetic for insufficient precision are adopted.

  In the former method, when many numerical values are added, they are arranged in order from the smallest absolute value to the largest one, and are added in order from the smallest absolute value. In short, the latter method improves the calculation accuracy by repeatedly repeating the calculation.

  In addition, in the floating-point cumulative adder, a method for increasing the circuit scale and performing the addition operation in a time-sharing manner is proposed in order to enable sufficiently accurate calculation even when the amount of calculation is large (for example, , See Patent Document 1).

Japanese Patent Laid-Open No. 10-55352

  However, the method of sorting the population in ascending order and performing floating-point arithmetic, and the method of performing iterative operations for insufficient precision, complicate processing and reduce the operation speed. Further, in the floating point number cumulative addition apparatus described in Patent Document 1, the circuit scale increases, leading to an increase in LSI size, an increase in power consumption, and an increase in circuit cost. There is.

  The present invention has been made in view of the above circumstances, and an object of the present invention is to provide a cumulative addition apparatus and a cumulative addition method capable of suppressing an increase in circuit scale and performing a precise cumulative addition operation.

  The present invention firstly has a plurality of cumulative adders, adds a cumulative addition result of the plurality of cumulative adders and outputs the result, and an absolute value of an input value to be calculated. Accordingly, there is provided a cumulative adder including a switching unit that selects any one of the cumulative adders and outputs the input value.

  With this configuration, the cumulative addition operation is performed with different cumulative adders according to the magnitude of the absolute value of the input value. In addition to being suppressed, the cumulative adder is switched according to the input value, so that the cumulative addition process can be performed without performing a process such as sorting the input value. Therefore, it is possible to perform a highly accurate cumulative addition calculation while suppressing a decrease in calculation speed and an increase in circuit cost.

  A second aspect of the present invention is the cumulative addition device according to the first aspect, wherein the cumulative addition circuit includes a first cumulative adder and a second cumulative adder, and the switching unit includes: The absolute value of the input value is compared with a threshold value, and when it is determined that the absolute value of the input value is greater than the threshold value, the input value is output to the first cumulative adder, When it is determined that the absolute value of the input value is equal to or less than the threshold value, the input value is output to the second cumulative adder.

  With this configuration, the first cumulative adder that focuses on cumulative addition of numerical data with a large absolute value and the second cumulative adder that focuses on cumulative addition of numerical data with a small absolute value are used. Since processing is performed, high-speed and high-precision cumulative addition can be performed with a simple configuration.

  The third aspect of the present invention is the cumulative addition apparatus according to the second aspect, further comprising a threshold update unit that updates the threshold, and the threshold update unit updates the threshold. It is performed every predetermined observation period, and the threshold value is adaptively updated based on the threshold value in the previous observation period and the average value of the input values in the observation period.

  With this configuration, even when the statistical distribution of the set of input values to be calculated changes over time, the threshold used for switching the output destination follows the distribution of the population. As a result, it is possible to always ensure an appropriate threshold value that matches the current distribution. Therefore, even when the distribution of input data fluctuates, the accuracy of cumulative addition can be maintained.

  Fourth, the cumulative addition apparatus according to the second or third aspect, wherein the first cumulative adder continues the cumulative addition during a predetermined observation period, and the second cumulative The adder periodically performs cumulative addition in the section obtained by dividing the observation period, and adds the cumulative addition result to the cumulative addition result of the first cumulative adder for each period.

  With this configuration, when the second cumulative adder periodically outputs the cumulative addition result to the first cumulative adder, information resulting from an increase in the absolute value processed by the second cumulative adder Can prevent falling.

  The fifth aspect of the present invention is the cumulative adder according to any one of the first to fourth aspects, wherein each of the cumulative adders is a floating-point type cumulative adder.

  With this configuration, it is possible to effectively suppress information loss in the calculation of numerical values in floating point representation.

  Sixthly, the present invention provides the cumulative adder according to any one of the first to fourth aspects, wherein each of the cumulative adders is a fixed-point type cumulative adder having different decimal point positions.

  With this configuration, it is possible to perform cumulative addition according to the magnitude of the absolute value by using a plurality of fixed-point type cumulative adders each having a different decimal point position.

  Seventhly, the present invention includes the cumulative addition device according to any one of the first to sixth aspects, wherein the cumulative addition device is configured to obtain a coefficient of a function serving as a predetermined model by a least square method. There is provided a least squares arithmetic operation device that calculates elements included in a determinant used.

  With this configuration, it is possible to perform accumulative addition calculation with high accuracy while suppressing a decrease in calculation speed and an increase in circuit cost.

  Eighthly, the present invention includes a distortion compensation circuit that performs predistortion processing on a transmission signal and outputs the transmission output signal to an amplifier, and the least squares arithmetic operation device according to claim 7, wherein the transmission signal And a distortion calculation circuit that outputs distortion information to the distortion compensation circuit based on the feedback signal from which the transmission output signal is branched, and the least squares arithmetic unit includes the transmission signal and the feedback signal. Thus, a distortion compensation apparatus that calculates a function indicating the relationship and outputs the function as the distortion information is provided.

  With this configuration, since the cumulative addition operation is performed with high accuracy, the nonlinear distortion of the output signal of the transmitter can be accurately approximated and evaluated. Therefore, the distortion compensation coefficient can be adaptively controlled more appropriately, and the accuracy of predistortion distortion compensation can be improved.

  Ninthly, according to the present invention, the switching unit selects one of a plurality of cumulative adders included in the cumulative adder circuit according to the magnitude of the absolute value of the input value to be calculated, and outputs the input value. And a step of adding the cumulative addition results of the plurality of cumulative adders and outputting the cumulative addition circuit.

  With this method, the cumulative addition operation is performed by different cumulative adders depending on the magnitude of the absolute value of the input value, so that information loss of small numerical values due to mixing and adding numerical values with large absolute values and small numerical values can be avoided. In addition to being suppressed, the cumulative adder is switched according to the input value, so that the cumulative addition process can be performed without performing a process such as sorting the input value. Therefore, it is possible to perform a highly accurate cumulative addition calculation while suppressing a decrease in calculation speed and an increase in circuit cost.

  The tenth aspect of the present invention is the cumulative addition method according to the ninth aspect, wherein the cumulative addition circuit includes a first cumulative adder and a second cumulative adder. The step of the output of the input value by comparing the absolute value of the input value with a threshold value, and if the absolute value of the input value is determined to be greater than the threshold value, Outputting to the first cumulative adder, and when the absolute value of the input value is determined to be less than or equal to a threshold value, outputting the input value to the second cumulative adder. .

  By this method, a first cumulative adder that focuses on cumulative addition of numerical data with a large absolute value and a second cumulative adder that focuses on cumulative addition of numerical data with a small absolute value are used. Since processing is performed, high-speed and high-precision cumulative addition can be performed with a simple configuration.

  According to the present invention, it is possible to provide a cumulative addition device and a cumulative addition method capable of suppressing an increase in circuit scale and performing a precise cumulative addition operation.

(First embodiment)
FIG. 1 is a block diagram showing the main configuration of the cumulative addition apparatus according to the first embodiment of the present invention. As shown in FIG. 1, the cumulative addition device of the present embodiment includes a switching unit 100, a first cumulative addition circuit 200, a second cumulative addition circuit 300, and an adder 204, and has a predetermined observation period. During T, an input value q (t) that is a value of numerical data input at a predetermined timing is cumulatively added, and an output value sum (q (t)) is output.

  The switching unit 100 is a data output path switching switch having two output terminals Q1 and Q2. The absolute value | q (t) | of the input value q (t), which is the value of the input numerical data, is compared with the threshold value Th to determine the magnitude, and based on the determination result, the output terminals Q1, Q2 Is selected to switch the output path of the input value q (t). Specifically, when | q (t) |> Th, the switch is connected to the output terminal Q1 side, and the input value q (t) is distributed to the first cumulative addition circuit 100. In the opposite case, that is, when | q (t) | ≦ Th, the input value q (t) is distributed to the second cumulative addition circuit 300.

  The first cumulative addition circuit 200 includes an adder 202 and a delay unit 206. The adder 202 adds the input value q (t) output from the output terminal Q1 of the switching unit 100 and the value output from the delay unit 206. The delay unit 206 delays the value output from the adder 202 by the input timing and outputs the delayed value. In this way, cumulative addition is performed by repeating the addition of the newly input value and the value that has been added so far.

  Since the absolute value | q (t) | of the input value q (t) output from the output terminal Q1 is larger than the threshold value Th, the first cumulative addition circuit 200 has a relatively absolute value. Cumulatively add large values of.

  Similarly, the second cumulative addition circuit 300 includes an adder 302 and a delay unit 306. The adder 302 adds the input value q (t) output from the output terminal Q2 of the switching unit 100 and the value output from the delay unit 306. The delay unit 306 delays the value output from the adder 302 by the input timing and outputs the result. In this way, cumulative addition is performed by repeating the addition of the newly input value and the value that has been added so far.

  Since the absolute value | q (t) | of the input value q (t) output from the output terminal Q2 is a value equal to or smaller than the threshold value Th, the second cumulative addition circuit 300 has a relatively absolute value. Cumulatively add small values of.

  The adder 204 adds the values output from the first cumulative addition circuit 200 and the second cumulative addition circuit 300. As a result, a value sum (q (t)) obtained by accumulating the input value q (t) is output.

  FIG. 2 is a flowchart showing an operation procedure of the cumulative addition apparatus according to the first embodiment of the present invention.

  First, the cumulative addition value sum_A of the first cumulative addition circuit 200 and the cumulative addition value sum_B of the second cumulative addition circuit 300 are initialized (step S101).

  Next, the switching unit 100 compares the absolute value | q [i] | of the input value with the threshold Th, and if the absolute value | q [i] | is larger than the threshold Th (YES in Step S103). The first cumulative addition circuit 200 adds the input value q [i] to the cumulative addition value sum_A (step S104). On the other hand, if the absolute value | q [i] | is equal to or smaller than the threshold value Th (NO in step S103), the second cumulative addition circuit 300 adds the input value q [i] to the cumulative addition value sum_B ( Step S105). The above steps S103 to S105 are repeated for the observation period T (i = 0 to T-1) (steps S102 and S106).

  When the observation period T elapses, the adder 204 uses the cumulative addition value sum_A cumulatively added by the first cumulative addition circuit 200 and the cumulative addition value sum_B cumulatively added by the second cumulative addition circuit 300. Add (step S107). In this way, the cumulative addition value sum (q (t)) of the input value q (t) in the observation period T is calculated.

  According to the first embodiment of the present invention as described above, it is selected which of the first / second cumulative addition circuits 100 and 200 is used by performing the absolute value determination of the input value in the input stage. Therefore, it is possible to perform cumulative addition according to the absolute value without performing a sorting process on the input value. In addition, since each of the first cumulative addition circuit 200 and the second cumulative addition circuit 300 performs cumulative addition on input values having different absolute values, the cumulative added value becomes large. Sometimes, it is possible to prevent information loss due to an input value having a small absolute value not being added. Therefore, an increase in circuit scale can be suppressed, and accumulative addition with high accuracy can be performed.

(Second Embodiment)
FIG. 3 is a block diagram showing the main configuration of the cumulative addition apparatus according to the second embodiment of the present invention. In FIG. 3, portions that are the same as those in FIG. 1 described in the first embodiment are denoted by the same reference numerals.

As shown in FIG. 3, the cumulative addition apparatus of this embodiment includes a threshold update unit 370 having an average calculation circuit 350 and a threshold calculation circuit 360, and changes in the statistical distribution of the input value q (t). The threshold value Th used for determining the absolute value | q (t) | of the input value in the switching unit 100 is updated. In the present embodiment, the threshold value Th _N indicates the threshold value updated for the Nth time.

The average calculation circuit 350 calculates the average value Ave _N of the input value q (t) from the addition result sum (q (t)) in the observation period T at the Nth update using the following equation (1). To do.
Ave _N = sum (q (t)) / T (1)

The threshold calculation circuit 360 uses the average value Ave _N obtained by the average calculation circuit 350 and the threshold Th _(N−1) updated at the previous (N−1) th update. Then, the threshold value Th _N updated this time (Nth time) is calculated using the following equation (2).
Th _N = Th _[N-1] * β + (1-β) * Ave _N * α (2)

That is, the threshold Th _N is calculated based on the average value of the input numerical values in the sampling period (observation period). The normalized amplitude is obtained by multiplying the ratio of the reference signal and the feedback signal, and is calculated as the following formula (3).

Th ₁ = Ave ₁ * α
Th ₂ = Th ₁ * β + (1−β) * Ave ₂ * α
Th ₃ = Th ₂ * β + (1-β) * Ave ₃ * α
Th _N = Th _(N-1) * β + (1-β) * Ave _N * α
... (3)

As shown in the above equations (2) and (3), the updated threshold value is updated last time with a value obtained by multiplying the average value Ave _N of the input values in the current observation period by a predetermined coefficient α. It is calculated | required by calculating a moving average using the weighting coefficient (beta ₎ with respect to the threshold value Th _(N-1) . Note that the weighting coefficient β follows a change in distribution using, for example, an IIR (infinite impulse response) average. The execution timing of the IIR average is performed every time processing for the number of samples in the least square method is completed.

  That is, in order to appropriately set the threshold value for determining the magnitude of the input numerical data, it is necessary to consider the average value of a large number of input data (population). Multiply the average value of the input numerical values by a predetermined coefficient α to obtain the current threshold value. However, if judging only from the distribution of the input values in the current observation period, it follows the instantaneous distribution fluctuation, and the error due to disturbance (noise) may increase. In order to prevent this (that is, from the viewpoint of mitigating follow-up to disturbances), the threshold value in the previous observation period is also taken into consideration, the previous and current threshold values are weighted, and a moving average is taken. Thus, a new threshold value (the updated threshold value) is obtained. Thereby, the threshold value can be updated appropriately and stably.

  In the case of cumulative addition of a large number of sampled numerical data, even if the statistical distribution during the observation period of the large number of numerical data changes, the threshold value is set as in the cumulative addition circuit of FIG. By appropriately updating and following changes in the distribution of the population, it is possible to always ensure an appropriate threshold value that matches the current distribution. Therefore, the accuracy of cumulative addition can be maintained even when the distribution of input values fluctuates during the transition period during adaptive control (negative feedback control) or the data distribution fluctuates due to disturbance.

FIG. 4 is a flowchart showing an operation procedure of the cumulative addition apparatus according to the second embodiment of the present invention. The procedure of steps S101 to S107 is the same as that in FIG. When the cumulative addition result in the observation period T is performed in step S201, the threshold value updating unit 370 calculates the next threshold value Th _{N + 1} .

  FIG. 5 is an explanatory diagram showing the concept of threshold update. FIG. 5A is a diagram showing the distribution of population data observed during the observation period at the Lth threshold update. B) is a diagram showing a distribution of input values of the population observed during the observation period when the threshold value is updated for the Mth time (L <M).

As shown in FIGS. 5A and 5B, the input value distribution is the data observed at the Mth threshold update from the input value distribution DL observed at the Lth threshold update. The distribution DM is changed. As described above, the signal distribution changes when the signal distribution fluctuates in the middle of the distortion compensation process or when the signal distribution changes due to disturbance of the apparatus.
In the cumulative addition apparatus of the present embodiment, the threshold update unit 370 generates a threshold value from the threshold value Th _L based on an average value Ave _L to Ave _M that changes according to a change from the distribution DL to the distribution DM. Update to Th _M.

  As shown in FIGS. 5A and 5B, the threshold Th is preferably always larger than the average value. Thus, the average numerical value (that is, the numerical value with a high appearance frequency) is determined to be “small” by the comparison determination of the absolute value and the threshold value, and is added to the small loop by the second cumulative addition circuit 300. As a result, it is ensured that small values are accumulated and steadily added. This ensures that information loss is reduced.

  According to the second embodiment of the present invention, the threshold used for switching the output destination even when the statistical distribution of the set of input values to be calculated changes over time. By making the value follow the change in the distribution of the population, an appropriate threshold value suitable for the current distribution can always be secured. Therefore, even when the distribution of input data fluctuates, the accuracy of cumulative addition can be maintained.

(Third embodiment)
FIG. 6 is a block diagram showing a main configuration of a cumulative addition apparatus according to the third embodiment of the present invention. In FIG. 6, the same reference numerals are given to the portions overlapping those in FIG. 1 described in the first embodiment.

  As shown in FIG. 6, the first cumulative addition circuit 200 is provided with an adder 204 that adds the output value from the second cumulative addition circuit 300 and the output value from the adder 202. , The output from the adder 204 is delayed.

  The second cumulative addition circuit 300 has a switch 304 for switching the output path of the output value from the adder 302. The switch 304 has output terminals Q3 and Q4, and the switch is connected to the output terminal Q3 for each addition period P shorter than the observation period T. That is, normally, it is connected to the output terminal Q4 and performs cumulative addition processing. When the time t is divisible by the addition cycle P of the second adder 300 (that is, mod (t, P) = 0), the switch Is connected to the output terminal Q3. As a result, the addition result of the second cumulative addition circuit 300 is added to the addition result of the first cumulative addition circuit 200.

  FIG. 7 is a flowchart showing an operation procedure of the cumulative addition apparatus according to the third embodiment of the present invention.

  First, the value of the cumulative addition value sum_A of the first cumulative addition circuit 200 is initialized (step S301). Next, the value of the cumulative addition value sum_B of the second cumulative addition circuit 300 is initialized (step S303).

  The switching unit 100 compares the absolute value | q [i * P + j] | of the input value with the threshold Th, and if the absolute value | q [i * P + j] | is larger than the threshold Th (YES in Step S305). ), The first cumulative addition circuit 200 adds the input value q [i * P + j] to the cumulative addition value sum_A (step S306). On the other hand, if the absolute value | q [i * P + j] | is equal to or smaller than the threshold value Th (NO in step S305), the second cumulative addition circuit 300 adds the input value q [i] to the cumulative addition value sum_B. (Step S307). The above steps S305 to S307 are repeated for the addition period P (j = 1 to P) (steps S304 and S308).

When the addition period P elapses, the adder 204 uses the cumulative addition value sum_A cumulatively added by the first cumulative addition circuit 200 and the cumulative addition value sum_B cumulatively added by the second cumulative addition circuit 300. Add (step S309). The above steps S303 to S309 are repeated during the observation period T (i = 0 to K−1) (steps S302 and S310).
Note that ((K−1) * P + 1) ≦ T−1 <((K−1) * P + (P−1)). In this way, the cumulative addition value sum (q (t)) of the input value q (t) in the observation period T is calculated.

  In the cumulative addition apparatus of this embodiment, in the second cumulative addition circuit 300 that focuses on cumulative addition of numerical values having small absolute values, cumulative addition is performed in a period P shorter than the observation period T, and the period P Is expired, the cumulative addition result is added to the addition result of the first cumulative addition circuit 200. In other words, the cumulative addition of the input value having a small absolute value is performed in a short cycle, and when the cumulative addition value becomes a certain size, the cumulative addition result of the small data is added to the addition result of the first adder. This is reflected in the overall addition result.

  According to the third embodiment of the present invention as described above, even if the effective digit is limited due to the bit width limit of the arithmetic unit, an input value having a relatively small absolute value is reliably included in the overall addition result. It is reflected and information loss can be reduced.

(Fourth embodiment)
FIG. 8 is a block diagram showing a main configuration of a cumulative addition apparatus according to the fourth embodiment of the present invention. FIG. 9 is a flowchart showing an operation procedure of the cumulative addition apparatus according to the fourth embodiment of the present invention. In FIG.8 and FIG.9, the same code | symbol is attached | subjected about the part which overlaps with the part demonstrated in the 1st-3rd embodiment.

  As shown in FIGS. 8 and 9, the cumulative addition apparatus of the present embodiment includes a second cumulative addition circuit 300 having a threshold update unit 370 and a switch 304. In this way, by using both the adaptive control of the threshold value and the control of returning the addition result in the short cycle of the second cumulative addition circuit to the first adder every time the cycle expires, Accurate cumulative addition is achieved.

(Fifth embodiment)
FIG. 10 is a block diagram showing the main configuration of a cumulative addition apparatus according to the fifth embodiment of the present invention. As shown in FIG. 10, the cumulative addition apparatus of the present embodiment further includes a third cumulative addition circuit 400, and the second cumulative addition circuit 300 includes a third cumulative addition circuit in a stage preceding the switch 304. An adder 308 that adds the output and the output value of the adder 302 is provided.

The switch 100 uses the two threshold values Th1 _N and Th2 _N (Th1 _N > Th2 _N ) to perform a comparison process with the absolute value | q (t) | of the input value q (t). Any one of the third cumulative addition circuits 200, 300, and 400 is selected. Specifically, when Th1 _N <| q (t) |, the input value q (t) is output to the first cumulative addition circuit 200, and when Th2 _N <| q (t) | ≦ Th1 _N , outputs an input value q (t) to the second cumulative addition circuit 300, | q (t) | for ≦ Th2 _N, and outputs an input value q (t) is the third cumulative addition circuit 400.

  The third cumulative addition circuit 400 has a configuration equivalent to that of the second addition circuit 300 shown in FIG. 6, the switch 404 has output terminals Q6 and Q7, and an addition cycle Q shorter than the observation period T. Each time, a switch is connected to the output terminal Q6.

  The second cumulative adder circuit 300 performs cumulative addition on the value added by the adder 308 via the delay unit 306. Note that the addition cycle P for switching the switch 304 and the addition cycle Q of the third cumulative addition circuit 400 may be the same cycle or different cycles.

  According to the fifth embodiment of the present invention as described above, it is possible to perform cumulative addition with higher accuracy by subdividing the absolute value of the input value to be calculated in each cumulative addition circuit.

(Sixth embodiment)
FIG. 11 is a block diagram showing a main configuration of a transmitter having a distortion compensation apparatus according to the sixth embodiment of the present invention.

  As shown in FIG. 11, the transmitter includes a distortion compensation circuit 500, a D / A converter 502, an up-converter 504, a power amplifier 506, an antenna 508, an RF frequency oscillator (local oscillator) 510, and an attenuation. 512, down converter 514, A / D converter 516, distortion calculation circuit 518, and delay device 520.

  The distortion compensation circuit 500 performs predistortion processing on the baseband digital transmission signal r (t) based on the distortion information d output from the distortion calculation circuit 518. The D / A converter 502 converts the digital transmission signal r (t) output from the distortion compensation circuit 500 and subjected to predistortion processing into an analog signal. The RF frequency oscillator 510 outputs a local oscillation signal having a predetermined local oscillation frequency.

  The up-converter 504 mixes the local oscillation signal output from the RF frequency oscillator 510 with the analog signal from the D / A converter 502 and converts it into a radio frequency band signal. The power amplifier 506 amplifies the radio signal from the up-converter 504 and outputs it as a transmission output signal s (t). The antenna 508 transmits the transmission output signal s (t) from the power amplifier 506.

  The attenuator 512 attenuates the transmission output signal s (t) from the power amplifier 506 branched from the transmission system. The down-converter 514 mixes the local oscillation signal output from the RF frequency oscillator 510 with the signal output from the attenuator 512 and converts it to a baseband signal.

  The A / D converter 516 converts the signal output from the down converter 514 into a digital signal. Here, the signal output from the A / D converter 516 is defined as a feedback signal y (t). Delay device 520 delays the transmission signal r (t) in the baseband, and matches the timing with feedback signal y (t). Here, the signal output from the delay device 520 is referred to as a reference signal x (t).

  The distortion calculation circuit 518 determines how much distortion is generated between the transmission signal r (t) and the transmission output signal s (t) based on the reference signal x (t) and the feedback signal y (t). The distortion information d shown is output. Here, as a method of generating a distortion compensation coefficient in the distortion calculation circuit 518, a look-up table method using a distortion compensation coefficient corresponding to the power value of the transmission signal r (t) or a polynomial method expressing the compensation coefficient by a polynomial. There is. Regardless of which method is used, in the distortion calculation, the reference signal x (t) and the feedback signal y (t) are compared, and distortion information d such as a distortion compensation coefficient is calculated based on the error, and the calculated distortion information d Is applied to the distortion distortion compensation circuit 500 to adaptively change the distortion compensation characteristics.

  FIG. 12 is a block diagram showing the main configuration of the distortion calculation circuit in the distortion compensation apparatus according to the sixth embodiment of the present invention.

  As shown in FIG. 12, the distortion calculation circuit 518 includes a mathematical model calculation unit 600, a cumulative addition device 602, and an equation calculation unit 604. The cumulative adder 602 includes the cumulative adders shown in the first to fifth embodiments.

  When the distortion calculation circuit 518 shown in FIG. 12 approximates the relationship between the input reference signal x (t) and the feedback signal y (t) to a predetermined mathematical expression, the coefficient of the mathematical expression is calculated using the least square method. It operates as a least square method computing device to calculate. Hereinafter, the least square method calculation will be described.

For example, it is considered that the relationship of x _i , y _i (i = 1... N) of the population A is approximated as in the following (4).
y = ax + b (4)

  When the coefficients a and b of the above equation (4) are calculated from the population A by the least square method, the following equation (5) is obtained.

  Here, equation (5) is defined as equation (6).

In Equation (6), α _i = x _i ² , β _i = x _i , δ _i = x _i , ε = 1, γ _i = y _i x _i , η _i = y _i .

Therefore, the coefficients a and b of the approximate expression shown in the equation (4) are expressed as α _i , β _i , γ _i , δ _i , ε, and η _i which are elements of the determinant of the equation (6), respectively, i = It can be calculated by cumulatively adding 1 to n.

  A case where the above-described calculation is performed in the distortion calculation circuit 518 will be described. FIG. 13 is a flowchart showing an operation procedure of the distortion calculation circuit in the distortion compensation apparatus according to the sixth embodiment of the present invention.

  First, for the observation period T (t: 0 to T-1), data of the reference signal x (t) and the period signal y (t) is acquired (step S601).

From the reference signal x (t) and the feedback signal y (t), the mathematical model calculation unit 600 uses the elements α _t , β _t , γ _t , δ _t , for the observation period T (t: 0 to T−1). ε and η _t are calculated and output to the cumulative adder 602 (step S602).

The cumulative adder 602 performs cumulative addition on each of the input α _t , β _t , γ _t , δ _t , ε, and η _t (step S 603). And a switching unit that switches the input source and the output destination in synchronization with the output side, and performs time-division computation on each element α _t , β _t , γ _t , δ _t , ε, η _t . Note that the threshold used in the switching unit 100 that switches according to the absolute value of the input value is held for each element. As a result, the operation can be performed with respect to a plurality of elements by one accumulative adding device, so that the circuit scale can be suppressed. Note that a plurality of cumulative addition devices may be provided, and the cumulative addition processing may be performed in parallel for each element or for each group.

  The equation calculation unit 604 calculates the coefficients a and b using the above formula (6) based on the cumulative addition result of each element output from the cumulative adder 602, thereby obtaining an approximate expression of the formula (2). Is obtained (step S604).

  As the distortion calculation circuit 518, the equation calculation unit 604 outputs the coefficients a and b as distortion information d. Note that an index indicating distortion or a predetermined distortion coefficient may be calculated using the coefficients a and b and output as distortion information d.

  In this way, the relationship between x (t) and y (t) can be approximated using the method of least squares. In addition, as the model equation to be approximated, equation (4) is an example, and it is preferable to use various equations suitable for distortion compensation, and a function that is not uniquely determined may be used.

For example, the following equation (7) may be used.
y _i = a (| x _i |) x _i (7)
Generally, this can be expressed in a look-up table (LUT) type, and the internal coefficient can be calculated by the least square method as described above.

  According to the sixth embodiment of the present invention, since the least square method is performed using the first to fifth cumulative adders, the observation data is fitted to a model function by the least square method. Therefore, the coefficient (parameter) of the polynomial for approximating the distortion can be calculated with high accuracy. Therefore, the distortion of the predistortion method can be obtained by generating the distortion compensation coefficient using the calculation result of the least squares arithmetic unit. The accuracy of compensation can be increased.

  The first to sixth cumulative adders of the present invention described above are assumed to be floating-point type arithmetic units, but are not limited to this, and can be applied to arithmetic of numerical values in fixed-point representation. It is. That is, a loop for performing cumulative addition of a numerical value with a large absolute value / small numerical value can be constructed by a fixed-point type cumulative adder having different decimal point positions.

  The cumulative addition device and cumulative addition method of the present invention have the effect of suppressing the increase in circuit scale and enabling accurate cumulative addition calculation, and are useful for the least square method calculation device, distortion compensation device, and the like.

The block diagram which shows the main structures of the cumulative addition apparatus which concerns on the 1st Embodiment of this invention. The flowchart which shows the operation | movement procedure of the cumulative addition apparatus which concerns on the 1st Embodiment of this invention. The block diagram which shows the main structures of the cumulative addition apparatus which concerns on the 2nd Embodiment of this invention. The flowchart which shows the operation | movement procedure of the cumulative addition apparatus which concerns on the 2nd Embodiment of this invention. Explanatory diagram showing the concept of threshold update The block diagram which shows the main structures of the cumulative addition apparatus which concerns on the 3rd Embodiment of this invention. The flowchart which shows the operation | movement procedure of the cumulative addition apparatus which concerns on the 3rd Embodiment of this invention. The block diagram which shows the main structures of the cumulative addition apparatus which concerns on the 4th Embodiment of this invention. The flowchart which shows the operation | movement procedure of the cumulative addition apparatus which concerns on the 4th Embodiment of this invention. The block diagram which shows the main structures of the cumulative addition apparatus which concerns on the 5th Embodiment of this invention. The block diagram which shows the main structures of the transmitter which has a distortion compensation apparatus which concerns on the 6th Embodiment of this invention. The block diagram which shows the main structures of the distortion calculation circuit in the distortion compensation apparatus which concerns on the 6th Embodiment of this invention. The flowchart which shows the operation | movement procedure of the distortion calculation circuit in the distortion compensation apparatus which concerns on the 6th Embodiment of this invention. Diagram for explaining error expansion when there is information loss

Explanation of symbols

DESCRIPTION OF SYMBOLS 100 Switching part 200 1st cumulative addition circuit 202,204 Adder 206 Delay device 300 2nd cumulative addition circuit 302,308 Adder 304 Switch 306 Delay device 350 Average arithmetic circuit 360 Threshold calculation circuit 370 Threshold update Unit 400 third cumulative adder circuit 402 adder 404 switch 406 delay unit 500 distortion compensation circuit 502 A / D converter 504 upconverter 506 power amplifier 508 antenna 510 RF frequency oscillator 512 attenuator 514 down converter 516 A / D converter 518 Distortion Calculation Circuit 520 Delay Device 600 Formula Model Calculation Circuit 602 Cumulative Adder 604 Equation Calculation Unit

Claims (10)

A cumulative addition circuit that has a plurality of cumulative adders and adds and outputs the cumulative addition results of the plurality of cumulative adders;
A cumulative addition apparatus comprising: a switching unit that selects any one of the cumulative adders according to a magnitude of an absolute value of an input value to be calculated and outputs the input value. The cumulative addition apparatus according to claim 1,
The cumulative addition circuit includes a first cumulative adder and a second cumulative adder,
The switching unit compares the absolute value of the input value with a threshold value, and if it is determined that the absolute value of the input value is greater than the threshold value, the input value is sent to the first cumulative adder. And a cumulative adder that outputs the input value to the second cumulative adder when the absolute value of the input value is determined to be equal to or less than a threshold value. The cumulative addition device according to claim 2,
A threshold update unit for updating the threshold;
The threshold update unit updates the threshold every predetermined observation period, and adaptively adjusts the threshold based on the threshold in the previous observation period and the average value of the input values in the observation period. Cumulative adder that updates. The cumulative addition device according to claim 2 or 3,
The first cumulative adder continues the cumulative addition during a predetermined observation period;
The second cumulative adder periodically performs cumulative addition in a section obtained by dividing the observation period, and adds the cumulative addition result to the cumulative addition result of the first cumulative adder for each period. Cumulative adder to do. The cumulative addition device according to any one of claims 1 to 4,
The cumulative adders are each a floating-point type cumulative adder. The cumulative addition device according to any one of claims 1 to 4,
The cumulative adders are fixed-point type cumulative adders each having a different decimal point position. The cumulative addition device according to any one of claims 1 to 6, comprising:
The cumulative addition device is a least square method arithmetic device that calculates elements included in a determinant used when a coefficient of a function serving as a predetermined model is obtained by a least square method. A distortion compensation circuit that performs predistortion processing on a transmission signal and outputs the transmission output signal to an amplifier;
A distortion calculation circuit comprising the least squares arithmetic unit according to claim 7 and outputting distortion information to the distortion compensation circuit based on the transmission signal and a feedback signal obtained by branching the transmission output signal. Prepared,
The least-squares operation device calculates a function indicating a relationship between the transmission signal and the feedback signal, and outputs the function as distortion information. The switching unit selects any one of a plurality of cumulative adders included in the cumulative addition circuit according to the magnitude of the absolute value of the input value to be calculated, and outputs the input value;
A cumulative addition circuit including a step of adding and outputting the cumulative addition results of the plurality of cumulative adders; The cumulative addition method according to claim 9,
The cumulative adder circuit includes a first cumulative adder and a second cumulative adder,
The step of outputting the input value by the switching unit includes comparing the absolute value of the input value with a threshold value, and determining that the absolute value of the input value is greater than the threshold value. A value is output to the first cumulative adder, and if the absolute value of the input value is determined to be less than or equal to a threshold value, the input value is output to the second cumulative adder. Addition method.

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