JP4394599B2 - QPSK modulation wave signal carrier wave synchronization determination circuit - Google Patents

Description

  The present invention relates to a carrier wave synchronization determination circuit of a modulated wave signal receiving apparatus in QPSK (Quadrature Phase keying).

  As is well known, the QPSK modulated wave signal is multiplied on the receiver side by a sine wave and a cosine wave (referred to as a demodulation signal) having the same frequency component (frequency and phase) as that of the carrier wave. The high-frequency signal is demodulated by cutting it with a low-pass filter. However, it is not easy to synchronize the carrier wave and the demodulation signal generated by the local oscillator on the receiver side.

  Conventionally, the carrier synchronization determination of this type of QPSK modulated wave signal is the result of calculating the absolute value at the bit timing of the modulated data of the in-phase signal (I-phase signal) and the quadrature signal (Q-phase signal) subjected to quadrature detection, Since the absolute value output of the I-phase signal and the absolute value of the Q-phase signal converge to 1 / √2, when each value is the same level and exceeds the specified level, it is determined that the carrier signal is synchronized. ing.

  In this method, when the carrier signal is close to the frequency component on the receiver side, the absolute value of the I-phase signal and the absolute value of the Q-phase signal rotate so as to draw a circle. Therefore, when the carrier signal is synchronized, the carrier synchronization can be normally determined.

  Further, the amplitude value of the reproduction signal of each of the I-phase and Q-phase channels is monitored, and when a predetermined threshold is exceeded, it is determined as “1”, and when it does not exceed, it is determined as “0”. A technique is known in which when the integrated value is equal to or greater than a predetermined threshold, it is determined that the synchronization is established (for example, see Patent Document 1). This method is basically similar in concept to the above method that takes the absolute values of the I-phase signal and the Q-phase signal, and has a factor that causes a false determination when the difference from the carrier signal increases.

  As a related technique, a Costas process for multiplying one code by the other data is performed on I-phase data that is data after sampling of the I-phase signal and Q-phase data that is data after sampling of the Q-phase signal. A technique is known in which a fast Fourier transform process for detecting a carrier frequency is sufficient by using this processing result (see, for example, Patent Document 2).

Japanese Patent Application Laid-Open No. 08-298529 (page 3 to page 4, FIG. 1) JP 2005-45684 (first page, FIG. 1)

  However, in the above-described prior art, when the difference in frequency component between the carrier wave and the demodulation signal on the receiver side is significantly different, the absolute value output of the I-phase signal and the absolute value output of the Q-phase signal are 1 / √2 Therefore, there is a problem that the carrier synchronization determination is erroneously determined to be synchronized because the convergence points overlap when the carrier wave is normally synchronized and when the frequency component is significantly shifted.

  Therefore, conventionally, to prevent the frequency difference from increasing, the input frequency conditions are tightened, or the frequency on the receiver side is monitored, and if there is a significant shift, an additional circuit is installed to perform frequency correction. This avoids erroneous determination of carrier wave synchronization determination.

  The object of the present invention is to make it possible to accurately determine the carrier synchronization of a QPSK modulated wave signal even when the difference between the frequency components of the carrier and the demodulated signal is large with a simple circuit / device configuration and to improve the reliability of the synchronization determination. An object of the present invention is to provide a QPSK modulated wave signal carrier wave synchronization determination circuit.

  The QPSK modulated wave signal carrier wave synchronization determination circuit of the present invention generates a sine wave and a cosine wave having the same frequency component as the carrier wave, and changes the frequency component to perform synchronization between the carrier wave and the demodulation signal (see FIG. 1) and a phase detector (1 in FIG. 1) for outputting the difference between frequency components of the input QPSK modulated wave signal and the sine wave and cosine wave as an I-phase signal and a Q-phase signal, A first adder (2 and 3 in FIG. 1) that cumulatively adds the signal and Q-phase signal at bit timing, and a first absolute value detector (2) that converts the output result of the first adder into an absolute value ( 8, 9) in FIG. 1, the second adder (4, 5 in FIG. 1) for accumulatively adding the output of the first absolute value detector until the dump timing, and the output of the first adder Costas converter (11 in FIG. 1) and costas conversion The absolute value detected by the second absolute value detector (10 in FIG. 1) for detecting the absolute value of the output and the absolute value detected by the second absolute value detector are cumulatively added until the external control timing, and the Costas absolute value is output. And a fourth adder (FIG. 1) that supplies the output to the PLL processing unit that accumulates and outputs the Costas-transformed output up to the external control timing and outputs the result as a Costas error. 7) and a PLL processing unit (13 in FIG. 1) that outputs a control signal for performing feedback processing to the numerical control transmitter based on the Costas error upon receipt of the Costas error. Features.

  According to the present invention, in addition to the conventional synchronization determination means, the output obtained by performing the absolute value conversion and addition processing of the Costas detector output is used for the synchronization determination, so that the difference between the frequency components of the carrier wave and the demodulated signal is large. Even so, the carrier wave synchronization determination can be performed accurately.

  In addition, since carrier wave synchronization can be normally determined, additional circuits can be reduced, and erroneous determination is eliminated, so that input frequency conditions can be relaxed.

  The QPSK modulated wave signal carrier wave synchronization determination circuit of the present invention includes a Costas converter that performs Costas conversion on the output of the first adder that cumulatively adds the demodulated I-phase signal and Q-phase signal at bit timing, and is subjected to Costas conversion. An absolute value detector for detecting the absolute value of the output, and a second adder for accumulatively adding the absolute value detected by the absolute value detector to the external control timing and outputting a Costas absolute value. The output of the adder is used to determine the synchronization between the carrier wave and the demodulation signal.

  Next, embodiments of the present invention will be described in detail with reference to the drawings.

  FIG. 1 is a block diagram showing an embodiment of a QPSK modulated wave signal carrier synchronization determination circuit of the present invention. This QPSK modulated wave signal carrier wave synchronization determination circuit includes a phase detector 1, six adders 2 to 7, three absolute value detectors 8 to 10, a Costas converter 11, a numerically controlled oscillator 12, a PLL. (Phase Lock Loop: phase lock loop) The processing part 13 is comprised.

  The phase detector 1 receives QPSK modulated wave signals S1 and S2. Here, although the QPSK modulated wave signals S1 and S2 are complex signals, they may be single-phase signals. In this case, for example, only S1 is displayed. The phase detector 1 inputs the QPSK modulated wave signals S1 and S2 and the sine wave S11 and cosine wave S12 output from the numerically controlled oscillator 8, and calculates the difference between these frequency components as the I-phase signal S3 and the Q-phase. Output as signal S4.

  The adders 3 and 4 cumulatively add the I-phase signal S3 and the Q-phase signal S4, respectively, at the bit timing t1. At this time, the well-known EARLY-LATE GATE method is used. The absolute value detectors 8 and 9 convert the output results of the adders 2 and 3 into absolute values, and the adders 4 and 5 cumulatively add the outputs of the absolute value detectors 8 and 9 to the dump timing t2, respectively. Output as S5 and S6.

  The Costas converter 11 performs Costas conversion on the outputs S5 and S6 of the adders 2 and 3. The absolute value detector 10 detects the absolute value S14 of the output S13 subjected to Costas conversion, and the adder 6 cumulatively adds the absolute value S14 until the external control timing t3, and outputs the Costas absolute value S15. Further, the adder 7 cumulatively adds the Costas converted output S13 until the external control timing t3, and supplies the result to the PLL processing unit 13 as a Costas error S16.

The PLL processing unit 13 outputs a control signal S18 for performing feedback processing to the numerically controlled oscillator 12 based on the Costas error S16. The numerically controlled oscillator 12 generates a sine wave (SIN) S11 and a cosine wave (COS) S12 having the same frequency as the carrier wave, and changes the frequency components of the sine wave S11 and the cosine wave S12 in response to the control signal S18. As a result, the carrier wave and the demodulation signal are synchronized.
[Description of operation]
Next, the operation of the QPSK modulated wave signal carrier wave synchronization determination circuit configured as described above will be described.

  A QPSK modulated wave complex signal composed of the I-phase signal S1 and the Q-phase signal S2 is input to the phase detector 1 and is orthogonally detected between the sine wave S11 and the cosine wave S12 input from the numerically controlled oscillator 12. The phase signal S3 and the Q phase signal S4 are output. The I-phase signal S3 and the Q-phase signal S4 are added in the adder 2 and 3 only during the bit timing t1, and are output as the I-phase signal S5 and the Q-phase signal S6 of the difference in frequency components.

  The I-phase signal S5 and the Q-phase signal S6 are added by the adder 4 and the adder 5. Now, when the carrier signal and the demodulation signal are synchronized, the difference S5, S6 between the two frequency components disappears, so the addition value S9 of the absolute value of the I-phase signal and the addition of the absolute value of the Q-phase signal Both values S10 converge to 1 / √2. By utilizing this fact, it is possible to make a synchronization determination that carrier synchronization is established when S9 and S10 exceed a predetermined threshold and S9 and S10 are substantially equal.

  If the difference is small without carrier synchronization, the output values of S9 and S10 will increase or decrease as the phase of the difference rotates, making use of the fact that the above conditions are not met, To implement.

  However, when the frequency component differences S5 and S6 are large, the added value S9 of the absolute value of the I-phase signal and the added value S10 of the absolute value of the Q-phase signal converge to 1 / √2 as in the case of carrier wave synchronization. To do. Therefore, the frequency component differences S5 and S6 are Costas converted by the Costas detector 9 and cumulatively added by the adder 12, and the Costas output value S13 is detected by the absolute value detector 10 as the absolute value S14.

  When the frequency component differences S5 and S6 are large, it is understood that the absolute value S14 converges to 1 / √2 of the effective value by converting the Costas output value S13 in this way. Further, when the synchronization of the carrier signal is established, the differences S5 and S6 disappear and the absolute value S13 converges to around zero. The carrier wave synchronization determination is performed using the above.

  Note that the output value converges to “0” when no signal is input only with the output obtained by converting the absolute value of the Costas detector. Therefore, the carrier synchronization determination is accurately performed by using it together with the synchronization determination by S9 and S10. It becomes possible.

  It should be noted that the present invention is not limited to the above-described embodiments, and it is obvious that the embodiments can be appropriately changed within the scope of the technical idea of the present invention.

The block diagram which shows one Example of the QPSK modulation wave signal carrier wave synchronization determination circuit of this invention

Explanation of symbols

DESCRIPTION OF SYMBOLS 1 Phase detector 2-7 Adder 8-10 Absolute value detector 11 Costas detector 12 Numerically controlled oscillator 13 PLL processing part

Claims (2)

A Costas converter that performs a Costas conversion on the output of the first adder that cumulatively adds the demodulated I-phase signal and Q-phase signal;
An absolute value detector for detecting the absolute value of the Costas transformed output;
A second adder that cumulatively adds the absolute values detected by the absolute value detector and outputs a Costas absolute value;
A QPSK modulated wave signal carrier synchronization determination circuit, wherein the output of the adder is used for synchronization determination between a carrier wave and a demodulation signal. In the carrier synchronization determination circuit of the QPSK modulated wave signal,
A numerically controlled oscillator that generates a sine wave and a cosine wave of the same frequency component as the carrier wave, and synchronizes the carrier wave and the demodulation signal by changing the frequency component;
A phase detector that outputs the difference in frequency components between the input QPSK modulated wave signal and the sine wave and cosine wave as an I-phase signal and a Q-phase signal;
A first adder that cumulatively adds the I-phase signal and the Q-phase signal at bit timing;
A first absolute value detector for converting an output result of the first adder into an absolute value;
A second adder for accumulating and outputting the output of the first absolute value detector until the dump timing;
A Costas converter for performing a Costas conversion on the output of the first adder;
A second absolute value detector for detecting an absolute value of the Costas transformed output;
A third adder for accumulatively adding the absolute value detected by the second absolute value detector until an external control timing and outputting a Costas absolute value;
A fourth adder that cumulatively adds the Costas-transformed output until an external control timing and supplies the result to a PLL processing unit that outputs the result as a Costas error;
A QPSK modulated wave signal carrier synchronization determination, comprising: a PLL processing unit that outputs a control signal for performing feedback processing to the numerical control transmitter based on a Costas error when receiving the status error circuit.

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