JP4397357B2 - Semiconductor memory device - Google Patents

Description

  The present invention relates to a semiconductor memory device, and more particularly to a clock synchronous semiconductor memory device that operates in synchronization with a clock signal. More specifically, the present invention relates to a configuration of an internal data transfer system of a clock synchronous semiconductor memory device capable of switching word configurations.

  FIG. 58 schematically shows an entire configuration of a conventional synchronous semiconductor memory device. 58, synchronous semiconductor memory device 900 is provided corresponding to each of memory arrays MAa, MAb, MAc, and MAd each having a plurality of memory cells arranged in a matrix, and memory arrays MAa to MAd. Multi-bit internal data buses 910a-910d, selector / driver 915 for selecting the bus lines of multi-bit internal data buses 910a-910d according to address signal CA and selection signal φsel, and data from selector / driver 915 are transmitted An internal read data bus 920 and an output circuit OB that generates external data in accordance with data supplied from the internal read data bus 920 are included.

  Memory arrays MAa-MAd form bank # 0-bank # 3, respectively, and are driven to a selected state independently of each other. Here, the “selected state” indicates a state in which the memory cell data connected to the selected word line is held by driving the word line to the selected state in the memory array.

  The selection signal φsel is selectively and fixedly set according to the bit width of the output data DQ from the output circuit OB. For example, one chip corresponds to a plurality of word configurations such as x4, x8, x16, and x32 bits.

  The reason why the multi-bit internal data buses 910a to 910d are provided corresponding to the memory arrays MAa to MAd is as follows. Banks # 0 to # 3 are driven to the selected state independently of each other, and therefore, a plurality of banks can be held in the selected state. However, an access operation for writing / reading data of a memory cell is performed for one bank. The number of banks can be changed. Therefore, in order to easily correspond to an arbitrary bank configuration, internal data buses 910a to 910d are provided corresponding to memory arrays MAa to MAd, respectively. The bit width of internal data buses 910a-910d is the same as the bit width of internal read data bus 920. Selector / driver 915 selects an internal data bus according to the selected bank and couples to internal read data bus 920. The selector / driver 915 switches the bus connection path according to the bit width of the output data bit DQ according to the selection signal φsel and the address signal CA.

  FIG. 59 schematically shows a structure of selector / driver 915. In FIG. FIG. 59 representatively shows a circuit portion for one internal data bus. Internal data bus 910 (910a to 910d) includes 4-bit bus lines 910-0 to 910-3. Output data of preamplifiers 925-0 to 925-3 for amplifying memory cell data IO0 to IO3 are transmitted to data bus lines 910-0 to 910-3, respectively.

  The read data bus 920 also includes 4-bit read data bus lines 920-0 to 920-3. These read data bus lines 920-0 to 920-3 are provided with output circuits OB0 to OB3, respectively, and output data DQ0 to DQ3 are output.

  Selector / driver 915 is provided corresponding to each of OR circuit 915a receiving address signal CA and selection signal φsel, inverter 915b for inverting the output signal of OR circuit 915a, and read data bus lines 920-0 to 920-3. Drive circuit DV0 to DV3 and transfer gate TX0 coupling data bus line 910-0 to the input of drive circuit DV1 according to the output signal of inverter 915b and data bus line 910-1 according to the output signal of OR circuit 915a Transfer gate TX1 coupled to the input section of drive circuit DV1 and transfer gate TX2 coupling data bus line 910-2 to the input section of drive circuit DV3 according to the output signal of inverter 915b and data according to the output signal of OR circuit 915a It includes transfer gates TX3 coupling the scan line 910-3 to the input of the drive circuit DV3. Drive circuits DV0 and DV2 are activated when select signal φsel is at H level, and drive read data bus lines 920-0 to 920-2 in accordance with read data applied on data bus lines 910-0 and 910-2. To do.

  When the selection signal φsel is at the H level, it indicates that the word configuration (number of output data bits) is a × 4 bit configuration, and when it is at the L level, it indicates that the word configuration is 2 bits. Next, the operation of the selector / driver 915 shown in FIG. 59 will be briefly described.

  When the word configuration is a × 4 bit configuration, selection signal φsel is fixedly set at the H level. In this state, the output signal of OR circuit 915a is at the H level, transfer gates TX1 and TX3 are conductive, and transfer gates TX0 and TX2 are nonconductive. Drive circuits DV0 and DV2 are also set in an operable state. Therefore, in this state, read data bus lines 920-0 to 920-3 are driven by drive circuits DV0 to DV3 in accordance with data transmitted to data bus lines 910-0 to 910-3, respectively, and output circuits OB0 to OB3. 4 bits of data DQ0 to DQ3 are output via.

  When selection signal φsel is at L level, drive circuits DV0 and DV2 are set in an inoperable state. In this state, transfer gates TX0 to TX3 are selectively turned on according to the H level / L level of address signal CA. When address signal CA is at H level, the output signal of OR circuit 915a is at H level, transfer gates TX1 and TX3 are turned on, and data bus lines 910-1 and 910-3 are coupled to drive circuits DV1 and DV3, respectively. Is done. Therefore, in this state, memory cell data IO1 and IO3 are transmitted to output circuits OB1 and OB3, respectively, and data DQ1 and DQ3 are generated. On the other hand, when address signal CA is at H level, transfer gates TX1 and TX3 are in a non-conductive state, and transfer gates TX0 and TX2 are in a conductive state. Data bus lines 910-0 and 910-2 are coupled to drive circuits DV1 and DV3, respectively. In this case, memory cell data IO0 and IO2 are transmitted to output circuits OB1 and OB3 to generate data bits DQ1 and DQ3. As a result, 2-bit data is output. Output circuits OB0 and OB2 are set to an inoperative state when the word configuration is a × 2 bit configuration.

  By using the selector / driver 915 as shown in FIG. 59, it is possible to cope with a plurality of word configurations without changing the internal circuit configuration.

Japanese Laid-Open Patent Publication No. 4-114395 (Patent Document 1) discloses a configuration in which a read operation is confined in a sense node of a sense amplifier in order to perform read transfer of internal data at high speed.
JP-A-4-114395

  As shown in FIG. 58, when a data bus is arranged corresponding to each of memory arrays MAa to MAd, the area occupied by the data bus increases. In particular, when the word structure becomes large, such as x16 bits or x32 bits, the occupied area of the bus increases. Further, when the bus connection is switched according to the word configuration by the selector / driver 915, a signal propagation delay occurs in the transfer gate for switching this connection, which causes a problem that the signal cannot be transmitted at high speed. In particular, when the word configuration is switched between x16 and x32 bits, the number of transfer gates of the selector / driver increases, and the occupied area increases. In particular, if the number of selectable word configurations is increased such that the word configuration is set to any of x4, x8, and x16, this selector / driver can select from 32 bits to 16 bits, 16 It is necessary to perform a three-stage selection operation of selecting from 8 bits to 8 bits and selecting from 8 bits to × 4 bits, and the area occupied by this selector / driver increases, and accordingly, the signal propagation delay also increases, resulting in high speed. Thus, data cannot be read out.

  This selector / driver is also provided for the data write path, which causes a problem that data cannot be transmitted to the selected memory cell at high speed.

  In the clock synchronous semiconductor memory device, an operation parameter called CAS latency exists. This is because an access command (a read command for instructing data reading or a write command for instructing data writing) is applied until data is actually written to the memory cell or data is read to the outside. The number of clock signal cycles required. Internally, the circuit is driven in accordance with the CAS latency. Therefore, in the case shown in FIG. 59, it is necessary to change the activation timing of the address signal CA for the selector / driver according to the CAS latency. Therefore, there is a difference between the timing of determining the address signal CA and the timing of determining the output data of the preamplifiers 625-0 to 925-3, so that a timing margin needs to be considered, and high-speed data reading cannot be performed. The same applies to data writing.

  In Patent Document 1 described above, a configuration is shown in which the sense operation is performed after the read data of the selected memory cell is confined in the sense node in the sense amplifier, but the timing for confining the charge in the sense node is fixedly fixed. The phase relationship with the external clock signal is not taken into consideration, and the configuration for changing the confinement timing according to the operating frequency is not taken into consideration.

  In Patent Document 1, no consideration is given to data transfer timing and output timing on the internal data bus.

  SUMMARY OF THE INVENTION An object of the present invention is to provide a semiconductor memory device capable of transferring internal data at a high speed during writing / reading with a simple circuit configuration.

  Another object of the present invention is to provide a semiconductor memory device capable of transferring internal data at high speed regardless of the word configuration.

  Still another object of the present invention is to provide a clock synchronous semiconductor memory device capable of stably transferring internal data at a high speed with a small occupation area.

A semiconductor memory device according to the present invention includes a data input circuit that takes in given data in synchronization with a clock signal, generates complementary internal data and transmits the data to a data bus, and amplifies differential data of the data bus when activated And a write driver that transmits output data of the write amplifier to a selected memory cell.
The data bus includes a plurality of bus line pairs provided corresponding to each of the plurality of pads. The semiconductor memory device according to the present invention further includes a bus selection gate for connecting one of the plurality of bus line pairs to the write amplifier according to word configuration information indicating the number of pads to be used among the plurality of pads, and a bus selection. A bus selection gate is connected in series between the gate and the write amplifier, and a sense gate is provided for separating the write amplifier and the bus selection gate when the write amplifier performs an amplification operation.

  By providing a plurality of data buses, each corresponding to each of a plurality of pads, and arranging the plurality of data buses in a plurality of memory arrays in common, it is not necessary to switch the bus connection path for switching the word structure Thus, there is no need to provide a bus selector, the bus occupation area can be reduced, and a data signal can be transmitted at high speed.

In one aspect of the present invention, it is configured to generate complementary internal data in synchronization with a clock signal and transmit differential data to a data bus, and transfer write data of a small amplitude signal. And high speed writing is realized.
In addition, the write amplifier and the data bus are separated, the write amplifier is disconnected and the write amplifier is activated, and data can be written by transmitting a small amplitude signal through the data bus. Furthermore, the data bus and the write amplifier are connected using a gate connected in series with the bus selection gate, the circuit configuration is simplified, and the circuit occupation area is reduced.

  In addition, accurate writing can be realized by equalizing the data bus to a predetermined potential for each cycle during data writing. Further, since the internal write signal changes from a predetermined potential, the signal change time can always be made the same regardless of the logic of the write data, and high-speed data transfer can be realized.

  Further, according to the word configuration, one of a plurality of bus line pairs is selected by the bus selection gate, and the write data driver and the write amplifier are connected via the bus selection gate and the separation gate. The circuit configuration for bus selection is simplified, and the circuit occupation area is reduced. Further, since the data bus and the write amplifier are disconnected during the operation of the write amplifier, high-speed write data can be amplified.

  In addition, the write amplifier is selectively operated in the word configuration information so that the ternary data is transmitted to the data bus according to the output data of the data input circuit by selectively using the write data control driver. Can do.

  Further, by deactivating the write amplifier at the time of data masking, it is possible to mask the write data from the outside with accurate timing.

  Further, when the read data driver is activated, the data bus and the write amplifier are separated from each other, so that the load on the read data driver is reduced and data can be read at high speed.

  In the multi-bit test mode, the output signal of the decision circuit that determines whether the data logic of the complementary data bus is the same is transmitted to the read amplifier via the transfer gate provided in parallel with the read amplifier isolation gate. By doing so, a multi-bit test can be performed using the data bus, and it is not necessary to provide a dedicated test bus, and the area occupied by the test circuit can be reduced.

  In addition, a plurality of read data drivers are connected in parallel to the data bus, and the read data driver is configured to drive the equalized bus to a voltage level different from the equalized voltage in the multi-bit test mode. In the multi-bit test mode, wired OR connection can be performed, and multi-bit test determination result output can be performed using a read data driver used for normal data reading.

According to inventions of another embodiment of the aspect of this, between the provided life-and-death bus line so as to have a cross-section a plurality of data buses, are arranged the bus lines of the other bus Therefore, the noise of the buses forming a pair is canceled and shielded by other bus lines, and noise due to capacitive coupling does not occur, and a small amplitude data signal can be transmitted stably at high speed.

  In addition, a bus used in a word configuration and an unused bus are paired, and by alternately arranging these bus lines, the unused bus can be used as a shield, and a pair can be reliably connected. Capacitive coupling noise between the formed bus lines can be prevented.

  Further, by configuring the unused bus line to be fixed at a predetermined potential, the unused bus line can be used as a shield for noise suppression more reliably.

  In addition, by setting the unused data bus to a predetermined potential in the multi-bit test mode, the output signal of the read data bus connected in wired OR connection in the multi-bit test mode is affected by capacitive coupling noise. Can be transmitted accurately without any problem.

  Further, since the data buses corresponding to the pads adjacent to each other are grouped, the lengths of the data buses are equal, the parasitic capacitance of the data bus can be equalized in each group, and noise can be canceled accurately.

According to a further embodiment of another aspect of this invention, in a different memory array in connection line block position of the global data bus and the memory block, selectively read data driver in accordance with a row block designating signal and word configuration information Therefore, the connection relationship between the row block and the data bus can be accurately maintained in a one-to-one correspondence, and a multi-bit test can be accurately realized.

  Further, by setting the connection relationship between the data bus and the row block according to whether or not the row block designation signal is an end block, there is no collision of selected memory cell data in the normal operation mode, and the pad And the row block can be set one-to-one.

  When all the pads are used according to the word configuration information, the circuit configuration for switching the data bus is simplified by ignoring the row block designation signal.

Further, by arranging the read data driver for each of the global data buses with respect to a predetermined data bus, it is possible to cope with a plurality of word configurations by arranging only the minimum necessary number of read drivers.
In yet another embodiment, the data bus is configured to transmit a complementary data signal, and the complementary data bus is equalized to a predetermined voltage level, so that the data bus for a small amplitude signal is transmitted. And high-speed data transfer is possible.
In addition, the amplification operation can be performed at high speed by configuring the read amplifier so as to perform the amplification operation by separating from the data bus.
Further, by configuring the read amplifier detection node to be coupled to the data bus during the equalization of the data bus, the read amplifier detection node can be easily initialized. In addition, a data bus equalization circuit can be provided outside the read amplifier, the area occupied by the read amplifier arranged near the pad can be reduced, and the layout area near the pad can be reduced.
In addition, by activating the read amplifier at the earlier timing of clock signal activation and deactivation of the detect signal, even if the clock frequency changes, the activation timing can be adjusted and data can be read accurately. The
In addition, by configuring the read amplifier to be inactivated according to the mask instruction and equalize the output node of the read amplifier to a predetermined potential, it is possible to easily mask the data output at the same timing regardless of CAS latency. . Further, since the read amplifier is inactivated, it is not necessary to consider the timing margin between the internal clock signal applied to the output circuit and the mask instruction, and an accurate data mask can be realized.

[Embodiment 1]
FIG. 1 schematically shows an overall configuration of the semiconductor memory device according to the first embodiment of the present invention. In FIG. 1, a semiconductor memory device 1 includes memory arrays 2a to 2d each having a plurality of memory cells arranged in a matrix, and data of memory cells of corresponding memory arrays provided in each of the memory arrays 2a to 2d. Column local circuits 3a-3d for writing / reading are provided with pads PPD0 and PPD1 for inputting / outputting data, and data bus DB0 provided corresponding to pads PPD0 and PPD1 in a one-to-one relationship. Includes DB1. Data buses DB0 and DB1 are formed of, for example, continuous low-resistance aluminum wiring, and are commonly provided in memory arrays 2a to 2d. Data buses DB0 and DB1 are not provided with a bus selector / driver for switching connection paths according to the word configuration. Data bits are input / output from / to the outside of the apparatus via pads PPD0 and PPD1. The semiconductor memory device 1 can operate in either a × 2 bit configuration or a × 1 bit configuration word configuration. The setting of the word configuration is specified by setting a specific bonding pad to a predetermined voltage level, for example.

  Each of memory arrays 2a to 2d can be driven to a selected state independently of each other, and memory arrays 2a to 2d constitute bank # 0 to bank # 3, respectively. In memory arrays 2a to 2d, array IO lines AIO0 and AIO1 corresponding to pads PPD0 and PPD1 are arranged, respectively. In the × 2 bit configuration, data is transmitted to array IO lines AIO0 and AIO1. In the case of the × 1 bit configuration, data to be read is output to one of array IO lines AIO0 and AIO1. This selection mode will be described in detail later. Here, only the fact that a plurality of memory cells are selected simultaneously in the memory arrays 2a to 2d regardless of the word configuration will be described here.

  In each of memory arrays 2a to 2d, array IO line AIO0 is coupled to data bus DB0 via read data drivers 4aa, 4ba, 4ca and 4da, respectively. On the other hand, in each of memory arrays 2a to 2d, array IO line AIO1 is coupled to data buses DB0 and DB1 via two read data drivers provided in the column local circuit. That is, in memory array 2a, array IO line AIO1 is coupled to data buses DB0 and DB1 via read data drivers 4ab and 4ac, respectively. In memory array 2b, array IO line AIO1 is coupled to data buses DB0 and DB1 via read data drivers 4bb and 4bc, respectively. In memory array 2c, array IO line AIO1 is coupled to data buses DB0 and DB1 via read data drivers 4cb and 4cc. In memory array 2d, array IO line AIO1 is coupled to data buses DB0 and DB1 via read data drivers 4db and 4dc, respectively.

  Depending on the word configuration, one of the set of read data drivers 4ab, 4bb, 4cb and 4db and the set of read data drivers 4ac, 4bc, 4cc and 4dc is set in an operable state. In the 1-bit configuration, 1-bit data is transferred through the data bus DB0. In this case, the pad PPD0 is used and the pad PPD1 is not used. Output control circuits 5a and 5b are arranged in proximity to pads PPD0 and PPD1, respectively. These output control circuits 5a and 5b amplify data transferred via data buses DB0 and DB1 and output the amplified data to corresponding pads PPD0 and PPD1.

  FIG. 2 is a diagram showing the arrangement of read data drivers when the semiconductor memory device shown in FIG. In FIG. 2, in the × 1 bit configuration, read data drivers 4ab, 4bb, 4cb and 4db are set in an operable state, and array IO lines AIO0 and AIO1 of memory arrays 2a to 2d are coupled to data bus DB0. The In each of the memory arrays 2a to 2d, which of the two read data drivers is selected is determined by using one bit of the column address signal. Therefore, for example, when memory 2a is accessed, one of read data drivers 4aa and 4ab is selected according to the address signal and outputs data to data bus DB0. In this case, as will be described later, an address signal is not applied to read data drivers 4aa to 4bb, but selective activation is performed according to, for example, a preamplifier address signal bit in the previous stage, and the read data driver is operated according to the read data. The output high impedance state may be set. Thus, 1-bit data can be input / output via pad PPD0.

  FIG. 3 is a diagram showing the arrangement of read data drivers when the semiconductor memory device 1 has a × 2 bit configuration. In FIG. 3, in memory arrays 2a to 2d, read data drivers 4ac, 4bc, 4cc, and 4dc are set in an operable state. Therefore, in the arrangement shown in FIG. 3, array IO lines AIO0 and AIO1 of memory arrays 2a to 2d correspond to data buses DB0 and DB1, respectively, and 2-bit data can be read out.

  Therefore, since the read data driver is selectively set in an operable state according to the word configuration and the correspondence relationship between the array IO line and the data bus is changed, a selector for changing the connection path of the data bus Is unnecessary, and high-speed data transfer can be realized.

  FIG. 4 is a diagram more specifically showing a configuration for one memory array. FIG. 4 shows a configuration of a portion corresponding to array IO line AIO1. Memory array 2 is divided into a plurality of column blocks C # 0 to C # n. For each of these column blocks C # 0 to C # n, read data drivers 4x0 to 4xn set to an operable state when selection signal SEL0 is activated and an operable state when selection signal SEL1 is activated are set. Read data drivers 4y0 to 4yn are provided. The read data drivers 4x0 to 4xn have their outputs commonly connected to the data bus DB0, and the read data drivers 4y0 to 4yn have their outputs commonly connected to the data bus DB1. Read data drivers 4x0 and 4y0 are activated when block select signal BS0 is activated, and amplify data read from column block C # 0.

  Read data drivers 4x1 and 4y1 are activated when block selection signal BS1 is activated. Read data drivers 4xn and 4yn are activated when block select signal BSn is activated. These block selection signals BS0 to BSn indicate that column blocks C # 0 to C # n are selected, respectively. These read data drivers 4x0 to 4xn and 4y0 to 4yn are set to an output high impedance state when inactive. When selection signal SEL (SEL0, SEL1) and block selection signal BS (BS0-BSn) are both active, the corresponding read data driver is activated and the data read from the corresponding column block is transferred to data bus DB0 or Transmit to DB1.

  By providing a read data driver for each of the column blocks C # 0 to C # n, the signal transmission time from each column block to the data bus DB0 or DB1 is the same, and there is no need to consider a timing margin, and data can be transferred at high speed. Reading can be performed.

  Block selection signals BS0 to BSn are generated by decoding the lower bits of the column address signal.

  FIG. 5 is a diagram illustrating an example of the configuration of the selection signal generation unit. In FIG. 5, a high-resistance resistance element Rz connected between a node ND connected to a specific pad PAD and a ground node, an inverter IV0 for inverting the signal of the node ND, and an output signal of the inverter IV0 are inverted. An inverter IV1 is provided. A selection signal SEL0 is output from the inverter IV0, and a selection signal SEL1 is output from the inverter IV1. Pad PAD is connected to frame lead FL for selectively transmitting power supply voltage Vcc through bonding wire BW. When pad PAD and frame lead FL are connected by bonding wire BW, node ND is at power supply voltage Vcc level, selection signal SEL0 is at L level, selection signal SEL1 is at H level, and connection of data bus DB1 is designated. The On the other hand, when the bonding wire BW is not provided for the pad PAD or when the pad PD is set to the ground voltage level (when there is a ground pad in the vicinity), the node ND becomes the ground voltage level and the selection signal SEL0. Becomes H level, the selection signal SEL1 becomes L level, and the connection to the data bus DB0 is designated.

  When the block selection signals BS0 to BSn are generated, when switching between the × 2 bit configuration and the × 1 bit configuration, the least significant bit of the address signal for block selection is in accordance with the selection signal SEL0 activated in the × 1 bit configuration. It is set to a degenerated state (both complementary bits are selected). As a result, in the x2 bit configuration, data from two column blocks are output in parallel, and in the x1 bit configuration, data from one column block is output to the data bus DB0.

  In the configuration shown in FIG. 4, column blocks C # 0 to C # n are shown to be configured by adjacent columns. However, these column blocks C # 0 to C # n may be arranged in a distributed manner in the memory array 2. That is, a configuration in which adjacent columns are included in different column blocks may be employed.

  In the configuration shown in FIG. 4, a set of read data drivers is arranged for each of column blocks C # 0 to C # n. However, a preamplifier is provided for each of column blocks C # 0 to C # n, and the outputs of the preamplifiers of these column blocks C # 0 to C # n are commonly coupled to a set of read data drivers. Good. A configuration in which the preamplifier is set to the output impedance state when not selected may be used.

[Example of change]
FIG. 6 schematically shows a configuration of a modification of the first embodiment of the present invention. FIG. 6 also shows a semiconductor memory device that can switch the word configuration between a × 1 bit configuration and a × 2 bit configuration. In the semiconductor memory device shown in FIG. 6, a data bus control circuit for writing and reading data is arranged in place of the read data driver. That is, in memory array 2a, data bus control circuit 6aa is arranged for array IO line AIO0, and data bus control circuits 6ab and 6ac are provided for array IO line AIO1. In memory array 2b, data bus control circuit 6ba is arranged for array IO line AIO0, and data bus control circuits 6bb and 6bc are arranged for array IO line AIO1. In memory array 2c, data bus control circuit 6ca is arranged for array IO line AIO0, and data bus control circuits 6cb and 6cc are arranged for array IO line AIO1. In memory array 2d, data bus control circuit 6da is arranged for array IO line AIO0, and data bus control circuits 6db and 6dc are arranged for array IO line AIO1.

  Input / output control circuits 7a and 7b for inputting / outputting data are arranged in the vicinity of pads PPD0 and PPD1.

  In the configuration shown in FIG. 6, data buses DB0 and DB1 transmit both write data and read data. Other configurations are the same as those shown in FIG. Therefore, in the configuration shown in FIG. 6, both write data and read data can be transmitted at high speed, and both data buses DB0 and DB1 are used for transmitting write data and read data. Compared with a configuration in which a data bus for transmitting write data and a data bus for transmitting read data are provided separately, the bus occupation area can be greatly reduced (each bus does not require a selector for path switching). To be).

  Data bus control circuits 6aa, 6ba, 6ca and 6da are always set to an operable state regardless of the word configuration. The data bus control circuit for the selected bank (memory array) is activated. On the other hand, one of the set of data bus control circuits 6ab, 6bb, 6cb and 6db and the set of data bus control circuits 6ac, 6bc, 6cc and 6dc is set in an operable state in accordance with the selection signal.

  FIG. 7 schematically shows a structure of a data bus control circuit for one memory array (bank) shown in FIG. In FIG. 7, data bus control circuits 6ia (i = a to d) are provided for array IO line AIO0, and data bus control circuits 6ic and 6ib are provided for array IO line AIO1. Data bus control circuit 6ia receives power supply voltage Vcc as a selection signal, is always set in an operable state, transmits read data RD0 to data bus DB0, and generates write data WD0 from data on data bus DB0. .

  Data bus control circuit 6ib is set in an operable state when select signal SEL0 is activated, and exchanges read data RD1 and write data WD1 between data bus DB0 and array IO line AIO1. Data bus control circuit 6ic is set to an operable state when select signal SEL1 is activated, and exchanges read data RD1 and write data WD1 between array IO line AIO1 and data bus DB1. Therefore, at the time of writing / reading, array IO line AIO1 is selectively coupled to data bus DB0 or DB1 according to the word configuration.

  Data bus control circuits 6ia, 6ib and 6ic are arranged corresponding to the respective column blocks of the memory array as shown in FIG.

  FIG. 8 shows an example of a specific configuration of the data bus control circuit shown in FIG. Since the data bus control circuits 6ia to 6ib have the same configuration, one data bus control circuit 6 is representatively shown in FIG. Data bus control circuit 6 includes a read data driver 4 that drives data bus DB in accordance with complementary read data RD and / RD, and a write data driver 8 that generates internal write data WD in accordance with data from data bus DB. Data bus DB includes complementary bus lines DBB and / DBB.

  Read data driver 4 includes an AND circuit G1 that receives read data driver activation signal RDRVj and selection signal SEL, a NAND circuit G2 that receives read data RD and an output signal of AND circuit G1, and an output signal of AND circuit G1. NAND circuit G3 receiving read data / RD, inverter G4 receiving the output signal of NAND circuit G3, inverter G5 receiving the output signal of NAND circuit G2, and when the output signal of NAND circuit G2 is at L level, P channel MOS transistor QT1 for driving output node DL to power supply voltage Vcc level, n channel MOS transistor QT2 for driving output node DL to ground voltage level, and conducting when output signal of inverter G4 is at H level, NAND circuit Conducted when the output signal of G3 is L level, P channel MOS transistor QT3 for driving power node / DL to power supply voltage Vcc level, and n channel MOS transistor QT4 for conducting output node / DL to the ground voltage level and conducting when output signal of inverter G5 is at H level. .

  Output nodes DL and / DL are connected to data bus lines DBB and / DBB, respectively. Selection signal SEL is selectively set to H level or L level according to the word configuration, and corresponds to selection signal SEL1 or SEL0 or power supply voltage Vcc shown in FIG.

  The write data driver 8 receives a NAND circuit G6 that receives the write data driver activation signal WDEj, the selection signal SEL, and the signal of the output node DL, the selection signal SEL, the write data driver activation signal WDEj, and the signal of the node / DL. It includes a NAND circuit G7 that receives the signal, a NAND circuit G8 that receives an output signal from the NAND circuit G6, and a NAND circuit G9 that receives an output signal from the NAND circuit G7. The output signal of NAND circuit G8 is applied to the input section of NAND circuit G9, and the output signal of NAND circuit G9 is applied to the input section of NAND circuit G8. These NAND circuits G8 and G9 constitute a flip-flop. Write data WD is generated from NAND circuit G8. Although write data WD does not take the form of complementary signals, when array IO lines are provided in common, this write data WD is also complementary data. Alternatively, a write driver provided in the memory array may be configured to generate complementary data from the write data WD and write it to the selected memory cell. Hereinafter, the operation of the data bus control circuit 8 shown in FIG. 8 will be described.

  When selection signal SEL is at L level, the output signal of AND circuit G1 is at L level, and the output signals of NAND circuits G2 and G3 are at H level. Therefore, nodes LRD and / LRD attain H level, so that MOS transistors QT1-QT4 are all turned off, and read data driver 4 is in an output high impedance state.

  Also in write data driver 8, the output signals of NAND circuits G6 and G7 are fixed at the H level, and transmission of write data WD to the output portions of data of nodes DL and / DL is prohibited.

  When the selection signal SEL is set to H level, the AND circuit G1 operates as a buffer circuit. In read data driver 4, when read data driver activation signal RDRVj is in the active state of H level, the output signal of AND circuit G1 becomes H level, NAND circuits G2 and G3 operate as inverters, and read data RD and / RD Invert. When read data RD is at H level, node / LRD is at L level, MOS transistors QT1 and QT4 are rendered conductive, node DL is driven to H level, and node / DL is driven to L level. Conversely, when read data RD is at L level and read data / RD is at H level, node / LRD is at H level, node LRD is at L level, MOS transistors QT2 and QT3 are turned on, and node DL is at L level. The level and node / DL are at the H level. Thus, when read data driver activation signal RDRVj is activated, read data can be generated according to read data RD and / RD and transmitted to data bus lines DBB and / DBB.

  In write data driver 8, when write data driver activation signal WDEj attains H level, NAND circuits G6 and G7 operate as inverters, and the data transmitted to nodes DL and / DL via data bus DB is the NAND circuit. Transmitted to G8 and G9 and latched. When node DL is at H level, the output signal of NAND circuit G6 is at L level, and write data WD from NAND circuit G8 is at H level. Conversely, when node DL is at L level and node / DL is at H level, the output signal of NAND circuit G7 is at L level, and the output signal of NAND circuit G6 is at H level. Embedded data WD is at L level.

  Data bus control circuit 6 shown in FIG. 8 is held in the output high impedance state during data reading and in a non-selected state. Therefore, for example, even when data bus control circuits 6ia and 6ib are coupled to data bus DB0 in FIG. 7, selected data bus control circuit 6ia or 6ib can accurately transmit read data to data bus DB0. it can. In addition, when data is written, the write data driver is prohibited from accepting the data when not selected. Therefore, the selected data bus control circuit accurately follows the write data on the data bus in the corresponding memory array. Data can be transmitted to the selected memory cell in the memory block.

  The data bus control circuit shown in FIG. 8 is arranged corresponding to each memory column block of the corresponding memory array, similarly to the configuration shown in FIG. Activation signals RDRVj and WDEj are activated for the data bus control circuit provided for the selected column block.

  FIG. 9 schematically shows a structure of the activation signal generating portion shown in FIG. 9, the control circuit receives a clock signal extCLK from the outside and generates an internal clock signal CLK, a control signal from the outside in synchronization with the internal clock signal CLK from the clock generation circuit 20, That is, a command that takes in a chip select signal / CS, a row address strobe signal / RAS, a column address strobe signal / CAS, and a write enable signal / WE, determines a specified operation mode, and outputs a signal indicating the determination result In response to a control signal from decode circuit 21 and command decode circuit 21, an address generation circuit 22 that takes in an external address signal ADD and generates an internal row and column address signal is included. These clock generation circuit 20, command decode circuit 21 and address generation circuit 22 are used in common by banks # 0 to # 3 and constitute a main control circuit. Command decode circuit 21 determines the designated operation mode according to the states of external control signals / CS, / RAS, / CAS and / WE at the rising edge of internal clock signal CLK. A combination of the states of external control signals / CS, / RAS, / CAS and / WE at the rising edge of internal clock signal CLK is referred to as “command”. Command decode circuit 21 decodes this command and generates read operation instruction signal φr, write operation instruction signal φw, and the like according to the decoding result.

  Address ADD applied to address generation circuit 22 includes a bank address that specifies a bank and a block address that specifies a column block included in one memory array.

  The control circuit further includes a read control circuit 23 for holding the read activation signal RP in an active state for a predetermined cycle of the internal clock signal CLK in accordance with the activation of the read operation instruction signal φr from the command decode circuit 21, and a command decode circuit. In response to the activation of the write operation instruction signal φw from 21, the write control circuit 24 that holds the write activation signal WP in an active state for a predetermined cycle period of the internal clock signal CLK and the internal clock signal CLK operate. And a block decoder 25 for decoding a block address among the internal addresses supplied from the address generation circuit 22 to generate a signal indicating a memory column block.

  Each of read control circuit 23 and write control circuit 24 includes a counter that counts internal clock signal CLK therein, and activates activation signals RP and WP for a burst long period. Here, “burst length” indicates the number of data that can be continuously read or written when one read command or write command is given.

  The control circuit further activates the shifter 26 that shifts the read activation signal RP from the read control circuit 23 by the internal clock signal CLK and delays it for a predetermined period, and the write activation signal WP from the write control circuit 24. In response, a WDE generation circuit 27 that generates a write data driver activation signal WDE in synchronization with the internal clock signal CLK, a shifter 28 that shifts a block selection signal from the block decoder 20 in synchronization with the internal clock signal CLK, RDRV generation circuit 29 for generating read data driver activation signal RDRV in accordance with the output signal of shifter 26, activation data RDRV from RDRV generation circuit 29, and block selection signal BSj from shifter 28 are received to activate read data driver AND circuit 30 for generating signal RDRVj and shifter 28 And an AND circuit 31 for generating write data driver activation signal WDEj receiving block selection signal BSj of the activation signal WDE from WDE generation circuit 20.

  The read control circuit 23, the write control circuit 24, the block decoder 25, and the subsequent circuit constitute a local control circuit and are activated according to a bank address signal supplied from the address generation circuit 22. The local control circuit is provided corresponding to each bank. WDE generation circuit 27 and RDRV generation circuit 29 are each formed of a one-shot pulse generation circuit that generates a one-shot pulse in response to the rising of internal clock signal CLK. Next, the operation of the control circuit shown in FIG. 9 will be described with reference to the timing chart shown in FIG.

  First, an operation during data reading will be described with reference to FIG. In FIG. 10A, control signals / CS, / RAS, / CAS, and / WE from the outside are collectively shown as commands. In clock cycle #a, a read command instructing data reading is applied. In accordance with this read command, read instruction signal φr from command decode circuit 21 is in an H level active state for a predetermined period, and read activation signal RP from read control circuit 23 is held in an H level active state for a burst long period. In accordance with this read command, an address from address generation circuit 22 is applied to block decoder 25. The block decoder 25 decodes the block address signal supplied from the address generation circuit 22 and generates a block selection signal BS for designating a memory column block. The block selection signal from the block decoder 25 changes every clock cycle of the internal clock signal CLK. This is because the address generation circuit 22 sequentially generates an address signal in a predetermined sequence using the counter included therein for the burst long period, using the address signal applied to the clock cycle #a as the head address. is there. Shifter 26 shifts read activation signal RP from read control circuit 2 in accordance with internal clock signal CLK. The shifter 26 performs a shift operation during a (CAS latency-2) clock cycle period. FIG. 10A shows the operation when the CAS latency is 3. Therefore, the output signal of shifter 26 rises to H level in clock cycle #b, and the output signal of shifter 26 is driven to H level for a burst long period, that is, for 4 clock cycle periods. RDRV generation circuit 29 is activated when the output signal of shifter 26 is in an active state of H level, and generates a one-shot pulse signal in synchronization with the rising of internal clock signal CLK to generate a read data driver activation signal. RDRV is generated.

  On the other hand, the shifter 28 also shifts and outputs the block selection signal from the block decoder 25 by a (CAS latency-2) clock cycle period. Therefore, block selection signal BSj is sequentially determined from clock cycle #b. The AND circuit 30 generates a read data driver activation signal RDRVj provided for each memory column block according to the output signal of the RDRV generation circuit 29 and the block selection signal from the shifter 28. Therefore, in the period from clock cycle #b to clock cycle #e, read data driver activation signal RDRVj is sequentially driven to an active state for a predetermined period in accordance with the block selection signal.

  This read data driver activation signal RDRVj is delayed for one clock cycle after a read command is applied for one clock cycle until data is transferred from the selected memory cell to the read data driver via the preamplifier. This is because a period is required.

  Next, an operation at the time of data writing will be described with reference to a timing chart of FIG. A write command is applied in clock cycle #a. In accordance with this write command, write operation instruction signal φw from command decode circuit 21 is in an active state at an H level for a predetermined period, and accordingly, write activation signal WP from write control circuit 24 is in an active state at an H level during a burst length clock cycle period. Retained. FIG. 10B also shows a case where the burst long period is a period of 4 clock cycles. In response to activation of write activation signal WP, WDE generation circuit 27 generates a one-shot pulse signal in response to the rise of internal clock signal CLK to generate write data driver activation signal WDE. . Block selection signal BS is output from block decoder 25 in clock cycle #a to clock cycle #d. A write data driver activation signal WDEj for activating the write data driver provided for the selected column block is sequentially generated from the AND circuit 31 according to the block selection signal BS and the write data driver activation signal WDE. Is done. Also in FIG. 10B, when the CAS latency is 2, the write data driver activation signal WDE is generated at the same timing. This is because one clock cycle period is required until data is written from the write data driver to the selected memory cell via the write driver (until the selected memory cell data is transmitted to the read data driver at the time of reading). 1 clock cycle period is required for writing to the same clock cycle period).

  Therefore, as shown in FIG. 9, by shifting block selection signal BS using shifter 28, the read data driver activation signal is driven to the active state accurately in accordance with the read data transmission timing. Can do.

  As described above, according to the first embodiment of the present invention, the data bus is provided corresponding to each pad, and the read data driver or the write data driver is selectively connected between the IO line of the memory array and the data bus. Therefore, a selector for switching the bus connection in the data bus becomes unnecessary, and data can be transferred at high speed. Further, no selector is required, and the circuit occupation area can be reduced.

[Embodiment 2]
FIG. 11 schematically shows a structure of a main portion of the semiconductor memory device according to the second embodiment of the present invention. FIG. 11 representatively shows a configuration of column local circuit 3 for one memory array 2. A similar configuration is provided for the remaining memory arrays.

  Memory cell 2 is divided into a plurality of column blocks C # 0 to C # n. In column local circuit 3, internal write / read circuits 30-0 to 30-n are provided corresponding to column blocks C # 0 to C # n, respectively. Internal write / read circuits 30-0 to 30-n have the same configuration, and FIG. 11 representatively shows the configuration of internal write / read circuit 30-0.

  Internal write / read circuit 30-0 amplifies data on array IO line AIO0 provided for column block C # 0 in response to activation of preamplifier activation signal PEA0; A shifter 34 that shifts the output signal in synchronization with the internal clock signal CLK, a data bus control circuit 60b that transmits output data RD of the shifter 34 to the data bus DB0, and internal read data RD from the shifter 34 to the data bus DB1 A data bus control circuit 60c for transmission is included. Data bus control circuits 60b and 60c also generate internal write data WD according to the data on data buses DB0 and DB1, respectively, at the time of data writing. Data bus control circuits 60b and 60c are set in an operable / inoperable state by selection signals SEL0 and SEL1, respectively. Since data bus control circuits 60b and 60c have the same configuration, FIG. 11 representatively shows the configuration of data bus control circuit 60b.

  The data bus control circuit 60b is activated in accordance with the activation of the selection signal SEL0 and the read data driver activation signal RDRV0 and drives the data bus DB0 in accordance with the read data RD from the shifter 35, and the selection signal SEL0 and the write signal A write data driver 8 that is activated in accordance with activation of data driver activation signal WDE0 and generates internal write data WD from data on data bus DB0 is included. The specific configuration of these data bus control circuits 60b and 60c is the same as the configuration shown in FIG. However, the preamplifier 32 does not particularly need to generate complementary data RD and / RD. Similar to the write data WD, only one data RD may be generated. Therefore, in the second embodiment, the configuration of the preamplifier 32 is arbitrary. Array IO line AIO0 is normally composed of complementary bus lines, and the write driver generates complementary data in accordance with write data WD from data bus control circuits 60b and 60c to complement column block C # 0. This is transmitted to the data bus line, but this is not shown in FIG.

  The shifter 34 performs a shift operation for (CAS latency-2) clock cycle period. That is, the output data of the preamplifier 32 is output with a delay of (CAS latency-2) clock cycles. In column local circuit 3, when a mask instruction signal DQMi for instructing a mask for writing / reading data is activated, the data bus control circuit is deactivated in this clock cycle. The input / output control circuit 7a does not perform data masking, but the internal writing / reading circuit masks writing / reading. Thereby, as will be described later, it is possible to prevent collision of write data and read data in the data bus DB0 or DB1 even during an interrupt operation for switching to data writing during data reading.

  FIG. 12 schematically shows a structure of a control signal generating portion of the semiconductor memory device according to the second embodiment of the present invention. In addition to the configuration of the control signal generator shown in FIG. 9, the control signal generator shown in FIG. 12 further includes a DQM buffer 35 that receives an external mask instruction signal DQM and generates an internal mask instruction signal DQMi. Provided. In addition, a PAE generation circuit 37 is provided that generates a preamplifier activation signal PAEF in synchronization with the internal clock signal CLK when the read activation signal RP from the read control circuit 23 is activated. Preamplifier activation signal PAEF from PAE generation circuit 37 is ANDed with block selection signal BSj from block decoder 25 in gate circuit G12 to generate preamplifier activation signal PAEj for column block C # j. The

  The DQM buffer 35 takes in an external mask instruction signal DQM in synchronization with the rising of the internal clock signal CLK, holds the mask instruction signal DQM taken in during the clock cycle period, and generates an internal mask instruction signal DQMi. RDRV generation circuit 29 and WDE generation circuit 27 are disabled when internal mask instruction signal DQMi from DQM buffer 35 is activated, and drives activation signals WDEF and RDRVF to an inactive state. Therefore, internally, when a mask instruction is given from the outside, the data bus control circuit is deactivated in the clock cycle, and reading / writing of internal data in the clock cycle is prohibited. The configuration of the control unit shown in FIG. 12 is a circuit configuration when the CAS latency CL is 3. Shifters 26 and 28 perform a shift operation for one clock cycle period. Next, the operation of the circuit shown in FIGS. 11 and 12 will be described with reference to the timing chart shown in FIG.

  A read command is applied in cycle #a of clock signal CLK, and read activation signal RP from read control circuit 23 is held in an active state for a burst long period (four clock cycle periods). Shifter 26 delays read activation signal RP from read control circuit 23 by one clock cycle period to generate delayed read activation signal RP2 and applies it to RDRV generation circuit 29. PAE generation circuit 37 is activated when read activation signal RP from read control circuit 23 is activated, and generates a one-shot pulse signal in response to internal clock signal CLK to generate preamplifier activation signal PAEF. . Therefore, PAE generation circuit 37 drives preamplifier activation signal PAEF to the active state in each clock cycle #a, #b, #c and #d.

  On the other hand, RDRV generation circuit 29 generates a one-shot pulse signal and generates read data driver activation signal RDRVF in synchronization with internal clock signal CLK after one clock cycle has elapsed since the read command was given. . The activation timing of read data driver activation signal RDRVF is earlier than the activation of preamplifier activation signal PAEF in each clock cycle. This is because, even when the CAS latency is 2, data is accurately transmitted on the data bus DB without causing data collision.

  In the clock cycle #c, when the external mask designating signal DQM is driven to the active state of H level, in this clock cycle #c, the internal mask designating signal DQMi is driven to the active state of H level, and accordingly RDRV Generation circuit 29 is deactivated. Therefore, in this clock cycle #c, all read data drivers are inactivated and in an output high impedance state. New data is not transmitted to the data bus DB (DB0, DB1). In this state, the data bus DB is held at a predetermined voltage level in the standby state (this configuration will be described in detail later).

  In clock cycle #b, the read data driver is activated in accordance with read data driver activation signal RDRVF, and first read data R0 is transmitted to data bus DB. The data R0 on the data bus DB is output as external data DQ via the data bus DB and the input / output control circuit 7 (7a, 7b).

  In clock cycle #c, the read data driver activation signal is inactive, so that external data is masked in clock cycle #d.

  In clock cycle #d, external mask instruction signal DQM is inactive at L level, and accordingly internal mask instruction signal DQMi is also at L level in this clock cycle. Therefore, read data driver activation signal RDRVF is activated again, and new data is transmitted to data bus DB.

  On the other hand, external data mask instruction signal DQM is again driven to an active state of H level at clock cycle #e, and internal mask instruction signal DQMi attains an H level at clock cycle #e, and read data driver activation signal RDRVF is The read data drivers 60b and 60c are all set to the output high impedance state.

  A write command is applied in the next clock cycle #f. Simultaneously with the write command, write data W0 is applied from the outside. In accordance with this write command, write activation signal WP from write control circuit 24 is driven to an active state, and in response, write data driver activation signal WDEF from WDE generation circuit 27 is driven to an active state. As a result, the data transmitted from the input / output control circuit 7 (7a, 7b) to the data bus DB (DB0, DB1) is amplified by the write data driver 8 and written to the selected memory cell. Next, when external mask instruction signal DQM is driven to the active state of H level again in clock cycle #g, internal mask instruction signal DQMi becomes H level in clock cycle #g, and write data driver activation signal WDEF is Writing to the selected memory cell of write data W1 held in the inactive state and transmitted to data bus DB is prohibited.

  As shown in FIG. 13, DQM latency (clock cycle period required from when an external mask instruction is given to when data is actually masked) is 2 in the read mode, and is internally 1 Mask the read data before the clock cycle. Thereby, it is possible to prevent the read data R3 and the write data W0 from colliding in the data bus DB at the time of transition from the read operation to the write operation. Thus, even when the data bus DB is used for both data writing and data reading, writing and reading can be performed accurately without any data collision.

  For read data R2, when a write command is applied, read activation signal RP is deactivated to complete the read operation, and the input / output control circuit activates the data input circuit, By adopting a configuration in which the output circuit is inactivated, it is possible to prevent collision between read data from the inside at external data input / output terminal DQ and write data given from an external device.

  FIG. 14 is a diagram illustrating an example of the configuration of the DQM buffer. In FIG. 14, DQM buffer 35 includes a transfer gate 35a that is selectively turned on in response to internal clock signal / CLK, an inverter latch 35b that inverts and latches data applied from transfer gate 35a, and an internal clock. Transfer gate 35c that conducts in synchronization with signal CLK and transmits the latch signal of inverter latch 35b, and inverter latch 35d that latches and inverts the signal applied from transfer gate 35c to generate internal mask instruction signal DQMi .

  In the configuration of DQM buffer 35 shown in FIG. 14, when internal clock signal CLK is at H level, transfer gate 35a is non-conductive and transfer gate 35c is conductive, and the latch signal of inverter latch 35b is transmitted to inverter latch 35d. Is done. When internal clock signal CLK is at L level, transfer gate 35a is turned on, transfer gate 35c is turned off, and external mask instruction signal DQM is newly latched by inverter latch 35b. Inverter latch 35d generates internal mask instruction signal DQMi according to the signal transmitted when internal clock signal CLK is at H level. Thus, external mask instruction signal DQM can be taken in synchronization with the rise of internal clock signal CLK, and internal mask instruction signal DQMi can be generated according to the external mask instruction signal taken during the clock cycle period.

  RDRV generation circuit 29 and PAE generation circuit 37 are each configured to be activated when read activation signal RP2 or RP is activated and generate a one-shot pulse signal in response to the rise of internal clock signal CLK. That's fine. This one-shot pulse generation operation is prohibited when internal mask instruction signal DQMi is at H level. This is easily realized by taking the logical product of the output signal of the one-shot pulse generation circuit and the inverted signal of the internal mask instruction signal DQMi.

  Note that the write data driver activation signal WDEF from the WDE generation circuit 27 is deactivated in accordance with the mask instruction signal DQMi, so that data can be transferred even during the transition from the data write operation to the data read operation as shown below. Collision of write data on the bus and array IO line can be prevented.

  FIG. 15 is a timing chart showing an operation when the write operation is interrupted by the read operation. In FIG. 15, a write command is applied in clock cycle #a, and write activation signal WP is driven to an active state. In accordance with write activation signal WP, WDE generation circuit 27 drives write data driver activation signal WDEF to an active state in synchronization with internal clock signal CLK, and is generated in accordance with write data supplied from the outside, and is applied to the data bus. Write data W0 and W1 transmitted to DB are written to the selected memory cell.

  In the clock cycle #c, when the external mask designation signal DQM is driven to the H level, the internal mask designation signal DQMi is driven to the H level active state in the clock cycle #c. In this case, WDE generation circuit 27 is inactivated, and write data driver activation signal WDEF is in an inactive state of L level. Therefore, in this case, write data WD2 transmitted to data bus DB is not transmitted to the selected memory cell array.

  When a read command is applied in clock cycle #d, read activation signal RP from read control circuit 23 is driven to an active state. Thus, preamplifier activation signal PAEF is driven to an active state from clock cycle #d in synchronization with internal clock signal CLK in each clock cycle. Write activation signal WP is driven to an inactive state in accordance with this read command. Therefore, write data driver activation signal WDEF is kept inactive. Data bus DB is in a standby state during clock cycle #d. In this clock cycle #d, a memory cell is selected in the memory array, and data in the selected memory cell is transmitted to the preamplifier via the array IO line. In this clock cycle #d, write data is not transmitted (by internal mask instruction signal DQMi). Therefore, collision of write data and read data on the array IO line can be prevented, and read data R0, R1, and R2 are sequentially applied to data bus DB in accordance with read data driver activation signal RDRVF after clock cycle #e. Can be output. Therefore, by controlling WDE generation circuit 27 with internal mask instruction signal DQMi, collision of write data and read data can be prevented even when the write operation is changed to the read operation.

  FIG. 16 is a diagram schematically showing the configuration of the control circuit when the CAS latency is 2. As shown in FIG. When CAS latency is 2, read activation signal RP from read control circuit 23 is applied to RDRV generation circuit 29. Preamplifier activation signal PAEFF from PAE generation circuit 37 is applied to RDRV generation circuit 29. Other configurations are the same as those shown in FIG. Preamplifier activation signal PAEFF is driven to an active state at a timing faster than preamplifier activation signal PAEF. RDRV generation circuit 29 drives read data driver activation signal RDRVF to an active state in response to activation of preamplifier activation signal PAEFF when read activation signal RP is activated. Next, the operation of the control unit shown in FIG. 16 will be described with reference to the timing chart shown in FIG.

  When a read command is applied in clock cycle #a, read activation signal RP from read control circuit 23 is driven to an active state. From this clock cycle #a, PAE generation circuit 37 generates preamplifier activation signals PAEF and PAEFF in accordance with internal clock signal CLK. In accordance with preamplifier activation signal PAEFF, RDRV generation circuit 29 drives read data driver activation signal RDRVF to an active state. As a result, the read data driver amplifies the data read from the selected memory cell and transmits it to the data bus DB. Therefore, read data R0 and R1 are transmitted to data bus DB in clock cycles #a and #b, respectively. In clock cycle #b, data R0 transmitted on data bus DB is output to the outside, and is sampled by an external device at the rise of clock signal CLK in clock cycle #c.

  When external mask designating signal DQM is set to H level in clock cycle #c, internal mask designating signal DQMi is activated to H level in clock cycle #c, and RDRV generation circuit 29 is deactivated. The Therefore, in clock cycle #c, read data driver activation signal RDRVF maintains an inactive state, and data bus DB maintains a standby state.

  When a write command is applied in clock cycle #d, read activation signal RP is deactivated, and write activation signal WP from write control circuit 24 is driven to an active state. From this clock cycle #d, WDE generation circuit 27 drives write data driver activation signal WDEF to the active state. Therefore, in accordance with externally applied write data W0 and W1, write data W0 and W1 are transmitted to data bus DB, and write data W0 and W1 on these data bus DB are selected by a write data driver. It is transmitted to the memory cell.

  Even when the CAS latency is 2, the read data and the write data collide with each other in the data bus DB by activating the external mask instruction signal DQM in a cycle one clock cycle before the cycle in which the read operation is interrupted. Can be prevented.

  In the configuration shown in FIG. 16, when the CAS latency is 2, the shifter 26 is shown not to be used. However, it is only necessary to change the number of shift stages in the shifter 26 according to the information indicating the CAS latency CL. That is, the number of shift stages may be set to 0. RDRV generation circuit 29 may be configured to select one of internal clock signal CLK and preamplifier activation signal PAEFF in accordance with CAS latency information CL. Therefore, the same circuit configuration can be used for both the CAS latency of 2 and 3 and there is no need to provide a dedicated circuit configuration.

  As described above, according to the second embodiment of the present invention, the read data driver and the write data driver are held in the inactive state in the clock cycle in accordance with the external mask instruction signal. In the case of shifting to the writing operation and vice versa, the collision between the read data and the write data can be reliably prevented, and the data bus can be used to transmit both the write data and the read data. it can.

[Embodiment 3]
FIG. 18 schematically shows a structure of a main portion of the semiconductor memory device according to the third embodiment of the present invention. In FIG. 18, the configuration of column local circuit 3a for memory array 2a is shown, but column local circuits 3b-3d having the same configuration are also provided in remaining memory arrays 2b-2c. Memory array 2a is divided into a plurality of column blocks C # 0, C # 1,..., C # m, C # n. Corresponding to each of these column blocks C # 0-C # n, array IO line pairs AIO0-AIOn for transmitting complementary data signals are arranged.

  Column local circuit 3a includes internal read circuits 30 # 0a-30 # na provided corresponding to each of array IO line pairs AIO0-AIOn. Internal read circuits 30 # 0a-30 # na have preamplifiers 32 # 0-32 # n for amplifying complementary signals of corresponding array IO line pairs AIO0-AIOn and output signals of corresponding preamplifiers 32 # 0-32 # n. CL shifters 34 # 0 to 34 # n for shifting the data buses and read data drive circuits 4 # 0 to 4 # n for driving data bus DB0 or DB1 in accordance with the output signals of corresponding CL shifters 34 # 0 to 34 # n. .

  Preamplifiers 32 # 0 to 32 # n are selectively activated by preamplifier activation signal PAF (PAEF or PAEFF) and block selection signal BS. These preamplifiers 32 # 0 to 32 # n can output ternary data, and in a standby state, their complementary output signals are both set to "L".

  CL shifters 34 # 0-34 # n transfer the output signals of corresponding preamplifiers 32 # 0-32 # n according to preamplifier activation signal PAF (PAEF) and read data driver activation signal RDRV. These CL shifters 34 # 0 to 34 # n can also transmit complementary data signals (ternary data). Buffering preamplifier activation signal PAEF generates signal PAF.

  Each of read data drive circuits 4 # 0-4 # n includes two read data drivers which are set in an operable state by selection signals SEL0 and SEL1, and drives data bus DB0 or DB1 according to selection signals SEL0 and SEL1. . Read data driver activation signal RDRV is commonly applied to read data drive circuits 4 # 0-4 # n. Read data drive circuits 4 # 0-4 # n can take the output 3 state, and when corresponding preamplifiers 32 # 0-32 # n are inactive, CL shifters 34 # 0-34 # n are used. When the signal applied is in the standby state, the output high impedance state is set.

  Preamplifier activation signal PAF and read data driver activation signal RDRV do not include block selection signals, and CL shifters 34 # 0 to 34 # n and read data drive circuits 4 # 0 to 4 # n In common according to control signals PAF and RDRV. Therefore, it is not necessary to provide block selection signals for CL shifters 34 # 0 to 34 # n and read data drive circuits 4 # 0 to 4 # n, and the timing margin between the block selection signals and these activation signals is taken into consideration. Therefore, accurate data transfer operation and data read operation can be performed. Further, it is not necessary to shift the block selection signal in accordance with the operation timings of the CL shifters 34 # 0 to 34 # n and read data drive circuits 4 # 0 to 4 # n, and the circuit configuration is simplified.

  Similarly in column local circuit 3b provided for bank # 1, the memory array is divided into column blocks, and a corresponding internal read circuit is provided for each column block. 18 shows read data drive circuits 30 # 0b to 30 # nb in column local circuit 3b. Select signals SEL0 and SEL1 and read data driver activation signal RDRV are applied to read data drive circuits 30 # 0b-30 # nb. Next, the operation of the column local circuit shown in FIG. 18 will be described.

  Now, an operation when column block C # 1 is selected and data “1” is read as shown in FIG. 19 will be described. In this case, in column local circuit 3a, preamplifier 32 # 1 is activated in accordance with a preamplifier activation signal (PAEF.BS), and remaining preamplifiers 32 # 0, 32 # 2,..., 32 # m and 32 # n are Inactive state, and L level signals are output from these complementary output nodes. Preamplifier 32 # 1 is activated in accordance with preamplifier activation signal (PAEF · BS), and generates H and L level complementary data signals in accordance with data read from column block C # 1 to array IO line pair AIO1. .

  CL shifters 34 # 0 to 34 # n take in data supplied from corresponding preamplifiers 32 # 0 to 32 # n according to preamplifier activation signal PAF, and take this data according to inactivation of read data driver activation signal RDRV. Output data signals. Therefore, complementary data signals of H level and L level are output from CL shifter 34 # 1, and the remaining CL shifters 34 # 0, 34 # 2,..., 34 # m and 34 # n are both at L level. The signal is transmitted. Assume that read data drive circuits 30 # 0a-30 # na are coupled to data bus DB0 in accordance with select signal SEL0. In this case, also in column local circuit 3b, read data drive circuits 30 # 0b-30 # nb are coupled to data bus DB0. Read data drive circuit 4 # 1 transmits a signal of "1" onto data bus DB0 in accordance with the H level and L level data signals from corresponding CL shifter 34 # 1. On the other hand, read data drive circuits 30 # 0a, 30 # 12a,..., 30 # ma, and 30 # na both enter an output high impedance state (HiZ state) in accordance with an L level signal from the CL shifter. Also in column local circuit 3b in bank # 1, read data drive circuits 30 # 0b to 30 # nb have corresponding preamplifiers inactive, so that read data driver activation signal RDRV is driven to an active state. The output high impedance state (HiZ) is maintained.

  Therefore, a data signal "1" is transmitted to data bus DB0 from read data drive circuit 4 # 1 included in column local circuit 3a in accordance with read data driver activation signal RDRV.

  As shown in FIG. 19, an internal read circuit is provided for each column block, and only the preamplifier is selectively activated according to the column block designation signal. The CL shifter and the read data drive circuit are commonly used for the preamplifier activation signal and the read data drive circuit. By driving according to the data driver activation signal, it is not necessary to shift the block selection signal, and the wiring occupation area is reduced. Further, a circuit for shifting the block selection signal is not required, and the circuit occupation area is reduced. Further, it is not necessary to consider a margin considering the timing skew between the preamplifier activation signal PAF, the read data driver activation signal RDRV, and the block selection signal, and high-speed operation is realized.

  FIG. 20A shows a structure of internal read circuits 30 # 0a-30 # na shown in FIG. FIG. 20A shows the structure of one internal readout circuit. 20A, preamplifier 32 amplifies complementary signals on array IO line pairs IO and / IO from the corresponding column block in response to preamplifier activation signal PAE and transmits them to output nodes PD and / PD. To do. Preamplifier activation signal PAE is output from AND circuit 51 that receives block selection signal BS and preamplifier activation signal PAEF. Block selection signal BS specifies one of column blocks C # 0 to C # n. Therefore, only the preamplifier provided corresponding to the selected column block is driven to the active state.

  The CL shifter 34 amplifies the signal of the output node PD of the preamplifier 32 in response to activation of the activation signal PAF, and the output node of the preamplifier 32 in response to activation of the activation signal PAF. A tri-state inverter buffer 34b for amplifying a signal from / PD, an inverter latch 34c for latching an output signal of the tri-state inverter buffer 34a, an inverter latch 34d for latching an output signal of the tri-state inverter buffer 34b, and a read data drive A tri-state inverter buffer 34e that amplifies data latched by the inverter latch 34c and activated when the signal RDRV is inactive, and an inverter that is activated when the read data driver activation signal RDRV is inactive. A tri-state inverter buffer 34f for amplifying the signal latched by the latch 34d, an inverter latch 34g for latching an output signal of the tri-state inverter buffer 34e, and an inverter latch 34h for latching an output signal of the tri-state inverter buffer 34f. . Activation signal PAF is output from buffer 52 that receives preamplifier activation signal PAEF. Activation signal PAF is a signal independent of the block selection signal. Therefore, in the column local circuit, CL shifters 34 # 0 to 34 # n simultaneously capture signals from the output nodes of the corresponding preamplifiers.

  Also, the read data driver activation signal RDRV does not include a block selection signal. Therefore, tri-state inverter buffers 34e and 34f operate simultaneously in CL shifters 34 # 0 to 34 # n, and the captured complementary signals are transmitted to output nodes RD and / RD.

  Read data drive circuit 4 # (4 # 0-4 # n) includes read data driver 4 # a transmitting output signals RD and / RD from CL shifter 34 to data bus lines DBB0 and / DBB0, and a CL shifter. 34 includes read data driver 4 # b for transmitting output signals RD and / RD of 34 to data bus lines DBB1 and / DBB1. Read data driver 4 # a is activated when select signal SEL0 and read data driver activation signal RDRV are activated. Read data driver 4 # b is activated when select signal SEL1 and read data driver activation signal RDRV are activated. Read data driver activation signal RDRV is the same signal as read data driver activation signal RDRVF shown in the second embodiment, and does not include a block selection signal. Therefore, the read data drive circuit operates simultaneously in the column local circuit. Next, the operation of the internal readout circuit shown in FIG. 20A will be described with reference to the timing chart shown in FIG.

  When a read command is applied in clock cycle #a, read activation signal RP is driven to an active state of H level for a predetermined period. In FIG. 20B, an operation when the burst length is 4 is shown as an example. From clock cycle #a, in response to the activation of read activation signal RP, preamplifier activation signal PAEF is driven to the active state for a predetermined period in response to the rise of clock signal CLK. On the other hand, read data driver activation signal RDRV is activated with a delay of one clock cycle when CAS latency is 3, as described in the second embodiment (read activation signal RP is set to 1 by the shifter circuit). Shifted by clock cycles). Therefore, read data driver activation signal RDRV is driven to an active state for a predetermined period in each clock cycle from clock cycle #b.

  When preamplifier activation signal PAEF is activated in clock cycle #a and data is read from preamplifier 32 to its output node PD / PD, CL shifter 34 responds to activation of preamplifier activation signal PAEF. Tristate inverter buffers 34a and 34b operate to take in and latch the output data of preamplifier 32. At this time, in clock cycle #a, read data driver activation signal RDRV is in an inactive state, tristate inverter buffers 34c and 34f are in an active state, and data applied from tristate inverter buffers 34a and 34b is inverted. Then, the data is transmitted to read data drivers 4 # a and 4 # b. However, read data drivers 4 # a and 4 # b are both inactive (read data driver activation signal RDRV is inactive). Therefore, read data drivers 4 # a and 4 # b are in an output high impedance state.

  When read data driver activation signal RDRV (RDRVF) is driven to an active state in clock cycle #b, tristate inverter buffers 34e and 34f are inactivated, and are in an output high impedance state. On the other hand, one of read data drivers 4 # a and 4 # b is activated, and signals RD and / RD shifted out from CL shifter 34 are amplified to data bus lines DBB0 and / DBB0 or DBB1 and / DBB1. introduce.

  In clock cycle #b, in response to activation of preamplifier activation signal PAEF, tristate inverter buffers 34a and 34b are activated, and take in and latch new data from preamplifier 32. Next, when read data driver activation signal RDRV is deactivated, tri-state inverter buffers 34e and 34f are activated, and the newly taken data is taken in to read data drivers 4 # a and 4 # b. introduce. Therefore, thereafter, in each clock cycle #b, #c, #d and #e, read data is transmitted onto the corresponding data bus DB by read data driver 4 # a or 4 # b.

  Therefore, as shown in FIG. 20A, the CL shifter captures the output signal of the preamplifier in response to the activation of the preamplifier activation signal, and captures this when the read data driver activation signal RDRV is inactive. By transmitting the signal, the internal data can be transferred in accordance with the operation of the preamplifier and the read data driver without using the internal clock signal. You can transfer. In the CL shifter 32, when the preamplifier 32 is activated, the output signal is taken, and the operation of transferring the signal taken when the read data driver is inactive to the read data driver is repeated. The control signal shown in FIG. 20A can be generated by using the control circuit shown in FIGS. 9 and 12 in the second embodiment.

  The configuration shown in FIG. 20A is an operation when the CAS latency is 3. When the CAS latency is 2, the CL shifter 34 may simply be set to the transparent state, that is, the passing state. This is because the switching path of the output nodes PD and / PD of the preamplifier 32 is switched according to the CAS latency information CL, or the inverter buffers 34a, 34b, 34e and 34f in the CL shifter 34 are always operated when the CAS latency is 2. This can be realized by using the configuration for the state. When the CAS latency is 2, for example, the tri-state inverter buffers 34a and 34b receive a signal that has passed through the OR circuit of the preamplifier activation signal PAEF and CAS latency information CL = 2 (indicating that CAS latency is 2). What is necessary is just to give as activation signal PAF. In tristate inverter buffers 34e and 34f, a signal obtained by passing an AND signal of CAS latency information CL = 2 and read data driver activation signal RDRV may be applied.

  Even when the CAS latency is 2, read data drivers 4 # a and 4 # b are activated when the output signal of preamplifier 32 is in a standby state. However, preamplifier 32 outputs an L level signal to both output nodes PD and / PD when inactive, and read data drivers 4 # a and 4 # b are set to an output high impedance state at that time. Is done. The configuration of read data drivers 4 # a and 4 # b is the same as that shown in FIG.

  FIG. 21 shows an example of a specific configuration of preamplifier 32 shown in FIG. In FIG. 21, preamplifier 32 is connected between a power supply node and node PDi, and has a gate connected to node / PDi, and p-channel MOS transistor 32a connected in series between node PDi and node NDx. N-channel MOS transistors 32b and 32e connected in series between power supply node and node / PDi and connected in series between p-channel MOS transistor 32c connected to node PDi, node / PDi and node NDx. N channel MOS transistors 32d and 32f, and an n channel MOS transistor 32g connected between node NDx and ground node and receiving preamplifier activation signal PAE at its gate.

  N channel MOS transistor 32b has its gate connected to node / PDi, and n channel MOS transistor 32e has its gate connected to array IO line / IO. N channel MOS transistor 32d has its gate connected to node PDi, and n channel MOS transistor 32f has its gate connected to array IO line IO.

  Preamplifier 32 further conducts when preamplifier activation signal PAE is inactive, and p-channel MOS transistors 32h and 32i for precharging nodes PDi and / PDi to the power supply voltage Vcc level and signals on node / PDi, respectively. Is inverted and transmitted to output node PD, inverter 32k which inverts the signal on node PDi and transmits the signal to output node / PD, and n-channel MOS cross-coupled to output nodes PD and / PD Transistors 32l and 32m. N channel MOS transistor 32l has its gate connected to the output of inverter 32j, one conduction node connected to the output node of inverter 32k, and the other conduction node connected to the ground node. N channel MOS transistor 32m has its gate connected to the output node of inverter 32k, one conduction node connected to the output (output node PD) of inverter 32j, and the other conduction node connected to the ground node. These n channel MOS transistors 32l and 32m prevent output nodes PD and / PD from being driven to the H level. Next, the operation of the preamplifier 32 shown in FIG. 21 will be briefly described.

  When preamplifier activation signal PAE is inactive, MOS transistor 32g is in a non-conductive state, and the amplification operation of signals on array IO lines IO and / IO is stopped. On the other hand, p channel MOS transistors 32h and 32i are rendered conductive, and nodes PDi and / PDi are precharged to power supply voltage Vcc level. Therefore, output nodes PD and / PD are held at the L level of the ground voltage level by inverters 32j and 32k. That is, inactive preamplifier 32 has its output nodes PD and / PD both set to L level. In this state, MOS transistors 32l and 32m are both non-conductive.

  When preamplifier activation signal PAE is activated, MOS transistors 32h and 32i are turned off. On the other hand, MOS transistor 32g is turned on, and amplifying operation of signals on array IO lines IO and / IO is performed.

  Consider a case where the signal on array IO line IO has a higher potential than the signal on array IO line / IO. In this state, the conductance of n channel MOS transistor 32f becomes larger than the conductance of n channel MOS transistor 32e, and the voltage level of node / PDi precharged to power supply voltage Vcc level is lowered. Here, nodes PDi and / PDi are precharged to the level of power supply voltage Vcc, and n channel MOS transistors 32b and 32d are both conductive. When the voltage level of node / PDi decreases, MOS transistor 32a starts to conduct, compensates for the decrease in voltage level of node PDi, and drives node PDi to power supply voltage Vcc level. On the other hand, p channel MOS transistor 32c maintains a non-conductive state, and node / PDi is discharged through MOS transistors 32d, 32f and 32g, and its voltage level decreases. Due to the decrease in the voltage level of node / PDi, the conductance of n channel MOS transistor 32b decreases, and the voltage difference between nodes PDi and / PDi increases. Inverters 32j and 32k invert the signals on nodes PDi and / PDi and transmit them to output nodes PD and / PD. Therefore, nodes PD and / PD are at L level and H level, respectively. At this time, n channel MOS transistor 32m is rendered conductive to drive output node PD to the ground voltage level.

  N channel MOS transistors 32l and 32m prevent output nodes PD and / PD from being driven to the H level. This corresponds to a state where nodes PDi and / PDi are both driven to the L level. For example, even if preamplifier 32 is suddenly activated and the voltage level of array IO lines IO and / IO is high, and internal nodes PDi and / PDi suddenly drop in voltage level, output nodes PD and Any one of / PD is driven to L level. By providing the MOS transistors 32l and 32m, the read data driver is prevented from malfunctioning. That is, in the read data driver, as shown in FIG. 8, the output stage drives the complementary data bus line by a pair of a p-channel MOS transistor and an n-channel MOS transistor. When read data RD and / RD are at H level (that is, when output nodes PD and / PD are both at H level), nodes / LRD and LRD of the read data driver (see FIG. 8) are at L level, and this read data driver MOS transistors QT1-QT4 are all turned on, and accurate data cannot be read out, and a large current flows through data bus lines DDB and / DDB. These cross-coupled n-channel MOS transistors 32l and 32m are provided to prevent such an unstable state and to set the state to any one of the three states according to the read data later.

  As a result, an internal read circuit that outputs three-state data of “1”, “0”, and high impedance (HiZ) onto the data bus line can be realized. The ternary data output by the preamplifier is “H, L”, “L, H”, “L, L”, and does not take the HiZ state.

  In the above description, the read data driver activation signal RDRV is a signal independent of the block selection signal, and all read data drive circuits are activated. However, the read data driver activation signal RDRV may be activated only for a selected bank by combining the read data driver activation signal RDRV with a bank address signal. In this case, the CL shifter and the read data driver can be operated only in the selected bank, and current consumption can be reduced.

  As described above, according to the third embodiment of the present invention, the preamplifier outputs ternary data, the ternary data of this preamplifier is transmitted to the read data driver via the CL shifter, and the read data driver Since the bus is configured to be driven in three states, an internal read circuit having the same configuration can be provided for each column block to read data, and the circuit layout is simplified. Further, only the preamplifier is activated based on the block selection signal, and the CL shifter and the read data driver are operated independently of the block selection signal, so that a circuit and wiring for shifting this clock selection signal are not required, The area occupied by the wiring is reduced, and a shift operation is not required, so that current consumption is reduced.

  FIG. 22 is a diagram showing a configuration of the read data driver shown in FIG. In addition to the configuration shown in FIG. 8, the read data driver shown in FIG. 22 further includes an AND circuit G20 that receives the output data PD from the preamplifier 32 and CAS latency information CL2, and an output signal RD and CAS from the CL shifter 34. From the AND circuit G21 that receives the latency information CL3, the OR circuit G22 that receives the output signals of the AND circuits G20 and G21, the AND circuit G23 that receives the output data signal / RD and the CAS latency information CL2 from the preamplifier 32, and the CL shifter 34 AND circuit G24 receiving the output data signal / RD and CAS latency information CL3, and OR circuit G25 receiving the output signals of AND circuits G23 and G24. The output signal of the OR circuit G22 is applied to the first input of the NAND circuit G2, and the output signal of the OR circuit G25 is applied to the first input of the NAND circuit G3. Output signals of AND circuit G1 receiving read data driver activation signal RDRV and selection signal SEL are applied to the second inputs of NAND circuits G2 and G3, respectively. Other configurations are the same as those shown in FIG. 8, and corresponding portions are denoted by the same reference numerals, and detailed description thereof is omitted. However, the node and the signal on it are referred to by the same symbol.

  The CAS latency information CL2 indicates that the CAS latency is 2, and the CAS latency information CL3 indicates that the CAS latency is 3. These CAS latency information CL2 and CL3 are set to the H level when activated.

  In the configuration shown in FIG. 22, when CAS latency is 2, AND circuits G20 and G23 operate as buffers, while AND circuits G21 and G24 have their output signals fixed at the L level. Therefore, when CAS latency is 2, output data signals PD and / PD from preamplifier 32 are both applied to the read data driver via AND circuits G20 and G23 and OR circuits G22 and G25. In this state, output data signals RD and / RD of CL shifter 34 are ignored. On the other hand, when CAS latency is 3, CAS latency information CL3 is driven to H level, and AND circuits G21 and G24 operate as a buffer, while AND circuits G20 and G23 have their output signals fixed at L level. . Therefore, when CAS latency is 3, output data signals RD and / RD from the CL shifter are transmitted to the read data driver via AND circuits G21 and G24 and OR circuits G22 and G25 and amplified. By using these AND circuits G20, G21, G23, G24 and OR circuits G22, G25, the output data signals of the preamplifier and the CL shifter can be selected according to the CAS latency information. This is because the read data driver shown in FIG. 8 is also provided with the same configuration (selection gate), so that data can be read in accordance with CAS latency. As a result, the output signal of the preamplifier and the CL shifter can be accurately selected according to the CAS latency information even in the configuration in which the output data of the preamplifier is shifted using the activation control signals PAF and RDRV without using the internal clock signal (When the shift operation is performed using the internal clock signal, it is possible to cope with CAS latency by simply changing the number of shift stages).

[Embodiment 4]
FIG. 23 shows a structure of a main portion of the semiconductor memory device according to the fourth embodiment of the present invention. FIG. 23 shows the configuration of output control circuit 5 arranged in the vicinity of pad PPD. A plurality of internal read / write circuits are coupled in parallel to data bus lines DBB and / DBB. In FIG. 23, preamplifier 32, CL shifter 34 and read data driver 4 constituting one internal read circuit are provided. # Is representatively shown. The configurations of preamplifier 32, CL shifter 34, and read data driver 4 # are the same as those shown in FIGS. 21, 20A, and 22, respectively.

  In FIG. 23, a data bus equalize circuit 55 for equalizing data bus lines DBB and / DBB to the ground voltage level according to output signal DBEQ of inverter 61 receiving data bus equalize instruction signal / DBEQ is applied to data bus lines DBB and / DBB. Provided. Data bus equalize circuit 55 includes transfer gates TG1 and TG2 which are rendered conductive in response to activation (H level) of data bus equalize instruction signal DBEQ and transmit the ground voltage to data bus lines DBB and / DBB, respectively.

  The output control circuit 5 is coupled to the data bus DB via the read amplifier isolation gate 56 and the read amplifier isolation gate 56 which are rendered non-conductive in response to the activation (L level) of the isolation instruction signal / SAI. Read amplifier 57 for amplifying the applied data in response to activation of activation signal / SAE, transfer circuit 58 for transmitting complementary output data RAD and / RAD of read amplifier 57 in accordance with read clock signal CLKQ, and transfer Output latch 59 for latching data from circuit 58, and output buffer 60 for transmitting output data to pad PPD in accordance with latch data OD and / OD of output latch 59 are included.

  Read amplifier isolation gate 56 includes transfer gates TG3 and TG4 which are rendered non-conductive when read amplifier isolation instruction signal / SAI is activated and disconnect data bus lines DBB and / DBB from read amplifier 57.

  Read amplifier 57 is turned on in response to activation (L level) of read amplifier activation signal / SAE, and transmits p channel MOS transistor PQ1 transmitting power supply voltage Vcc, and between p channel MOS transistor PQ1 and node RAD. P-channel MOS transistor PQ2 whose gate is connected to node / RAD, p-channel MOS transistor PQ3 which is connected between MOS transistor PQ1 and node / RAD and whose gate is connected to node RAD, N-channel MOS transistor NQ1 connected between node RAD and ground node and having its gate connected to node / RAD, and n channel MOS transistor NQ1 connected between node / RAD and ground node and having its gate connected to node RAD Includes channel MOS transistor NQ2

  Read amplifier 57 has a configuration of a cross-coupled sense amplifier, and an amplifying unit composed of cross-coupled p-channel MOS transistors PQ2 and PQ3 is activated. Nodes RAD and / RAD are connected to data bus lines DBB and / DBB via read amplifier isolation gate 56, and in a standby state, nodes RAD and / RAD are equalized to the ground voltage level. Therefore, when read amplifier 57 is activated, the voltage level of the high potential node among nodes RAD and / RAD is raised. The low potential data bus line maintains the ground voltage level.

  Read amplifier isolation instruction signal / SAI is output from NOR circuit 62 that receives output signal RDLI of DQ control circuit 65 and read clock signal CLKQ, and read amplifier activation signal / SAE is read from output signal RDLAT of DQ control circuit 65 It is generated from gate circuit 63 that receives clock signal CLKQ.

  Transfer circuit 58 is activated when the output signal of inverter 64 receiving read clock signal CLKQ is inactivated (L level), and includes tristate inverter buffers 58a and 58b for amplifying the signals of nodes RAD and / RAD. The transfer circuit 58 further amplifies the data amplified by the read amplifier 57 and transmits it to the output latch 59 while the read clock signal CLKQ is at the H level. When the read clock signal CLKQ is at the L level, the transfer circuit 58 outputs the high impedance state. It becomes. Next, operations of the output control circuit and the internal readout circuit shown in FIG. 23 will be described with reference to time charts shown in FIGS.

  First, with reference to FIG. 24, a data read operation when the CAS latency is 2 will be described.

  When a read command is applied in clock cycle #a, read data driver activation signal RDRV is activated for a predetermined period in response to the rise of internal clock signal CLK, and then preamplifier activation signal PAE is activated. Thus, selected preamplifier 32 amplifies the data read on array IO lines IO and / IO, and supplies the amplified data to read data driver 4 #. When CAS latency is 2, CL shifter 34 is bypassed, and output signals PD and / PD from preamplifier 32 are directly applied to read data driver 4 #. In response to activation of read data driver activation signal RDRV, read data driver 4 # performs an amplification operation, and internal nodes LRD and / LRD (see FIG. 22) according to signals PD and / PD transmitted from preamplifier 32. Then, the voltage level of data bus lines DBB and / DBB changes from the precharge level L level by the amplification operation of read data driver 4 #.

  On the other hand, in response to the rise of internal clock signal CLK, read detect signal RDET is activated, and isolation instruction signal / SAI rises to an H level via NOR circuit 62 under the control of DQ control circuit 65. (During this time, read clock signal CLKQ is at L level). As a result, read amplifier isolation gate 56 is rendered conductive, and the signal potential on data bus lines DBB and / DBB is transmitted to read amplifier 57. After read amplifier isolation gate 56 becomes conductive, data bus equalize instructing signal / DBEQ becomes H level in response to the rise of internal clock signal CLK, and accordingly data bus equalize instructing signal DBEQ from inverter 61 is applied. Becomes L level, and data bus equalize circuit 55 is deactivated. Thus, data from read data driver 4 # is transmitted to read amplifier 57 via data bus lines DBB and / DBB. When read amplifier isolation gate 56 is rendered conductive, data bus lines DBB and / DBB are still in an equalized state, thereby reliably resetting the internal node of read amplifier 57 to the initial L level.

  Then, read amplifier activation signal / SAE is driven to the active state at the L level at the earlier timing of deactivation of read detect signal RDET and activation (rise) of internal read clock signal CLKQ. The gate circuit 63 receives the read clock signal CLKQ and the read data latch instruction signal RDLAT from the DQ control circuit 65, and when one rises to the ground level, the read amplifier activation signal / SAE is activated. It is driven to the L level of the state. When read amplifier activation signal / SAE is activated, read amplifier isolation instruction signal / SAI then goes to L level, and read amplifier isolation gate 56 is rendered non-conductive. As a result, read amplifier 57 is disconnected from data bus lines DBB and / DBB, the load on the sense nodes (nodes RAD and / RAD) is reduced, and the amplification operation is performed at high speed. One of RAD and / RAD is raised from the ground voltage level to power supply voltage Vcc level.

  When read amplifier 57 performs an amplifying operation and latches amplified data by read amplifier activation signal / SAE, the output signal of inverter 64 becomes L level in response to the rise of read clock signal CLKQ, and transfer circuit 58 is activated. Then, the data amplified by read amplifier 57 is transmitted to output latch 59, and the read data is transmitted to output nodes OD and / OD of output latch 59. Next, the output buffer 60 transmits the data latched by the output latch 59 to the pad PPD. Therefore, when a read command is applied to clock cycle #a, the determined data is sampled by the external device at the rising edge of internal clock signal CLK in clock cycle #c. As a result, data reading with a CAS latency of 2 (CL = 2) is realized.

  On the other hand, when read amplifier isolation instruction signal / SAI attains an L level and data bus lines DBB and / DBB are separated from read amplifier 57, data bus equalize instruction signal / DBEQ attains an L level, and accordingly, a data bus equalize circuit 55 is activated to equalize data bus lines DBB and / DBB to the ground voltage level. Next, read amplifier activation signal / SAE is driven to an inactive state of H level, read amplifier 57 is deactivated, then read amplifier isolation instruction signal / SAI becomes H level, and read amplifier 57 is connected to a read amplifier isolation gate. 56 is connected to data bus lines DBB and / DBB. Thereby, nodes RAD and / RAD are reset to the ground voltage level.

  In clock cycle #b, preamplifier activation signal PAE and read data driver activation signal RDRV are activated again, and the next data is transmitted to data bus lines DBB and / DBB. Data bus equalize instructing signal / DBEQ is again deactivated to an H level, data bus equalize circuit 55 is deactivated, and data from read data driver 4 # is transmitted to data bus lines DBB and / DBB. When data is read onto data bus lines DBB and / DBB, read amplifier isolation instruction signal / SAI is at H level, read amplifier isolation gate 56 is in a conductive state, and read amplifier 57 is connected to data bus line Data on DBB and / DBB is transmitted. Then, read amplifier activation signal / SAE is activated, read amplifier 57 performs an amplification operation, and transfer circuit 58 amplifies data from read amplifier 57 in response to the rise of read clock signal CLKQ. To the output latch 59. Thereafter, this operation is repeated until the burst length cycle number elapses or a read operation stop (interrupt or precharge command) is given.

  The read amplifier 57 is separated from the data bus DB by the read amplifier isolation gate 56, and the read amplifier 57 performs an amplification operation, so that the voltage difference between the nodes RAD and / RAD in the read amplifier 57 can be sensed. When the range is reached, the read amplifier 57 can perform an amplification operation. Therefore, read amplifier 57 can perform an amplification operation before a CMOS level signal is transmitted to data bus lines DBB and / DBB. That is, a small amplitude data signal can be transmitted to data bus lines DBB and / DBB, and high-speed reading is realized.

  Next, with reference to FIG. 25, a data read operation when the CAS latency is 3 will be described. When a read command is applied in clock cycle #a, first, preamplifier activation signal PAE is activated. Preamplifier 32 amplifies signals on array IO lines IO and / IO and transmits them to CL shifter 34. When the CAS latency is 3 (CL = 3), the CL shifter 34 performs a shift operation, takes the output data signal of the preamplifier 32 in response to the activation of the preamplifier activation signal PAE, and sets the read data driver activation signal RDRV. In response to the deactivation, the taken data signal is transmitted to read data driver 4 #. In clock cycle #a, read data driver activation signal RDRV is in an inactive state, so that a signal from CL shifter 34 is applied to read data driver 4 #. On the other hand, read detect signal RDET is activated with a delay of one clock cycle when CAS latency is 3, and therefore, inactive in clock cycle #a, read amplifier activation signal / SAE is maintained. Inactive state at H level and read amplifier isolation instruction signal / SAI is at L level, separating data bus DB and read amplifier 57 from each other. Data bus equalize instruction signal / DBEQ is at L level, data bus equalize circuit 55 is activated, and data bus lines DBB and / DBB are equalized to the ground voltage level.

  In clock cycle #b, in response to the rise of internal clock signal CLK, read data driver activation signal RDRV is driven to an active state, read data driver 4 # performs an amplification operation, and data transmitted from CL shifter 34 is transmitted. Amplify. In response, the voltage levels of internal nodes LRD and / LRD of read data driver 4 # change in response to activation of read data driver activation signal RDRV.

  In clock cycle #b, in response to the rise of internal clock signal CLK, read detect signal RDET is activated, and when read clock signal CLKQ falls to L level, read amplifier isolation instruction signal / SAI is at H level. Data bus lines DBB and / DBB are coupled to read amplifier 57. Data bus equalize instruction signal / DBEQ attains an H level in response to the rise of internal clock signal CLK, data bus equalize circuit 55 is deactivated, and the voltage levels of data bus lines DBB and / DBB are set to this read level. It changes according to the output data signal of data driver 4 #. Further, the voltage levels of nodes RAD and / RAD of read amplifier 57 change according to a signal applied from read data driver 4 # via data bus lines DBB and / DBB.

  When read data driver activation signal RDRV attains an inactive state of L level, read data driver 4 # enters an output high impedance state. At this time, data bus equalize instruction signal / DBEQ is still at the H level, and data bus equalize circuit 55 is in an inactive state. Next, when read detect signal RDET falls to L level, read amplifier activation signal / SAE is activated, and then read amplifier isolation instruction signal / SAI goes to L level. Thereby, read amplifier 57 performs an amplification operation in a state where it is disconnected from data bus lines DBB and / DBB, and sets the voltage level of nodes RAD and / RAD to a voltage level corresponding to the transmitted signal level.

  Data bus line isolation instructing signal / SAI is in an active state (L level), and data bus equalize instructing signal / DBEQ becomes L level while read amplifier 57 performs an amplifying operation. / DBB is equalized to the ground voltage level by data bus equalize circuit 55.

  In this clock cycle #b, the preamplifier activation signal PAE is activated and the preamplifier 32 performs an amplifying operation to transmit the next data to the CL shifter 34 to be latched. The data amplified by preamplifier 32 in clock cycle #b is taken in and amplified by read data driver 4 # in accordance with activation of read data driver activation signal RDRV in clock cycle #c, and data bus line DBB And transmitted on / DBB. Thereafter, the same operation as the previous clock cycle #b is performed.

  The data latched in the output latch 59 is transmitted to the pad PPD via the output buffer 60 in the clock cycle.

  Valid data is output to pad PPD in clock cycle #c, and is sampled by an external device at the rising edge of internal clock signal CLK in the next clock cycle #d (not shown). As a result, data reading is performed with a CAS latency of 3.

  FIG. 26 schematically shows a structure of a portion for generating the control signal shown in FIG. In FIG. 26, the control signal generation circuit receives an external clock signal extCLK and generates an internal clock signal CLK and a read clock signal CLKQ, and is synchronized with the internal clock signal CLK from the clock generation circuit 20. A command decode circuit 21 that takes in control signals (commands) / CS, / RAS, / CAS, and / WE from the outside and generates a signal indicating the designated operation mode, and externally in accordance with an output signal of the command decode circuit 21 In response to activation of read operation instruction signal .phi.r from command decode circuit 21, address generation circuit 22 that takes in the address signal AD and drives the burst long-term read activation signal RP to an active state. Read control circuit 23 and read from read control circuit 23 (CL-2) shifter 26 that shifts the enable signal RP by (CAS latency-2), and is activated when the read activation signal RP from the read control circuit 23 is activated, and is synchronized with the internal clock signal CLK. A PAE generating circuit 27 for generating a preamplifier activation signal PAE.

  The configuration of these circuits is the same as that of the control signal generating circuit shown in FIG. (CL-2) When the CAS latency is 2, the shifter 26 transmits the read activation signal RP supplied from the read control circuit 23 as it is to generate the read operation activation signal RPP. When the CAS latency is 3, (CL-2) shifter 26 shifts read activation signal RP from read control circuit 23 for one clock cycle period of internal clock signal CLK to generate read operation activation signal RPP.

  The control signal generation circuit further decodes an internal address signal from the address generation circuit 22 to generate a block selection signal for designating a memory column block, and a preamplifier activation signal from the PAE generation circuit 27. It includes a gate circuit G12 that receives PAEF and a block selection signal from block decoder 25 and generates preamplifier activation signal PAE (PAEj). Only the preamplifier provided corresponding to the selected column block is activated in accordance with preamplifier activation signal PAE (PAEj). The remaining preamplifiers remain inactive.

  The control signal generation circuit further generates a read data driver activation signal RDRV (RDRVF) in synchronization with the internal clock signal CLK when the read operation activation signal RPP from the (CL-2) shifter 26 is activated. Generation circuit 29, RDET generation circuit 66 for generating read data detect signal RDET in response to internal clock signal CLK when read operation activation signal RPP is activated, and internal operation when read operation activation signal RPP is activated A DBEQ generation circuit 67 for driving data bus equalize instruction signal / DBEQ in synchronization with clock signal CLK is included. When read operation activation signal RPP is in an inactive state, RDRV generation circuit 29 and RDET generation circuit 66 hold signals RDRV and RDET in an inactive state at L level, respectively. DBEQ generation circuit 67 holds data bus equalize instruction signal / DBEQ at the L level in the active state when read operation activation signal RPP is inactivated.

  FIG. 27A schematically shows structures of RDRV generation circuit 29, RDET generation circuit 66, and DBEQ generation circuit 67 shown in FIG. Since these RDRV generation circuit 29, RDET generation circuit 66, and DBEQ generation circuit 67 have substantially the same circuit configuration, FIG. 27A representatively shows the configuration of one circuit. In FIG. 27A, each of generation circuits 29, 66 and 67 includes a delay circuit 69a for delaying internal clock signal CLK for a predetermined time, and an AND circuit 69b receiving an output signal of delay circuit 69a and read operation activation signal RPP. And a one-shot pulse generating circuit 69c for generating a one-shot pulse signal φPUL having a predetermined time width in response to the rise of the output signal of AND circuit 69b. The delay time of the delay circuit 69a can be changed according to the CAS latency information CL. Thereby, as shown in FIG. 24 and FIG. 25, the generation timing of each instruction signal can be varied. Next, the operation of the signal generation circuit shown in FIG. 27A will be described with reference to timing charts shown in FIGS. 27B and 27C.

  First, an operation when the CAS latency is 3 (CL = 3) will be described with reference to FIG. When a read command is applied in clock cycle #a, read activation signal RP is driven to an active state for a predetermined period (burst long time). When the CAS latency is 3, (CL-2) shifter 26 drives read operation activation signal RPP to the active state in the next clock cycle #b. AND circuit 69b generates an output signal according to read operation activation signal RPP and the delayed internal clock signal from delay circuit 69a. Therefore, the AND circuit 69b sequentially outputs signals that rise to the H level after a predetermined time has elapsed since the internal clock signal CLK rises. One shot pulse generation circuit 69c generates a one shot pulse signal φPUL in response to the rise of the output signal of AND circuit 69b. Therefore, in clock cycles #b, #c, #d and #e, one shot pulse signal φPUL is activated while read operation activation signal RPP is in an active state. While read operation activation signal RPP is at L level, the output signal of AND circuit 71 is fixed at L level, and one-shot pulse signal φPUL is fixed at L level.

  Next, an operation when the CAS latency is 2 will be described with reference to FIG. When a read command is applied in clock cycle #a, read activation signal RP and read operation activation signal RPP are both driven to H level in clock cycle #a. When the CAS latency is 2, the (CL-2) shifter 26 is not performing a shift operation. Therefore, from this clock cycle #a, the output signal of AND circuit 69b rises to the H level in accordance with internal clock signal CLK, and one-shot pulse generating circuit 69c generates one-shot pulse signal φPUL.

  Therefore, by delaying internal clock signal CLK using delay circuit 69a, when read activation signal RP is driven to the active state even in clock cycle #a to which a read command is applied, internal clock signal A one-shot pulse signal can be generated according to CLK, and a one-shot pulse signal having a predetermined time width can be generated accurately.

  The delay circuit 69a can easily change the delay time if the number of stages of the inverter is changed according to the CAS latency information CL.

  FIG. 28 schematically shows a structure of DQ control circuit 65 shown in FIG. In FIG. 28, the DQ control circuit 65 delays the read detect signal RDET for a predetermined time and inverts it to generate a signal RDLI, and delays the read detect signal RDET for a predetermined time to read the data latch instruction signal RDLAT. Is included in the delay circuit 65b. Signal RDLI is applied to NOR circuit 62 shown in FIG. 23, and read data latch instruction signal RDLAT is applied to gate circuit 63 shown in FIG.

  Next, with reference to FIG. 28, FIG. 23, and FIG.

  In FIG. 29A, read detect signal RDET is driven to the H level for a predetermined time after read clock signal CLKQ rises. The inverting delay circuit 65a outputs a signal RDLI obtained by delaying and inverting the read detect signal RDET. Therefore, read amplifier isolation instruction signal / SAI rises to H level in synchronization with the fall of read clock signal CLKQ, and falls to L level in synchronization with the rise of signal RDLI. When signal / SAI is at H level, read amplifier isolation gate 56 is in a non-conductive state, and data bus DB and read amplifier 57 are isolated.

  On the other hand, as shown in FIG. 29B, read detect signal RDET rises after read clock signal CLKQ falls, and read detect signal RDET rises to the L level before the next read clock signal CLKQ rises. When rising, read amplifier isolation instruction signal / SAI rises and falls in synchronization with the fall and rise of signal RDLI. In this case, therefore, separation of read amplifier 57 and data bus DB is controlled in accordance with read detect signal RDET.

  By using this NOR circuit 62, even when the timings of the read clock signal CLKQ and the read detect signal RDET are shifted, the transfer instruction signal / SAI is set to H after the transfer circuit 58 shown in FIG. As a level, the data bus DB and the read amplifier 57 can be connected, and the next new data can be prevented from being transmitted to the output buffer 60 via the output latch 59.

  FIG. 30 is a diagram showing an example of the configuration of the gate circuit 63 shown in FIG. In FIG. 30, gate circuit 63 responds to the rise of the output signal of inverter 63a receiving read data latch instruction signal RDLAT, OR circuit 63b receiving the output signal of inverter 63a and read clock signal CLKQ, and OR circuit 63b. A one-shot pulse generation circuit 63c for generating a one-shot pulse signal having a predetermined time width is included. The one-shot pulse generation circuit 63c generates a one-shot pulse signal that falls from the H level to the L level. Read amplifier activation signal / SAE is output from this one-shot pulse generation circuit 63c. Next, the operation of gate circuit 63 shown in FIG. 30 will be described with reference to signal waveform diagrams shown in FIGS.

  First, as shown in FIG. 31, when the rise of read detect signal RDET is later than the rise of read clock signal CLKQ, read data latch instruction signal RDLAT rises to H level later than read clock signal CLKQ. One shot pulse generating circuit 63c holds read amplifier activation signal / SAE at the H level. Now, when read clock signal CLKQ becomes L level, read detect signal RDET falls to L level, and then read data latch instruction signal RDLAT falls to L level, the output signal of inverter 63a becomes H level, and OR circuit The output signal 63b rises to the H level. In response, one shot pulse generating circuit 63c generates an L level one shot pulse signal, and read amplifier activation signal / SAE is in an active state at an L level for a predetermined period.

  Further, as shown in FIG. 32, when read detect signal RDET rises earlier than read clock signal CLKQ, the output signal of OR circuit 63b is at the H level in response to the rise (activation) of read clock signal CLKQ. Get up to. Therefore, read amplifier activation signal / SAE from one shot pulse generating circuit 63c is activated in response to read clock signal CLKQ being activated (rising). At this time, even if read data latch instruction signal RDLAT falls to L level, read amplifier activation signal / SAE from one-shot pulse generation circuit 63c has already been driven to L level, and its state does not change. As a circuit configuration for generating such a one-shot pulse, a set / reset flip-flop is provided, and the output signal of the flip-flop is reset by delaying for a predetermined time, so that the one-shot pulse is doubled. It can be prevented from being generated.

  By activating the read amplifier at the timing of activation of the read clock signal CLKQ (rise) or deactivation of the read detect signal RDET (L level), whichever is earlier, the CAS latency differs, and the clock frequency Even when the voltage changes, the sensing operation can be accurately performed in synchronization with the high-speed clock signal.

[Example of change]
FIG. 33 schematically shows a structure of a modification of the fourth embodiment of the present invention. FIG. 33 shows the configuration of the DQ control circuit 65.

  In FIG. 33, a DQ control circuit 65 is set when the mask instruction signal DQMi from the DQM buffer 35 is delayed for a predetermined time, and when the output signal of the delay circuit 65a is activated, and the clock signal CLK is activated (rising). ) Reset / set flip-flop 65b, output / Q from output / Q of set / reset flip-flop 65b and AND circuit 65c receiving read data latch instruction signal RDLAT, and set / reset flip-flop 65b AND circuit 65d receiving output signal / OE and read amplifier separation instruction signal RDLI is included. Signals RDLAT and RDLI are generated according to read detect signal RDET as shown in FIG. Mask instruction signal DQMi is also applied to an RDRV generation circuit (see FIG. 12). When a mask instruction is applied, read data driver activation signal RDRV is held in an inactive state in that clock cycle.

  Gate circuit 63 for generating read amplifier activation signal / SAE has the same configuration as that shown in FIG. 30, but is set as one-shot pulse generating circuit 63c in response to the output signal of OR circuit 63b, and A set / reset flip-flop is used that is reset after a predetermined time has elapsed when the output signal is activated. However, FIG. 33 does not show a delay circuit that applies a reset signal to the reset input R of the flip-flop as the one-shot pulse generating circuit 63c. Next, the operation of DQ control circuit 65 shown in FIG. 33 will be described with reference to the timing charts shown in FIGS.

First, the operation when the CAS latency is 2 will be described with reference to FIG.
34 also shows the control signals shown in FIG. First, when a read command is applied in clock cycle #a, preamplifier activation signal PAE is activated, and data in the selected memory is transmitted to output nodes PD and / PD of preamplifier 32. In addition, read data driver activation signal RDRV is activated, and the data amplified by preamplifier 32 is taken and transmitted onto data bus DB. When data is read by read data driver 4 #, data bus equalize instruction signal / DBEQ is at H level, and data bus DB corresponds to data read by read data driver 4 # from the precharge voltage (L level). The voltage level changes.

  In addition, read detect signal RDET is activated, and signals RDLAT and RDLI are each driven to an active state. In this clock cycle #a, mask instruction signal DQM is in an inactive state of L level, so that read amplifier isolation instruction signal / SAI attains H level in accordance with read detect signal RDET, and data bus DB and read amplifier 57 are connected. Then, read amplifier activation signal / SAE is activated and read amplifier 57 performs an amplification operation. Therefore, in clock cycle #a, data is transmitted to internal nodes RAD and / RAD of read amplifier 57, and then this data is transmitted to output latch 59 via transfer circuit 58 in accordance with read clock signal CLKQ. Is done. Therefore, data is output via output buffer 60 in clock cycle #b.

Similarly, in the clock cycle #b, internal reading of the next data is performed.
In mask cycle #c, external mask instruction signal DQM is set to the H level. In this state, internal mask instruction signal DQMi is at H level during clock cycle #c, and signal / OE is in an active state at L level after a predetermined time has elapsed. Preamplifier activation signal PAE is activated independently of internal mask instruction signal DQMi, and data is read out also in clock cycle #c. However, read data driver activation signal RDRV is held in an inactive state in accordance with internal mask instruction signal DQMi, and the internal node of read data driver 4 # is held at the H level in the standby state.

  Data bus equalize instructing signal / DBEQ is also activated in accordance with clock signal CLK to equalize data bus DB. In clock cycle #c, therefore, data bus DB is held at the L level high impedance state. The

  On the other hand, read clock signal CLKQ and read detect signal RDET are activated. Since signal / OE attains L level, the output signal of AND circuit 65c is held at L level, read amplifier activation signal / SAE maintains an inactive state of H level, and read amplifier isolation instruction signal / SAI is also maintained. Since the output signal of NAND circuit 65d becomes H level, it is held at L level. Therefore, in this clock cycle #c, read amplifier 57 is maintained in an inactive state, and data bus DB and read amplifier 57 are maintained in a separated state. In read amplifier 57, internal nodes RAD and / RAD are held at the L level in the standby state by an equalize circuit, as will be described later. Therefore, no data is read in clock cycle #c, and output buffer 60 maintains the output high impedance state.

  In clock cycle #d, external mask instruction signal DQM is set to L level, and internal mask instruction signal DQMi is also set to L level. Therefore, in clock cycle #d, data read by preamplifier 32 and read data driver 4 # is transmitted to read amplifier 57 and amplified, and externally via transfer circuit 58, output latch 59 and output buffer 60. Read out.

  When the CAS latency is 2, when mask designation signal DQM is activated, internal data reading is prohibited in that clock cycle, and external read data in the next clock cycle is masked. Therefore, in this state, the external read data two clock cycles after the mask instruction is given is masked. In FIG. 34, the data in the clock cycle #e is masked.

Next, the operation when the CAS latency is 3 will be described with reference to FIG.
A read command is applied in clock cycle #a. Mask instruction signal DQM is in an inactive state of L level, and signal / OE maintains H level. When the CAS latency is 3, the circuits after the preamplifier are sequentially activated from the next clock cycle #b. Therefore, preamplifier activation signal PAE is activated in clock cycle #b, and data is transmitted to data bus DB via CL shifter and read data driver 4 #. Then, read amplifier activation signal / SAE is activated, performs an operation of amplifying the data transmitted on data bus DB, and transfers in accordance with activation (rise) of read clock signal CLKQ in the next clock cycle #c. Data is transmitted to output latch 59 through circuit 58, and then data is transmitted to pad PPD.

  When mask instruction signal DQM is set to H level in clock cycle #c, internal mask instruction signal DQMi is activated to H level in clock cycle #c. Therefore, in cycle #c, although preamplifier activation signal PAE is activated, read data driver activation signal RDRV maintains an inactive state, and data bus DB maintains an L level standby state. On the other hand, read detect signal RDET is also activated in clock cycle #c, but signal / OE is in the active state at the L level, so that the output signal of AND circuit 65c shown in FIG. 33 is fixed at the L level. Read amplifier activation signal / SAE is maintained at the H level inactive state. On the other hand, the output signal of NAND circuit 65d becomes H level, read amplifier isolation instruction signal / SAI also maintains L level, and data bus DB and read amplifier 57 are maintained in a separated state. Therefore, read amplifier 57 does not perform the amplification operation, its internal node is held at the L level in the standby state, and the output latch also maintains the standby state. Therefore, in this state, the output buffer is in an output high impedance state, and no data is output.

  When mask designation signal DQM is set to L level in clock cycle #d, internal mask designation signal DQMi is driven to L level, and signal / OE is also held at H level. Therefore, in clock cycle #d, memory cell data is transmitted to data bus DB in accordance with preamplifier activation signal PAE and read data driver activation signal RDRV. Next, the data transmitted on the data bus DB is transmitted to the read amplifier 57 via the read amplifier isolation gate 56. Since signal / OE is at H level, read amplifier activation signal / SAE and read amplifier separation instruction signal / SAI are activated / deactivated in accordance with signals RDLAT and RDLI, and read amplifier 57 performs an amplification operation. Data amplified by read amplifier 57 in clock cycle #d is transmitted to pad PPD through transfer circuit 58, output latch 59 and output buffer 60. Similarly, data is read in clock cycle #e.

  Even when the CAS latency is 3, when a mask instruction is given, the output data after two clock cycles have been masked. That is, even when the CAS latency changes, the DQM latency (the number of clock cycles required from when the mask instruction is given until the external read data is masked) is 2, which is constant regardless of the CAS latency. The output data can be masked with the DQM latency.

  Further, the read amplifier can be set to a standby state by driving the read amplifier activation signal to an inactive state in accordance with the mask instruction signal DQM. The data held by the read amplifier is transmitted to the output latch via the transfer circuit 58 in response to the activation of the read clock signal CLKQ. Therefore, the output buffer can be set to the output high impedance state in accordance with the data held by the read amplifier. Unlike the case where the output buffer itself is set to the output high impedance state in accordance with the mask instruction signal, the timing shift at the time of data transfer according to the read clock signal CLKQ from the read amplifier and the setting of the output high impedance state of the output buffer is considered. There is no need to consider the timing difference between the internal mask instruction signal and the read clock signal CLKQ when the mask instruction is applied, and the external read data can be accurately masked. It is possible to reliably prevent erroneous data from being output.

  FIG. 36 is a diagram more specifically showing the configuration of the data output unit of the modification of the fourth embodiment of the present invention. 36, an equalize circuit 70 is provided for precharging nodes RAD and / RAD of read amplifier 57 to the ground voltage level in accordance with the output signal of inverter 70c receiving signal / OE. Equalize circuit 70 includes n channel MOS transistors 70a and 70b for driving nodes RAD and / RAD to the ground voltage level when the output signal of inverter 70c is at H level.

  The output latch 59 is composed of a NOR type flip-flop that latches the output signal of the transfer circuit 58. Output latch 59 includes NOR circuits 59a and 59b receiving the output signals of tristate inverter buffers 58a and 58b, respectively. The outputs of these NOR circuits 59a and 59b are cross-coupled.

  The output buffer 60 includes an AND circuit 60a that receives the output permission signal OEM and the output signal of the NOR circuit 59a, an AND circuit 60b that receives the output permission signal OEM and the output signal of the NOR circuit 59b, and the output signal of the AND circuit 60a is at the H level. N channel MOS transistor 60c that conducts when power supply voltage Vcc level is generated and n channel MOS transistor that conducts when output signal of AND circuit 60b is at H level and generates read data at the ground voltage level Including 60d. The output permission signal OEM is a signal that is activated for a long burst period after the elapse of (CL-2) clock cycles when a read instruction is given. This output permission signal OEM is a signal independent of the mask instruction signal. Next, the operation of the output unit shown in FIG. 36 will be described with reference to the timing chart shown in FIG.

FIG. 37 shows the operation when the CAS latency is 2 or 3.
In clock cycle #b, read amplifier activation signal / SAE is activated, and read amplifier 57 performs an amplification operation. In this clock cycle #b, if read clock signal CLKQ is at H level when read amplifier activation signal / SAE is activated, tristate inverter buffers 58a and 58b of transfer circuit 58 operate, and read amplifier 57 The amplified data is transferred to the output latch 59. In clock cycle #b, output permission signal OEM is activated again, and the data transferred to output latch 59 is transmitted to output buffer 60. In output buffer 60, since output permission signal OEM is at the H level, the data transferred from output latch 59 is output to the outside via a pad.

  In clock cycle #c, read amplifier activation signal / SAE is driven to the active state again, the data transmitted through read amplifier isolation gate 56 is amplified, and output buffer is connected through transfer circuit 58 and output latch 59. The amplified data is transferred to 60.

  When signal / OE is driven to an L level in accordance with a mask instruction signal in clock cycle #d, read amplifier activation signal / SAE maintains an H level inactive state in clock cycle #d. Equalize circuit 70 is activated to fix nodes RAD and / RAD to the L level. During this time, as described above, the read amplifier isolation gate 56 is also disconnected from the data bus and the read amplifier 57 because the isolation instruction signal / SAI is at the L level. Therefore, nodes RAD and / RAD are equalized to the ground voltage level by equalize circuit 70. When read clock signal CLKQ rises to H level, this L level signal is transmitted to output latch 59 via transfer circuit 58. Tristate inverter buffers 58a and 58b included in transfer circuit 58 both output H level signals, and the output signals of NOR circuits 59a and 59b both attain L level. Therefore, even if output permission signal OEM is at H level, the output signals of AND circuits 60a and 60b are at L level, and output buffer 60 is in an output high impedance state because MOS transistors 60c and 60d are both nonconductive. Thus, the output data is masked.

  When the mask is released in clock cycle #e, read amplifier activation signal / SAE is activated again, and data is output via read amplifier 57, transfer circuit 58, output latch 59 and output buffer 60. . When the burst length data is read, output enable signal OEM is driven to the inactive state at L level in clock cycle #f, and output buffer 60 enters the output high impedance state.

  As shown in FIG. 36, when equalizing circuit 58 is provided and masking is applied, nodes RAD and / RAD of read amplifier 57 are driven to the same ground voltage level as in the standby state, so that output buffer 60 can be reliably connected. In addition, the output high impedance state can be set. Even if the timings of the signal / OE and the read clock signal CLKQ are different, the data to be masked is reliably prevented from being output. That is, if signal / OE is in an active state at L level when read clock signal CLKQ is at H level, nodes RAD and / RAD are driven to L level, and the output signals of transfer circuit 58 are both at H level. The output buffer 60 is driven to the output high impedance state.

  In the case where the signal / OE becomes L level after the read clock signal CLKQ becomes L level, the transfer circuit 58 enters the output high impedance state after the read data is transferred via the transfer circuit 58. The equalize circuit 70 is activated. The L level signals of nodes RAD and / RAD are transferred through transfer circuit 58 in accordance with the fall of the next read clock signal CLKQ. Therefore, in any case, it is possible to accurately prevent the data to be masked from being transferred through the transfer circuit 58.

  Therefore, even when the CAS latency is different and the timing relationship between read clock signal CLKQ and read amplifier activation signal / SAE is different, nodes RAD and / RAD are equalized according to signal / OE, so that output data can be easily obtained. The mask can be applied accurately.

  As described above, according to the fourth embodiment of the present invention, the read amplifier is provided, the data bus is equalized to the ground voltage level every cycle, and based on the read clock signal CLKQ and the read detect signal RDET, Since the sense operation is started, the read data sense operation (amplification operation) can be performed accurately regardless of the clock frequency. In addition, since the read amplifier isolation gate is in a conducting state during the equalization period of the data bus, the data bus equalization circuit can reset the node of the read amplifier to the L level, thereby enabling an accurate amplification operation. Become. In addition, since the data bus equalize circuit is provided outside the read amplifier, this equalize circuit does not need to be arranged near the pad, and the circuit area occupied around the pad of the output control circuit section can be reduced. Becomes easy. Further, since the node potential of the read amplifier is simply equalized according to the equalization of the data bus, it is not necessary to generate a new control signal for node equalization of the read amplifier, and the timing control is facilitated.

  Further, at the time of data output masking, both the read amplifier separation instruction signal and the read amplifier activation signal are inactivated, and the output data can be masked accurately without controlling the DQM latency. In addition, at the time of masking, it is possible to reliably prevent the data to be masked from being output instantaneously and to prevent malfunction.

  Further, since the data bus amplified to the L level is amplified using the differential amplification type read amplifier, even when the data bus amplitude is small, the sense amplification operation is performed by activating the read amplifier. A small amplitude signal can be transmitted to the read data bus, high speed signal transmission can be performed, an accurate read data amplifying operation can be realized, and data propagation of the data bus can be achieved. The time required can be shortened, and high-speed reading can be performed.

  In the above description, the data bus and the read amplifier node are equalized to the L level of the ground voltage level. However, the equalize voltage level may be the power supply voltage Vcc level or an intermediate voltage level.

[Embodiment 5]
FIG. 38 schematically shows a structure of a main portion of the semiconductor memory device according to the fifth embodiment of the present invention. FIG. 38 shows the configuration of the data writing unit for one memory array 2. In FIG. 38, memory array 2 is divided into a plurality of column blocks C # 0 to C # n. Internal write circuits 30 # 0-30 # n are provided corresponding to column blocks C # 0-C # n, respectively. Internal write circuits 30 # 0-30 # n are included in internal write / read circuits 30-0-0-30-n shown in FIG. Data buses DB0 and DB1 for transmitting complementary data signals are provided in common to column blocks C # 0 to C # n. These data buses DB0 and DB1 are also provided in common for the memory arrays of other banks (not shown). Input control circuits 7 # 0 and 7 # 1 are arranged corresponding to data buses DB0 and DB1, respectively. Input control circuits 7 # 0 and 7 # 1 transmit write data from pads PPD0 and PPD1 arranged nearby to corresponding data buses DB0 and DB1, respectively. Data buses DB0 and DB1 are provided with data bus equalizing circuits 55 # 0 and 55 # as in the fourth embodiment.

  Each of internal write circuits 30 # 0-30 # n receives data bus selectors (DBMUX) 71 # 0-71 # n for selecting one of data buses DB0 and DB1 according to a selection signal, and outputs of the corresponding data bus selectors. Write amplifiers 72 # 0-72 # n for amplifying signals, and write drivers 74 # 0-74 # n for further amplifying data supplied from corresponding write amplifiers 72 # 0-72n and writing them into selected memory cells Including. In the configuration of write / write circuits 30 # 0-30 # n shown in FIG. 38, the write data driver is not selectively activated in response to a selection signal, but data for selecting a bus in accordance with the selection signal. Bus selectors 71 # 0 to 71 # n are provided. As a result, it is possible to reduce the load on the data bus during data reading.

  FIG. 39 shows a structure of input control circuits 7 # 0-7 # 1 shown in FIG. In FIG. 39, since these input control circuits 7 # and 7 # 1 have the same configuration, one input control circuit 7 # is representatively shown.

  Referring to FIG. 39, input control circuit 7 # includes a data input circuit 75 which takes in the data applied to pad PPD in synchronization with write clock signal CLKD and generates complementary internal write data DIN and / DIN, and when activated. Write data driver 76 for driving data bus lines DBB and / DBB according to complementary write data DIN and / DIN from data input circuit 75 is included. Data input circuit 75 has a configuration similar to that of the DQM buffer shown in FIG. 14, takes in write data applied to pad PPD in synchronization with write clock signal CLKD, and performs complementary internal write data DIN and / DIN is generated. Write clock signal CLKD is external clock signal ext. It is generated from a clock generation circuit shown in FIG.

  The write data driver 76 includes an AND circuit 76a that receives the write data driver activation signal WDRVF and the selection signal SEL, an NAND circuit 76b that receives the output signal WDRV of the AND circuit 76a and the data signal DIN from the data input circuit 75, and an AND circuit 76a. Output signal WDRV and complementary data signal / DIN from data input circuit 75, inverter 76e receiving the output signal of NAND circuit 76b, inverter 76d receiving the output signal of NAND circuit 76c, and power supply node P channel MOS transistor 76f connected between data bus line DBB and receiving the output signal of NAND circuit 76b at its gate, and connected between data bus line DBB and the ground node and connected at its gate to the output signal of inverter 76d. Receive n-channel MOS transistor 76g, n-channel MOS transistor 76i connected between data bus line / DBB and the ground node and receiving the output signal of inverter 76e at its gate, and connected between the power supply node and data bus line / DBB And a p channel MOS transistor 76h receiving the output signal of NAND circuit 76c at its gate.

  The write data driver 76 has the same configuration as the read data driver, and is selectively set to an operable state in accordance with the selection signal SEL. In the non-selected write data driver, the output signals of NAND circuits 76b and 76c are at H level, the output signals of inverters 76d and 76e are at L level, and write data driver 76 is in the output high impedance state.

  Data bus equalize circuit 55 is activated in response to data bus equalize instruction signal / DBEQ applied through inverter 61a, and equalizes data bus lines DBB and / DBB to the ground voltage level.

  40 shows a structure of the internal write circuit shown in FIG. Since internal write circuits provided corresponding to column blocks C # 0 to C # n have the same configuration, FIG. 40 representatively shows the configuration of one internal write circuit. As shown in FIG. 38, the internal write circuit includes a data bus selector 71 #, a write amplifier 72 #, and a write driver 74 #. Data bus selector 71 # selects data bus lines DBB0 and / DBB0 provided for pad PPD0 according to selection signal SEL0, and data bus line DBB1 provided for pad PPD1 according to selection signal SEL1. And a selection circuit 71b for selecting / DBB1. In FIG. 40, these selection circuits 71a and 71b are shown as comprising transfer gates.

  Write amplifier 72 # is activated in response to activation (L level) of write driver activation signal / WDE to perform a sense amplification operation, and to activate write driver activation signal / WDE. In response, it includes a write amplifier isolation gate 73b which becomes non-conductive and disconnects the write amplifier circuit 73a and the data bus line. Similarly to the read amplifier, write amplifier 73a has cross-coupled p-channel MOS transistor and cross-coupled n-channel MOS transistor, and this cross-coupled p-channel in response to activation of write driver activation signal / WDE. A sense activation transistor (p-channel MOS transistor) for transmitting a power supply voltage to the MOS transistor is included.

  Write driver 74 # is activated in response to activation of write driver activation signal WDE, amplifies a signal on node WAD of the write amplifier to generate internal write data WD, and selects array IO to the selected memory cell. AND circuit 75a transmitting via a line (not shown), and activated in response to activation of write driver activation signal WDE, amplifies the signal on node / WAD to generate internal write data / WD An AND circuit 75b is generated and transmitted onto the array IO line. Write driver 74 # includes AND circuits 75a and 75b, and holds both internal write data WD and / WD at the ground voltage level during standby (when write driver activation signal WD is inactive). However, this write driver 74 # may be a drive circuit constituted by a NAND circuit. Next, the operation of the data writing unit shown in FIGS. 39 and 40 will be described with reference to the timing chart shown in FIG.

  First, with reference to FIG. 41A, a writing operation when the CAS latency at the time of data writing is 2 will be described.

  A clock signal CLKD for writing is generated in each clock cycle in synchronization with the internal clock signal CLK. When a write command is applied in clock cycle #a, write data is also applied to pad PPD at the same time. Data input circuit 75 takes in the data applied to pad PPD in accordance with write clock signal CLKD, and generates internal write data DIN and / DIN. Consider a case where the burst length is 4 and four data are given consecutively. When a write command is applied, write data driver activation signal WDRV is driven to an active state, and internal write data signals DIN and / DIN from data input circuit 75 are amplified and transmitted onto data bus DB. Data bus lines DBB and / DBB that have been equalized to the ground voltage level by data bus equalize circuit 55 according to data bus equalize instruction signal / DBEQ so far change in voltage level according to the output signal from write data driver 76. . A signal transmitted from write data driver 76 to data bus DB is transmitted to write amplifier 72 # via data bus selector 71 #. In this clock cycle #a, write driver activation signal WDEF rises to H level, block selection signal BS is activated, and write driver activation signal WDE rises to H level. At the rise of write driver activation signal WDE, write driver activation signal / WDE is at L level, write amplifier isolation gate 73b is turned off, and write amplifier 73a is activated simultaneously or with a delay. . Thereby, the data transmitted via data bus DB is amplified at high speed by write amplifier 73a, and internal write data WD and / WD are generated via write driver 74 #.

  Even during the data writing, by providing write amplifier isolation gate 73b for the write amplifier, write amplifier 73a can perform high-speed amplification of the small amplitude signal transmitted to nodes WAD and / WAD (node). The load of WAD and / WAD is small). Thus, a small amplitude signal can be transmitted to the data bus DB, and high-speed data transfer is possible. Further, since the data bus DB and the write amplifier 73a are simply connected by connecting transfer gates in series, the circuit configuration for this data bus selection and write amplifier separation is simplified, and the occupied area is reduced. Can do.

  Next, with reference to FIG. 41B, the operation when the CAS latency at the time of writing is 3 will be described. When a write command is applied in clock cycle #a, data input circuit 75 generates internal write data signals DIN and / DIN in synchronization with write clock signal CLKD in clock cycle #a, and write data drive Activation signal WDRV is activated, and write data is transmitted onto data bus DB. When the CAS latency is 3, almost one clock cycle period is required to transmit the data signal to the write amplifier 72 # via the data bus DB. In the clock cycle #b, the node WAD of the write amplifier circuit 73a is required. And the signal potential to / WAD changes according to the write data. Then, write driver activation signal WDEF is activated in clock cycle #b, amplifies the small amplitude signal transmitted on nodes WAD and / WAD, and write driver WD and write data WD and / WD are amplified by write driver 74 #. Is generated. When amplification operation by write amplifier 72 # is completed, write amplifier isolation gate 73b is rendered conductive, data bus DB and nodes WAD and / WD are connected, and data bus equalize circuit 55 causes nodes WAD and / WAD to be connected to the ground voltage level. Equalize. Write data applied in clock cycles #a, #b, #c and #d, respectively, are generated as internal write data WD and / WD in clock cycles #b, #c, #d and #e, This data is written to the selected memory cell over approximately one clock cycle period.

  In the above description, the data bus DB is equalized to the ground voltage level. However, the data bus DB may be equalized to an intermediate voltage or a power supply voltage level. When equalized to the power supply voltage level, data bus selection circuits 71a and 71b and write amplifier isolation gate 73b included in data bus selector 71 # are replaced with p channel MOS transistors.

  Control signals WDRVF and WDEF are generated from the write control circuit when a write command is applied and write activation signal φw is activated using the control circuit described in the first to third embodiments. . The block selection signal BS is also shifted for a predetermined period according to the CAS latency at the time of data writing. This is easily realized by using the shifter shown in FIG. Data bus equalize instruction signal / DBEQ is generated according to signal WDRF.

[Example of change]
FIG. 42 shows a structure of a modified example of the fifth embodiment of the present invention. 42, an internal read / write circuit 30 is provided for data buses DB0 and DB1. As described in the second embodiment, a plurality of internal read / write circuits are coupled in parallel to data buses DB0 and DB1, but in FIG. 42, one internal read / write circuit 30 is connected. Is representatively shown.

  Internal read / write circuit 30 includes an internal read circuit 30R (30 # ia) for reading data and an internal write circuit 30W (30 # i) for writing data. Internal read circuit 30R is activated in response to a preamplifier activation signal PAE (including a block selection signal), and a preamplifier 32 for amplifying the read memory cell data and an output signal of preamplifier 32 for a predetermined period (CAS). (Latency-2 clock cycles) The CL shifter 34 to be shifted, and activated in response to the activation of the selection signal SEL and the read data drive activation signal RDRV, amplifies the data from the CL shifter 34 to the data bus DB0 or DB1 A read data drive circuit 4 for transmitting to is included.

  Internal write circuit 30W is selectively activated in response to a logical product signal (/ RDRV · SEL) of selection signal SEL and read data drive activation signal / RDRV to select data bus DB0 or DB1. Activated in response to activation of the selector (DBMUX) 71 and the write drive activation signal / WDE, and activates the write amplifier 72 that amplifies data from the data bus selector 71 and the write driver activation signal WDE. It includes a write driver 74 that is activated in response and amplifies the data amplified by the write amplifier 72 and transmits the amplified data to an array IO line (not shown).

  As shown in FIG. 22, read data drive circuit 4 transmits data to data bus DB0 or DB1 when read data drive activation signal RDRV is activated in accordance with selection signal SEL. This read data drive activation signal RDRV does not include a block selection signal. When the read data drive circuit 4 is activated, the data bus selector 71 is turned off. That is, all data bus selectors coupled to data buses DB0 and DB1 are set to a non-conductive state when read data drive activation signal RDRV is activated. Thereby, internal write circuit 30W is separated from data buses DB0 and DB1, and the load on read data drive circuit 4 is reduced. Thereby, data can be transmitted to input / output control circuits 7a and 7b via data buses DB0 and / or DB1 at high speed.

  FIG. 43 schematically shows a structure of the data bus selector shown in FIG. 43, data bus selector 71 is provided for data bus lines DBB0 and / DBB0, and is a bus whose conduction / non-conduction is controlled by AND circuit 81 receiving selection signal SEL0 and read data driver activation signal / RDRV. Select circuit 71a is provided for data bus lines DBB1 and / DBB1, and is selectively set to a conductive / non-conductive state according to a signal from AND circuit 82 receiving selection signal SEL1 and read data driver activation signal / RDRV. Including a selection circuit 71b.

  When read data driver activation signal RDRV is activated, signal / RDRV is at L level, and selection circuits 71a and 71b are both rendered non-conductive. These selection circuits 70 are coupled to a write amplifier 72. Therefore, during operation of read data drive circuit 4, data bus lines DBB0, DBB1, and / DBB1 can be separated from write amplifier 72 by turning off data bus selector 70, and these bus lines DBB0 , / DBB0, DBB1, and / DBB1 can be reduced, and read data can be transferred at high speed.

  Also in the configuration shown in FIG. 42, read data driver activation signal RDRV has a logic with the bank address signal, and a configuration in which read data drive activation signal RDRV is activated only in the selected bank is used. May be.

  As described above, according to the fifth embodiment of the present invention, even during data writing, a complementary data signal is transmitted, and the write amplifier and the data bus are separated to activate the write amplifier. Data can be written by transmitting the amplitude signal through the data bus. Further, since the connection between the data bus and the write amplifier is performed using a transfer gate, the circuit configuration is simplified, and the circuit occupation area is reduced.

  In addition, when the read data drive activation signal is activated, all data bus selectors are set in a non-conductive state, so that the load on the data bus is reduced and read data can be transmitted at high speed.

[Embodiment 6]
FIG. 44 schematically shows a structure of a main portion of the semiconductor memory device according to the sixth embodiment of the present invention. In FIG. 44, internal read / write circuits 30-0 to 30-n are commonly connected to data buses DB1 and DB0. Connection paths of these internal read / write circuits 30-0 to 30-n are forcibly set to data bus DB1 in accordance with multi-bit test mode instruction signal MBT. Therefore, in the x2-bit configuration, even when these internal read / write circuits 30-0 to 30-n are coupled to data bus DB0, these internal read / write circuits are in the multibit test mode. Insertion circuits 30-0 to 30-n are coupled to data bus DB1. Therefore, in the memory array corresponding to internal read / write circuits 30-0 to 30-n, even if 2-bit data is read from each column block, they are all on multi-bit test mode on data bus DB1. Transmitted when. In the × 1 bit configuration, only the data bus DB1 is used. Data buses DB0 and DB1 are coupled to pads PPD0 and PPD1 through input / output control circuits 7a and 7b, respectively. Data bus DB1 is provided with a determination circuit 85 for determining whether or not the logic of complementary data signals transmitted on data bus DB1 is the same in the multi-bit test mode. The output signal of the determination circuit 85 is output to the pad PPD1 through a read amplifier included in the input / output control circuit 7b. These configurations will be described in detail later.

  FIG. 45 schematically shows a structure of a portion for generating a selection signal and a block selection signal in the multi-bit test mode. In FIG. 45, the control signal generation unit includes an OR circuit 86a receiving multi-bit test mode instruction signal MBT and block selection signal BS, and an OR circuit 86b receiving multi-bit test mode instruction signal MBT and bus selection signal SEL <1>. Inverter 86c receiving multi-bit test mode instruction signal MBT, and AND circuit 86d receiving the output signal of inverter 86c and bus select signal SEL <0>. The OR circuit 86a outputs a block selection signal BS applied to the internal read / write circuits 30-0 to 30-n, the OR circuit 86b outputs a selection signal SEL1, and the AND circuit 86d outputs a selection signal SEL0. Is done. Therefore, in the multi-bit test mode, all block selection signals BS are selected, block selection signals for all column blocks included in the memory array are selected, and the internal read / write shown in FIG. The embedded circuits 30-0 to 30-n all operate in parallel. Select signal SEL1 is forcibly set to the active state at the H level in the multi-bit test mode, and all internal read / write circuits 30-0 to 30-n are coupled to data bus DB1 regardless of the word configuration. The On the other hand, selection signal SEL0 is forcibly set to an inactive state of L level in the multi-bit test mode, and internal write / read circuits 30-0 to 30-n are disconnected from data bus DB0.

  By using this configuration, data can be written and read using the complementary data bus even in the multi-bit test mode.

  FIG. 46 shows a structure of a read data driver included in internal read / write circuits 30-0 to 30-n shown in FIG. 46, the read data driver shown in FIG. 8, NOR circuit G80 receiving multibit test mode instruction signal MBT and the signal of node LRD instead of inverters G4 and G5, multibit test The difference is that a NOR gate circuit G81 for receiving a signal on mode instruction signal MBT and a signal on node / LRD is used. Other configurations are the same as those shown in FIG. 8, and corresponding portions are denoted by the same reference numerals.

  In the normal operation mode, multi-bit test mode instruction signal MBT is at L level, and NOR circuits G80 and G81 function as inverters. The selection signal SEL is also determined according to the word configuration, and in response to the activation of the read data driver activation signal RDRV, the read data driver is connected to the node PD and / PD (preamplifier output node) or the node RD and Data bus lines DBB and / DBB are driven in accordance with a signal from / RD (CL shifter output node).

  In the multi-bit test mode, this selection signal SEL is forcibly set to H level or L level regardless of the word configuration. When the read data driver is connected to the data bus, the selection signal SEL becomes H level, and the read data driver operates in accordance with the activation of the read data driver activation signal RDRV. On the other hand, when the read data driver is disconnected from the corresponding bus, the selection signal SEL is at the L level, and even if the read data driver activation signal RDRV is activated, the read data driver has an output high impedance state. maintain. NOR circuits G80 and G81 have their output signals fixed at the L level in the multi-bit test mode, and MOS transistors QT2 and QT4 are turned off. Data bus lines DBB and / DBB are precharged to the L level of the ground voltage level as described in the third and fourth embodiments. At the time of data reading, one output signal of NAND circuits G2 and G3 is at H level and the other is at L level. Therefore, one of MOS transistors QT1 and QT3 is rendered conductive, and one of data bus lines DBB and / DBB is driven to the H level. A plurality of read data drivers are wired-connected in parallel to the data bus lines DBB and / DBB.

  When data is written in the multi-bit test mode, bus connection is performed by the data bus selector described in the sixth embodiment, and column blocks of the memory array are simultaneously selected, as shown in FIG. The same bit of data is written in parallel via pad PPD1 and write data driver included in input / output control circuit 7b and data bus DB1. At the time of reading, data is read in parallel from these memory cells to which data has been simultaneously written, and read operations are performed in parallel by internal write / read circuits 30-0 to 30n.

  Now consider the operation of the two read data drivers 4-0 and 4-1, as shown in FIG. It is assumed that data “1” is read to the read data driver 4-0 and data “0” is read to the read data driver 4-1. In this case, nodes PD0 and / PD0 are at H level and L level, respectively, while nodes PD1 and / PD1 are at L level and H level, respectively. In the multi-bit test mode, n channel MOS transistors for discharging data bus lines DBB and / DBB to the ground voltage level receive a low level signal at their gates and are in a non-conductive state. Therefore, an H level signal is output from the corresponding p-channel MOS transistor to read data driver 4-1 on data bus line DBB, and read data driver 4-0 is connected to high level on data bus line / DBB. Hold in impedance state. On the other hand, in read data driver 4-1, data bus line DBB is set to a high impedance state, and an H level signal is output to data bus line / DBB. Therefore, both data bus lines DBB and / DBB are driven to the H level by read data drivers 4-0 and 4-1. Therefore, when the voltage levels of these data bus lines DBB and / DBB are both at the H level, it is identified that different logic data has been read, and a defective memory cell exists in these simultaneously selected memory cells. Can be identified. When one of data bus lines DB and / DBB is at L level, it is determined that accurate data reading has been performed.

  FIG. 48 schematically shows a structure of determination circuit 85 shown in FIG. 48, determination circuit 85 includes a NAND circuit G85 receiving signals on data bus lines DBB1 and / DBB1 and multibit test mode instruction signal MBT, and a NAND circuit receiving an output signal of NANDG85 and multibit test mode instruction signal MBT. G86 is selectively turned on when isolation instruction signal / MAI is inactive, and includes a test isolation gate 86 for coupling the output signals of NAND circuits G85 and G86 to nodes RAD and / RAD of read amplifier 57. Test isolation gate 86 is provided in parallel with read amplifier isolation gate 56 which is provided for read amplifier 57 and is rendered non-conductive when read amplifier isolation instruction signal / SAIT is activated. As in the fourth embodiment, the output control circuit includes a transfer circuit 58 that transfers signals of nodes RAD and / RAD of read amplifier 57, an output latch 59 that latches an output signal of transfer circuit 58, and an output buffer (not shown). Including.

  When multi-bit test mode instruction signal MBT is inactive, the output signals of NAND circuits G85 and G86 are fixed at the H level. In this state, test isolation gate 86 is non-conductive, and the output signals of NAND circuits G85 and G86 do not adversely affect the amplification operation of read amplifier 57. In the normal operation mode, read amplifier isolation gate 56 is selectively turned on / off in accordance with read amplifier separation instruction signal / SAIT, and data bus lines DBB1 and / DBB1 are coupled to read amplifier 57.

  In the multi-bit test mode, multi-bit test mode instruction signal MBT is at H level. When one of data bus lines DBB1 and / DBB1 is at the L level, the output signal of NAND circuit G85 is at the H level, while the output signal of NAND circuit G86 is at the L level, and nodes RAD and / RAD have the H level and An L level signal is transmitted and amplified by the read amplifier 57. Next, data is read through transfer circuit 58 and output latch 59, and data "1" is output. On the other hand, when both data bus lines DBB1 and / DBB1 are at H level, the output signal of NAND circuit G85 is at L level, while the output signal of NAND circuit G86 is at L level. Therefore, the data amplified by the read amplifier 57 and read to the outside through the transfer circuit 58 and the output latch 59 becomes “0”. The normality / abnormality of the selected memory cell can be determined by looking at the logic of these read data.

  NAND circuits G85 and G86 are used at the time of data reading in the multi-bit test mode, and data bus lines DBB1 and / DBB1 have a CMOS level amplitude. However, in the multi-bit test mode, it is merely determined whether or not the memory cell data has been correctly written / read, and the operation timing margin and the like are not measured. Therefore, since the operating frequency is slow in the multi-bit test mode, data bus lines DBB1 and / DBB1 can be sufficiently driven at the CMOS level.

  In addition, since all the read data drivers are coupled to the data bus in common and the data bus line is configured to change in one direction from the equalize voltage (voltage in the standby state), these read data drivers are By wired connection, read data can be accurately transmitted on the data bus line.

  FIG. 49 schematically shows a structure of a portion generating separation instruction signals / SAIT and / MAI.

  49, the separation instruction signal generation unit includes an inverter G87 that receives multibit test mode instruction signal MBT, an AND circuit G88 that receives read amplifier separation instruction signal / SAI and an output signal of inverter G86, and a read amplifier separation instruction signal / An AND circuit G89 receiving SAI and multi-bit test mode instruction signal MBT is included. AND circuit G88 outputs separation instruction signal / SAIT and applies it to read amplifier separation gate 56 shown in FIG. AND circuit G89 outputs a separation control signal / MAI and applies it to test separation gate 86 shown in FIG.

  In the configuration shown in FIG. 49, in multi-bit test mode, isolation instruction signal / SAIT from AND circuit G88 is always at L level, and read amplifier isolation gate 56 shown in FIG. 48 maintains a non-conductive state. . On the other hand, the output signal of AND circuit G89 changes according to read amplifier isolation instruction signal / SAI, and drives test isolation gate 86 to the conductive / nonconductive state. Therefore, the output signal of the determination circuit 85 can be transmitted to the read amplifier 57 at the same timing as in the normal operation mode.

  In the normal operation mode, multi-bit test mode instruction signal MBT is at L level, the output signal of AND circuit G88 changes according to read amplifier separation instruction signal / SAI, and the output signal of AND circuit G89 is at L level. Fixed. Therefore, test isolation gate 86 is rendered non-conductive in the normal operation mode and does not adversely affect the read operation.

  As described above, according to the sixth embodiment of the present invention, in the multi-bit test mode, a plurality of read data drivers are commonly coupled to a data bus line, and the logic of signals on the data bus line is matched. / Because it is configured to determine inconsistency, there is no need to provide a new bus line dedicated for testing, and the same data bus can be used in normal operation mode and multi-bit test mode. The occupied area can be reduced.

  In the above description, the data bus lines are both equalized to the L level, but this may be configured to be equalized to the intermediate voltage level or the power supply voltage level. The configuration of the read data driver is appropriately modified according to the equalize voltage of each data bus line.

[Embodiment 7]
FIG. 50 schematically shows a structure of pad arrangement of the semiconductor memory device according to the present invention. In FIG. 50, eight pads PPD0 to PPD7 are arranged in alignment. This pad arrangement is a LOC (lead on chip) structure pad arrangement. Pads PPD0, PPD1, PPD2 and PPD3 input / output data DQ0, DQ1, DQ2 and DQ3 via a lead frame extending to one side. Pads PP4 to PPD7 disposed between these pads PPD0 to PPD3 input / output data DQ4 to DQ7 via a lead frame extending to the other side. Input / output circuits are arranged close to each of these pads PPD0 to PPD7.

  In the semiconductor memory device according to the present invention, consider a case where the number of bits of input / output data, that is, the word configuration is switched between the x8 bit configuration and the x4 bit configuration. In the case of the × 8 bit configuration, all the pads PPD0 to PPD7 are used. In the case of the × 4 bit configuration, pads PPD0, PPD2, PP4, and PPD6 are used. In the multi-bit test mode, of these eight pads PPD0 to PPD7, pads PPD2, PPD4, PPD5, and PPD6 used in the x4 bit configuration are used. The data bus is arranged in a one-to-one correspondence with each of these pads PPD0 to PPD7.

  FIG. 51 schematically shows a data bus arrangement according to the seventh embodiment of the present invention. In FIG. 51, the data bus line used in the x4 bit configuration, the x8 bit configuration, and the multibit test mode and the data bus bus line used only in the x8 bit configuration are alternately arranged and predetermined. The position is exchanged through the intersection in the area of. Four data bus lines are arranged as a set. In each set of data bus lines, bus lines used only in the x8-bit configuration and bus lines used in the x8-bit configuration, the x4-bit configuration, and the multi-bit test mode are alternately arranged. A bus line corresponding to another pad is disposed between the paired bus lines. Therefore, as shown in FIG. 51, 16 bus lines DBB0, / DBB0 to DBB7, / DBB7 are arranged to correspond to the x8 bit configuration. Data bus lines DBB0, / DBB0 and DBB1, / DBB1 are arranged in one set, data bus lines DBB7, DBB6, / DBB7 and / DBB6 are arranged in a set, and data bus lines DBB5, / DBB5 , DBB4, / DBB4 form one set, and data bus lines DBB2, DBB3, / DBB2, and / DBB3 are arranged in a set.

  In each set, adjacent data bus lines are always another pair of bus lines (bus lines corresponding to different pads). Even in the case of having an intersection, in each segmented region, another pair of bus lines is arranged between the paired bus lines.

  In the × 8 bit configuration, all of these bus lines are used. Since each data bus line has an intersecting portion, capacitive coupling is reduced in each data bus line, and noise due to capacitive coupling is reduced between adjacent buses. Since the paired data bus lines have a twist structure (a structure having an intersection), noise is generated in the same phase in the paired bus lines, so that the noise is canceled and the data signal can be stably transmitted. . Thereby, a small amplitude signal can be transmitted at high speed and stably. In particular, since a bus line used only in the x8 bit configuration is arranged between a pair of bus lines used in the x8 bit, x4 bit and multibit test modes, in the x4 bit configuration By setting unused data buses to a fixed potential, these unused data bus lines can be completely used as shield lines, and noise can be almost completely canceled out.

  In each group, a data bus corresponding to a pair of pads as close as possible is selected. This is because the data buses are arranged in one-to-one correspondence with the pads PPD0 to PPD7, and the data buses DB0 to DB7 extend in one direction from these pads (see FIG. 1) and are as close as possible. By selecting the pair of pads to be used, the length of the paired data buses can be made almost equal, the parasitic capacitance of each wiring can be made almost equal, and the effect of capacitive coupling can be accurately canceled (See FIG. 52).

  The × 4 bit configuration and the × 8 bit configuration can be realized using the selection signals SEL and SEL1. In the multi-bit test mode, the data bus used in the x4 bit configuration is used by a multi-bit test mode instruction signal MBT (indicated by the same sign as the multi-bit test). This is realized by forcibly setting the selection signal in the previous sixth embodiment with multi-bit test mode instruction signal MBT.

  FIG. 52 is a diagram showing an example of the configuration of the data bus line. In FIG. 52, data bus lines DBBa, DBBb, / DBBa, and / DBBb are shown as one set of data bus lines. Data bus lines DBBa and / DBBa are used only in the x8 bit configuration. Data bus lines DBBb and / DBBb are used in the x8 bit configuration, the x4 bit configuration, and the multi-bit test mode. These data bus lines DBBa, DBBb, / DBBa and / DBBb are sequentially arranged. Data bus lines DBBa and / DBBa are provided with n channel MOS transistors TRa and TRb for receiving an output signal from OR circuit G99 and fixing data bus lines DBBa and / DBBa to a predetermined potential (ground voltage or power supply voltage) level, respectively. It is done.

  OR circuit G99 receives multi-bit test mode instruction signal MBT and column selection signal φsel4 indicating that the word configuration is a × 4 bit configuration. Therefore, in the x4 bit configuration, since bus lines DBBa and / DBBa are not used, MOS transistors TRa and TRb are rendered conductive, and bus lines DBBa and / DBBa are fixed at a predetermined voltage level. Also in the multi-bit test mode, the output signal of OR circuit G99 is at H level, and data bus lines DBa and / DBa are fixed at a predetermined voltage level.

  When data bus lines DBBa and / DBBa are fixed at the power supply voltage level, p-channel MOS transistors are used as MOS transistors TRa and TRb. As a result, the data buses DBBb and / DBBb to be used can be shielded by the data bus lines DBBa and / DBBa set to a fixed potential level in the × 4 bit configuration and in the multi-bit test mode, and noise is completely eliminated. Can be offset.

  FIG. 53 schematically shows a structure of a data bus potential control unit. 53, an OR circuit G100 is provided which receives multi-bit test mode instruction signal MBT, bus selection signal φsel4, and data bus equalization instruction signal / DBEQ. Signal / DBEQ from OR circuit G100 is applied to the data bus equalize circuit. In a normal x8-bit configuration, signal φsel4 is at L level, and multi-bit test mode instruction signal MBT is also at L level. Therefore, equalization of the corresponding data bus can be controlled in accordance with data bus equalization instruction signal / DBEQ.

  In the × 4 bit configuration, bus selection signal φsel4 is at H level, data bus equalization instruction signal / DBEQ is at H level, the corresponding data bus equalization circuit is always on, and the corresponding data bus line is at the ground voltage level. Fixed to. Similarly in multi-bit test mode, multi-bit test mode instruction signal MBT causes data bus equalize instruction signal / DBEQ from OR circuit G100 to be at H level, and the corresponding data bus equalize circuit is always in a conductive state and is not used. The data bus line is fixed to the ground voltage level.

  When the control circuit shown in FIG. 53 is used, an already provided data bus equalize circuit can be used to fix the potential of the data bus line, and the area occupied by the circuit can be reduced.

  In the configuration for selecting the 4-bit bus line of the data bus used in the x4-bit mode in the multi-bit test mode, the data bus selector in the sixth embodiment is connected to the multi-bit test mode instruction signal MBT and This is realized by setting a route according to the logical sum of the × 4 selection signals.

  Also, as shown in FIG. 52, the bus lines forming a pair are data bus pairs provided corresponding to adjacent pads, and the lengths thereof can be made substantially equal, their parasitic capacitances are equal, and the intersections Even if this is provided, the parasitic capacitance distribution in each inter-intersection region can be made equal, and an accurate noise canceling operation is realized.

  In the above description, switching between the x4 bit configuration and the x8 bit configuration is described. However, the configuration shown in the seventh embodiment can be similarly expanded in the mutual switching of multi-bit configurations such as a × 32-bit configuration, a × 16-bit configuration, and a × 8-bit configuration. In addition, the intersection is easily realized by different layer wiring.

  As described above, according to the seventh embodiment of the present invention, the data bus lines used at the time of one word configuration and the data bus lines not used are arranged to form a pair and are alternately arranged. In addition, since the crossing portion is provided, it is possible to accurately reduce capacitive coupling noise between the data bus lines, and to transmit a signal at high speed and stably. Even in the multi-bit test mode, the read data driver is wired-OR connected to the data bus line, but these adjacent bus lines are shielded by the bus line fixed at a constant potential, so that the test is stable. A signal indicative of the result can be generated.

  Further, even in a semiconductor memory device having a multi-bit configuration and high current consumption and high possibility of generating power supply noise, the data bus line can be accurately transmitted at high speed without being affected by capacitive coupling.

[Embodiment 8]
FIG. 54 shows a structure of a main portion of the semiconductor memory device according to the eighth embodiment of the present invention. FIG. 54 representatively shows a configuration of one column block C #. Column block C # is divided along a column direction into a plurality of row blocks UR # 0-UR # 7 and LR # 0-LR # 7 each including a plurality of word lines. Row blocks UR # 0 to UR # 7 constitute an upper row block (global block) URB, and row blocks LR # 0 to LR # 7 constitute a lower row block (global block) LRB. At the time of selection, one row block is selected from the upper row block URB, and one row block is selected from the lower row block LRB. Global IO buses GIO0 to GIO7 are arranged extending in the column direction over row blocks UR # 0 to UR # 7 and LR # 0 to LR # 7. Global IO buses GIO0, GIO2, GIO4 and GIO6 are provided for the lower row block LRB, while global IO buses GIO1, GIO3, GIO5 and GIO7 are provided for the upper row block URB.

  Local IO buses LIO0 to LIO33 are arranged for row blocks UR # 0 to UR # 7 and LR # 0 to LR # 7, respectively. These local IO buses LIO0 to LIO33 are provided at a ratio of four to one row block, and two local IO buses are shared in adjacent row blocks. For example, row block UR # 0 exchanges data with local IO buses LIO0 to LIO3. Local IO buses LIO2 and LIO3 are shared by row blocks UR # 0 and UR # 1. These local IO buses LIO0 to LIO33 exchange data only with the corresponding row blocks.

  Local IO buses LIO0 to LIO33 are connected to global IO buses GIO0 to GIO7 via block selection gates BG, respectively. A local IO bus provided for a selected row block (a row block including a selected word line) is coupled to a global IO bus via a block selection gate BG.

  In the global / local IO bus arrangement shown in FIG. 54, global IO buses GIO0, GIO2, GIO4, and GIO6 are provided for the row blocks of lower row block LRB, while global IO buses GIO1, GIO3, GIO5 and GIO7 are provided for the upper row block URB. However, local IO buses LIO16 and LIO17 provided for row block LR # 0 included in lower row block LRB are connected to global IO buses GIO5 and GIO7 provided for upper row blocks via block selection gate BG. Respectively.

  On the other hand, local IO buses LIO0 and LIO1 provided for row block UR # 0 are coupled to global IO buses GIO4 and GIO6 via block selection gate BG. The reason why the connection between the local IO bus and the local IO bus is changed in the row blocks UR # 0 and LR # 0 is as follows. In operation, one row block is selected in each of the upper row block URB and the lower row block URB. When row block UR # 7 is selected, row block LR # 7 is also selected. This is because the row block at the same position is selected in each of the upper row block URB and the lower row block LRB.

  When row block UR # 7 is selected, when local IO buses LIO16 and LIO17 are coupled to global IO buses GIO4 and GIO6, row block LR # 7 and local IO buses LIO32 and LIO33 are also global IO bus GIO. And GIO6. In this case, therefore, data conflict occurs in global IO buses GIO4 and GIO6. In order to prevent this data collision, local IO buses LIO16 and LIO17 are coupled to global IO buses GIO5 and GIO7.

  On the other hand, when row block LR # 0 is selected and row block UR # 0 is selected, data of row block LR # 0 is transmitted to local IO buses LIO16 and LIO17. When local IO buses LIO0 and LIO1 are coupled to global IO buses GIO5 and GIO7, a collision between data from row block UR # 0 and data in row block LR # 0 occurs. Therefore, to prevent this, local IO buses LIO0 and LIO1 are coupled to global IO buses GIO4 and GIO6, respectively.

  When row blocks (hereinafter referred to as end blocks) UR # 0 and LR # 0 located at one end of each of the upper row block URB and the lower row block LRB are selected, the upper row block and the lower row block However, the connection mode of the local IO bus and the global IO bus is different from when other row blocks are selected. In other words, in end block UR # 0, local IO buses LIO0 and LIO1 are coupled to global IO buses GIO4 and GIO6, while in remaining row blocks UR # 1 to UR # 7, global IO buses GIO5 and GIO7 are connected. Selected memory cell data is transmitted. In end block LR # 0, local IO buses LIO16 and LIO17 are coupled to global IO buses GIO5 and GIO7. In the remaining row blocks LR # 1 to LR # 7, global IO buses GIO4 and GIO6 are connected. Thus, memory cell data is transmitted. For global IO buses GIO0 to GIO3, the connection between the local IO bus and the global IO bus is the same for each row block of the upper row block URB and the lower row block LRB.

  In the present invention, each data bus is provided in a one-to-one correspondence with the pad. In the multi-bit test mode, data from the pad is transmitted to a plurality of memory cells. In this multi-bit test mode, the coupling between the data bus and the global IO bus is changed depending on whether or not the end block is selected so that the defective memory cell column can be determined, that is, the spare can be determined.

  FIG. 55 is a diagram showing the correspondence between the global IO bus and the data bus. In FIG. 55, global IO bus GIO0 is coupled to data bus DB0 in the x8-bit configuration and x4-bit configuration, and is coupled to data bus DB2 in the x2-bit configuration. Global IO bus GIO1 is coupled to data bus DB4 in the x8-bit configuration and x4-bit configuration, and is coupled to data bus DB6 in the x2-bit configuration. Global IO bus GIO2 is coupled to data bus DB1 in the x8 bit configuration, coupled to data bus DB0 in the x4 bit configuration, and coupled to data bus DB2 in the x2 bit configuration.

  Global IO bus GIO3 is coupled to data bus DB5 in the x8 bit configuration, coupled to data bus DB4 in the x4 bit configuration, and coupled to data bus DB6 in the x2 bit configuration. The These global data buses GIO0 to GIO3 have a unique connection relationship between the global IO bus and the data bus in each word configuration regardless of the selection / non-selection of the end block. As shown in FIG. 54, for the global IO buses GIO0 to GIO3, the connection relationship between the local IO bus and the global IO bus is the same in each of the upper row block URB and the lower row block LRB. It is not necessary to do.

  Global IO bus GIO4 is coupled to data bus DB2 in the x8-bit configuration, and is coupled to data bus DB2 in the x4-bit configuration or the x2-bit configuration when a row block other than the end block is selected. When the end block is selected in the × 4 bit configuration and the × 2 bit configuration, global IO bus GIO4 is coupled to data bus DB6. Here, in FIG. 55, symbol ZX4 indicates a state in which a row block other than the end block is selected in the × 4 bit configuration, and symbol ZX2 indicates a case in which a row block other than the end block is selected in the × 2 bit configuration. Indicates. Symbol SX4 indicates that an end block is selected in the × 4 bit configuration, and symbol SX2 indicates that an end block is selected in the × 2 bit configuration.

  Global IO bus GIO5 is coupled to data bus DB6 in the x8 bit configuration, and when a row block other than the end block is selected in the x4 bit configuration or the x2 bit configuration, and has a x4 bit configuration or x2 bit. When an end block is selected in the configuration, it is coupled to the data bus DB2.

  Global IO bus GIO6 is coupled to data bus DB3 in the x8 bit configuration, and is coupled to data bus DB2 when a row block other than the end block is selected in the x4 bit configuration or the x2 bit configuration. When the end block is selected in the × 4 bit configuration or the × 2 bit configuration, it is coupled to the data bus DB6.

  Global IO bus GIO7 is coupled to data bus DB7 in the x8 bit configuration, and is coupled to data bus DB6 when a row block other than the end block is selected in the x4 bit configuration or the x2 bit configuration, and x4 When the end block is selected in the bit configuration or the × 2 bit configuration, it is coupled to the data bus DB2.

  In FIG. 55, each global IO bus is shown coupled to the data bus by a mechanical switch. However, the selection signal for the read data driver in the internal read / write circuit described in the previous embodiment is switched or switched. The generation of a selection signal for the bus selector switches the connection between the global IO bus and the data bus.

  In the × 8 bit configuration, global IO buses GIO0 to GIO7 are coupled to data buses DB0 to DB7, respectively. This connection relationship related to the selection / non-selection of the end block is fixed. This is because the test is not performed in the x8 bit configuration in the multi-bit test mode (forcibly set to the x4 or x2 bit configuration).

  FIG. 56 shows a connection relationship between row blocks UR # 0-UR # 7 and global data buses GIO4-GIO7 in the upper row block shown in FIG. Row block UR # 0 is coupled to global IO buses GIO4 and GIO6 via a local IO bus. Row blocks UR # 1-UR # 7 are coupled to global IO buses GIO5 and GIO7 via corresponding local IO buses, respectively. Column selection lines CSLa and CSLb are arranged in common for row blocks UR # 0 to UR # 7. These transmit a column selection signal from a column decoder (not shown) to select a 2-bit memory cell.

  When a block other than the end block is selected in the × 4 bit configuration and the × 2 bit configuration, global IO buses GIO4 and GIO7 are coupled to data bus DB2, and global IO buses GIO5 and GIO6 are coupled to data bus DB6. Is done. When the end block, that is, row block UR # 0 is selected, global IO bus GIO4 is coupled to data bus DB6, and global IO bus GIO6 is coupled to data bus DB2. Therefore, data (6) from data bus DB6, that is, pad PPD6 is stored in the memory cell on column select line CSLa, and data bus DB2, that is, from pad PPD2 is stored in the memory cell on column select line CSLb. Data (2) is stored. Therefore, in the multi-bit test mode, it is possible to easily identify whether there is a memory cell defect along the column direction.

  In multi-bit test mode, data written from pad PPD6 is transmitted to data bus DB6 regardless of which of row blocks UR # 0 to UR # 7 is selected, and data written from pad PPD2 is data It is transmitted to the bus DB2, and it is possible to determine the logic match / mismatch. A plurality of column blocks are provided in parallel. Similarly, in each column block, data written from the same pad is read out to the same data bus. Therefore, in each column block, by determining whether the memory cells on the same column are good / bad, the distribution of defective memory cells in the column direction in each column block can be identified, and by replacement using redundant columns A defective memory cell can be repaired. The distribution of defective memory cells in the row direction can be easily identified for each row block. Thus, even when the data bus and the pad are provided in a one-to-one correspondence, and the coupling relationship between the data bus and the memory array row block differs depending on the position of the row block, the multi-bit test mode is used. It can be determined whether or not the defective column can be repaired.

  FIG. 57 schematically shows a structure of a bus connection switching control signal generation unit. 57, the bus switching control signal generator receives row address signal bits RA0 to RA2 (RA0-2) and outputs a signal φha indicating whether or not the designated row block is an end block. Circuit G101, inverter G102 for inverting the output signal of decode circuit G101, AND circuit G103 for receiving signal SX4 in response to end block instruction signal φha and × 4 bit configuration instruction signal SEL <4>, and end block designation The AND circuit G104 that receives the signal φha and the × 2 bit configuration instruction signal SEL <2> and outputs the signal SX2, and the output signal of the inverter G102 and the × 4 bit configuration instruction signal SEL <4> that receives the signal ZX4. The AND circuit G105 to output, the × 2 bit configuration instruction signal SEL <2>, and the output signal of the inverter G102 are received. AND circuit G106 for outputting signal ZX2, OR circuit G107 for receiving selection signals SELa in response to output signals SX4 and SX2 of AND circuits G103 and G104, and signals ZX4 and ZX2 from AND circuits G105 and G106 An OR circuit G108 that outputs a selection signal SELb is included. Select signals SELa and SELb are applied to an internal read / write circuit provided corresponding to each global IO bus of each column block.

  In the × 8 bit configuration, the end block instruction signal φha is not used. A signal x8 is generated from the x8-bit configuration instruction signal SEL <8>. By using the configuration shown in FIG. 57, the coupling relationship between the data bus and the global IO bus can be easily switched according to the selection / non-selection of the end block, and the connection shown in FIG. 55 is realized. Can do.

  As described above, according to the eighth embodiment of the present invention, the correspondence between the data bus provided in a one-to-one correspondence with the pad and the global IO bus is switched depending on whether or not the end block is selected. Therefore, it is possible to easily determine whether redundant replacement is possible using a multi-bit test.

  In the multi-bit test mode, whether the data bus is a × 4 data bus or a × 2 bit data bus is arbitrary.

  In the × 2 bit configuration and the × 4 bit configuration, which of the global IO buses is selected for data access can be easily determined by changing the number of bits of the column block selection signal according to the word configuration. Can do.

  Even if the word configuration is a × 32-bit configuration or a × 16-bit configuration, it can be easily realized by using the same configuration.

  In this × 8-bit configuration, as shown in FIG. 55, two and three circuit portions (read data drivers and bus selectors) for receiving selection signals are alternately arranged for each global IO bus. Therefore, the layout becomes easy.

  The present invention is applied to a semiconductor memory device capable of handling various word configurations with a single circuit layout, thereby realizing a semiconductor memory device capable of transferring internal data at high speed regardless of the word configuration. can do. In particular, by applying the present invention to a clock synchronous semiconductor memory device that operates in synchronization with a clock signal, a clock synchronous semiconductor memory device capable of transferring internal data at high speed can be realized.

1 schematically shows a structure of a main portion of the semiconductor memory device according to the first embodiment of the invention. FIG. FIG. 2 schematically shows a bus arrangement when the semiconductor memory device shown in FIG. FIG. 2 schematically shows a bus arrangement when the semiconductor memory device shown in FIG. FIG. 2 schematically shows a configuration of a column local circuit for one memory array in the semiconductor memory device shown in FIG. 1. It is a figure which shows an example of a structure of a selection signal generation part. It is a figure which shows schematically the structure of the example of a change of Embodiment 1 of this invention. FIG. 7 is a diagram more specifically showing a configuration of a main part of the semiconductor memory device shown in FIG. 6. FIG. 8 is a diagram illustrating a configuration example of a data bus control circuit illustrated in FIG. 7. FIG. 7 schematically shows a configuration of a control signal generation unit of the semiconductor memory device shown in FIG. 6. FIG. 10 is a timing chart showing the operation of the control signal generator shown in FIG. 9. FIG. 11 schematically shows a structure of a main portion of a semiconductor memory device according to the second embodiment of the present invention. FIG. 12 schematically shows a configuration of a control signal generation unit of the semiconductor memory device shown in FIG. 11. FIG. 13 is a timing chart showing an operation of the control signal generation circuit shown in FIG. 12. It is a figure which shows an example of a structure of the DQM buffer shown in FIG. FIG. 13 is a timing chart showing an operation during data writing of the control signal generation circuit shown in FIG. 12. It is a figure which shows the example of a change of the control signal generation circuit shown in FIG. FIG. 17 is a timing chart showing the operation of the circuit shown in FIG. 16. It is a figure which shows roughly the structure of the principal part of the semiconductor memory device according to Embodiment 3 of this invention. FIG. 19 is a diagram showing an example of an output signal during operation of the semiconductor memory device shown in FIG. 18. (A) shows the configuration of the internal readout circuit shown in FIG. 19, and (B) is a timing chart showing the operation thereof. FIG. 21 is a diagram illustrating a configuration of a preamplifier illustrated in FIG. 20. FIG. 21 is a diagram showing a configuration of a read data driver shown in FIG. FIG. 14 schematically shows a structure of a main portion of a semiconductor memory device according to the fourth embodiment of the invention. FIG. 24 is a timing chart showing an operation of the semiconductor memory device shown in FIG. 23. FIG. 24 is a timing chart showing an operation of the semiconductor memory device shown in FIG. 23. FIG. 24 is a diagram schematically showing a configuration of a circuit for generating a control signal shown in FIG. 23. (A) shows the configuration of the signal generation circuit shown in FIG. 26, (B) shows its operation, and (C) is a timing chart showing the operation of the circuit shown in (A). FIG. 24 schematically shows a configuration of a DQ control circuit shown in FIG. 23. FIG. 29 is a signal waveform diagram representing an operation of the DQ control circuit shown in FIG. 28. FIG. 24 is a diagram schematically showing a configuration of a gate circuit shown in FIG. 23. FIG. 31 is a signal waveform diagram representing an operation of the gate circuit shown in FIG. 30. FIG. 31 is a signal waveform diagram representing an operation of the gate circuit shown in FIG. 30. FIG. 24 schematically shows another configuration of the DQ control circuit shown in FIG. 23. FIG. 34 is a timing chart showing the operation of the circuit shown in FIG. 33. FIG. 34 is a timing chart showing the operation of the circuit shown in FIG. 33. FIG. 24 is a diagram showing a modification of the semiconductor memory device shown in FIG. 23. FIG. 37 is a timing chart showing the operation of the output circuit shown in FIG. 36. FIG. 10 schematically shows a structure of a main portion of a semiconductor memory device according to a fifth embodiment of the present invention. It is a figure which shows the structure of the input control circuit shown in FIG. FIG. 39 shows a structure of an internal write circuit shown in FIG. 38. 41 is a timing chart showing the operation of the circuit shown in FIGS. 38 to 40. FIG. It is a figure which shows schematically the structure of the example of a change of Embodiment 5 of this invention. FIG. 43 is a diagram schematically showing a configuration of a data bus selector shown in FIG. 42. It is a figure which shows roughly the structure of the principal part of the semiconductor memory device of Embodiment 6 of this invention. It is a figure which shows schematically the structure of the selection signal generation part in Embodiment 5 of this invention. FIG. 45 schematically shows a configuration of a read data driver included in the internal read / write circuit shown in FIG. 44. It is a figure which shows an example of the output data at the time of the multibit test in Embodiment 5 of this invention. FIG. 45 is a diagram showing a configuration of a determination circuit shown in FIG. 44. It is a figure which shows the structure of the control signal generation part shown in FIG. It is a figure which shows the pad arrangement | positioning of the semiconductor memory device according to Embodiment 7 of this invention. It is a figure which shows arrangement | positioning of the data bus in Embodiment 7 of this invention. It is a figure which shows schematically the structure of the example of a change of Embodiment 7 of this invention. FIG. 53 is a diagram showing a modification of the control signal generator shown in FIG. 52. It is a figure which shows roughly the structure of the array part of the semiconductor memory device of Embodiment 8 of this invention. It is a figure which shows roughly the correspondence of the global data bus | bath of Embodiment 8 of this invention, and a data bus. It is a figure which shows typically the operation | movement of the semiconductor memory device of Embodiment 8 of this invention. It is a figure which shows roughly the structure of the selection signal generation part in Embodiment 8 of this invention. 1 is a diagram schematically showing an entire configuration of a conventional semiconductor memory device. FIG. 59 is a diagram schematically showing a configuration of a selector / driver shown in FIG. 58.

Explanation of symbols

  DESCRIPTION OF SYMBOLS 1 Semiconductor memory device, 2, 2a-2d Memory array, 3, 3a-3d Column local circuit, 5a, 5b Output control circuit, PPD0, PPD1 pad, DB0, DB1 Data bus, 4aa-4dc Read data driver, 4x0-4xn , 4y0 to 4yn Read data driver, 6aa to 6dc Data bus control circuit, 7a and 7b Input / output control circuit, QT1 to QT4 MOS transistor, 6 Data bus control circuit, DBB, / DBB Data bus line, 7 Read data driver, 8 Write data driver, 60a, 60c Data bus control circuit, 35 DQM buffer, 30 # 0a-30 # na, 30 # 0b-30 # nb Read data drive circuit, 32 # 0-32 # n preamplifier, 34 # 0-34 #N CL Shifter, 4 # 0 to 4 # n Read data drive circuit, 32 preamplifier, 34 CL shifter, 4 # a, 4 # b Read data driver, 55 Data bus equalize circuit, 56 Read amplifier isolation gate, 57 Read amplifier, 58 Transfer Circuit, 59 output latch, 60 output buffer, 65 DQ control circuit, 70 equalize circuit, 71 # 0-71 # n data bus selector, 72 # 0-72 # n write amplifier, 74 # 0-74 # n write driver, 7 # 1, 7 # 0 input control circuit, 55 # 0, 55 # 1 data bus equalization circuit, 71a, 71b selection circuit, 73a amplification circuit, 73b write amplifier isolation gate, 30W internal write circuit, 30R internal read circuit, 85 judgment circuit, 86 transfer gate, PPD0 to PPD7 pad, DB 0, / DBB0~DBB7, / DBB7 data bus lines, UR♯0~UR♯7, LR♯0~LR♯7 row block, GIO0～GIO7 global IO bus, LIO0～LIO33 local IO bus.

Claims (4)

A data input circuit that takes in given data in synchronization with a clock signal, generates complementary internal data and transmits the data to a data bus, and the data bus includes a plurality of bus lines provided corresponding to a plurality of pads, respectively. Including pairs ,
A write amplifier that amplifies complementary data of the data bus when activated,
A write driver for transmitting output data of the write amplifier to a selected memory cell ;
A bus selection gate for connecting one of the plurality of bus line pairs to the write amplifier according to word configuration information indicating the number of pads used among the plurality of pads; and
A semiconductor memory device comprising a sense gate that is connected in series with the bus selection gate between the bus selection gate and the write amplifier, and separates the write amplifier and the bus selection gate during an amplification operation of the write amplifier. . A read data driver for transmitting read data to the data bus at the time of data reading;
The data reading, further comprising, a semiconductor memory device according to claim 1, wherein a circuit for setting the bus selection gate in a non-conductive state. A determination circuit for determining whether or not the logic of the data of the bus line pair of the data bus is the same at the time of the multi-bit test mode,
The transfer gate and provided in parallel, the multi-bit test mode, the complementary signal of the decision circuit further comprises a second transfer gate for transferring to the read amplifier, a semiconductor memory device according to claim 1, wherein. A plurality of read data drivers are commonly coupled to the data bus, and each of the read data drivers is in an output high impedance state when inactive, and drives the data bus according to the data read when activated. In addition, in the multi-bit test mode, a drive element for driving the data bus to a voltage level different from the equalize voltage of the data bus is activated according to the read data, and the data to the same voltage level as the equalize voltage 4. The semiconductor memory device according to claim 3 , wherein a drive element for driving the bus is disabled.

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