JP4397764B2 - Manufacturing method of semiconductor device - Google Patents

Description

  The present invention relates to a method for manufacturing a semiconductor element, and more particularly to a method for manufacturing a semiconductor element including a zinc oxide (ZnO) semiconductor layer.

  In recent years, development of transistors and the like in which a semiconductor film such as zinc oxide (ZnO) is formed has been promoted. A semiconductor on which a ZnO film is formed can be expected to have higher mobility than an amorphous silicon semiconductor.

Conventionally, fine processing of a ZnO film is performed by etching using a photoresist patterned on the ZnO film as a mask. Alternatively, the method disclosed in Patent Document 1 can be applied. That is, the patterned photoresist is processed into an overhang shape by dry etching, and a ZnO thin film is formed on the surface of the resist and the substrate surface. Thereafter, the resist is peeled off and eliminated by side etching (lift-off) to remove the ZnO thin film on the resist and form a desired pattern on the substrate. However, the process disclosed in Patent Document 1 has a large number of steps and low production efficiency.
JP-A-4-364726

  On the other hand, wet etching can be applied to fine processing of the ZnO film. An etch rate suitable for processing (for example, approximately 50 nm to approximately 100 nm / min) can be achieved using a weak acid such as 0.5 wt% acetic acid and 0.05 wt% phosphoric acid.

  10- (a) to (d) are plan views for explaining the step of etching the ZnO layer, and FIGS. 11- (a) to (d) are respectively E in FIGS. 10 (a) to (d). It is sectional drawing which follows the -E 'line. The wet etching proceeds as shown in FIGS. 10- (a) to (d) and FIGS. 11- (a) to (d). At this time, the peripheral portion of the pattern edge is etched extremely fast. That is, in the state in which a ZnO layer is formed on a substrate having a layer wiring pattern formed on the upper surface, and a mask is patterned on the ZnO layer (FIGS. 10A and 11A), Etching of the ZnO layer is started by the etching solution. At this time, although details will be described in detail in the embodiment of the present application, since the peripheral portion of the pattern edge is etched extremely fast, only the region corresponding to the pattern edge of the ZnO layer is first completely etched (FIG. 10-). (B), FIG. 11- (b)). Next, in the etching region, etching proceeds from around the pattern edge, and at the same time, an etchant enters from the side of the pattern edge, and side etching of the mask portion proceeds (FIGS. 10C and 11C). Then, as shown in FIGS. 10- (d) and 11- (d), when the ZnO layer in the etching region is finally removed, there is a problem that the side surface of the ZnO layer in the mask portion is significantly etched. there were.

  The present invention has been made in view of the above circumstances, and an object thereof is to provide a method of manufacturing a semiconductor element in which side etching of a semiconductor film is suppressed.

In order to achieve the above object, a method of manufacturing a semiconductor device according to the first aspect of the present invention includes:
A semiconductor film containing zinc oxide is formed on the substrate as a film to be etched,
A plurality of masks each having a width narrower than a width disappeared by side etching generated when the etching target film is etched are formed in the removal target region of the etching target film, and the remaining target of the etching target film is formed. Forming a mask of a pattern having a size larger than the width disappeared by side etching and having an area smaller than the removal target region of the etching target film in the region;
Etching in the width direction of the etching target film using the plurality of masks and the mask of the pattern as an etching mask and having a concentration of 0.05 wt% to 0.5 wt% in the thickness direction of the etching target film. A predetermined pattern is formed in the remaining target region by etching using acetic acid or phosphoric acid at a concentration that increases the speed, and the etching target film in the removal target region is removed, and the plurality of masks are peeled off. To
It is characterized by that.

According to this method, the etching rate at the edge of the mask is remarkably higher (twice or more) than other parts, and the etching in the thickness direction of the film to be etched around the mask is promoted. The etching target film in the region where the mask is formed can be removed, and the mask can be peeled off and lost. Therefore, the etching target film in the region where the pattern mask is formed can be suppressed to a range in which the amount of side etching is allowed.

The plurality of masks are preferably formed to have a width less than twice the amount of side etching that occurs when an etching target film having a predetermined pattern is formed in the remaining target region.

In the above case, a plurality of masks, be formed to have a minimum of two times with an adjacent mask allowable amount of side etching is desirable.

A plurality of masks, it is further desirable to be spaced from the mask adjacent in the width and same distance.

The plurality of masks may be formed to alternately repeat two different patterns.
The plurality of masks may be formed to repeat a certain pattern.
The plurality of masks may be formed such that a plurality of elongated masks adjacent to each elongated mask are arranged in a rectangular shape.

  The plurality of masks may be formed so as to be connected to each other to form a continuous mask region.

  ADVANTAGE OF THE INVENTION According to this invention, the manufacturing method of the semiconductor element with the high patterning precision by which side etching was suppressed can be provided.

  A method for manufacturing a semiconductor device according to an embodiment of the present invention will be described below with reference to the drawings.

  A zinc oxide (ZnO) layer 3 having a thickness of about 100 nm is formed on a glass substrate 2 having other layers (not shown) on which electrodes and wirings are formed by magnetron sputtering using high-purity Zn as a target.

  A photoresist solution containing a known resist material is applied on the ZnO layer 3 and exposed and developed to obtain the semiconductor element 1 on which the mask pattern shown in FIG. 1 is formed.

  As shown in the figure, a mask 4 is formed over the entire region where the ZnO layer 3 remains. On the other hand, a plurality of elongated rectangular masks 5 are also formed in a staggered pattern in the region where the ZnO layer 3 is removed. That is, the rectangular masks 5 in other rows or columns adjacent to one row or column are formed to have the same arrangement.

  The rectangular mask 5 is formed so that its width is less than twice the side etch amount and its interval is two to three times the side etch amount, preferably substantially the same as the mask width. Here, the side etching amount is a depth at which the ZnO layer 3 covered with the mask 4 and forming a predetermined pattern is side-etched from one side surface.

  The exposed ZnO layer 3 of the semiconductor element 1 is etched using 0.1 wt% weak acid such as acetic acid or phosphoric acid. At this time, as shown in FIG. 2, the vicinity of the pattern mask end portion has a remarkably high etching rate, and is faster, that is, selectively etched as compared with other etching regions. When 0.1 wt% phosphoric acid is used, an etching rate of 8.0 nm / second is obtained at the periphery of the pattern mask, and a speed of 2.7 nm / second is obtained in the other etching regions.

  Thus, as shown in FIG. 3, first, the ZnO layer 3 is completely etched in the vicinity of the end portions of the mask 4 and the rectangular mask 5.

On the other hand, the weak acid also penetrates from the side surface of the ZnO layer 3 under the rectangular mask 5 and side-etches the penetrated ZnO layer 3. As shown in FIG. 4, when 0.1 wt% acetic acid is used, the side etch amount becomes 0.5 μm 10 seconds after the start of etching and 1.5 μm after 20 seconds. That is, while the etching rate from the top is 0.2 μm / min, the etching rate from the side is remarkably high at 6 μm / min, and etching using weak acid such as 0.1 wt% acetic acid is from the top. The etching rate and the etching rate from the side are greatly different .

Therefore, ZnO layer 3 to be removed, the error etching rate is removed by etching from the faster side than the etching rate of the thickness direction. That is, as shown in FIG. 5, the rectangular mask 5 is peeled off and lifted off by etching from the side surface of the underlying ZnO layer 3. At this time, since the removal target ZnO layer 3 is removed in a shorter time than in the case where the rectangular mask 5 is not disposed, the side etch amount of the remaining target ZnO layer 3 is reduced as compared with the conventional case.

As described above, a plurality of elongated rectangular masks 5 are formed in the region where the ZnO layer 3 is to be removed, and the etching of the ZnO layer 3 in the vicinity of the end portion is promoted, and the ZnO layer 3 below the rectangular mask 5 is formed. The rectangular mask 5 is lifted off by etching from the width direction . Therefore, a high etching rate of the pattern around the edges is applied to the entire ZnO layer 3 to be removed, which by the Rie etching is promoted. Therefore, the etching time can be shortened to suppress the side etching of the ZnO layer 3 to be left, and the etching unevenness can be suppressed. Further, the rectangular masks 5 can be easily removed by making the width of the plurality of rectangular masks 5 correspond to the amount of side etching that occurs when the ZnO layer 3 having a predetermined pattern is formed in the remaining target region. .

  The present invention is not limited to the above embodiment, and its application, modification, and the like are arbitrary.

In the above embodiment, the rectangular mask 5 has been described as being formed in a staggered pattern, but is not limited thereto, and may be formed in a striped pattern as shown in FIG. Alternatively, as shown in FIG. 7, the rectangular mask may be formed in a lattice shape, that is, a plurality of rectangular masks surrounding each rectangular mask may be arranged at lattice points forming a rectangle. Further, as shown in FIG. 8, the mask of the region from which the ZnO layer 3 is removed may be formed as a continuous region having openings formed with the above width and interval.
In FIG. 6, the rectangular mask is formed so as to be continuous in the row or column direction, but a plurality of rectangular masks may be arranged linearly apart from each other.

In the above embodiment, it has been described that a plurality of rectangular masks 5 are formed in the entire region from which the ZnO layer 3 is removed. However, as shown in FIG. It may be formed in the part. In this case, the ZnO layer 3 in the region where the rectangular mask is disposed is completely removed by etching in the width direction, while the ZnO layer 3 in the other region where the rectangular mask is not formed is also etched in the thickness direction and lateral direction. It can be completely removed.

  In the above embodiment, 0.1 wt% acetic acid or phosphoric acid is used as the weak acid. However, the concentration is not limited to 0.1 wt%, for example, in the concentration range of 0.05 wt% to 0.5 wt%. Can be used. In addition to acetic acid or phosphoric acid, other acids having a low ionization degree can be used.

  In the above embodiment, it has been described that the ZnO layer is formed by magnetron sputtering. However, the ZnO layer is not limited to magnetron sputtering, but may be formed by other methods such as molecular beam epitaxy or metalorganic vapor phase epitaxy.

  In the above embodiment, it has been described that the substrate on which the ZnO layer to be patterned is formed is composed of a glass substrate. However, in the present invention, ZnO formed on a substrate such as a Si substrate, a GaAs substrate, or a plastic substrate is used. Can be applied to layers. Furthermore, the present invention is not limited to the ZnO layer, but can be applied to other semiconductor layers made of, for example, ZnMgO, AlZnO, or the like. The present invention can also be applied to insulating layers other than semiconductor layers.

It is a figure which shows the mask pattern of the semiconductor element which concerns on embodiment of this invention. (A) is a top view of a semiconductor element. (B) is sectional drawing of a semiconductor element. It is a figure which shows the measurement result of the etching amount of a mask peripheral part. It is a figure which shows typically the etching state of the mask vicinity. (A) is a top view. (B) is sectional drawing. It is a figure which shows typically the advancing state of the side etching of the mask vicinity. (A) is a top view. (B) is sectional drawing. It is a figure which shows the semiconductor element at the time of completion | finish of an etching. (A) is a top view of a semiconductor element. (B) is sectional drawing of a semiconductor element. It is a figure which shows the other mask pattern of the semiconductor element which concerns on embodiment of this invention. (A) is a top view of a semiconductor element. (B) is sectional drawing of a semiconductor element. It is a figure which shows the other mask pattern of the semiconductor element which concerns on embodiment of this invention. (A) is a top view of a semiconductor element. (B) is sectional drawing of a semiconductor element. It is a figure which shows the other mask pattern of the semiconductor element which concerns on embodiment of this invention. (A) is a top view of a semiconductor element. (B) is sectional drawing of a semiconductor element. It is a figure which shows the other mask pattern of the semiconductor element which concerns on embodiment of this invention. (A) is a top view of a semiconductor element. (B) is sectional drawing of a semiconductor element. It is a top view which shows the conventional mask pattern and the etched semiconductor element. It is sectional drawing which shows the conventional mask pattern and the etched semiconductor element.

Explanation of symbols

DESCRIPTION OF SYMBOLS 1 Semiconductor element 2 Glass substrate 3 Zinc oxide (ZnO) layer 4 Mask 5 Rectangular mask

Claims (8)

A semiconductor film containing zinc oxide is formed on the substrate as a film to be etched,
A plurality of masks each having a width narrower than a width disappeared by side etching generated when the etching target film is etched are formed in the removal target region of the etching target film, and the remaining target of the etching target film is formed. Forming a mask of a pattern having a size larger than the width disappeared by side etching and having an area smaller than the removal target region of the etching target film in the region;
Etching in the width direction of the etching target film using the plurality of masks and the mask of the pattern as an etching mask and having a concentration of 0.05 wt% to 0.5 wt% in the thickness direction of the etching target film. A predetermined pattern is formed in the remaining target region by etching using acetic acid or phosphoric acid at a concentration that increases the speed, and the etching target film in the removal target region is removed, and the plurality of masks are peeled off. A method for manufacturing a semiconductor device, characterized in that: The plurality of masks are formed to have a width less than twice the amount of side etching that occurs when an etching target film having a predetermined pattern is formed in the remaining target region. A method for manufacturing a semiconductor device. It said plurality of masks, The method according to claim 2, characterized in that it is formed to have a minimum of two times with an adjacent mask the allowable amount of side etching. It said plurality of masks, the method of manufacturing a semiconductor device according to claim 2, characterized in that it is formed spaced apart from the mask adjacent in the width and same distance.   The method of manufacturing a semiconductor device according to claim 1, wherein the plurality of masks are formed so as to alternately repeat two different patterns.   2. The method of manufacturing a semiconductor device according to claim 1, wherein the plurality of masks are formed to repeat a certain pattern.   2. The method of manufacturing a semiconductor device according to claim 1, wherein the plurality of masks are formed such that a plurality of masks adjacent to each mask are arranged in a rectangular shape.   The method of manufacturing a semiconductor device according to claim 1, wherein the plurality of masks are connected to each other to form a continuous mask region.

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