JP4398965B2 - Data setting device in SIMD processor - Google Patents

Description

  The present invention relates to a single instruction-stream multiple data-stream (SIMD) type microprocessor that performs the same processing on a plurality of data with the same instruction in order to process image data and the like at high speed.

  In recent years, in image processing such as digital copying machines and facsimile machines, image quality has been improved by increasing the number of pixels and diversifying image processing. In such image processing, the same processing is often performed simultaneously on a plurality (many) of data. At this time, in order to improve the high speed, a single instruction-single instruction-simulation (single instruction-stream) single-stream data (SIMD) type microprocessor that processes one piece of data at a time, rather than a single instruction-stream single data-stream (SISD) type microprocessor. -Stream (Multiple Data-stream) type microprocessor is often used.

  FIG. 1 is a block diagram showing a schematic configuration of a general SIMD type microprocessor 2. The SIMD type microprocessor 2 is roughly composed of a global processor (hereinafter referred to as GP) 4 and a processor element 3, and a plurality of processor elements 3 are used to process a plurality of data at a time. Equipped with pieces. Each processor element 3 includes a register file 6 and an operation array 8. The GP 4 controls the entire processor 2, and the processor element 3 inputs data from the external input / output device, performs data processing, and outputs the data to the external input / output device.

  The SIMD type microprocessor 2 normally processes one instruction in one clock cycle, but can process data for the number of processor elements 3 at one time with one instruction. When expressing the performance of the SIMD type microprocessor 2, the operating frequency of the SIMD type microprocessor 2 and the number of processor elements 3, that is, the number of data that can be processed by one instruction, are emphasized. Number is also an important factor. In other words, as long as the same image processing is performed, the performance is better when the number of instruction cycles is small. However, in order to perform complicated processing with one instruction, if a complicated circuit is designed and used, the cost inevitably increases.

  It is an object of the present invention to reduce the number of instruction execution cycles of instructions associated with image data processing as described above by providing effective instructions and simple means for realizing the instructions.

The present invention has been made to achieve the above object. According to the first aspect of the present invention, there is provided a SIMD type microprocessor.
A global processor for overall control and a SIMD type microprocessor including a plurality of processor elements ,
Each processor element is given an integer number for identification, in order,
Each processor element
A connection line to which an integer number for identification attached to the processor element is input from the outside;
A mask circuit in which a logic circuit for receiving a mask control signal from the global processor is inserted into the connection line;
A SIMD type microprocessor having

  By utilizing the present invention, it is possible to reduce the number of instruction execution cycles for instructions associated with image data processing. Therefore, the circuit that needs to be added is only a simple one.

  DESCRIPTION OF THE PREFERRED EMBODIMENTS Preferred embodiments according to the present invention will be described below with reference to the drawings.

  FIG. 1 is a block diagram showing a schematic configuration of a general SIMD type microprocessor 2 including the present invention. From a global processor (hereinafter referred to as GP) 4 that mainly controls the entire processor 2, and a processor element 3 that mainly inputs data from an external input / output device, performs data processing, and outputs data to the external input / output device. Composed. A plurality of processor elements 3 are prepared for simultaneously processing a plurality of data. In FIG. 1, a SIMD type microprocessor 2 is configured by one GP 4 and 256 processor elements 3.

FIG. 2 is a block diagram showing a more detailed configuration of the SIMD type microprocessor 2 according to the present invention. As shown in the figure, GP4 is
A program RAM 10 for storing a program composed of instruction codes;
A data RAM 12 for storing calculation data in GP4;
A sequential unit (SCU) 9 that decodes the program and sends various control signals to various blocks;
A plurality of general purpose registers (G0 to G3) for storing data;
A program counter (PC) 14 that holds the address of the program to send the instruction code of the program to the SCU 9;
A stack pointer (SP) 24 for storing the address of the data memory in order to form a stack in the data memory;
-When performing subroutine processing in the middle of a program, a branch occurs, but a plurality of link registers (LS, LI, LN) for storing addresses before branching;
An arithmetic and logic unit (ALU) 11 that performs an arithmetic and logical operation on any combination of data in data memory, numeric (immediate) data described in an instruction code, or data stored in a general-purpose register;
A processor status register (not shown) that holds the state of the processor;
An interrupt control circuit (not shown) for controlling hardware interrupts and software interrupts;
An external I / O control circuit (not shown) that is directly connected to the external input / output and controls the input / output of data from the outside.

  Although not shown in FIG. 2, the SCU 9 decodes the GP instruction and generates a control signal mainly in each block in the GP, and decodes the processor element instruction and mainly in each block in the processor element. And a processor element instruction decoder for generating a control signal. That is, the instruction code related to this processor is a GP instruction that mainly controls each block in GP4, determines a program sequence, and processes common data to be transferred to processor element 3 by ALU11 in GP4. These are classified into processor element instructions for processing data input at a time from the external input / output for each processor element 3.

  As shown in FIG. 1, each processor element 3 includes a register file 6 that temporarily holds input / output data from the outside, and an operation array for performing data processing of arithmetic logic operations and bit operations in the processor element 3. 8 is included. Further, as shown in FIG. 2, the register file 6 includes 32 8-bit registers 34 from R0 to R31, for example. Data is transferred from these registers 34 to the operation array 8, and conversely, data is transferred from the operation array 8 and stored in the register 34. The bus between the register 34 and the arithmetic array 6 is an 8-bit bidirectional bus.

Further, as shown in FIG. 2, the single arithmetic array 8 is an arithmetic unit,
A shift / extension unit 44 that shifts data from the register file 6 to perform signed extension or unsigned extension to process the data into 16-bit data;
For example, a plurality of general purpose registers such as A register 36 and F register 40,
An arithmetic logic unit (ALU) 36 that processes the data from the register file 6 via the shift / extension unit 44 to make one input and the other input from the A register 36;
The outputs from the PE number mask circuit, fixed value selection circuit, and n-th bit pattern data output circuit according to the present invention are input to the A register 38 and the T register 54 (described later). And a selection circuit 35 to be connected. The output of the arithmetic logic unit (ALU) 36 is set so as to be temporarily stored in the A register 36 or the F register 40, but data is transferred from the A register 36 to a predetermined one register 34 of the register file 6. Is also possible.

  The arithmetic array 8 includes an arithmetic control register 54 called “T register” as will be described later. The output from the ALU 36 is controlled by the T register 54 to be written to the A register 36 or the F register 40. For example, according to the state of a predetermined 1 bit in the arithmetic control register (T register) 54, if “1”, writing to the A register 36 or the F register 54 is performed, and if “0”, it is not performed. Such control is performed.

  FIG. 3 is a block diagram showing the function of the multiplexer that connects the register 34 of the register file 6 and the operation array 8. The multiplexers provided in the processor elements of PEi (i = 0, 1, 2,... 255) are 7 to 1 (7 to 1) multiplexers, PEi-3 (3 left neighbors of PEi), PEi-2 (PEi 2), PEi-1 (next to the left of PEi), PEi, PEi + 1 (next to the right of PEi), PEi + 2 (2 to the right of PEi), PEi + 3 (3 to the right of PEi) It is set so that data from the register file 6 of the processor element 3 can be input / output. This function is referred to as a PE shift function. The data selected by the multiplexer is transferred to the shift / extension unit 44 of the arithmetic array 8.

  Here, a name including the number of the processor element 3 is defined. As shown in FIG. 2, the SIMD type microprocessor 2 according to the present invention is provided with 256 processor elements 3, and each of the processor elements 3 (from the left side in the figure) PE0, PE1, PE2 , PE3,..., PE254, PE255, and so on, are defined as processor element numbers (PE numbers).

<< First Embodiment >>
FIG. 4 is a circuit diagram of a PE (processor element) number mask circuit according to the first embodiment of the present invention. In the PE number mask circuit, a logic circuit that takes in a mask control signal (ie, PE number mask signal) from GP4 is inserted into a connection line for inputting a PE number (which is a prior art) to a predetermined general-purpose register. It is formed by. As will be described later, in the circuit configuration of FIG. 4, masking is performed with “0”.

  In each PEi (i = 0, 1, 2,... 255), a connection line unit 50 that forms each PE number and a logic circuit (AND circuit) unit 51 that captures a PE number mask signal are combined and installed. Has been. The output from there is connected to a selection circuit 35 (see FIG. 2) installed for each processor element 3, as will be described later. The output is stored in the A register 38 through the selection circuit 35, for example.

  It has been possible in the past to set the PE number in the A register 38 by using the connecting line portion 50 that forms each PE number (which is a conventional technique). For example, it is assumed that the above function is realized by executing an instruction “LDPN” (Load PE Number). Here, even with the circuit according to the first embodiment of the present invention, the same function is realized, that is, the transmission of each PE number to each selection circuit 35 is realized by using the instruction “LDPN”. Can be set to As is apparent from FIG. 4, the PE number mask signal when the LDPN instruction is used (8 bits) is all “1”. With this setting, data representing the PE number in a pattern formed by VCC and GND is input to the selection circuit 35 of each processor element 3.

Specifically, the data input to the selection circuit 35 is
-PE0, PE1, PE2, ... PE255 in this order
・ 0, 1, 2, ... 255
It becomes the value of.

  Furthermore, in the circuit according to the first embodiment of the present invention, the input data can be masked by setting the bit designated by the instruction to the SIMD type microprocessor 2 to “0”. As an instruction for performing such processing, an “LDNM” (Load PE Number Masking) instruction is prepared. The LDNM instruction masks output data by designating a mask pattern with an immediate value. The immediate value is taken into the circuit of FIG. 4 as a PE mask signal. The LDNM instruction is described as follows.

  LDNM / 0 # 00000011b

  In the above description, “b” at the end of “00000011b” indicates binary notation. In the above instruction, the output values from bit 3 to bit 7 of the PE number are masked. “/ 0” is an optional description representing a mask by “0”.

Therefore, the data input to each selection circuit 35 is
-PE0, PE1, PE2, PE3, PE4, PE5, PE6, ... PE254, PE255 in this order,
・ 0, 1, 2, 3, 0, 1, 2, ... 2, 3
It becomes the value of.

  In the circuit according to the first embodiment of FIG. 4, an AND circuit is used, but it may be assumed that this is replaced with an OR circuit. That is, in each PEi (i = 0, 1, 2,... 255), a connection line portion 50 that forms each PE number and a logic circuit (OR circuit) portion that captures a PE number mask signal (not shown). Will be installed in combination. At this time, in the circuit configuration described above (FIG. 4), masking is performed with “0”. However, in the case of a circuit that is replaced with an OR circuit, masking with “1” is performed. The instructions are written as follows:

  LDNM / 1 # 11111100b

  In the above description, the input values from bit 3 to bit 7 of the PE number are masked with “1”. / 1 is an optional description representing a mask by “1”.

At this time, the data input to each selection circuit 35 is:
-PE0, PE1, PE2, PE3, PE4, PE5, PE6, ... PE254, PE255 in this order,
252 (11111100b), 253 (11111101b), 254 (11111110b), 255 (11111111b), 252, 253, 254, ... 254, 255
It becomes the value of.

By using the circuit according to the first embodiment of the present invention shown in FIG. 4, a control line corresponding to a bit of “0” is masked by a mask control signal (PE number mask signal), and a predetermined value is masked. It is possible to set (form) data represented by only this bit and having repetitive regularity with one instruction. For example, by masking all the upper 6 bits, only the lower 2 bits are valid, and for each selection circuit 35 of the processor element 3 of PE0, PE1, PE2, PE3, PE4, PE5, PE6,.
・ 0, 1, 2, 3, 0, 1, 2, 3, ...
It is possible to output a repeated value with regularity in one instruction. In the circuit of FIG. 4, even if all the AND circuits are OR circuits, the rules for the selection circuits 35 of the processor elements 3 of PE0, PE1, PE2, PE3, PE4, PE5, PE6,. It is possible to output a repeated value with a single instruction. However, at this time, the mask is made by “1”.

When using the prior art, if the PE number is once set in the A register 38 by the LDPN instruction, and the remainder when the value of the A register 38 is divided by 4 is also set in the A register 38, the same as in FIG. Result is obtained. But,
・ One instruction cycle with LDPN instruction
-1 instruction cycle with division instruction (assuming there is a multiplier / divider)
A total of two instruction cycles are required. However, if the multiplier / divider is set in all the processor elements 3 of the SIMD type microprocessor 2, an enormous circuit scale is required. Since a multiplier / divider is not set in the normal SIMD type microprocessor 2, division is performed by subtracting up to the number of bits of the dividend using the ALU 36. If the A register 38, which is a general-purpose register, is 16 bits, for example, subtraction is required at least 16 times (actually, setting before division requires several instruction cycles). Here, it takes 16 instruction cycles, and the total is 18 instruction cycles at the shortest.

  As is apparent from the above, a considerable number of instruction cycles can be reduced by the circuit according to the first embodiment of the present invention.

<< Second Embodiment >>
FIG. 5 is a circuit diagram of a fixed value selection circuit according to the second embodiment of the present invention. The fixed value selection circuit has a cycle variation every n (n is a natural number), and inputs a numerical value monotonously increasing from 0 to 1 within one cycle to the selection circuit 35 (described later). It is a circuit that outputs under the selection control by. In the circuit shown in FIG. 5, 3, 5, and 7 are assumed as the value of n.

As shown in FIG. 5, each processor element 3 includes a separate connection line portion 50 ′ and a multiplexer portion 51 ′. The connecting line section 50 'generates a 9-bit signal, but the left 2 bits have periodic fluctuations every "3", and the middle 3 bits have periodic fluctuations every "5". The connection lines are set so that the 4 bits have periodic fluctuations every "7". As is apparent from FIG. 5, every third periodic variation is
・ PE0, PE1, PE2, PE3, PE4, PE5, PE6, ...
・ 0, 1, 2, 0, 1, 2, 0, ...
It becomes. Periodic fluctuation every 5th
PE0, PE1, PE2, PE3, PE4, PE5, PE6,. . . In the order
・ 0, 1, 2, 3, 4, 0, 1, ...
It becomes. Periodic fluctuation every 7th
-PE0, PE1, PE2, PE3, PE4, PE5, PE6, PE7, PE8,.
・ 0, 1, 2, 3, 4, 5, 6, 0, 1, ...
It becomes.

  Which period variation output is selected is given by an input value selection signal. The input value selection signal gives an instruction to the multiplexer unit 51 ′ in each processor element 3. The next instruction “LDRN” (Load Repeating Number) is set as an instruction related to the above-described extraction of the period variation.

  LDRN # 3

  In the above-described instruction, the selection circuit 35 of each processor element 3 has a period variation every third, and a numerical value that increases monotonically from 0 to 2 within one period follows the order of PE numbers of the processor element 3. Will be output.

  If the fixed value selection circuit according to the second embodiment of the present invention shown in FIG. 5 is used, the numerical value input to the selection circuit 35 (A register 38) as described above is performed in one instruction cycle. Can do. Here, it is known that the numbers 3, 5, and 7 shown in the above example are values that are frequently used in image processing.

<< Third Embodiment >>
FIG. 6 is a circuit diagram of an n-th bit pattern data output circuit according to the third embodiment of the present invention. The n-bit bit pattern data output circuit inserts a logic circuit that takes in a bit mask signal from GP4 to a connection line that sets “1” every n (in the order of PE numbers) in individual bits. It is formed.

  In each PEi (i = 0, 1, 2,... 255), a connection line portion 50 for setting every n to “1” in each bit and a logic circuit (AND circuit) portion for taking in a bit mask signal 51 ″ are installed in combination. The output from there is connected to a selection circuit 35 (see FIG. 2) installed in each processor element 3 in the same manner as the circuit according to the first embodiment and the circuit according to the second embodiment. The output is stored in the A register 38 through the selection circuit 35, for example.

Each PEi connection line section 50 "includes 8 individual bits. For example, bit 0 is" every 2 ", bit 1 is" every 3 ", bit 2 is" every 5 ", and bit 3 is" every 7 ". , Bit 4 is “every 11”, bit 5 is “every 13”, bit 6 is “every 17”, and bit 7 is “every 23”. If each bit has a PE number corresponding to each periodic characteristic, the connection line portion 50 ”of each PEi is set so that the bit is“ 1 ”(that is, the corresponding bit is connected to the VCC). (FIG. 6) That is,
Bit 0 having every other periodic characteristic is PE0, PE2, PE4, PE6, PE8,.
-Bit 1 having periodic characteristics of every third is PE0, PE3, PE6, PE9, PE12, ...
Bit 2 having periodic characteristics every 5 is connected to VCC at PE0, PE5, PE10, PE15, PE20,.

  The next instruction “LDRB” (Load Repeating Bit) is prepared as an instruction relating to the extraction of the setting contents of the connection line portion 50 ″ of each PEi set as described above.

  LDRB

By this instruction, all the setting contents of the connection line portion 50 ″ of each PEi are input to, for example, the selection circuit 35 (or the A register 38).
-PE0, PE1, PE2, PE3, PE4, PE5, PE6, PE7, PE8, PE9, PE10, PE11,.
11111111b (binary notation; the same applies hereinafter), 00000000b, 00000001b, 00000010b, 00000001b, 00000100b, 00000011b, 00001000b, 00000001b, 00000110b, 00000001b, ...
It becomes.

  However, as described above, since the logic circuit for taking in the bit mask signal from GP4 is inserted into the connection line, the selection circuit 35 is set by setting the bit specified in the instruction code to “0”. Input data to (or A register 38) may be masked. When performing the mask processing, the instruction is described as follows. The mask pattern is designated as an immediate value and is taken into the circuit of FIG. 6 as a bit mask signal to mask input data to the selection circuit 35 (or A register 38).

  LDRB / 0 # 00000100b

In the above instruction, only the output data related to the PE in which “1” is set in bit 2 has a numerical value of “00000100b”. For example, “00000100b” is set in the A register 38.
PE0, PE5, PE10, PE15, PE20,. . .
It is. For other PEs, the value is “00000000b”.

  In the n-bit bit pattern data output circuit according to the third embodiment, the numerical value input to the selection circuit 35 (A register 38) as described above can be performed in one instruction cycle.

<< Fourth Embodiment >>
A SIMD type microprocessor 2 according to a fourth embodiment of the present invention will be described.

  In the “LDPM” instruction according to the first embodiment of the present invention, when the immediate value (PE number mask signal) is a numerical value (# 11111111b) that does not mask all, the PE number is directly selected by the selection circuit 35 (or A register 38). Is input. In addition, as described above, the PE number is not changed by using the connection line for inputting the PE number to a predetermined general-purpose register or the like without inserting a logic circuit for taking in the PE number mask signal from GP4. The data is input to the selection circuit 35 (or A register 38).

Therefore, the selection circuit 35 includes
-PE0, PE1, PE2, ... PE255 in this order
・ 0, 1, 2,. . . 255
The value of is entered.

  In each processor element 3, the value input to the selection circuit 35 is compared with the immediate value specified by the instruction (to the SIMD type microprocessor 2) in the comparator 80 (FIG. 7) provided in the selection circuit 35. The result is stored in a bit at a predetermined position of the T register (arithmetic control register) 54. By storing the result in the T register 54, the calculation after the next instruction is performed only in one specific processor element 3 among the 256 processor elements 3, and the other processor elements 3 are not operated. You can set it.

  FIG. 7 shows a schematic circuit block diagram of the selection circuit 35 according to the present invention. Output data from the PE number mask circuit, the fixed value selection circuit and the n-th bit pattern data output circuit shown in FIGS. 4, 5, and 6 is connected to the selection circuit 35 in the arithmetic array 8 shown in FIG. The input data selection signal 2 which is a control signal from the GP 4 is selected by the multiplexer 78, and one of the three data is input to the A register 38. Also, the selected 1 data is compared with the immediate data IMM2 in the instruction code by the comparator 80, and when the result is coincident, “1” is output. If they do not match, “0” is output.

  Here, the T register 54 according to the present invention will be described. As shown in FIG. 2, each processor element 3 is equipped with an operation control register (T register) 54 for specifying an execution condition. FIG. 8 is an example of a circuit block diagram of the T register 54. In FIG. 8, the T register 54 includes 8-bit registers (T0, T1,... T7), and each 1-bit register is controlled separately. Therefore, eight control patterns can be held by one processor element 3.

  Each bit in the T register 54 can be controlled to invalidate / validate the execution of the operation of each processor element 3 and to select only a specific processor element 3 as an operation target. For example, the following instructions are assumed.

  ADD / T1 # 12

  This instruction is an addition instruction, the value of the A register 38 and the immediate value “12” are added, and the result is stored in the A register 38. In this instruction, by describing the execution control option “/ T1”, only the processor element 3 whose T1 (bit) flag value is “1” in the T register 38 is sent from the ALU 36 to the A register 38. Data is stored. Data is not stored in the A register 54 of the processor element 3 whose T1 flag is “0”.

In the example of FIG. 8, the input to the T register 54 is
An input from the overflow flag (V) and carry flag (C) generated in the ALU 36 of the arithmetic unit 6 in the PE 3
-Input from the result of OR operation to the result of mask operation by immediate value IMM2 to all T flags,
Input from the storage means 2 shown in FIG.
The input from the comparator 80 output in the selection circuit 35 in FIG.

  According to the SIMD type microprocessor 2 according to the fourth embodiment of the present invention described above, it is possible to perform the process of performing the operation only on the processor element 3 having a specific PE number with a small number of instructions. According to the conventional technique, first, “0” is set to the T registers 54 of all the processor elements 3, and further, “1” is set to the T registers 54 of the processor elements 3 that perform the operation. However, the number of instructions inevitably increases as compared with the fourth embodiment of the present invention.

<< Fifth Embodiment >>
A SIMD type microprocessor 2 according to a fifth embodiment of the present invention will be described.

  In each processor element 3 of the SIMD type microprocessor 2 according to the fifth embodiment, the (data) value connected to the selection circuit 35 from the PE number mask circuit according to the first embodiment is transferred to the selection circuit 35. The provided comparator 80 (FIG. 7) compares the immediate data specified in the instruction code and stores the result in a bit at a predetermined position of the T register 54. By storing the result in the T register 54, it is possible to perform control such that only the processor element 3 having the PE number every “power of 2” is executed in the calculation after the next instruction.

  The output of the PE number mask circuit shown in FIG. 4 is input to the selection circuit 35 of FIG. 7, and the selection circuit 35 executes an “LDTM” (Load to T register Masked PE Number) instruction (prepared in advance). Thus, the output data of the PE number mask circuit is selected by the input data selection signal 2. Further, when the LDTM instruction is executed, immediate data (one of them) is input to the IMM 2, and the output data of the PE number mask circuit and the IMM 2 are compared by the comparator 80. If they match, the output of the comparator 80 of the processor element 3 becomes “1”, and the processor element 3 that does not match becomes “0”. The following instruction is an example of an instruction to be executed.

  LDTM / T2 # 00000011b, # 1

In the above instruction, the first operand of the immediate operand is a mask pattern. The second operand is a comparison value. However, the mask pattern is expressed in binary notation, and the comparison value is expressed in decimal.
The value of the result masked to PE0, PE1, PE2, PE3, PE4, PE5, PE6, PE7,.
・ 0, 1, 2, 3, 0, 1, 2, 3, ...
It is a repetitive value like
・ PE1, PE5, PE9, ...
"1" is set in the T2 flag of the T register 54. “0” is set in the T2 flag of the T register 54 of another PE. As a result, if the T2 flag of the T register 54 is used for execution control in subsequent instructions, only the processor element 3 having a PE number starting with a specific PE, that is, every “2 2”, starting with PE 1 can be executed.

<< Sixth Embodiment >>
A SIMD type microprocessor 2 according to a sixth embodiment of the present invention will be described.

  In each processor element 3 of the SIMD type microprocessor 2 according to the sixth embodiment, the (data) value connected to the selection circuit 35 from the fixed value selection circuit according to the second embodiment is transferred to the selection circuit 35. The provided comparator 80 (FIG. 7) compares the immediate data specified in the instruction code and stores the result in a bit at a predetermined position of the T register 54. By storing the result in the T register 54, it is possible to perform control such that only the processor element 3 having a PE number every specific numerical value such as 3, 5, 7 is executed in the calculation after the next instruction. it can.

  The output of the fixed value selection circuit shown in FIG. 5 is input to the selection circuit of FIG. 7, and the selection circuit 35 executes an “LDTN” (Load to T register Predefined Number) instruction (prepared in advance). The output data of the fixed value selection circuit is selected by the input data selection signal 2. Furthermore, when the LDTN is executed, immediate data (one of them) is input to the IMM 2, and the output data of the fixed value selection circuit and the IMM 2 are compared by the comparator 80. If they match, the output of the comparator 80 of the processor element 3 becomes “1”, and the processor element 3 that does not match becomes “0”. The following instruction is an example of an instruction to be executed.

  LDTN / T2 # 3, # 2

In the above instruction, the first operand of the immediate operands is a selected fixed value. The second operand is a comparison value.
-PE0, PE1, PE2, PE3, PE4, PE5, PE6, PE7, ...
0, 1, 2, 0, 1, 2, 0, 1,. . .
It is a repetitive value like
・ PE2, PE5, PE8, ...
"1" is set in the T2 flag of the T register 54. “0” is set in the T2 flag of the T register 54 of another PE. As a result, if the T2 flag of the T register 54 is used for execution control in subsequent instructions, only the processor element 3 having a PE number starting with PE2 and having every other “3” PE number can be executed.

<< Seventh Embodiment >>
A SIMD type microprocessor 2 according to a seventh embodiment of the present invention will be described.

  In each processor element 3 of the SIMD type microprocessor 2 according to the seventh embodiment, a (data) value connected to the selection circuit 35 from the n-th bit pattern data output circuit according to the third embodiment is selected. The comparator 80 (FIG. 7) provided in the circuit 35 compares it with the immediate data specified in the instruction code, and stores the result in a bit at a predetermined position of the T register 54. By storing the result in the T register 54, the control is executed so that only the processor element 3 having a PE number every specific numerical value such as 2, 3, 5, 7, 11 is executed in the operation after the next instruction. It can be performed.

  The output of the n-bit bit pattern data output circuit shown in FIG. 6 is output to the selection circuit 35 of FIG. 7, and the selection circuit 35 executes an “LDTB” (Load to T register Bit Number) instruction (prepared in advance). As a result, the output data of the n-th bit pattern data output circuit is selected by the input data selection signal 2. Further, when the LDTB instruction is executed, immediate data (one of them) is input to the IMM 2, and the output data of the n-th bit pattern data output circuit is compared with the IMM 2 by the comparator 80. If they match, the output of the comparator of the processor element 3 becomes “1”, and the processor element 3 that does not match becomes “0”. The following instruction is an example of an instruction to be executed.

  LDTB / T2 # 00000010b, # 1

In the above instruction, the first operand of the immediate operand is designated every n bits. The second operand is a comparison value.
-PE0, PE1, PE2, PE3, PE4, PE5, PE6, PE7, ...
1, 0, 0, 1, 0, 0, 1, 0,. . .
It is a repetitive value like
・ PE0, PE3, PE6, ...
"1" is set in the T2 flag of the T register 54. “0” is set in the T2 flag of the T register 54 of another PE. As a result, if the T2 flag of the T register 54 is used for execution control in the subsequent instructions, only the processor element 3 having a PE number starting with a specific PE, that is, every third, starting with PE0 can be executed.

1 is a block diagram showing a schematic configuration of a general SIMD type microprocessor. FIG. It is a block diagram which shows the more detailed structure of the SIMD type | mold microprocessor which concerns on this invention. It is a block diagram which shows the function of the multiplexer which connects the register | resistor of a register file, and an arithmetic array. 1 is a circuit diagram of a PE number mask circuit according to a first embodiment of the present invention. FIG. 5 is a circuit diagram of a fixed value selection circuit according to a second embodiment of the present invention. It is a circuit diagram of the n every bit pattern data output circuit based on the 3rd Embodiment of this invention. 1 shows a schematic circuit block diagram of a selection circuit according to the present invention. FIG. It is an example of a circuit block diagram of an arithmetic control register (T register).

Explanation of symbols

2 ... SIMD type microprocessor, 3 ... processor element, 4 ... global processor, 6 ... register file, 8 ... arithmetic array, 34 ... register, 35 ... arithmetic circuit, 36 ... ALU (arithmetic logic unit), 38 ... A register, 50, 50 ', 50 "... connection line part, 51, 51" ... logic circuit part, 51' ... multiplexer 54, T register (operation control register), 78, multiplexer, 80, comparator.

Claims (1)

A global processor for overall control and a SIMD type microprocessor including a plurality of processor elements ,
Each processor element is given an integer number for identification, in order,
Each processor element
A connection line to which an integer number for identification attached to the processor element is input from the outside;
A mask circuit in which a logic circuit for receiving a mask control signal from the global processor is inserted into the connection line;
SIMD type microprocessor having

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