JP4401941B2 - Game machine - Google Patents

Description

  The present invention is a pachinko gaming machine or slot in which a player can play a predetermined game using a game medium and pays out a prize game medium as a prize based on the winning of the game medium in a predetermined winning area. It relates to gaming machines such as machines.

  As a gaming machine, a game medium such as a game ball is launched into a game area by a launching device, and when a game medium wins a prize area such as a prize opening provided in the game area, a predetermined number of prize balls are paid out to the player. There is something to be done. Furthermore, there is provided a variable display unit capable of changing the display state, and configured to give a predetermined game value to the player when the display result of the variable display unit is in a predetermined specific display mode. is there.

  Note that the game value is the right that the state of the variable winning ball device provided in the gaming area of the gaming machine is advantageous for a player who is likely to win a ball, or the advantageous state for a player. In other words, or a condition for winning a prize ball is easily established.

  In a pachinko gaming machine, a combination of a predetermined display mode with a display result of a variable display unit that displays a special symbol is usually referred to as “big hit”. When a big hit occurs, for example, the big winning opening is opened a predetermined number of times, and the game shifts to a big hit gaming state in which a hit ball is easy to win.

  Game progress in the gaming machine is controlled by game control means including a game control microcomputer. When the payout control means including the payout control microcomputer for controlling the prize ball payout is mounted on a payout control board different from the main board on which the game control means is mounted, the progress of the game is transferred to the main board. Since it is controlled by the mounted game control means, the number of winning balls based on the winning is determined by the game control means, and a control signal indicating the number of winning balls is transmitted to the payout control board. Then, the payout control means performs a process of paying out the number of prize balls based on the winning based on the control signal from the game control means.

  In the gaming machine, the number of winning balls according to winning is determined as, for example, 10 or 15 according to each of a plurality of winning areas provided. There are some gaming machines that pay out a ball for each win when a win occurs, but in order to shorten the total payout time, if consecutive wins occur, a prize ball based on multiple wins is awarded. There are also gaming machines that pay out in a lump without dividing. For example, when winnings corresponding to 10 winning balls are generated three times in succession, 30 winning balls are continuously paid out in a lump.

  Further, when the payout control means is performing the prize ball payout control, if the information regarding the new prize ball payout is received from the game control means, the payout control means newly sets the number of unpaid prize balls at that time. There is a gaming machine that controls such that the number of prize balls is added and paid out in a lump including prize balls based on newly generated winnings (see, for example, Patent Document 1).

  Further, in the gaming machine, even when the power supply to the gaming machine is stopped, the backup power source is set so that the contents of the RAM provided in the game control means and the contents of the RAM provided in the payout control means are saved. A detection signal from a power supply monitoring means for detecting a drop in power supply voltage is input to the main board and the payout control board, and the game control means and the payout control means execute processing for storing information in the RAM. (For example, refer patent document 2). In the gaming machine configured as described above, a clear switch for clearing the contents of the stored RAM is provided, and when the power supply to the gaming machine is started, the game control is performed when the clear switch is pressed. The means and the payout control means are configured to clear the contents of the RAM.

  In such a gaming machine, in order to prevent a situation in which the payout control means cannot receive a control signal (command) transmitted from the game control means to the payout control means when power supply to the gaming machine is started. In addition, there is provided a delay means for delaying the timing at which the game control means starts up (becomes able to execute the game control device control process) than the timing at which the payout control means starts up (becomes able to execute the payout control process). May be.

Japanese Patent Laid-Open No. 2001-212321 (paragraphs 0039-0048, FIGS. 4 and 5) JP 2002-136754 A (paragraphs 0010-0014, 0021-0023, FIG. 1, FIG. 3, FIG. 5)

  As described above, in the gaming machine described in Patent Document 1, the payout sensor that detects the game ball after being paid out from the payout device driven by the payout motor has detected the last game ball (game ball). On the condition that the value stored in the number-of-payout storage area has become 0 by the detection of (), the driving of the payout motor is stopped assuming that the game ball has been paid out. Then, when the payout sensor detects the last game ball, there is a possibility that a new game ball is paid out by driving the payout motor. That is, there is a problem that the accuracy of the continuous payout control that is not divided for each prize ball that is executed in order to realize quick prize ball payout is low.

  Also, in the gaming machine described in Patent Document 2, when the power supply to the gaming machine is started, the timing at which the game control means starts up is set to be later than the timing at which the payout control means starts up If the clear switch is pressed by a game clerk or the like when the power supply to the gaming machine is started to clear the contents of the RAM, the payout control is performed if the pressing timing is delayed or the pressing time is short. Although the means can recognize the depression of the clear switch, the game control means may not recognize the depression of the clear switch. The reason for pressing the clear switch is to clear and initialize the data stored when the power supply to the gaming machine is stopped, that is, the data related to the control state when the power supply is stopped. When a situation occurs in which the payout control means can recognize the press of the clear switch but the game control means cannot recognize the press of the clear switch, the control state of the payout control means is initialized, but the game control means The control state remains the same as when the power supply is stopped, the control states of both control means are not consistent, and the entire gaming machine cannot be controlled normally. Also, even if the configuration is such that the timing at which the game control means rises is later than the timing at which the payout control means rises, depending on how the clear switch is depressed, one control means can recognize the depression of the clear switch. However, there may be a situation where the other control means cannot recognize the pressing of the clear switch. Furthermore, depending on the difference in execution time of the RAM content clear process executed by the game control means and the payout control means, the game control before the preparation for receiving the control signal is completed by the payout control means. Since the control signal may be transmitted by the means, the control signal may be missed.

  Therefore, according to the present invention, the game control means and the payout control means are provided separately, and the game control means and the payout control means can store the stored contents for at least a predetermined period when the power supply to the gaming machine is stopped. In a gaming machine having a storage means and having an operation means for initializing the storage contents of the storage means, it is possible to perform more reliable payout control while realizing quick payout of game media. It is an object of the present invention to provide a gaming machine that can reliably initialize the contents of each storage means in the game control means and the payout control means based on the operation, and can prevent the control signal from being missed.

The gaming machine according to the present invention allows a player to play a predetermined game using a game medium (for example, a game ball), and a predetermined winning area (for example, fixed winning ports 29 provided in the gaming area, 30, 33, 39 or the variable winning ball apparatus 15), which is a gaming machine that pays out a prize game medium as a prize based on the winning of the game medium, and controls the progress of the game (for example, steps S 41 to S 41). S56) is executed, and a payout number signal (for example, a prize ball number signal) for instructing the take-in of the payout number signal indicating the payout number of the prize game medium based on the winning of the game medium in a predetermined winning area is acquired. payout number signal output means My gaming control including a game control microcomputer (e.g. CPU56 containing (e.g. portions for performing the prize balls processing shown in FIG. 30) for outputting with the signal A game control board (for example, the main board 31) equipped with a computer 560), a payout means (for example, a ball payout device 97) for paying out game media, and a payout drive means for driving out the game media by driving the payout means (For example, a payout motor 289) and a prize game medium payout control process for controlling the payout driving means in accordance with a payout number signal input from a game control microcomputer (for example, a prize ball lending control process shown in FIG. A payout control board on which a payout control microcomputer (for example, a payout control microcomputer 370) that executes a payout ball control process in the payout motor control process shown in FIG. 5 and an operation for outputting an operation signal according to the operation Means (for example, clear switch 921), and the game control microcomputer executes the game control process. The game control variable data storage means (for example, the RAM 55 that is backed up by the power source) that retains the stored contents for a predetermined period even if the power supply to the gaming machine is stopped and the power supply to the gaming machine are stored. When started, a payout control start signal output means for outputting a payout control start signal to a payout control microcomputer together with a takein signal for instructing to take in the payout control start signal (for example, step S11 in the game control microcomputer 560). A delay processing unit that executes a delay process for delaying a start time of a process of outputting a payout control start signal by the payout control start signal output unit by a predetermined period from a time when power supply to the gaming machine is started (For example, a portion for executing steps S4 to S9 in the game control microcomputer 560) and a payout system After the activation signal output means outputs the payout control activation signal, the game control operation signal confirmation means for confirming whether or not the operation signal is outputted from the operation means (for example, execute step S13 in the game control microcomputer 560) And when the game control operation signal confirmation means confirms that no operation signal is output, the execution state of the game control process based on the stored contents held in the game control variation data storage means The game control execution state return means (for example, the part that executes steps S16 to S17 in the game control microcomputer 560) and the game control operation signal confirmation means confirm that the operation signal is output. Sometimes the game control process is initialized by initializing the stored contents stored in the game control variation data storage means. Wherein the gaming control execution state initialization means for starting from the state (e.g., portions for performing the steps S21~S23 in the gaming control microcomputer 560), and a payout number signal output by the payout number signal output means, payout The payout control start signal output by the control start signal output means is a signal transmitted from the game control board to the payout control board through the same plurality of signal lines, and the payout number signal output by the payout number signal output means. The take-in signal and the take-in signal of the payout control start signal output by the payout control start signal output means are signals transmitted from the game control board to the payout control board through the same signal line, is input to the interrupt terminal of the computer, the payout control micro computer, the payout number signal from the payout number signal output means Data including a prize game medium number data storage means (for example, a prize ball payout total number counter) for storing data indicating the number of game medium payouts, and data that varies in accordance with the payout control A payout control variation data storage means (for example, a RAM that is backed up by a power source) and a game control microcomputer capable of storing the stored contents at least for a predetermined period when power supply to the gaming machine is stopped In response to a capture signal (for example, a prize ball REQ signal) being input to the interrupt terminal, the value of a specific register (for example, an external interrupt request register) is updated to a predetermined value and interrupted to the payout control process. Interrupt process execution means for executing an interrupt process (for example, executing a prize ball REQ interrupt process in the payout control microcomputer 370) A portion for executing interrupt processing by the interrupt processing execution means, an interrupt prohibiting means for controlling to an interrupt prohibited state (for example, executing the step S701 in the payout control microcomputer 370), and the number of payouts. When the supply of power to the gaming machine is started, and the number-of- payout signal input means for inputting the number- of-payout signal from the signal output means in the interruption process (for example, the portion for executing step S545 in the payout control microcomputer 370) In addition, after controlling to the interrupt prohibited state by the interrupt prohibiting means, initial setting means for initial setting of the internal state of the payout control microcomputer (for example, a part for executing steps S701 to S705 in the payout control microcomputer 370); After the initial setting by the initial setting means, the value of the specific register is a predetermined value A register confirmation means for confirming whether or not (e.g., portions for performing the steps S721~S723 in payout control microcomputer 370), after being controlled to interrupt disabled state by the interrupt disabled section, the register check means within a predetermined time When the value of the specific register is confirmed to be a predetermined value by the payout control start signal input means for inputting the payout control start signal output from the game control microcomputer (for example, step in the payout control microcomputer 370) S725) and when the interrupt prohibition means controls the interrupt prohibited state, the register value confirmation means confirms that the value of the specific register is the predetermined value even if the predetermined time has elapsed. Otherwise, a payout control activation signal may not be received from the game control microcomputer. And unstartable information storage means for storing unstartable information indicating, dispensing the payout control activation signal input unit checks whether the condition that enter the payout control activation signal, the operation signal from the operating means is being output When the control signal confirming means for control (for example, the part that executes step S708 in the payout control microcomputer 370) and the payout control signal confirming means confirm that no operation signal is output, the fluctuation for payout control A payout control execution state return means (for example, a portion for executing step S711 in the payout control microcomputer 370) for returning the execution state of the payout control process based on the stored contents held in the data storage means, and a payout control operation. When the signal confirmation means confirms that an operation signal has been output, the fluctuation data for payout control is recorded. A payout control execution state initializing means (for example, a part for executing steps S712 to S716 in the payout control microcomputer 370) for initializing the storage contents held in the memory means and starting the payout control process from the initial state ; The payout control microcomputer confirms whether or not the operation signal is output from the operation means by the payout control operation signal confirming means when the start impossible information is stored in the unstartable information storage means. Without executing, the storage contents held in the payout control variation data storage means are initialized and the payout control process is started from the initial state, and the payout control microcomputer is executed by the payout control execution state return means. Interrupt processing after the stored contents are initialized by the execution status initialization means Interrupt permission means (for example, a part for executing step S717 in the payout control microcomputer 370) for controlling to an interrupt permission state permitting execution of interrupt processing by the line means, and interruption permission means being set to the interrupt permission state. in response to controlled, input state signal output means for outputting the input state signal indicating that the payout number signal becomes possible input in the interrupt processing to the game control microcomputer by payout number signal input means (e.g. portions for performing the steps S718 in the payout control microcomputer 370) and, when the payout number signal input means inputs a payout number signal from the payout number signal output means, the number of payouts instructed by該払out number signal Is added to the data stored in the prize game medium number data storage means (for example, a payout control manager). The portion of the black computer 370 that executes step S545) and the data stored in the prize game medium number data storage means indicate that there is a game medium to be paid out. A payout starting means for starting driving (for example, a portion for executing steps S631 to S635 and steps S627 and S628 in the payout control microcomputer 370) and a prize game medium when the payout driving means drives the payout means Increase determination means for determining whether or not the data stored in the numerical data storage means has increased (for example, the portion of the payout control microcomputer 370 that executes step S694), and the increase determination means increases the data. Increase number specifying means to identify the increase number when it is determined that (For example, a part that executes the process of calculating the difference in the process of step S695 in the payout control microcomputer 370) and data that can specify the drive amount of the payout driving means until the payout means finishes paying out the game medium Drive amount data storage means (for example, payout operation counter), and drive amount subtraction means (for example, payout control) that subtracts the data stored in the drive amount data storage means by the amount corresponding to the drive amount of the payout drive means. Portion of the microcomputer 370 that executes the process of step S513) and when the increase determining means determines that the data has increased (or when the payout driving means drives the payout means, for example). The drive amount data storage means stores the data indicating the drive amount according to the increase number specified by the increase number specifying means. Driving amount data adding means for adding to data (for example, the portion for executing addition processing in step S695 in the payout control microcomputer 370) and driving of the payout means by the payout driving means by the payout starting means are started. When the data stored in the quantity data storage means becomes a value (for example, 0) corresponding to the end of payout of the game medium, a payout stop means (for example, a payout control micro) that stops driving of the payout means by the payout drive means. And a portion for executing a process of stopping driving of the payout motor 289 in response to the value of the payout operation counter being 0 in the payout motor brake process of step S525 in the computer 370, and the game control microcomputer , The return of the execution state or the game system by the execution state return means for game control In response to the input ready state signal being input from the input ready state signal output means after the preparation of execution of the game control process is completed by the initialization of the stored contents by the execution state initialization means (for example, step (Y in S24), the execution of the game control process is started, and a process of outputting a payout control command by the payout number signal output means (for example, a prize ball process: see FIG. 30) is executed in the game control process. To do.

  The payout control microcomputer is a previous prize game medium number data storage means (for example, a payout control microcomputer) that holds the data stored in the prize game medium number data storage means when the drive amount data addition means adds the data. The increase determination means includes data stored in the prize game medium number data storage means and data stored in the previous prize game medium number data storage means. It is determined whether or not the data has increased by comparing with the existing data (for example, step S694), and the increase number specifying means has the data stored in the prize game medium number data storage means and the previous prize game medium number data. The difference from the data stored in the storage means is specified as the increase number (for example, step S695). It may be configured.

  When the increase determination means determines that the data has increased, the payout control microcomputer uses the data stored in the premium game medium number data storage means after the data is added by the addition means as the previous premium game medium number. The configuration may include a prize game medium number data setting means (for example, a part for executing step S697 in the payout control microcomputer 370) to be set in the data storage means.

  When a predetermined standby period has elapsed without inputting a payout control activation signal from the payout control activation signal output means (for example, Y in step S723), the payout control microcomputer enters a stopped state in which the control is stopped. You may be comprised so that it may transfer (for example, control stop state).

  When the predetermined standby period has elapsed without inputting the payout control activation signal from the payout control activation signal output means (for example, Y in step S723), the payout control microcomputer has an abnormality related to communication. Communication abnormality detecting means (for example, a part of step S724 in the payout control microcomputer 370) that detects the abnormality, and when the communication abnormality detecting means detects that an abnormality has occurred, a communication abnormality notification means that notifies that fact. (For example, a portion for executing processing for displaying “A” (see FIG. 57) on the error display LED 374 in the payout control microcomputer 370).

  When power supply to the gaming machine is started, an allowable signal output means (for example, a power supply monitoring circuit 920) that outputs an allowable signal (for example, a reset signal) that makes the gaming control microcomputer and the payout control microcomputer operable. ) And when the payout control microcomputer and the game control microcomputer become operable based on the allowance signal from the allowance signal output means, than when the payout control microcomputer becomes operable. There may be provided delay means (for example, a delay circuit 69) for delaying the specified period to make the game control microcomputer operable.

  According to the first aspect of the present invention, the prize game medium can be paid out quickly, and the prize game medium can be paid out accurately. Further, even if the game control microcomputer is configured to execute the delay process, the variable data storage means in the other microcomputer is initialized even though the contents of the variable data storage means in one microcomputer are initialized. It is possible to prevent the occurrence of a situation where the contents of the game data are not initialized, and to reliably initialize the contents of each variation data storage means in the game control microcomputer and the payout control microcomputer based on the operation of the operation means. At this time, there is no problem that the payout control microcomputer does not execute the initial setting process normally due to the interrupt process based on the signal from the game control microcomputer. Further, it is possible to prevent the payout command signal from being missed.

  In the invention according to claim 2, the increase determination means increases the data by comparing the data stored in the prize game medium number data storage means with the data stored in the previous prize game medium number data storage means. The increase number specifying means specifies the difference between the data stored in the prize game medium number data storage means and the data stored in the previous prize game medium number data storage means as the increase number. Therefore, the number of increases can be accurately specified with a simple configuration.

  In the invention according to claim 3, when the payout control microcomputer determines that the increase determination means has increased the data, it is stored in the prize game medium number data storage means after the data is added by the addition means. Since the prize data is set in the previous prize game medium number data storage means, the increase number can be specified accurately with a simple structure.

  In the invention according to claim 4, when the predetermined waiting period elapses without inputting the payout control activation signal from the payout control activation signal output means, the payout control microcomputer stops the control. Therefore, the payout control process can be prevented from being executed in a state where the game control process may not be started in the game control microcomputer.

  In the invention according to claim 5, an abnormality relating to communication has occurred when a predetermined waiting period has elapsed without the dispensing control microcomputer inputting the dispensing control activation signal from the dispensing control activation signal output means. Communication abnormality detecting means for detecting this, and communication abnormality notifying means for notifying that when the communication abnormality detecting means detects that an abnormality has occurred, the payout control microcomputer starts the payout control. It is possible to reliably notify that the signal has not been received.

  According to the sixth aspect of the present invention, when the power supply to the gaming machine is started, the permission signal output means for outputting the permission signal for making the game control microcomputer and the payout control microcomputer operable, and the permission When the payout control microcomputer and the game control microcomputer become operable based on the allowance signal from the signal output means, the delay is delayed by a specific period from the time when the payout control microcomputer becomes operable. Since the delay control means for enabling the game control microcomputer to operate is performed, the delay processing is also performed by hardware. Therefore, the delay processing by software is performed in preparation for a specification change. It can retain versatility and simplify software delay processing. Can be done, it is possible to reduce the data capacity of software for delay processing. In addition, the payout control microcomputer can reliably receive the control signal from the game control microcomputer.

Hereinafter, an embodiment of the present invention will be described with reference to the drawings.
First, the overall configuration of a pachinko gaming machine that is an example of a gaming machine will be described. FIG. 1 is a front view of a pachinko gaming machine as viewed from the front, and FIG. 2 is a front view showing the front of the game board. In the following embodiments, a pachinko gaming machine will be described as an example. However, the gaming machine according to the present invention is not limited to a pachinko gaming machine, and can be applied to other gaming machines such as a slot machine.

  The pachinko gaming machine 1 includes an outer frame (not shown) formed in a vertically long rectangular shape, and a game frame attached to the inside of the outer frame so as to be openable and closable. Further, the pachinko gaming machine 1 has a glass door frame 2 formed in a frame shape that is provided in the game frame so as to be opened and closed. The game frame includes a front frame (not shown) installed to be openable and closable with respect to the outer frame, a mechanism plate to which mechanism parts and the like are attached, and various parts attached to them (excluding a game board described later). Is a structure including

  As shown in FIG. 1, the pachinko gaming machine 1 has a glass door frame 2 formed in a frame shape. On the lower surface of the glass door frame 2 is a hitting ball supply tray (upper plate) 3. Under the hitting ball supply tray 3, an extra ball receiving tray 4 for storing game balls that cannot be accommodated in the hit ball supply tray 3 and a hitting operation handle (operation knob) 5 for launching the game balls are provided. A game board 6 is detachably attached to the back surface of the glass door frame 2. The game board 6 is a structure including a plate-like body constituting the game board 6 and various components attached to the plate-like body. A game area 7 is formed on the front surface of the game board 6.

  Near the center of the game area 7, there is provided a variable display device (decorative symbol display device) 9 including a plurality of variable display portions each variably displaying an effect decorative symbol. The variable display device 9 has, for example, three variable display portions (symbol display areas) of “left”, “middle”, and “right”. In addition, the variable display device 9 is provided with four special symbol start memory display areas (start memory display areas) 18 for displaying the number of effective winning balls that have entered the start winning opening 14, that is, the start memory number. Each time there is a valid start prize, the display color changes (for example, changes from blue display to red display), and the start storage display area is increased by one. Each time the variable display of the variable display device 9 is started, the start memory number display area where the display color is changed is reduced by 1 (that is, the display color is returned to the original).

  A special symbol display (special symbol display device) 8 that variably displays a special symbol as identification information is provided on the variable display device 9. In this embodiment, the special symbol display 8 is realized by a simple and small display (for example, 7 segment LED) capable of variably displaying numbers 0 to 9, for example. The special symbol display 8 may be configured to variably display a larger number of numbers such as 0 to 99 in order to make it difficult for the player to grasp a specific stop symbol. The variable display device 9 performs variable display of a decorative symbol as a symbol for decoration (production) during the variable symbol display period of the special symbol by the special symbol indicator 8. The variable display device 9 that performs variable display of decorative symbols is controlled by an effect control microcomputer mounted on the effect control board. In addition, the pachinko gaming machine 1 includes an operation switch 81 that can be operated by the player while the game is in progress.

  Below the variable display device 9, a variable winning ball device 15 is provided as a start winning port 14. The winning ball that has entered the start winning opening 14 is guided to the back of the game board 6 and detected by the start opening switch 14a. A variable winning ball device 15 that opens and closes is provided below the start winning opening 14. The variable winning ball device 15 is opened by a solenoid 16.

  A variable winning ball apparatus 20 using an opening / closing plate that is opened by a solenoid 21 in a specific gaming state (big hit state) is provided below the variable winning ball apparatus 15. The variable winning ball apparatus 20 is a means for opening and closing a big winning opening. Of the winning balls that are won by the variable winning ball apparatus 20 and guided to the back of the game board 6, the winning balls that enter one (V winning area: special area) are detected by the V count switch 22 and enter the other area. A game ball is detected by the count switch 23. On the back of the game board 6, a solenoid 21A for switching the route in the special winning opening is also provided.

  When the game ball passes through the gate 32 and is detected by the gate switch 32a, variable display of the normal symbol display 10 is started. In this embodiment, variable display is performed by alternately lighting left and right lamps (designs can be visually recognized when lit). For example, if the left lamp is lit at the end of variable display, it is a win. When the stop symbol on the normal symbol display 10 is a predetermined symbol (winning symbol), the variable winning ball device 15 is opened for a predetermined number of times. In the vicinity of the normal symbol display 10, a normal symbol start memory display 41 having a display unit with four LEDs for displaying the number of winning balls that have passed through the gate 32 is provided. Each time a game ball passes to the gate 32, the normal symbol start memory display 41 increments the LED to be lit by one. Each time variable display on the normal symbol display 10 is started, the number of LEDs to be lit is reduced by one.

  The game board 6 is provided with a plurality of winning holes 29, 30, 33, 39, and winning of game balls to the winning holes 29, 30, 33, 39 is performed by winning hole switches 29a, 30a, 33a, 39a, respectively. Detected. Each winning opening 29, 30, 33, 39 constitutes a winning area provided in the game board 6 as an area for accepting game media and allowing winning. The start winning opening 14 and the big winning opening also constitute a winning area that accepts game media and allows winning. Around the left and right of the game area 7, there are provided decorative lamps 25 blinking and displayed during the game, and at the lower part there is an outlet 26 for absorbing a game ball that has not won a prize. Two speakers 27 that emit sound effects are provided on the left and right upper portions outside the game area 7. On the outer periphery of the game area 7, a top frame lamp 28a, a left frame lamp 28b, and a right frame lamp 28c are provided. Further, a decoration LED is installed around each structure (such as a big prize opening) in the game area 7. The top frame lamp 28a, the left frame lamp 28b, the right frame lamp 28c, and the decoration LED are examples of a decorative light emitter provided in the gaming machine.

  In this example, a prize ball LED 51 that is lit while paying out a prize ball is provided in the vicinity of the left frame lamp 28b, and a ball break LED 52 that is lit when the refill ball is cut is provided in the vicinity of the top frame lamp 28a. It has been. As described above, the pachinko gaming machine 1 of this embodiment is provided with lamps and LEDs as light emitters in various places. Further, a prepaid card unit (hereinafter referred to as “card unit”) 50 that enables lending a ball by inserting a prepaid card is installed adjacent to the pachinko gaming machine 1.

  The card unit 50 includes, for example, a usable display lamp that indicates whether or not the card unit 50 is in a usable state, a connection table direction indicator that indicates which side of the pachinko gaming machine 1 corresponds to the card unit 50, a card A card insertion indicator lamp indicating that a card is inserted into the unit 50, a card insertion slot into which a card as a recording medium is inserted, and a card reader / writer mechanism provided on the back surface of the card insertion slot are inspected. In some cases, a card unit lock for releasing the card unit 50 is provided.

  A game ball launched from the ball striking device by the player's operation enters the game area 7 through the hit ball rail, and then descends the game area 7. When the game ball enters the start winning opening 14 and is detected by the start opening switch 14a, the special symbol on the special symbol display 8 starts variable display (variation) if the variable display of the symbol can be started. If the variable display of the symbol cannot be started, the start memory number is increased by one.

  The variable display of the special symbol on the special symbol indicator 8 stops when a certain time has passed. If the special symbol (stop symbol) at the time of stoppage is a jackpot symbol (specific display result), the game shifts to a jackpot gaming state. That is, the variable winning ball apparatus 20 is released until a predetermined time elapses or until a predetermined number (for example, 10) of gaming balls wins. When a game ball is won in the V winning area while the variable winning ball device 20 is opened and is detected by the V count switch 22, a continuation right is generated and the variable winning ball device 20 is opened again. The generation of the continuation right is allowed a predetermined number of times (for example, 15 rounds).

  When the special symbol on the special symbol display 8 at the time of stoppage is a jackpot symbol (probability variation symbol) with a probability variation, the probability of the next jackpot increases. That is, it becomes a more advantageous state for the player in the probability variation state.

  When the game ball passes through the gate 32, the normal symbol display unit 10 enters a state in which the normal symbol is variably displayed. Further, when the stop symbol on the normal symbol display 10 is a predetermined symbol (winning symbol), the variable winning ball device 15 is opened for a predetermined time. Further, in the probability variation state, the probability that the stop symbol in the normal symbol display 10 becomes a winning symbol is increased, and the opening time and the number of times of opening of the variable winning ball device 15 are increased.

  Next, the structure of the back surface of the pachinko gaming machine 1 will be described with reference to FIG. FIG. 3 is a rear view of the gaming machine as seen from the back side.

  As shown in FIG. 3, on the back side of the pachinko gaming machine 1, a ball storage tank 38 is provided above the mechanism plate in the outer frame 2A, and the pachinko gaming machine 1 is installed on the gaming machine installation island. A game ball is supplied to the ball storage tank 38 from above. The game balls in the ball storage tank 38 reach the ball payout device 97 (see FIG. 4) that passes through the guide basket 39 and is covered with the prize ball case 40A.

  Further, on the back side of the gaming machine, a variable display control unit 49 including an effect control board 80 on which an effect control microcomputer for controlling the variable display device 9 is mounted, and a game on which a game control microcomputer and the like are mounted. A control board (main board) 31 is installed. In addition, a payout control board 37 on which a payout control microcomputer for performing ball payout control is mounted is installed.

  Display control means for performing variable display control of the variable display device 9 is realized by an effect control microcomputer mounted on the effect control board 80, a VDP (video display processor), or the like. Further, the gaming machine drives a frame side lamp driver board 35 on which circuits for driving a top frame lamp 28a, a left frame lamp 28b, a right frame lamp 28c, etc. provided on the frame side are mounted, and a speaker 27. A voice control board 70 on which a circuit to be mounted is mounted.

  Further, a power supply board 910 and other boards (not shown) on which power supply circuits for creating DC30V, DC21V, DC12V, and DC5V are mounted are provided. A central relay board 77 is provided for relaying signals output from the main board 31 to other boards.

  The electrical component control boards (payout control board and effect control board) are each equipped with electrical component control means (payout control means and effect control means) including an electric component control microcomputer. The payout control means and the effect control means control electrical components (game device: ball payout device 97, variable display device 9 and the like) provided in the gaming machine according to a command signal (control signal) from the game control means. Further, the light emitters such as lamps and LEDs provided on the frame side, and electrical components such as the speaker 27 are mounted on the frame side lamp driver board 35 and the sound control board 70 in accordance with a control signal from the effect control means. Driven by circuit components. Furthermore, game machines include a board on which a switch is mounted and a board on which a light emitting body such as a lamp or LED (hereinafter also referred to as a lamp / LED) is mounted. The substrate is a printed wiring board on which electrically driven electrical components, circuit components, connection components such as connectors and terminals, and the like are mounted.

  On the back side of the gaming machine, a terminal board 160 provided with terminals for outputting various information to the outside of the gaming machine is installed above. The terminal board 160 includes at least a ball break terminal for introducing the output of the ball break detection switch 167 and outputting it externally, a prize ball terminal and a ball for outputting prize ball information (prize ball number signal) to the outside. A ball lending terminal for externally outputting lending information (ball lending number signal) is provided. Near the center, an information terminal board (information output board) 34 having terminals for outputting various information from the main board 31 to the outside of the gaming machine is installed.

  The game balls stored in the ball storage tank 38 pass through the guide rod 39 and reach the ball payout device covered with the payout case 40A via the curve bag 39. Above the ball payout device 97, a ball break switch as a game medium break detection means is provided. When the ball break switch detects a ball break, the dispensing operation of the ball dispensing device stops. The ball break switch is a switch for detecting the presence or absence of a game ball in the game ball passage, but the ball break detection switch 167 for detecting the shortage of supply balls in the storage tank 38 is also an upstream portion of the guide rod 39 (in the storage tank 38). (Proximate part). When the ball break detection switch 167 detects the shortage of game balls, the game machine is replenished to the game machine from the supply mechanism provided on the gaming machine installation island.

  Hereinafter, the electrical component control board on which the microcomputer is mounted and the board for inputting a signal from the main board 31 may be collectively referred to as a peripheral board.

  FIG. 4 is a front view (FIG. 4 (A)) and a cross-sectional view (FIG. 4 (B)) showing the ball dispensing device 97 covered with the dispensing case 40A. The ball payout device 97 is fixed to the lower part of the passage body installed between the ball break switch 187 and the ball payout device 97. The passage body has a ball passage for flowing down two rows of game balls whose flow-down direction is converted into the left-right direction by a curve saddle. A ball break switch 187 is installed on the upstream side of the ball passage. In practice, a ball break switch is installed in each ball passage. The ball break switch 187 detects the presence or absence of a game ball in the ball passage. When the ball break switch 187 no longer detects a game ball, the ball dispensing device 97 rotates the dispensing motor 289 (see FIG. 6). It stops and the payout operation of the game ball is immobilized.

  The ball break switch 187 is locked by a locking piece at a position where it can be detected that 27 to 28 game balls are present in the ball path.

  In the ball payout device 97, a payout motor 289 using a stepping motor, for example, rotates a cam, thereby paying out one winning ball or one game ball based on a ball lending request. Also, below the ball payout device 97, for example, a payout number count switch 301 using a proximity switch is provided. Each time one game ball falls from the ball payout device 97, the payout number count switch 301 is turned on. That is, the payout number count switch 301 detects a game ball actually paid out from the ball payout device 97. Therefore, the payout control microcomputer 370 can count the number of game balls actually paid out by the detection signal of the payout number count switch 301. In this example, the payout number count switch 301 detects both the paid-out prize balls and rental balls. That is, the payout of prize balls and the payout of rental balls are detected by the same detection means. Therefore, the number of parts can be reduced, and the cost of the gaming machine can be reduced. However, the payout of the winning ball and the payout of the rental ball may be detected by separate detection means.

  In this embodiment, the ball payout device 97 is configured to perform both prize ball payout and ball lending. However, a ball payout device for paying out a prize ball and a ball payout device for lending a ball may be provided separately. When separately provided, the payout means is composed of a ball payout device for paying out a prize ball and a ball payout device for lending a ball. Further, for example, it may be configured to change the direction of rotation of the cam or sprocket to separate the prize ball payout and the lending ball payout, or the ball payout device 97 illustrated in the present embodiment (the cam is rotated by the motor). The present invention can be applied to a ball payout device having any structure other than the structure to be used.

  FIG. 5 is a block diagram illustrating an example of a circuit configuration in the main board 31. FIG. 5 also shows the payout control board 37, the effect control board 80, and the like. The main board 31 has a basic circuit (corresponding to a game control means) 53 for controlling the pachinko gaming machine 1 according to a program, a gate switch 32a, a start port switch 14a, a V count switch 22, a count switch 23, a winning port switch 29a, 30a, 33a, 39a and an input driver circuit 58 for supplying a signal from the clear switch 921 to the basic circuit 53, a solenoid 16 for opening and closing the variable winning ball device 15, a solenoid 21 for opening and closing the variable winning ball device 20, and a special winning opening And a solenoid circuit 59 for driving the solenoid 21A for switching the path according to a command from the basic circuit 53.

  The gate switch 32a, the start port switch 14a, the V count switch 22, the count switch 23, the winning port switches 29a, 30a, 33a, 39a, and other switches may be referred to as sensors. That is, the name of the game medium detection means is not limited as long as it is a game medium detection means (game ball detection means in this example) that can detect a game ball. Each of the start port switch 14a, the V count switch 22, the count switch 23, and the winning port switches 29a, 30a, 33a, and 39a that perform winning detection is also a winning detection means that detects the winning of a game ball in the winning area. . Note that even if a passing gate such as the gate 32 is used, if a prize ball is to be paid out, a game ball entering the passing gate becomes a prize, and a switch (for example, a switch provided in the passing gate) The gate switch 32a) becomes a winning detection means. Further, in this embodiment, since the game balls won in the V winning area are detected only by the V count switch 22, the number of game balls won in the big winning opening is the number detected by the V count switch 22 and the count switch 23. It becomes the sum with the detection number by. However, the game ball that has won the V winning area may be detected by the V count switch 22 and also by the count switch 23. In this case, the number of game balls won in the big winning opening corresponds to the number detected by the count switch 23.

  Further, according to the data given from the basic circuit 53, the jackpot information indicating the occurrence of the jackpot, the effective starting information indicating the number of starting winning balls used for starting the variable display of the symbols in the variable display device 9, the probability variation has occurred. An information output circuit 64 for outputting an information output signal such as probability variation information indicating the above to an external device such as a hall computer is mounted.

  The basic circuit 53 includes a ROM 54 for storing a program for game control (game progress control), a RAM 55 as storage means (variation data storage means for storing fluctuation data) used as a work memory, and a control operation according to the program. A game control microcomputer 560 having a game control microcomputer 560 to be performed and an I / O port unit 57 are included. In this embodiment, the ROM 54 and the RAM 55 are built in the game control microcomputer 560. That is, the game control microcomputer 560 is a one-chip microcomputer. The one-chip microcomputer only needs to include at least the RAM 55, and the ROM 54 may be external or internal. Further, the I / O port unit 57 may be built in a one-chip microcomputer.

  In addition, since the game control microcomputer 560 executes control according to the program stored in the ROM 54 in the game control microcomputer 560, hereinafter, the game control microcomputer 560 executes (or performs processing). Specifically, the game control microcomputer 560 executes control according to a program. The same applies to microcomputers mounted on substrates other than the main substrate 31. The game control means is realized by a basic circuit 53 including a game control microcomputer 560.

  The RAM 55 is a backup RAM as a non-volatile storage means that is partially or entirely backed up by a backup power source created on the power supply substrate 910. That is, even if the power supply to the gaming machine is stopped, a part or all of the contents of the RAM 55 is saved for a predetermined period (until the backup power supply cannot be supplied because the capacitor as the backup power supply is discharged). In particular, at least data (special symbol process flag, etc.) corresponding to the game state, that is, the control state of the game control means, and data indicating the number of unpaid winning balls are stored in the backup RAM. Note that the data according to the control state of the game control means is data necessary for restoring the control state before the occurrence of a power failure or the like based on the data when the power supply is restored after a power failure or the like. . In this embodiment, it is assumed that the entire RAM 55 is backed up.

  The reset signal from the power supply board 910 is input to the reset terminal of the game control microcomputer 560, but the reset signal from the power supply board 910 is delayed by the delay circuit 69 in the main board 31. The reset signal is shared as a game control permission signal (a signal for making the CPU operable) for the game control microcomputer 560 and a payout control permission signal for the payout control microcomputer 370 (see FIG. 6). Therefore, the delay circuit 69 is configured such that the timing at which the game control permission signal is input to the game control microcomputer 560 is greater than the timing at which the payout control permission signal is input to the payout control microcomputer 370. This is delayed for a period determined by the amount of delay. When the reset signal becomes high level, the game control microcomputer 560 and the payout control microcomputer 370 become operable, and when the reset signal becomes low level, the game control microcomputer 560 and the payout control microcomputer 370 become The operation stops. Therefore, during the period in which the reset signal is at a high level, an allowable signal that allows the operation of the game control microcomputer 560 and the payout control microcomputer 370 is output, and the period in which the reset signal is at a low level. Thus, an operation stop signal for stopping the operations of the game control microcomputer 560 and the payout control microcomputer 370 is output.

  Further, a power-off signal indicating that the power supply voltage from the power supply board 910 has decreased to a predetermined value or less is input to the input port of the basic circuit 53 via the payout control board 37. A clear signal indicating that the clear switch 921 for instructing to clear the contents of the RAM is operated is input to the input port of the basic circuit 53.

  The hitting ball launching device for hitting and launching the game ball includes a launch motor 94 controlled by a circuit on the launch board 90, and the launch motor 94 rotates to launch the game ball toward the game area 7. A drive signal for driving the firing motor 94 is transmitted from the main board 31 to the firing motor 94 via the launch board 90. The touch sensor detects that the player is touching the operation knob (hitting ball handle) 5, and the touch sensor circuit (player touches the operation knob 5) mounted on the launch board 90. A circuit including a detection circuit or the like for detecting whether or not there is. When the signal from the touch sensor circuit indicates an off state, the circuit on the launch board 90 stops transmission of the drive signal from the main board 31 to the launch motor 94 using, for example, an AND circuit, The driving of the firing motor 94 is stopped. The operation knob 5 is provided with a touch ring that adjusts the resilience and is a part that the player contacts. In the gaming machine, the launch board 90 is disposed between the touch ring and the main board 31 and is disposed in the vicinity of the touch ring. Specifically, the wiring length between the touch ring and the launch board 90 is shorter than the wiring length between the launch board 90 and the main board 31.

  In this embodiment, the effect control means (configured by the effect control microcomputer) mounted on the effect control board 80 is the effect from the game control microcomputer 560 via the central relay board 77. A control command is received, and display control of the variable display device 9 that performs variable display of decorative symbols and the like is performed. The lamp control means (comprised of a lamp control microcomputer) mounted on the lamp control board 35 includes a normal symbol display 10, a normal symbol start memory display 41 provided on the game board 6, and The display control of the decoration lamp 25 is performed, and the display control of the top frame lamp 28a, the left frame lamp 28b, and the right frame lamp 28c provided on the frame side is performed.

  Further, the game control microcomputer 560 used in this embodiment has a non-maskable interrupt terminal (NMI terminal) used to generate a non-maskable interrupt (NMI) that cannot be set to disable interrupt by software. ) And an interrupt terminal (INT terminal) used to generate an interrupt (external interrupt; maskable interrupt that can be interrupted by software) from outside the game control microcomputer 560. However, this embodiment does not use non-maskable interrupts and external interrupts. Therefore, the NMI terminal and the INT terminal are pulled up to Vcc (+5 V) through resistors. Therefore, the input levels of the NMI terminal and the INT terminal are always high, and there is a possibility that the input level of the NMI terminal and the INT terminal falls due to noise or the like, and an interrupt is generated, as compared with the case where the terminal is open. To reduce.

  FIG. 6 is a block diagram showing components related to payout, such as the payout control board 37 and the ball payout device 97. As shown in FIG. 6, a payout control microcomputer 37 (an example of an electric component control microcomputer) 370 including a payout control CPU 371 is mounted on the payout control board 37. In this embodiment, the payout control microcomputer 370 is a one-chip microcomputer and incorporates at least a RAM. The payout control microcomputer 370, the RAM (not shown), the ROM (not shown) storing the payout control program, the I / O port, and the like constitute the payout control means. That is, the payout control means is realized by a payout control CPU 371, a payout control microcomputer 370 having a RAM and a ROM, and an I / O port. The I / O port may be built in the payout control microcomputer 370. At least a part of the RAM in the payout control microcomputer 370 is backed up by a backup power source mounted on the power supply board 910. In this embodiment, it is assumed that all RAM areas are backed up. Therefore, even when power is not supplied to the gaming machine, the storage contents of the RAM are preserved for a predetermined period (until the backup power supply cannot be supplied because the capacitor as the backup power supply is discharged).

  Detection signals from the ball break switch 187, the full switch 48, and the payout count switch 301 are input to the I / O port 372 f of the payout control board 37 via the relay board 72. A detection signal from the payout motor position sensor 295 is input to the I / O port 372e of the payout control board 37 via the relay board 72. The payout motor position sensor 295 is a sensor comprising a light emitting element (LED) and a light receiving element for detecting the rotational position of the payout motor 289, and is used for detecting that the game ball is clogged, that is, so-called ball biting. . The payout control microcomputer 370 mounted on the payout control board 37 receives a detection signal (non-reserved detection signal) indicating a ball-out state from the ball-out switch 187 and a full-out from the full switch 48. When a detection signal (storage detection signal) indicating the tongue state is input, the ball payout process is stopped.

  Further, a detection signal (storage detection signal) indicating a full state from the full tank switch 48 is branched by the payout control board 37 (see FIG. 7), and the payout control microcomputer 370 as a low level fullness signal. Each is input to the launch board 90. A drive signal (launch control signal) from the game control microcomputer 560 to the launch motor 94 is transmitted to the launch motor 94 via the launch board 90. When the full tank signal is input to the launch board 90, transmission of the drive signal to the launch motor 94 on the launch board 90 is stopped, and the ball launch from the hitting ball launcher is stopped. The full signal branched by the payout control board 37 is inputted to one of the input sides of the AND circuit 91 mounted on the launch board 90, and the launch control signal from the game control microcomputer 560 is sent from the AND circuit 91. Input to the other input side. The output signal of the AND circuit 91 is input to the firing motor 94. That is, the output of the drive signal to the firing motor 94 is stopped while the full tank signal branched by the payout control board 37 is being output (while it is at the low level).

  In this example, the game control microcomputer 560 outputs a drive signal (launch control signal) to the launch motor 94, but without receiving a signal from the game control microcomputer 560, The launch board 90 may be configured to always output a drive signal to the launch motor 94 as long as power is supplied. Even when the launch board 90 always outputs a drive signal, when the full signal is output by the AND circuit 91 or the like, or when the signal from the touch sensor circuit indicates an off state, etc. In that case, the drive signal to the firing motor 94 is stopped.

  When there is a winning at the winning opening, the output circuit 67 of the main board 31 outputs a prize ball number signal indicating the number of prize balls to be paid out (turns on) as a payout command signal. Further, when the game control microcomputer 560 is started up (when the operation is started), a payout start command (payout start command) is output. Then, a prize ball REQ signal (prize ball request signal) for instructing to take in a prize ball number signal or a payout activation command is output (turned on).

  In this embodiment, the prize ball number signal and the payout activation command are transmitted through the same signal line. The award ball number signal and the payout activation command are composed of 5-bit data (binary 5-digit data) and are output through five signal lines. Note that the on state of the signal, that is, the output state is a state where the signal is significant, and turning on means that the signal receiving side is instructed to start some processing based on the signal. To do. For example, when the prize ball number signal indicating the number of prize balls and the prize ball REQ signal are turned on, this means that the payout control means is instructed to recognize the number of prizes indicated by the prize ball number signal. To do.

  The prize ball number signal and the payout activation command are input to the I / O port 372e via the input circuit 373A. The prize ball REQ signal is input to a maskable interrupt terminal (hereinafter also simply referred to as an interrupt terminal) of the payout control CPU 371. The payout control CPU 371 inputs the prize ball number signal via the I / O port 372e in the interrupt process based on the prize ball REQ signal being inputted to the interrupt terminal, and the number of prize balls indicated by the prize ball number signal is indicated. In order to pay out the game ball, the ball paying device 97 is controlled to be driven. A power supply confirmation signal (connection confirmation signal) indicating that the main board 31 is connected is also output from the output circuit 67 of the main board 31.

  The payout control microcomputer 370 transmits a command receivable state signal to the main board 31 when preparation for execution of the payout control process is completed after power supply to the gaming machine is started. The command receivable state signal is transmitted to the main board 31 via the output port 372b of the payout control board 37 and the output circuit 373B. Then, in the main board 31, the data is input to the CPU 56 via the input circuit 68 and the I / O port 57. In this embodiment, when the command receivable state signal is turned on, the main board 31 is notified that the command receiving process by the external terminal interrupt can be executed.

  In this example, when the payout control microcomputer 370 confirms the payout of one prize ball based on the detection signal from the payout number count switch 301, it outputs a prize ball count signal to the main board 31. Send. Further, the payout control means means an error related to game ball payout (an error indicating that the game ball payout process cannot be performed. When this occurs, a payout error signal is transmitted to the main board 31. The prize ball count signal and the payout error signal are transmitted to the main board 31 via the output port 372b and the output circuit 373B of the payout control board 37. Then, in the main board 31, the data is input to the CPU 56 via the input circuit 68 and the I / O port 57.

  In addition, a power-off signal indicating that the power supply voltage has dropped below a predetermined value and a clear signal indicating that the clear switch 921 for clearing the contents of the RAM has been operated are input from the power supply board 910 to the input port 372g. Is input.

  The payout control microcomputer 370 receives, via the output port 372b, a prize ball information signal indicating the number of prize balls to be paid and a ball lending number signal indicating the number of balls to be lent. Output to 160). A driver circuit is provided outside the output port 372b, but is not shown in FIG.

  Also, the payout control microcomputer 370 outputs an error signal to the error display LED 374 using a 7-segment LED via the output port 372c. Further, a signal for instructing turning on / off is output to the winning ball LED 51 and the ball running out LED 52 via the output port 372b. A detection signal from an error release switch 375 for releasing the error state is input to the input port 372f of the payout control board 37. The error cancel switch 375 is used to cancel the error state by software reset.

  Further, a drive signal from the payout control microcomputer 370 to the payout motor 289 is transmitted to the payout motor 289 in the payout mechanism portion of the ball payout device 97 via the output port 372a and the relay board 72. Although a driver circuit (motor drive circuit) is installed outside the output port 372a, the description is omitted in FIG.

  A card unit control microcomputer is mounted on the card unit 50 installed adjacent to the gaming machine. In addition, the card unit 50 is provided with a usable display lamp, a connecting table direction indicator, a card insertion display lamp, and a card insertion slot. A frequency display LED 60, a ball lending LED 61, a ball lending switch 62, and a return switch 63 provided in the vicinity of the hitting ball supply tray 3 are connected to the interface board (relay board) 66.

  A card lending switch signal indicating that the ball lending switch 62 has been operated and a return switch signal indicating that the return switch 63 has been operated are provided to the card unit 50 from the interface board 66 in accordance with the player's operation. . Further, a card balance display signal indicating a prepaid card balance and a ball lending display signal are given from the card unit 50 to the interface board 66. Between the card unit 50 and the payout control board 37, a connection signal (VL signal), a unit operation signal (BRDY signal), a ball lending request signal (BRQ signal), a ball lending completion signal (EXS signal) and a pachinko machine operation signal ( PRDY signal) is transmitted / received via the input port 372f and the output port 372d. An interface board 66 is interposed between the card unit 50 and the payout control board 37. Therefore, a signal such as a connection signal (VL signal) is transmitted and received between the card unit 50 and the payout control board 37 via the interface board 66 as shown in FIG.

  When the power of the pachinko gaming machine 1 is turned on, the payout control microcomputer 370 mounted on the payout control board 37 outputs a PRDY signal to the card unit 50. The card unit control microcomputer outputs a VL signal when the power is turned on. The payout control microcomputer 370 determines the connected / unconnected state of the card unit 50 according to the input state of the VL signal. When a card is received in the card unit 50, the ball lending switch is operated and a ball lending switch signal is input, the card unit control microcomputer outputs a BRDY signal to the payout control board 37. When a predetermined delay time elapses from this point, the card unit control microcomputer outputs a BRQ signal to the payout control board 37.

  Then, the payout control microcomputer 370 raises the EXS signal to the card unit 50 and, when detecting the fall of the BRQ signal from the card unit 50, drives the payout motor 289 to give a predetermined number of rental balls to the player. Pay out. When the payout is completed, the payout control microcomputer 370 causes the EXS signal to the card unit 50 to fall. Thereafter, on the condition that the BRDY signal from the card unit 50 is not in the ON state, the winning ball payout control is executed when a payout command signal is received from the game control means.

  The power supply voltage AC24V used in the card unit 50 is supplied from the payout control board 37. That is, power supply from the power supply board 910 to the card unit 50 is performed via the payout control board 37 and the interface board 66. In this example, a fuse for protecting the card unit 50 is provided in a 24 V AC power supply line for the card unit 50 arranged in the interface board 66, and a voltage higher than a predetermined voltage is supplied to the card unit 50. It is prevented.

  The payout control microcomputer 370 used in this embodiment includes a non-maskable interrupt terminal (NMI terminal) used for generating a non-maskable interrupt (NMI) and a maskable interrupt. And an interrupt terminal (INT terminal) used for generation. However, this embodiment does not use non-maskable interrupts and external interrupts. Therefore, the NMI terminal and the INT terminal are pulled up to Vcc (+5 V) through resistors.

  In this embodiment, the case where the card unit 50 is installed adjacent to the gaming machine as a separate body from the gaming machine is taken as an example, but the card unit 50 may be integrated with the gaming machine. . Further, the present invention can be applied even in the case where game balls corresponding to the amount of money are lent out in accordance with coin insertion.

  FIG. 7 is a block diagram illustrating a circuit configuration example for transmitting signals transmitted and received between the card unit 50 and the payout control board 37. As shown in FIG. 7, the connection signal (VL signal) from the card unit 50 is input to the payout control board 37 via the interface board 66. The VL signal input to the payout control board 37 is input to the payout control microcomputer 370 via the photocoupler 151 mounted on the payout control board 37. Note that passive elements such as a resistor 152 and capacitors 153 and 154 are connected to the photocoupler 151.

  In this example, an output signal from the photocoupler 151 is branched on the payout control board 37 and input to one of the input sides of the AND circuit 155, and is branched to the other input side of the AND circuit 155 at the payout control board 37. One of the full signals is input. The output of the AND circuit 155 is input to one of the input sides of the AND circuit 91 mounted on the launch board 90. Therefore, when the output signal from the photocoupler 151 is at a low level, or when a low level full signal is output, it is connected to one of the input sides of the AND circuit 91 mounted on the launch board 90. The low level signal is input, and the output of the drive signal to the firing motor 94 is stopped regardless of the state of the firing control signal inputted to the other input side of the AND circuit 91.

  A unit operation signal (BRDY signal) from the card unit 50 is input to the payout control board 37 via the photocoupler 66a mounted on the interface board 66, and is input to the payout control microcomputer 370. Similarly, a ball lending request signal (BRQ signal) from the card unit 50 is input to the payout control board 37 via the photocoupler 66b mounted on the interface board 66, and is input to the payout control microcomputer 370.

  Further, a ball lending completion signal (EXS signal) from the payout control microcomputer 370 is input to the card unit 50 via the photocoupler 66 c mounted on the interface board 66. Similarly, a pachinko machine operation signal (PRDY signal) from the payout control microcomputer 370 is input to the card unit 50 via a photocoupler 66 d mounted on the interface board 66.

  Since the photocoupler 151 for transmitting the VL signal transmitted from the card unit 50 to the payout control microcomputer 370 is mounted on the payout control board 37 as described above, the resistor connected to the photocoupler 151 Passive elements such as the condenser 152 and the capacitors 153 and 154 can also be mounted on the dispensing control board 37, and no capacitor can be mounted on the interface board 66. Therefore, when any illegal circuit is attached to the interface board 66 or when the interface board 66 is replaced with an illegal board, the illegal action can be easily detected. In other words, if there is a capacitor on the interface board 66 that should not be mounted at all, it can be determined that some sort of fraud is being performed, so that fraud can be easily detected. , Will be able to prevent fraud.

  In a conventional gaming machine, a capacitor is mounted on an interface board as described in, for example, Japanese Patent Application Laid-Open No. 2001-347054 (particularly FIG. 11). Therefore, when a fraudulent board having an illegal circuit for inputting an illegal signal to the payout control microcomputer is created on the interface board and the authorized interface board is replaced with the illegal board, the board is replaced. There was a problem that it was difficult to discover.

  For example, a fraudulent interface is provided with a fraudulent circuit for inputting a signal for executing a payout operation to the payout control board even though no winning is made or a ball lending request is not made. A substrate is assumed. Then, the unauthorized interface board is illegally attached, and a signal output command is issued from the unauthorized interface board to the payout control board by an operation from the outside of the gaming machine (for example, button operation, wireless communication operation). ) May be illegally acquired to illegally acquire game media. When creating an illegal interface board, a capacitor is required to stabilize a circuit (or a signal output from the illegal interface board) mounted on the illegal interface board, and a passive element such as a capacitor is used. Will be mounted on the unauthorized interface board.

  On the other hand, in this example, since the capacitor is not mounted on the interface board 66 at all, it is easily determined whether or not the board is an illegal board only by checking whether or not the capacitor is mounted on the interface board. be able to. In addition, when the capacitors 153 and 154 of the VL signal line are mounted on the payout control board 37, the photocoupler 151 is also mounted on the payout control board 37, and therefore, between the interface board 66 and the payout control board 37. In this case, it is possible to eliminate unnecessary reciprocation of the signal path, and to save space and reduce the number of wires.

  In the example shown in FIG. 7, only the photocoupler 151 to which the resistor 152 and the capacitors 153 and 154 are connected is mounted on the payout control board 37. However, the card unit 50 and the payout control board 37 All the photocouplers 151 and 66a to 66d that transmit signals transmitted and received between them may also be mounted on the dispensing control board 37. With this configuration, when there is a photocoupler that should not be mounted at all on the interface board 66, it can be determined that some sort of fraud is being performed.

  Further, as described above, the output of the VL signal (lending request accepting apparatus connection signal) from the photocoupler 151 mounted on the payout control board 37 is branched, and the payout control microcomputer 370 and the launch motor 94 are driven. Since it is configured to be input to the firing substrate 90 that transmits the firing control signal, the driving of the firing motor 94 can be stopped according to the transmission state of the VL signal by the photocoupler 151. As shown in FIG. 6, the VL signal transmitted by the photocoupler 151 branched by the payout control board 37 and transmitted to the launch board 90 and the launch control signal from the main board 31 are input to the AND circuit 91. Is done. Therefore, in this example, when the VL signal transmitted by the photocoupler 151 is in the off state (low level state), or when the low level full signal is output, the emission control from the main board 31 is controlled. Regardless of the state of the signal, the firing control signal that is the output signal from the AND circuit 91 is maintained in the OFF state. Therefore, when the photocoupler 151 is not transmitting the VL signal, the driving of the firing motor 94 is stopped.

  FIG. 8 is a block diagram showing a connection state of main boards provided in the gaming machine. In this example, the signal from the main board 31 to the peripheral board (excluding the payout control board 37. The signal is not limited to being formed as a board but includes a terminal board in which a plurality of terminals are arranged) is concentrated. It is output via the relay board 77. In the example shown in FIG. 8, signals to the information terminal board 34 and the effect control board 80 are output via the concentrated relay board 77. Note that the detection signals of the respective switches (such as the above-described prize opening switch) provided in the gaming machine are input to the main board 31 via the switch relay board 78.

  FIG. 8 illustrates the information terminal board 34 and the effect control board 80, but when there are more boards as peripheral boards for inputting signals from the main board 31, the main board 31 is shown. Is preferably output to all peripheral boards via one centralized relay board 77. That is, it is preferable that one central relay board 77 is provided for all peripheral boards. Furthermore, a drive signal from a solenoid circuit 59 (see FIG. 5) that outputs a drive signal to a solenoid as an electrical component that is one of the gaming devices may be routed through the centralized relay board 77.

  Although not shown, the central relay board 77 is accommodated in a board box on the back side of the gaming machine. That is, the central relay board 77 is housed in a board box as a housing means and attached to the gaming machine. The board box has a structure in which a box body in which the central relay board 77 is accommodated is covered with a lid. The box body and the lid are formed of a synthetic resin or the like that can be visually recognized from the outside (for example, transparent). When the lid portion of the substrate box is closed and fixed to the mechanism plate, the surface side of the central relay substrate 77 can be visually recognized through, for example, a transparent lid portion. Further, in the state in which the lid portion of the substrate box is opened, the back surface side of the central relay substrate 77 can be visually recognized through the back surface of the transparent box body, for example. As described above, since the front and back surfaces of the central relay board 77 can be easily seen from the outside of the board box, it is possible to easily investigate whether the central relay board 77 is fraudulent.

  FIG. 9 is an explanatory diagram showing a signal output unit in the main board 31 and components mounted on the centralized relay board 77. As shown in FIG. 9, in the main board 31, an information output circuit 64 for outputting a signal from the basic circuit 53 (specifically, an output port of the game control microcomputer) to the information terminal board 34, and an effect control board 80 The output buffer circuit 67 (not shown in FIG. 5) that outputs a signal passes only in the direction toward the central relay board 77 (does not pass the signal in the direction from the central relay board 77 to the main board 31). ) It consists of a unidirectional circuit as a signal direction regulating means. As the unidirectional circuit, a transistor or an IC circuit is used. Note that the unidirectional circuit may have a current amplification function.

  The signal output from the main board 31 to the central relay board 77 connects the connector 31A mounted on the main board 31, the connector 77A mounted on the central relay board 77, and the connector 31A and the connector 77A. The signal is transmitted to the central relay board 77 by a cable. The central relay board 77 is a signal direction regulating means that allows a signal input from the main board 31 to pass only in the direction toward the peripheral board (no signal is passed in the direction from the peripheral board to the central relay board 77). The unidirectional circuits 74 and 76 are mounted. As the unidirectional circuits 74 and 76, for example, a diode or a transistor is used. FIG. 9 illustrates a diode. Unidirectional circuits 74 and 76 are provided for each signal.

  In the example shown in FIG. 9, the signal output to the information output circuit 64 is output via the connector 77 </ b> B mounted on the central relay board 77. The signal output to the effect control board 80 is output via the connector 77D mounted on the central relay board 77.

  FIG. 9 shows an example in which a signal is output from the main board 31 to the centralized relay board 77 via one connector, but centralized relaying from the main board 31 via a plurality of connectors and cables is shown. A signal may be output to the substrate 77. In this embodiment, the signal between the main board 31 and the payout control board 37 does not pass through the central relay board 77, but as a signal between the main board 31 and the payout control board 37, from the main board 31. When there is only a signal directed to the payout control board 37, a signal from the main board 31 toward the payout control board 37 may be configured to pass through the central relay board 77.

  In addition to the signal direction regulating means, noise removing components such as a noise filter may be mounted on the centralized relay board 77. That is, in the relay board, all the signals input from the game control board (or main signals such as production control commands and INT signals for which noise countermeasures are particularly required, that is, if they are not input correctly, the game progress is hindered. It is preferable that noise removing means is provided for the signal. By mounting the noise removing component, it is possible to reduce the possibility that noise is added to the signal reaching the peripheral board even if the wiring length between the main board 31 and the peripheral board is long. Further, the central relay board 77 may be equipped with an amplifying means for amplifying a signal (for example, a current for the signal) input from the main board 31. In the case of such a configuration, amplification processing is performed on the relay substrate, so that the amplification circuit mounted on the main substrate 31 or the peripheral substrate can be eliminated.

  FIG. 10 is a block diagram illustrating a circuit configuration example of the effect control board 80, the frame side lamp driver board 35, and the sound control board 70. In the example shown in FIG. 10, the frame side lamp driver substrate 35 is not equipped with a microcomputer. In the effect control board 80, the effect control CPU 101 in the effect control microcomputer operates in accordance with a program stored in a ROM (not shown), and a strobe signal from the main board 31 input via the centralized relay board 77. An effect control command is received via the input port 103 in response to the (effect control INT signal). Further, the effect control CPU 101 causes the VDP 109 to execute display control of the variable display device 9 using the LCD based on the effect control command.

  The effect control command and the effect control INT signal are first input to the input driver 102 on the effect control board 80. The input driver 102 passes the signal input from the centralized relay board 77 only in the direction toward the inside of the effect control board 80 (the signal passes in the direction from the inside of the effect control board 80 to the centralized relay board 77). It is also a unidirectional circuit as signal direction regulating means.

  Further, the production control CPU 101 outputs sound number data to the sound control board 70 via the output port 104 and the output driver 110. A bus (including an address bus, a data bus, and a control signal line such as a write / read signal) input / output to / from the effect control CPU 101 is extended to the frame side lamp driver board 35 via the bus driver 105. . Further, the production control CPU 101 inputs an operation signal indicating whether or not an operation has been performed by the player from the operation switch 81.

  In the frame side lamp driver substrate 35, a bus that is input to and output from the effect control CPU 101 is connected to the output port 352 via the bus receiver 351. A signal for driving each lamp output from the output port 352 is amplified by the lamp driver 354 and supplied to each lamp. A signal for driving each LED output from the output port 352 is amplified by the LED driving circuit 355 and supplied to each LED.

  In this embodiment, the lamps / LEDs provided on the frame side are controlled by effect control means including an effect CPU 101 mounted on the effect control board 80. Further, data for controlling the variable display device 9 and lamps / LEDs are stored in the ROM. The effect CPU 101 controls the variable display device 9 and the lamps / LEDs based on the data stored in the ROM. Then, the lamp / LED is driven through the output port 352 mounted on the frame side lamp driver substrate 35 and each driver or drive circuit.

  The effect control board 80, the frame side lamp driver board 35, and the sound control board 70 are independent boards, but are installed in a single box on the back of the gaming machine, for example.

  In the sound control board 70, the sound number data from the effect control board 80 is input to a sound control CPU (in this example, a sound control microcomputer incorporating an I / O port) 701 via an input driver 702. . When the sound control CPU 701 receives the sound number data from the effect control board 80, it outputs a response signal to the effect control board 80. In the effect control board 80, the response signal is input to the effect control CPU 101 via the input port 103. In this embodiment, in response to a voice control command (sound number data) transmitted from the effect control board 80 to the voice control board 70, a response signal is transmitted from the voice control board 70 to the effect control board 80. Although the command is transmitted by the directional communication, the command may be transmitted from the effect control board 80 to the sound control board 70 by the unidirectional communication. In FIG. 10, the input / output driver for the response signal is not shown, but it is preferable to provide an input / output driver for passing the response signal as in the case of the voice control command.

  The voice control CPU 701 reads data corresponding to the sound number data from the voice data ROM 704, and outputs a control signal corresponding to the read data to the voice synthesis IC 703 using a digital signal processor, for example. The voice synthesis IC 703 generates voice and sound effects according to the control signal input from the voice control CPU 701 and outputs the voice and sound effects to the amplifier circuit 705. The amplification circuit 705 outputs an audio signal obtained by amplifying the output level of the speech synthesis IC 703 to a level corresponding to the volume set by the volume 706 to the speaker 27. Note that the voice control board 70 may not be equipped with a voice control microcomputer. In this case, the sound number data from the effect control CPU 101 is input to the speech synthesis IC 703. When the voice control board 70 is not equipped with a voice control microcomputer, the voice synthesis IC 703 receives a feedback signal for confirming voice operation in response to receiving a signal from the effect control CPU 101. Is output to the CPU 101 for effect control.

  Next, the configuration of the power supply substrate 910 will be described with reference to the block diagram of FIG. The power supply board 910 is provided with a power switch 914 for executing or shutting off power supply to each electrical component control board and mechanism component in the gaming machine. Note that the power switch 914 may be provided outside the power supply board 910 in the gaming machine. When the power switch 914 is in a closed state (on state), AC power (AC 24 V) is applied to the rectifier circuit 912 via a varistor 918 as an overvoltage protection circuit. In other words, power is supplied to the gaming machine.

  The power supply board 910 is installed independently of the electrical component control board (the main board 31 and the payout control board 37 and the like), and generates a voltage used by each board and mechanism component in the gaming machine. In this example, AC24V, VSL (DC + 30V), VLP (DC + 24V), VDD (DC + 12V) and VCC (DC + 5V) are generated. Further, a capacitor 916 serving as a storage holding means for holding the stored contents in the backup power supply (VBB), that is, the backup RAM, is charged from DC + 5V (VCC), that is, a power supply line for driving an IC or the like on each substrate. Further, a backflow prevention diode 917 is inserted between the +5 V line and the backup +5 V (VBB) line. Note that VSL is generated by rectifying and boosting AC 24 V with a rectifying element in the rectifying and smoothing circuit 915. VSL is a solenoid driving power source. VLP is a lamp lighting voltage, and is generated by rectifying AC24V with a rectifier element in the rectifier circuit 912.

  A DC-DC converter 913 serving as a power supply voltage generation unit has one or a plurality of regulator ICs (two regulator ICs 924A and 924B are shown in FIG. 11), and generates VDD and VCC based on VSL. Relatively large capacitors 923A and 923B are connected to the input sides of the regulator ICs (switching regulators) 924A and 924B. Accordingly, when the power supply to the gaming machine from the outside is stopped, the DC voltages such as VSL, VDD, VCC, etc., decrease relatively slowly.

  As shown in FIG. 11, AC24V is supplied to the connector 922B as it is. The VLP is supplied to the connector 922C. VCC, VDD and VSL are supplied to connectors 922A, 922B and 922C.

  The cable connected to the connector 922A is connected to the main board 31. The cable connected to the connector 922B is connected to the payout control board 37. Therefore, VBB is also supplied to the connectors 922A and 922B. The cable connected to the connector 922C is connected to the lamp control board 35. Each voltage is supplied to the effect control board 80 and the sound control board 70 via the lamp control board 35.

  In addition, a clear switch 921 having a push button structure is mounted on the power supply board 910. When the clear switch 921 is pressed, a clear switch signal at a low level (on state) is output and transmitted to the payout control board 37 via the connector 922B. If the clear switch 921 is not pressed, a high level (off state) signal is output. The clear switch 921 may have a configuration other than the push button structure. Further, the clear switch 921 may be provided on a board other than the power supply board 910 such as the payout control board 37 or other places in the gaming machine.

  Further, the power supply board 910 has a system reset signal for each microcomputer mounted on each electric component control board (the microcomputer operation is prohibited at the reset level, and the microcomputer can be operated when the non-reset level is reached). Power supply monitoring circuit 920 that outputs a power-off signal, and a reset signal from the power-supply monitoring circuit 920 are amplified and output to the connectors 922A, 922B, and 922C, and the power-off signal is amplified. An output driver circuit 925 for outputting to the connector 922B is mounted. The system reset signal for the game control microcomputer 560 and the payout control microcomputer 370 is directly transmitted to the main board 31 and the payout control board 37, but the system reset signal for the display control microcomputer and the voice control microcomputer. Is transmitted to the effect control board 80 and the sound control board 70 via the lamp control board 35. However, it may be transmitted directly from the power supply board 910 to each of the effect control board 80, the lamp control board 35, and the sound control board 70.

  The power supply monitoring circuit 920 is a circuit that realizes power supply monitoring means for outputting a power-off signal and reset signal generation means for generating a system reset signal. A commercially available power failure monitoring reset module IC is used as the power supply monitoring circuit 920. be able to. The power supply monitoring circuit 920 outputs a power-off signal when a period during which a predetermined voltage (for example, + 24V) used in the gaming machine is equal to or lower than a predetermined value (for example, + 17V) continues for a predetermined time (for example, 56 ms). . Specifically, the power-off signal is turned on (low level). Further, the power supply monitoring circuit 920 enters a state in which the system reset signal can be set to a low level when, for example, VCC becomes +4.5 V or less.

  When the power supply to the gaming machine is stopped, the power supply monitoring circuit 920 sets the system reset signal to a low level when a predetermined period has elapsed after the power-off signal is output (set to a low level). Become. In addition, when the power supply to the gaming machine is started and VCC exceeds +4.5 V, for example, the system reset signal is set to high level. In this case, after the power-off signal is not output (set to high level). From the condition that the predetermined period has elapsed, the system reset signal is set to the high level.

  The power-off signal from the power monitoring circuit 920 is input to the payout control CPU 371 via the input port 372g on the payout control board 37 (see FIG. 5). Therefore, the payout control CPU 371 can confirm the occurrence of the stop of the power supply to the gaming machine by monitoring the input signal of the input port 372g.

  In this embodiment, the power supply monitoring means monitors the output of the power supply of a predetermined potential, and the voltage from the outside of the gaming machine (this implementation) is used as a detection condition related to the stop of the supply of power supplied to the gaming machine from the outside. However, the detection condition is not limited to this, and other conditions can be used as long as it is possible to detect that power from the outside has been cut off These conditions may be used. For example, the AC wave itself may be monitored and the AC wave may be detected as a detection condition, or the signal obtained by digitizing the AC wave may be monitored and the AC signal may be stopped when the digital signal becomes flat. May be used as a detection condition.

  12 and 13 are explanatory diagrams showing examples of output port assignment in the game control means. As shown in FIG. 12, the output port 0 is an output port for prize ball number signals (CD0 to CD4) transmitted to the payout control board 37. Further, 8-bit data (CD0 to CD7) of the effect control command transmitted to the effect control board 80 is output from the output port 1.

  Further, from the output port 2, a solenoid (large winning port door solenoid) 21 for opening and closing the opening / closing plate 2 of the large winning port, a solenoid (large winning port guide plate solenoid) 21A for switching the route in the large winning port, and a variable A drive signal for a solenoid (normal electric accessory solenoid) 16 for opening and closing the winning ball apparatus 15 is output. Further, an effect control INT signal (strobe signal) for the effect control command transmitted to the effect control board 80 is also output. The effect control INT signal is a signal for instructing the effect control means to capture 8-bit data of the effect control command. Further, signals of each phase supplied to the firing motor 94 by the stepping motor are output from the output port 2.

  Then, various information output signals from the output ports 3 and 4 to the information terminal board 34 and the terminal board 160 through the information output circuit 64, that is, output data of information related to control are output.

  FIG. 14 is an explanatory diagram showing an example of bit assignment of input ports in the game control means. As shown in FIG. 14, the bits 0 to 7 of the input port 0 are detected by the V count switch 22, the count switch 23, the gate switch 32a, the winning port switches 33a, 39a, 29a and 30a, and the start port switch 14a, respectively. A signal is input. In addition, bits 0 to 1, 3 to 6 of the input port 1 respectively include a power-off signal from the power supply monitoring board 910, a detection signal of the clear switch 921 from the power supply board 910, a switch common monitoring signal, and a payout control board 37. The command reception enable state signal, the award ball count signal and the payout error signal from the payout control board 37 are input. The detection signal from each switch is logically inverted in the input driver circuit 58. Further, the prize ball count signal and the payout error signal are logically inverted in the input circuit 68.

  Next, the operation of the gaming machine will be described. FIG. 15 and FIG. 16 are flowcharts showing a main process executed by the game control means on the main board 31. When the gaming machine is turned on and the input level of the reset terminal to which a reset signal is input becomes high, the CPU 56 performs a security check process that is a process for confirming whether the contents of the program are valid. After execution, the main processing after step S1 is started. In the main process, the CPU 56 first performs necessary initial settings.

  In the initial setting process, the CPU 56 first sets the interrupt prohibition (step S1). Next, the interrupt mode is set to interrupt mode 2 (step S2), and a stack pointer designation address is set to the stack pointer (step S3).

  Next, a software delay process for delaying the start timing of the game device control process (game control process) for controlling the progress of the game by software is executed. Specifically, first, the initialization wait number specification value 1 is set in the wait counter 1 (step S4). Further, the initialization wait number specification value 2 is set in the wait counter 2 (step S5). Note that general-purpose registers (HL register and BC register) built in the CPU 56 are used as the wait counters 1 and 2. Then, the value of the wait counter 2 is decremented by 1 until the value of the wait counter 2 becomes 0 (steps S6 and S7). When the value of the weight counter 2 becomes 0, the value of the weight counter 1 is decremented by 1 (step S8). When the value of the weight counter 1 is not 0 (step S9), the process returns to step S5. If the value of the wait counter 1 is 0, the software delay process is terminated.

  By the software delay processing (steps S4 to S9) as described above, only [(initialization wait number specification value 1) × (initialization wait number specification value 2) × (processing time of steps S6, S7)] is obtained. The start timing of the game control process can be delayed as compared with the case where the software delay process is not executed. In other words, the initialization weight count designation values 1 and 2 are determined so that the start timing of the game control process can be delayed by a desired time. Note that the values of the initialization wait times designation values 1 and 2 are set in the ROM 54. Further, the software delay processing described here is an example, and the software delay processing may be realized by other methods.

  The CPU 56 used in this embodiment also incorporates an I / O port (PIO) and a timer / counter circuit (CTC) as built-in devices (built-in peripheral circuits). A clock / timer trigger input CLK / TRG 2 and 3 and two timer outputs ZC / TO 0 and 1 are provided.

  When the software delay processing is completed, the built-in device registers are initialized (settings such as input / output assignment of the built-in devices) and the built-in devices CTC (counter / timer) and PIO (parallel input / output port) are initialized It performs (step S10). The initialization of PIO is, for example, setting an off state value to all bits of the output port. The initialization of the CTC is a timer mode setting or the like.

  The CPU 56 used in this embodiment is provided with the following three modes as maskable interrupt modes. When a maskable interrupt occurs, the CPU 56 automatically sets the interrupt disabled state and saves the contents of the program counter in the stack.

  Interrupt mode 0: The built-in device that has issued the interrupt request sends an RST instruction (1 byte) or a CALL instruction (3 bytes) onto the internal data bus of the CPU. Therefore, the CPU 56 executes the instruction at the address corresponding to the RST instruction or the address specified by the CALL instruction. At reset, the CPU 56 automatically enters interrupt mode 0. Therefore, when setting to interrupt mode 1 or interrupt mode 2, it is necessary to perform a process for setting to interrupt mode 1 or interrupt mode 2 in the initial setting process.

  Interrupt mode 1: In this mode, when an interrupt is accepted, the mode always jumps to address 0038 (h).

  Interrupt mode 2: A mode in which the address synthesized from the value (1 byte) of the specific register (I register) of the CPU 56 and the interrupt vector (1 byte: least significant bit 0) output by the built-in device indicates the interrupt address It is. That is, the interrupt address is an address indicated by 2 bytes in which the upper address is the value of the specific register and the lower address is the interrupt vector. Therefore, an interrupt process can be set at an arbitrary address (although it is skipped). Each built-in device has a function of sending an interrupt vector when making an interrupt request.

  Therefore, when the interrupt mode 2 is set, it becomes possible to easily process an interrupt request from each built-in device, and it is possible to install an interrupt process at an arbitrary position in the program. . Furthermore, unlike interrupt mode 1, it is also easy to prepare each interrupt process for each interrupt generation factor. As described above, in this embodiment, the CPU 56 is set to the interrupt mode 2 in step S2 of the initial setting process.

  Next, the CPU 56 executes a payout start command transmission process for transmitting a payout start command (payout start command) to the payout control board 37 (step S11), and then sets the RAM 55 in an accessible state (step S12).

  Then, the CPU 56 confirms the state of the output signal of the clear switch 921 input via the input port 1 only once (step S13). When the on-state is detected in the confirmation, the CPU 56 executes normal initialization processing (steps S21 to S27). When the clear switch 921 is on (when pressed), a low-level clear switch signal is output. In the input port 1, the clear switch signal is in the low level. Further, for example, the game clerk can easily execute the initialization process by starting the power supply to the gaming machine (for example, turning on the power switch 914) while turning the clear switch 921 on. That is, RAM clear or the like can be performed.

  If the clear switch 921 is not in the on state, whether or not data protection processing of the backup RAM area (for example, power supply stop processing such as addition of parity data) has been performed when power supply to the gaming machine is stopped Confirm (step S14). In this embodiment, when power supply is stopped, a process for protecting data in the backup RAM area is performed. If it is confirmed that such protection processing has been performed, the CPU 56 determines that there is a backup. When it is confirmed that such a protection process has not been performed, the CPU 56 executes an initialization process.

  Whether or not the protection process has been performed depends on the value of the backup monitoring timer stored in the backup RAM area in the power supply stop process described later according to the execution of the data protection process in the backup RAM area (for example, It is confirmed by whether or not 2). Note that such a confirmation method is an example. For example, a flag indicating that data protection processing has been executed is set in the backup flag area in the power supply stop processing, and the flag is set in step S14. If it is confirmed that there is a backup, it may be determined that there is backup.

  If it is determined that there is a backup, the CPU 56 performs a data check of the backup RAM area (parity check in this example) (step S15). In this embodiment, clear data (00) is set in the checksum data area, and the checksum calculation start address is set in the pointer. Also, the number of checksum calculations corresponding to the number of data to be checksum is set. Then, the exclusive OR of the contents of the checksum data area and the contents of the RAM area pointed to by the pointer is calculated. The calculation result is stored in the checksum data area, the pointer value is incremented by 1, and the checksum calculation count value is decremented by 1. The above processing is repeated until the value of the checksum calculation count becomes zero. When the value of the checksum calculation count reaches 0, the CPU 56 inverts the value of each bit of the contents of the checksum data area and uses the inverted data as the checksum.

  In the power supply stop process, a checksum is calculated by the same process as described above, and the checksum is stored in the backup RAM area. In step S15, the calculated checksum is compared with the stored checksum. When the power supply is stopped after an unexpected power failure or the like, the data in the backup RAM area should be saved, so the check result (comparison result) is normal (matched). That the check result is not normal means that the data in the backup RAM area is different from the data when the power supply is stopped. In such a case, since the internal state cannot be returned to the state when the power supply is stopped, the initialization process (the process of steps S21 to S27) executed at the time of power-on that is not the time of recovery from the stop of the power supply is performed. Execute.

  If the check result is normal, the CPU 56 performs a game state restoration process for returning the internal state of the game control means and the control state of the electric component control means such as the display control means to the state when the power supply is stopped. Specifically, the start address of the backup setting table stored in the ROM 54 is set as a pointer (step S16), and the contents of the backup setting table are sequentially set in the work area (area in the RAM 55) (step S17). ). The work area is backed up by a backup power source. In the backup setting table, initialization data for an area that may be initialized in the work area is set. As a result of the processing in steps S16 and S17, the saved contents of the work area that should not be initialized remain. The portion that should not be initialized is, for example, a portion in which data indicating a gaming state before stopping power supply (a special symbol process flag or the like) or data indicating the number of unpaid prize balls is set.

  Next, the CPU 56 confirms whether or not the command receivable state signal from the payout control board 37 is on (step S18). That is, it is confirmed whether or not the payout control board 37 is in a state in which a signal input process corresponding to the external terminal interrupt can be executed.

  When the CPU 56 confirms that the command receivable state signal is ON, the CPU 56 sets the start address of the backup command transmission table stored in the ROM 54 as a pointer (step S19), and the sub-board (payout control) according to the contents. Control is performed such that a control command indicating that the power supply has been restored is transmitted to the board 37 and the effect control board 80) (step S20). Then, the process proceeds to step S27.

  In the initialization process, the CPU 56 first performs a RAM clear process (step S21). The entire area of the RAM 55 may not be initialized, and predetermined data (for example, count value data of a counter for generating a big hit determination random number) may be left as it is. For example, if the count value data of the counter for generating the big hit determination random number is left as it is, the big hit determination random number is generated even if the initialization process is executed by unauthorized means. Therefore, it is difficult to aim at the timing at which the count value of the counter matches the jackpot determination value. Further, the initial address of the initialization setting table stored in the ROM 54 is set as a pointer (step S22), and the contents of the initialization setting table are sequentially set in the work area (step S23). By the processing in steps S22 and S23, for example, a normal symbol determination random number counter, a normal symbol determination buffer, a special symbol left middle right symbol buffer, a total prize ball number storage buffer, a special symbol process flag, an award ball flag, a ball break An initial value is set for a flag for selectively performing processing according to a control state, such as a flag or a payout stop flag.

  Next, the CPU 56 checks whether or not the command receivable state signal from the payout control board 37 is on (step S24). That is, it is confirmed whether or not the payout control board 37 is in a state in which a signal input process corresponding to the external terminal interrupt can be executed.

  When confirming that the command receivable state signal is in the on state, the CPU 56 sets the start address of the initialization command transmission table stored in the ROM 54 as a pointer (step S25), and initializes the sub-board according to the contents. A process of transmitting an initialization command for converting to a sub-board is executed (step S26). Examples of the initialization command include a command indicating an initial symbol displayed on the variable display device 9.

  In step S27, the CPU 56 sets a CTC register built in the CPU 56 so that a timer interrupt is periodically generated every predetermined time (for example, 4 ms). That is, a value corresponding to, for example, 4 ms is set as an initial value in a predetermined register (time constant register). In this embodiment, it is assumed that a timer interrupt is periodically taken every 4 ms.

  When the execution of the initialization process (steps S21 to S27) is completed, the CPU 56 repeatedly executes the display random number update process (step S29) and the initial value random number update process (step S30). The CPU 56 disables the interrupt when the display random number update process and the initial value random number update process are executed (step S28), and interrupts when the display random number update process and the initial value random number update process are completed. The permitted state is set (step S31). The display random number is a random number for determining a symbol displayed on the variable display device 9, and the display random number update process is a process for updating the count value of the counter for generating the display random number. It is. The initial value random number update process is a process for updating the count value of the counter for generating the initial value random number. The initial value random number is a random number for determining an initial value of a count value such as a counter for generating a random number for determining whether or not to make a big hit (a big hit determination random number generation counter). Game control processing described later (a game control microcomputer controls a game device such as a variable display device 9, a variable winning ball device, a ball payout device, etc. provided in the game machine itself, or other In a process of sending a command signal to cause the microcomputer to control, also referred to as a gaming apparatus control process), when the count value of the jackpot determination random number generation counter makes one round, an initial value is set in the counter.

  Note that when the display random number update process and the initial value random number update process are executed, the interrupt disabled state is caused by the timer interrupt process described later. This is to avoid conflict with the processing in the timer interrupt processing. That is, if a timer interrupt is generated during the processing of steps S29 and S30 and the count value of the counter for generating the display random number and the initial value random number is updated during the timer interrupt processing, The continuity of values may be impaired. However, such an inconvenience does not occur if the interrupt disabled state is set during the processes of steps S29 and S30.

  FIG. 17 is a flowchart showing the payout activation command transmission process in step S11. In the payout activation command transmission process, the CPU 56 outputs [1, 0, 0, 0, 0] (the position of “1” is bit 4) to the lower 5 bits of the output port 0 (see FIG. 12) (step S61). ). That is, a payout activation command is output to the output port 0 as a 5-bit prize ball number signal. Next, bit 6 of the output port 0 is set to “0” (step S62). That is, the prize ball REQ signal is turned on. Then, a delay process for setting the ON time of the prize ball REQ signal is performed by software (step S63). In this delay processing, for example, a value corresponding to the delay time is set in a general-purpose register (HL register or BC register), and processing for decrementing the register value by −1 is repeatedly executed, so that the register value becomes zero. Then, the process ends. The delay time is set to a time sufficient for the payout control CPU 371 to recognize that the prize ball REQ signal has been input to the interrupt terminal.

  Then, bit 6 of the output port 0 is set to “1” (step S64). That is, the prize ball REQ signal is turned off. Thereafter, the lower 5 bits of the output port 0 are set to [0, 0, 0, 0, 0] (step S65). That is, all 0 is output as the award ball number signal.

  FIG. 18 is a timing chart showing how the microcomputer operates when power supply to the gaming machine is started and when power supply is stopped. Here, a case where the initialization process is executed when power supply is started will be described as an example. When power supply to the gaming machine is started and the voltage of the DC + 24V power supply exceeds a predetermined value, the power-off signal is turned off. When the value of VCC exceeds a predetermined value, the reset signal becomes high level. As described above, the power supply monitoring circuit 920 sets the reset signal to high level after turning off the power-off signal. The reset signal is input to the main board 31 and the payout control board 37 and is input to the effect control board 80 via the lamp driver board 36. Then, it is input to the reset terminal of the payout control CPU 371 mounted on the payout control board 37 and the effect control CPU 101 mounted on the effect control board 80.

  When the reset signal input to the main board 31 is input to the reset terminal of the CPU 56 (when the input level of the reset terminal becomes high level), the CPU 56 is ready to operate (the microcomputer is reset and the program is executed). However, when the operation is enabled, the CPU 56 first executes a security check process for confirming whether or not the contents of the ROM are valid based on the security check program. When the security check process ends, a software delay process is executed. Thereafter, the payout activation command transmission process is executed, and then the state of the output signal of the clear switch 921 is checked, and then a part of the initialization process (a process other than the command transmission process) is performed. After that, a command reception ready state signal reception wait state is entered. When receiving the command receivable state signal, the game control process is started after executing a part of the initialization process. If the output signal of the clear switch 921 indicates an on state, RAM clear processing or the like is performed.

  The payout control CPU 371 becomes operable when the reset signal becomes high level. When in an operable state, first, a part of the initial setting process is executed. Thereafter, it waits for the payout start command to be transmitted from the main board 31. If the payout start command can be received, it performs processing for checking the state of the output signal of the clear switch 921, and then transmits the command receivable state signal. The process is executed, and thereafter the payout control process is started. If the output signal of the clear switch 921 indicates an on state, RAM clear processing or the like is performed.

  The CPU 56 transmits a payout activation command immediately before performing the process of checking the state of the output signal of the clear switch 921, and the payout control CPU 371 checks the state of the output signal of the clear switch 921 after confirming the payout start command. I do. Further, when the CPU 56 starts the payout activation command transmission process by executing the security check process and the software delay process, the payout control CPU 371 waits for the payout start command to be transmitted.

  Therefore, for example, it is possible to prevent a situation in which the on state of the output signal of the clear switch 921 is not detected by the CPU 56 even though the on state of the output signal of the clear switch 921 is detected by the payout control CPU 371. The On the other hand, it is possible to prevent a situation in which the on state of the output signal of the clear switch 921 is not detected by the payout control CPU 371 even though the on state of the output signal of the clear switch 921 is detected by the CPU 56. . That is, since the confirmation process of whether or not the operation means is operated is performed almost simultaneously, the state of the output signal of the clear switch 921 in the game control microcomputer 560 and the payout control microcomputer 370 is confirmed. The results can be matched, and when the clear switch 921 is pressed, the contents of each variation data storage means can be initialized reliably.

  In this example, the payout control CPU 371 starts the payout control process after transmitting the command receivable state signal, and the CPU 56 performs part of the initialization process (performs command transmission) after confirming the command receivable state signal. After executing (part), the game control process is started. Therefore, the payout control command received by the external terminal interruption is reliably prevented from being transmitted by the CPU 56 before the payout control process is started. Therefore, it is possible to reliably avoid the payout control command from being missed.

  When the power supply to the gaming machine is stopped, the voltage of the DC + 24V power supply also gradually decreases. However, when the voltage of the DC + 24V power supply falls below a predetermined value, the power supply monitoring circuit 920 outputs a power-off signal (set to a low level). ). The power-off signal is input to the main board 31 and the payout control board 37. The game control means mounted on the main board 31 and the payout control means mounted on the payout control board 37, according to the power-off signal being output, the power supply stop process (both power-off control process) Say). The power supply monitoring circuit 920 sets the reset signal to a low level when VCC falls below a predetermined value. The game control means mounted on the main board 31 and the payout control means mounted on the payout control board 37 are system reset in response to the reset signal becoming low level. That is, the CPU 56 and the payout control CPU 371 are not operated. Note that the power supply monitoring circuit 920 sets the reset signal to a low level when a predetermined time elapses from the time when the power supply cutoff signal is output when the power supply voltage decreases.

  Next, the game control process will be described. FIG. 19 is a flowchart showing the timer interrupt process. If a timer interrupt occurs during execution of the main process, specifically, during the execution of the loop process of steps S28 to S31, the CPU 56 performs a timer interrupt process that is activated in response to the occurrence of the timer interrupt. A game control process is executed. In the timer interrupt process, the CPU 56 first executes a power-off process (power-off detection process) for detecting whether or not a power-off signal has been output (whether the power-off signal has been turned on) (step S40). Further, an excitation pattern output process for the firing motor 94 (output of the patterns of the firing motors φ1 to φ4 to the output port 0) is performed (step S41). In the firing motor control process in step S42, the excitation pattern is stored in the excitation pattern buffer that is the RAM area. In step S41, the CPU 56 performs a process of outputting the contents of the excitation pattern buffer to the upper 4 bits of the output port 2. Do.

  Next, the CPU 56 executes a firing motor control process (step S42). In the firing motor control process, the patterns of the firing motors φ1 to φ4 are stored in the excitation pattern buffer.

  Next, the CPU 56 inputs detection signals of switches such as the gate switch 32a, the start port switch 14a, the count switch 23, and the winning port switches 29a, 30a, 33a, and 39a via the switch circuit 58, and determines their state. Performed (switch processing: step S43). Specifically, if the state of the input port for inputting the detection signal of each switch is ON, the value of the switch timer provided corresponding to each switch is incremented by one. In addition, in response to receiving a prize ball count signal from the payout control board 37, a process for notifying a player that a prize ball has been paid out, specifically, a prize ball payout confirmation designation command is displayed and controlled. The process (refer FIG. 28) transmitted to the board | substrate 80 is performed (prize ball notification process: step S44).

  Next, a process of updating the count value of each counter for generating each determination random number such as a big hit determination random number used for game control is performed (step S45). The CPU 56 further performs a process of updating the count value of the counter for generating the display random number and the initial value random number (steps S46 and S47).

  Further, the CPU 56 performs special symbol process processing (step S48). In the special symbol process control, corresponding processing is selected and executed according to a special symbol process flag for controlling the pachinko gaming machine 1 in a predetermined order according to the gaming state. The value of the special symbol process flag is updated during each process according to the gaming state. Further, normal symbol process processing is performed (step S49). In the normal symbol process, the corresponding process is selected and executed according to the normal symbol process flag for controlling the display state of the normal symbol display 10 in a predetermined order. The value of the normal symbol process flag is updated during each process according to the gaming state.

  Next, the CPU 56 performs a process of setting an effect control command related to the decorative design in a predetermined area of the RAM 55 and sending the effect control command (decorative design command control process: step S50). Further, a process for setting the effect control command for the normal symbol in a predetermined area of the RAM 55 and sending the effect control command is performed (normal symbol command control process: step S51).

  Further, the CPU 56 performs information output processing for outputting data such as jackpot information, start information, probability variation information supplied to the hall management computer, for example (step S52).

  Further, the CPU 56 executes a prize ball process for setting the number of prize balls based on detection signals from the prize opening switches 29a, 30a, 33a, 39a and the like (step S53). Specifically, a prize ball number signal indicating the number of prize balls is output to the payout control board 37 in response to detection of a prize based on turning on the prize opening switches 29a, 30a, 33a, 39a and the like. The payout control CPU 371 mounted on the payout control board 37 drives the ball payout device 97 according to the prize ball number signal indicating the number of prize balls.

  And CPU56 performs the memory | storage process which checks the increase / decrease in the number-of-start winning memory | storage number (step S54). In addition, a test terminal process, which is a process for outputting a test signal for enabling the control state of the gaming machine to be confirmed outside the gaming machine, is executed (step S55). In this embodiment, a RAM area (output port buffer) corresponding to the output state of the output port is provided, but the CPU 56 relates to the solenoid in the RAM area of the output port 2 (see FIG. 12). Is output to the output port (step S56: solenoid output processing). Thereafter, the interrupt permission state is set (step S57), and the process ends.

  With the above control, in this embodiment, the game control process is started periodically (for example, every 4 ms). In this embodiment, the game control process is executed by the timer interrupt process. However, in the timer interrupt process, for example, only a flag indicating that an interrupt has occurred is set, and the game control process is performed by the main process. May be executed. Further, the processing of steps S41 to S56 (excluding steps S52 and S55) corresponds to a game control process for controlling the progress of the game.

  20 and 21 are flowcharts showing an example of the power-off process in step S40. In the power-off process, the CPU 56 first checks whether or not a power-off signal is output (whether it is in an on state) (step S450). If not on, the value of the backup monitoring timer formed in the RAM 55 is cleared to 0 (step S451). If it is on, the value of the backup monitoring timer formed in the RAM 55 is incremented by 1 (step S452). If the value of the backup monitoring timer matches the determination value (for example, 2) (step S453), the power supply stop processing after step S454, that is, the preparation processing for power supply stop is executed. That is, the state shifts from the state in which the progress of the game is controlled to the state in which the power supply stop process (the power-off control process) for saving the game state is executed.

  By using the backup monitoring timer and the determination value, if the power-off signal is kept on for a time corresponding to the determination value, the power supply stop process is started. That is, even when the power-off signal is turned on for a moment due to noise or the like, the power supply stop process is not erroneously started. Note that the value of the backup monitoring timer formed in the RAM 55 is stored by the backup power source for a predetermined period even if the power supply to the gaming machine is stopped. Therefore, in step S14 in the main process, it can be confirmed that the process result of the power supply stop process is stored because the value of the backup monitoring timer is the same as the determination value.

  In the power supply stop process, the CPU 56 creates parity data (steps S454 to S463). That is, first, clear data (00) is set in the checksum data area (step S454), and the checksum calculation start address corresponding to the start address of the RAM area in which the contents are to be stored even when power supply is stopped is set in the pointer. (Step S455). Further, the number of checksum calculations corresponding to the final address of the RAM area where the contents are to be stored even when the power supply is stopped is set (step S456).

  Next, an exclusive OR of the contents of the checksum data area and the contents of the RAM area pointed to by the pointer is calculated (step S457). The calculation result is stored in the checksum data area (step S458), the value of the pointer is incremented by 1 (step S459), and the value of the checksum calculation count is decremented by 1 (step S460). Then, the processes in steps S457 to S460 are repeated until the value of the checksum calculation count becomes 0 (step S461).

  When the value of the checksum calculation count becomes 0, the CPU 56 inverts the value of each bit of the contents of the checksum data area (step S462). Then, the inverted data is stored in the checksum data area (step S463). This data becomes parity data to be checked when the power is turned on. Next, an access prohibition value is set in the RAM access register (step S471). Thereafter, the built-in RAM 55 cannot be accessed.

  Further, the CPU 56 sets the head address of the port clear setting table stored in the ROM 54 as a pointer (step S472). In the port clear setting table, the number of processes (the number of output ports to be cleared) is set to the head address, and then the output port address and output value data (clear data: the value of the off state of each bit of the output port) However, the output ports for the number of processes are sequentially set.

  The CPU 56 loads data at the address pointed to by the pointer (that is, the number of processes) (step S473). Further, the value of the pointer is incremented by 1 (step S474), and the data at the address pointed to by the pointer (that is, the output port address) is loaded (step S475). Further, the value of the pointer is incremented by 1 (step S476), and the data of the address pointed to by the pointer (that is, output value data) is loaded (step S477). Then, the output value data is output to the output port (step S478). Thereafter, the number of processes is reduced by 1 (step S479), and if the number of processes is not 0, the process returns to step S474. If the number of processes is 0, that is, if all the output ports to be cleared are cleared, the timer interrupt is stopped (step S481) and the loop process is started.

  In the loop processing, it is monitored whether or not the power-off signal is turned off (step S482). When the power-off signal is turned off, the execution address at power-on (address in step S1) is set as a return address and a return command is executed (step S483). That is, the process returns to the main process. Specifically, a state in which a gaming device provided in the gaming machine is controlled (a concept including both controlling by itself and sending a command signal to cause another microcomputer to control). Return.

  When the power supply is stopped by the above process, the power supply stop process in steps S454 to S481 is executed, and data indicating that the power supply stop process has been executed (specified value with backup and checksum) Is stored in the backup RAM, the RAM access is disabled, the output port is cleared, and the timer interrupt for executing the game control process is disabled.

  In this embodiment, the entire area of the RAM 55 is backed up by a backup power source (the contents of the RAM 55 are preserved for a predetermined period even when power supply to the gaming machine is stopped). Therefore, the checksum based on the contents of the RAM 55 when the power-off signal is output is stored in the RAM 55 together with the value of the backup monitoring timer by the processing in steps S452 to S479. After the power supply to the gaming machine is stopped, when the power supply is restored within a predetermined period, the game control means performs data stored in the RAM 55 (immediately before the power supply is stopped) by the processing of steps S16 to S20 described above. In accordance with the data indicating the game state that is the control state by the game control means (for example, including the process flag state, the big hit flag state, the probability change flag state, the output port output state, etc.) It is possible to return to the state immediately before the supply is stopped. If the power supply stop period exceeds the predetermined period, the value of the backup monitoring timer and the checksum should be different from the regular values. In this case, the initialization process of steps S21 to S27 is executed. The

  As described above, the power supply stop process (preparation process for stopping the power supply) ensures that the data for returning the gaming state to the state immediately before the power supply stopped is the fluctuation data storage means (in this example) Stored in the entire area of the RAM 55). Therefore, even if the power is cut off due to a power failure or the like, if the power is restored within a predetermined period, the gaming state can be returned to the state immediately before the power supply is stopped. The entire area of the RAM 55 may not be backed up by power, but only the area for storing data for returning the gaming state to the state immediately before the power supply is stopped may be backed up.

  If the power-off signal is turned off, the process returns to step S1. In this case, since data indicating that the power supply stop process has been executed is set, the game state recovery process of steps S16 to S20 is executed. Therefore, when the detection signal from the power supply monitoring unit is turned off after executing the power supply stop process, the process returns to the state of controlling the progress of the game. Therefore, even if a power interruption or the like occurs, the game control process does not stop, and the game control process is automatically continued.

  The connection confirmation signal transmitted to the payout control board 37 is set to the off state by the process of clearing the output port. In the setting of the work area in steps 17 and S23, the content of the output port buffer corresponding to the connection confirmation signal is set to a value corresponding to the ON state of the connection confirmation signal. When the prize ball processing in step S53 is executed, the contents of the output port buffer are output to the output port, so that the connection confirmation signal to the payout control board 37 is turned on. Therefore, the connection confirmation signal is output (turned on) when the main board 31 rises. Note that a connection confirmation signal is also output when the power supply is recovered from an instantaneous power interruption or the like.

  FIG. 22 is a flowchart showing the firing motor control process in step S42. In the firing motor control process, the CPU 56 increments the firing motor excitation pattern counter by 1 (step S151). Then, data corresponding to the value of the excitation pattern counter is read from the firing motor excitation pattern table stored in the ROM 54 (step S152). Further, the read data is set in the firing motor excitation pattern buffer (step S153). As described above, the contents of the firing motor excitation pattern buffer are output to the output port in step S41. In the firing motor excitation pattern table, the excitation pattern data (shooting motors φ1 to φ4) for each step for rotating the firing motor 94 is sequentially set.

  Next, the switch process (step S43) in the main process will be described. In this embodiment, when the ON state of the detection signal of each switch related to winning detection or gate passage continues for a predetermined time, it is determined that the switch is surely turned on, and processing corresponding to the switch on is started. FIG. 23 is an explanatory diagram showing each 1-byte buffer formed in the RAM 55 used in the switching process. The previous port buffer is a buffer in which the previous switch-on / off determination result (for example, 4 ms before) is stored. The port buffer is a buffer in which the contents of port 0 inputted this time are stored. The switch-on buffer is a buffer in which the corresponding bit is set to 1 when switch on is detected and the corresponding bit is set to 0 when switch off is detected.

  FIG. 24 is a flowchart illustrating a processing example of the switch processing in step S43 in the game control processing. In the switch process, the CPU 56 first inputs data input to the input port 0 (see FIG. 14) (step S101), and sets the input data in the port buffer (step S102). Next, the initial value of the weight counter formed in the RAM 55 is set (step S103), and the value of the weight counter is decremented by 1 until the value of the weight counter becomes 0 (steps S104 and S105).

  When the value of the wait counter becomes 0, the data of the input port 0 is input again (step S106), and a logical product is obtained for each bit between the input data and the data set in the port buffer (step S106). S107). Then, the logical product operation result is set in the port buffer (step S108). Of the two input data input from the input port 0 with a time interval of approximately [initial value of weight counter × (processing time of steps S14 and S105)] by the processing of steps S103 to S108, both “ Only the bits that are “1” will be “1” in the port buffer. In other words, if the ON state of the switch detection signal continues for a predetermined period [initial value of wait counter × (processing time of steps S14 and S105)], the corresponding bit in the port buffer becomes “1”.

  Further, the CPU 56 performs exclusive OR for each bit between the data previously set in the port buffer and the data set in the port buffer (step S109). In the result of the exclusive OR operation, the bit corresponding to the switch for which the previous switch-on / off determination result (for example, 4 ms before) differs from the switch-on / off determination result determined to be on this time is “ 1 ”. The CPU 56 further performs a logical product for each bit between the operation result of the exclusive OR and the data set in the port buffer (step S110). As a result, of the bits corresponding to the switches for which the previous switch on / off determination result and the switch on / off determination result determined to be on this time are different (according to the exclusive OR operation result), the current on Only the bit corresponding to the switch determined to be (by AND operation) remains as “1”.

  Then, the CPU 56 sets the operation result of the logical product in step S110 in the switch-on buffer (step S111), and sets the contents of the port buffer in which the operation result in step S108 is set in the previous port buffer (step S112). .

  By the above processing, among the switches that have been on for a predetermined period of time, the switch on / off determination result of the previous time (for example, 4 ms ago) was off, that is, the switch changed from the off state to the on state. The bit corresponding to the switch is “1” in the switch-on buffer.

  Next, control signals transmitted and received between the main board 31 and the payout control board 37 will be described. FIG. 25 is an explanatory diagram showing an example of the contents of a control signal output from the game control means to the payout control means and a control signal input from the payout control means to the game control means. In this embodiment, a plurality of types of control signals are transmitted and received between the main board 31 and the payout control board 37 in order to perform various controls relating to payout control and the like. As shown in FIG. 25, the connection confirmation signal is output when the main board 31 rises (when the game control means starts the game control process), and indicates that the main board 31 has risen with respect to the payout control board 37. This is a signal for notification (connection confirmation signal for the main board 31). The connection confirmation signal indicates that the winning ball can be paid out. In this embodiment, since the game control means transmits the payout activation command before starting the game control process, the connection confirmation signal need not be used. When the connection confirmation signal is not used, the payout activation command also serves as a signal indicating that the prize ball can be paid out.

  The prize ball REQ signal is a signal that is in an output state (= ON state) when a prize ball is requested to be dispensed or when a dispensing activation command is transmitted. In addition, the prize ball REQ signal is in a stopped state (off state = all 0 state) when a predetermined period of time elapses after the on state is turned on. The award ball number signal is used as a signal (award ball number command) output for designating the number of game balls (1 to 15) for which a payout request is made.

  The command receivable state signal is a signal that is turned on when the payout control means can execute command input processing by external terminal interruption. That is, when the command receivable state signal is on, it indicates that the command input processing by the external terminal interrupt is executable, and when the command receivable state signal is off, the external terminal interrupt Indicates that command input processing cannot be executed.

  The prize ball count signal is a signal that is turned on when the payout control means confirms the payout of one prize ball, and is turned off after a predetermined period. The payout error signal is a signal that is turned on when an error state relating to payout occurs and is turned off when the error state is canceled.

  FIG. 26 is a block diagram showing signal lines and the like used for transmission / reception of each control signal shown in FIG. As shown in FIG. 26, the connection confirmation signal, the prize ball REQ signal, and the prize ball number signal are output by the CPU 56 via the output circuit 67 and input to the payout control CPU 371 via the input circuit 373A. Further, the command receivable state signal, the prize ball count signal, and the payout error signal are output by the payout control CPU 371 via the output circuit 373B and input to the CPU 56 via the input circuit 68. Each of the connection confirmation signal, the prize ball REQ signal, the command receivable state signal, the prize ball count signal, and the payout error signal is 1-bit data and is transmitted through one signal line. The award ball number signal designates 1 to 15 award ball payouts and is also used as a payout start command, so is composed of 5-bit data and transmitted through 5 signal lines.

  FIG. 27 is a timing chart showing an example of how to output a prize ball number signal. As shown in FIG. 27, the game control means transmits a payout start command (payout start command) to the payout control means in connection with the start of power supply to the gaming machine. Specifically, 10 (H) is output as the prize ball number signal, and the prize ball REQ signal is turned on.

  The payout control means sets the command receivable state signal to the on state before starting the payout control process after executing the initial setting process or the like in response to the reception of the payout activation command. When the game control means confirms that the command receivable state signal is on, the game control means starts the game control process. The game control means turns on the connection confirmation signal when starting the game control process.

  Thereafter, when the winning detection switch detects the winning of the game ball, the game control means turns on the winning ball REQ signal and sets the output state of the winning ball number signal according to the number of winning balls to be paid out according to the winning. To the state. In this embodiment, when a game ball is detected by the start port switch 14a, four prize balls are paid out, and when a game ball is detected by any of the prize port switches 33a, 39a, 29a, 30a. Seven prize balls are paid out. When a game ball is detected by the V count switch 22 or the count switch 23, 15 prize balls are paid out. As described above, since the prize ball number signal is composed of 5 bits, the lower 5 bits of the prize ball number commands of 00 (H) to 0F (H) represented by 8 bits are The signal is transmitted from the main board 31 to the payout control board 37 by the award ball number signal. Hereinafter, it may be expressed as “00 (H) to 0F (H) prize ball number signal”, but in reality, the prize ball number signal is represented by 8 bits. This corresponds to the lower 5 bits of 0F (H). When the prize ball number signal is used to transmit the number of prize balls to be paid out in accordance with winning, the most significant bit (bit 4) is 0.

  FIG. 28 is a timing chart showing an example of how to output a prize ball count signal. As shown in FIG. 28, the payout control CPU 371, when the payout number count switch 301 detects the payout of the game ball, confirms whether or not the detection is the detection of the payout of the prize ball. For example, the prize ball count signal is turned on for a predetermined period (eg, 0.5 seconds). That is, each time a payout of one prize ball is confirmed, the prize ball count signal is turned on for a predetermined period. Therefore, for example, the payout count switch 301 detects the payout of seven game balls. If the detected game ball is a prize ball, the on / off of the prize ball count signal is repeated seven times.

  In the above-described prize ball notification process (step S44), the CPU 56 receives a prize ball payout confirmation designation control command (award ball payout) indicating that a prize ball has been paid out each time a prize ball count signal is received. Confirmation designation command) is transmitted to the production control board 80. The production control board 80 outputs a control signal to the frame-side lamp driver board 35 every time a prize ball payout confirmation designation command is received, and executes control to turn on a predetermined lamp for a predetermined period (for example, 0.5 seconds), for example. To do. The effect control board 80 may be configured to control the prize ball lamp 51, and the prize ball lamp 51 may be turned on each time a prize ball payout confirmation designation command is received.

  It should be noted that every time the CPU 56 receives a prize ball count signal, the CPU 56 has sent a prize ball payout confirmation designation command to the effect control board 80 indicating that the payout of one prize ball has been confirmed. When a predetermined number (for example, 7 times) of winning ball count signals indicating the number of winning balls (for example, 7) are received, it indicates that the predetermined number (for example, 7) of winning balls has been confirmed. A prize ball payout confirmation designation command may be transmitted to the effect control board 80, and the payout of the first prize ball out of a predetermined number (for example, 7) prize balls to be paid out is detected. In response to receiving a prize ball count signal based on the prize ball, a prize ball payout confirmation designation command indicating that a predetermined number (for example, seven) of prize balls has been paid out is transmitted to the effect control board 80. It may be. In this case, when the effect control board 80 receives a prize ball payout confirmation designation command indicating that a predetermined number of prize balls have been paid out, the effect control board 80 has confirmed the payout of one prize ball as described above. It is preferable to execute control to turn on a predetermined lamp (for example, the prize ball lamp 51 controlled by the effect control board 80) for a longer period (for example, 3 seconds) than when a prize ball payout confirmation designation command is received.

  FIG. 29 is a timing chart showing an example of how to output a payout error signal. As shown in FIG. 29, the payout control CPU 371 turns on the payout error signal when it shifts to the error state, and turns off the payout error signal when the error state is canceled. In this example, a payout error signal is output when an error state occurs due to the occurrence of an error related to payout of a game ball. Specifically, for example, the payout error signal is output when the lower pan is full, the ball is out, or a communication abnormality occurs between the main board 31 and the payout control board 37.

  As shown in FIG. 29, when the CPU 56 mounted on the main board 31 receives an error signal from the payout control CPU 371 (when the error signal is turned on), it is displayed as a display control command toward the effect control board 80. Send an error occurrence notification command. The error occurrence notification command is a command indicating that an error has occurred. In addition, when the error signal from the payout control CPU 371 is stopped (when the error signal is turned off), the CPU 56 transmits an error release notification command as a display control command to the effect control board 80. The error release notification command is a command indicating that the error state has been released.

  When receiving the error occurrence notification command from the CPU 56, the effect control CPU 101 mounted on the effect control board 80 displays the error display on the variable display device 9 and executes a process of notifying the error condition. To do. The notification of the error state is performed by displaying, for example, characters or figures such as “An error has occurred!” In the display area of the variable display device 9. In addition, when receiving the error release notification command from the CPU 56, the production control CPU 101 deletes the error display displayed on the variable display device 9 to notify that it is in an error state, and is in an error state. Is terminated.

  As described above, the error notification is made when an error state occurs, so that it is possible to easily notify the player or game clerk that an error has occurred.

  FIG. 30 is a flowchart showing an example of the prize ball processing in step S51. In the prize ball process, the CPU 56 executes a prize ball number addition process (step S201) and a prize ball control process (step S202). Then, the contents of the port 0 buffer formed in the RAM 55 are output to port 0 (step S203). The contents of the port 0 buffer are updated in the prize ball control process.

  In the winning ball number adding process, a winning ball number table shown in FIG. 31 is used. The prize ball number table is set in the ROM 54. The number of processes (in this example, “7”) is set in the top address of the winning ball number table, and then the lower address of the switch-on buffer, and each switch of the winning opening that will pay out the winning ball by winning. The switch input bit determination value and the number of winning balls are sequentially set corresponding to each switch of the winning opening. The switch input bit determination value is a value corresponding to the bit to which the detection signal of each switch at the input port 0 is input (see FIG. 14). The upper address of the switch-on buffer is a fixed value (for example, 7F (H)).

  FIG. 32 is a flowchart showing the prize ball number adding process. In the winning ball number adding process, the CPU 56 sets the start address of the winning ball number table in the pointer (step S211). Then, the data at the address pointed to by the pointer (in this case, the number of processes) is loaded (step S212). Next, the upper address (8 bits) of the switch-on buffer is set in the upper 1 byte of the 2-byte check pointer (step S213).

  Then, the value of the pointer is incremented by 1 (step S214), the prize ball number table data pointed to by the pointer (in this case, the lower address of the switch-on buffer) is set in the lower 1 byte of the check pointer (step S215), The pointer value is increased by 1 (step S216). Next, the address data pointed to by the check pointer, that is, the contents of the switch-on buffer is loaded into the register (step S217), and the loaded contents and the data of the prize ball number table pointed to by the pointer (in this case, the switch input bit judgment value) ) And the logical product (step S218). As a result, 7 bits other than the bit corresponding to the detection signal of the switch to be inspected become 0 in the register loaded with the contents of the switch-on buffer. Then, the pointer value is incremented by 1 (step S219).

  If the calculation result in step S218 is 0, that is, if the detection signal of the switch to be inspected is on, the prize ball number table data pointed to by the pointer (in this case, the prize ball number) is used as the prize ball addition value. (Steps S220 and S221), and the prize ball addition value is added to the contents of the 16-bit total prize ball number storage buffer formed in the RAM 55 (step S222). The total winning ball number storage buffer is formed in the backup RAM. If a carry occurs as a result of the addition, the content of the total number of winning balls storage buffer is set to 65535 (= FFFF (H)) (steps S223 and 224). Further, “formed in RAM” means an area in the RAM.

  In step S225, the number of processes is reduced by 1. If the number of processes is 0, the process ends. If the number of processes is not 0, the process returns to step S214 (step S226). In step S220, when it is confirmed that the calculation result in step S218 is 0, that is, the detection signal of the switch to be inspected is in the OFF state, the process proceeds to step S225.

  FIG. 33 is a flowchart showing the prize ball control process in step S201. In the prize ball control process, the CPU 56 executes any one of steps S231 to S233 according to the value of the prize ball process code.

  FIG. 34 is a flowchart showing the prize waiting process 1 (step S231) executed when the value of the prize ball process code is zero. In the award ball waiting process 1, the CPU 56 sets the award ball waiting output value (60 (H)) in the port 0 buffer (step S243). When the output value during waiting for a prize ball is set in the port 0 buffer, the contents of the port 0 buffer are output to port 0 in step S203, whereby the prize ball REQ signal is turned off, and the connection confirmation signal The on state is maintained (see FIG. 12). In addition, the award ball number signal enters an invalid command (00 (H)).

  Next, the CPU 56 checks whether or not the prize ball timer is 0 (step S244). If the prize ball timer is not 0, the value of the prize ball timer is decreased by 1 (step S245), and the process is terminated. The prize ball timer is a timer for measuring the time required for prize ball processing. At this stage, if the value of the prize ball timer is not 0, the next prize ball after the previous payout process is completed. Waiting time until the REQ signal is turned on (time for providing an interval between the ON periods of a plurality of prize ball REQ signals when prize ball payout is continuously executed, 00 (H ) During which the award ball number signal is output). The prize ball timer is set in step S263 of the prize ball waiting process 2 described later. In addition, after the execution of the prize ball process 2 in step S233 is completed and the previous payout process is completed, the process of steps S243 to S245 sets the prize ball REQ signal to the OFF state and the invalid command as the prize ball number signal. This is a process for outputting (00 (H)).

  If the value of the prize ball timer is 0, the CPU 56 then checks the contents of the total prize ball number storage buffer (step S247). If the value is 0, the process ends. If not, the value of the prize ball process code is set to 1 (step S248), and the process ends.

  FIG. 35 is a flowchart showing a prize ball transmission process (step S232) executed when the value of the prize ball process code is 1. In the prize ball transmission process, the CPU 56 checks whether or not the content of the total prize ball number storage buffer is smaller than the prize ball command maximum value (“15” in this example) (step S251). If the content of the total prize ball number storage buffer is equal to or greater than the prize ball command maximum value, the prize ball command maximum value is set in the prize ball number buffer (step S252). If the content of the total prize ball number storage buffer is smaller than the maximum value of the prize ball command, the content of the total prize ball number storage buffer is set in the prize ball number buffer (step S253).

  Thereafter, the output value (20 (H)) during the prize ball REQ is set in the output port 0 buffer (step S254). When the output value in the prize ball REQ is set in the output port 0 buffer, the contents of the output port 0 buffer are outputted to the port 0 in step S203, so that the prize ball REQ signal is turned on and the connection confirmation is made. The on state of the signal is maintained (see FIG. 12). Further, the contents of the winning ball number buffer are set in the lower 4 bits of the output port 0 buffer (step S255).

  Next, the CPU 56 subtracts the contents of the prize ball number buffer (the number of prize balls paid out to the payout control means) from the contents of the total prize ball number storage buffer (step S256). Further, the CPU 56 sets a REQ end determination time value (for example, 3) in the prize ball timer (step S257). The REQ end determination time value is a value for setting a time from when the prize ball REQ signal is turned on to when it is turned off. Thereafter, the value of the prize ball process code is set to 2 (step S258), and the process is terminated.

  In this embodiment, the maximum value of the prize ball command is “15”. Accordingly, a prize ball number signal designating a payout number of “15” at the maximum is transmitted to the payout control board 37.

  FIG. 36 is a flowchart showing the prize waiting process 2 (step S233) executed when the value of the prize ball process code is 2. In the award ball waiting process 2, the CPU 56 confirms the value of the award ball timer (step S261). If the value is not 0, the value of the award ball timer is decreased by 1 (step S262), and the process is terminated. When the value of the prize ball timer becomes 0, the prize ball REQ waiting time is set in the prize ball timer (step S263). The prize ball REQ signal is turned off in step S243 of the prize ball waiting process 1. Then, the value of the prize ball process code is set to 0 (step S264), and the process is terminated. The award ball REQ waiting time is a waiting time until the next award ball REQ signal is turned on (when consecutive award ball payouts are executed, during the on periods of a plurality of award ball REQ signals). Time for providing an interval).

  By the above processing, the game control means stores the total number of game balls as prize balls to be paid out based on the establishment of the payout condition in the total prize ball number storage buffer so as to be specified. The total award ball number storage buffer corresponds to a prize game medium number storage means for storing stored contents for at least a predetermined period by a backup power source as a variable data storage means when power supply to the gaming machine is stopped. Further, the game control means transmits a payout command signal for designating a payout number of a predetermined number of prize balls to the payout control means based on the number of prize balls stored in the total prize ball number storage buffer. Here, the predetermined number is 15 if the number of prize balls stored in the total prize ball number storage buffer is 15 or more, and is stored in the total prize ball number storage buffer if it is less than 15. The number of prize balls. When a predetermined condition is satisfied, a subtraction process is performed for subtracting the number of payouts specified by the payout command signal from the number of prize balls stored in the total prize ball number storage buffer.

  In this embodiment, the predetermined condition for executing the subtraction process is that when a prize ball control signal (a prize ball number signal and a prize ball REQ signal) is transmitted to the payout control means, specifically, a prize is awarded. This is when the sphere REQ signal is turned on. That is, when the game control means sets the output state of the prize ball number signal to the state corresponding to the number of prize balls to be paid out in accordance with the winning, specifically, when the prize ball number signal is output to the output port 0. More specifically, when the content of the winning ball number buffer is set in the lower 4 bits of the output port 0 buffer, the total winning ball number storing buffer is subtracted.

  In this embodiment, as the prize game medium number storage means for storing the total number of prize game media to be paid out based on the establishment of the payout condition, a total prize ball number storage buffer for storing the total number itself is exemplified. However, the prize game medium number storage means for storing the total number of prize game media in an identifiable manner stores the number of prizes received in each prize area or the number of prizes for each prize area (for example, 4). The number of winning holes 14 corresponding to the number of winning balls, the number of winning holes 33, 39, 29, 30 corresponding to the number of 7 winning balls, and the number of winning prizes corresponding to the number of 15 winning balls, , The number of winning prizes for which the winning ball payout has not ended yet) may be stored.

  Next, the operation of the payout control means (the payout control CPU 371 and peripheral circuits such as ROM and RAM) will be described. FIG. 37 is an explanatory diagram showing an example of output port assignment in the payout control means. As shown in FIG. 37, the output port 0 is an output port for outputting a signal of each phase supplied to the payout motor 289 by the stepping motor. Also, the output port 1 outputs a ball-out LED 52, a prize ball LED 51, and a command receivable state signal, and a prize ball in-game signal, prize ball information, ball rental information, and a gaming machine error status signal outputted to the outside of the gaming machine. Is an output port.

  The output port 2 is an output port of each segment output of the error display LED 374 by 7 segment LED. The output port 3 is an output port for outputting an EXS signal and a PRDY signal to the card unit 50. The output port 3 is an output port for outputting a prize ball count signal and a payout error signal.

  FIG. 38 is an explanatory diagram showing an example of bit assignment of input ports in the payout control means. As shown in FIG. 38, a 5-bit prize ball number signal is input to bits 0 to 4 of the input port 0, and a connection confirmation signal from the main board 31 and the main board 31 are input to bits 5 to 7, respectively. The prize ball REQ signal and the detection signal of the payout motor position sensor 295 are input. In addition, the detection signal of the payout number count switch 301, the operation signal from the error release switch 375, and the detection signal of the full switch 48 are input to bits 1 to 3 of the input port 1, respectively. The VL signal, the BRDY signal, the BRQ signal, and the detection signal of the ball break switch 187 from the card unit 50 are input to bits 4 to 7 of the input port 1, respectively. An output signal and a power-off signal from the clear switch 921 from the power supply board 910 are input to the input port 2.

  FIG. 39 is a timing chart for explaining communication between the payout control means of the gaming machine and the card unit 50. The payout control means turns on the PRDY signal when power supply to the gaming machine is started and a payout operation is possible. When the power supply is started, the card unit 50 turns on the VL signal as a connection signal. When a card is received in the card unit 50, the ball lending switch is operated and a ball lending switch signal is input, the card unit 50 outputs a BRDY signal to the payout control means. That is, the BRDY signal is turned on. When a predetermined delay time elapses from this point, the card unit 50 outputs a BRQ signal to the payout control means. That is, the BRQ signal is turned on.

  Then, when the payout control means turns on the EXS signal for the card unit 50 and detects the fall (off) of the BRQ signal from the card unit 50, the payout control unit 289 drives the payout motor 289 to set a predetermined number (for example, 25). Pay out the rental balls to the player. Then, when the payout is completed, the payout control means causes the EXS signal to the card unit 50 to fall. That is, the EXS signal is turned off.

  Next, the operation of the payout control means will be described. FIG. 40 is a flowchart showing main processing executed by the payout control means. When power is turned on to the gaming machine and the input level of the reset terminal to which a reset signal is input becomes high, the payout control CPU 371 first performs necessary initial settings. That is, the payout control CPU 371 first sets the interruption prohibition (step S701). Next, the interrupt mode is set to interrupt mode 2 (step S702), and a stack pointer designation address is set to the stack pointer (step S703).

  The payout control CPU 371 initializes the built-in device register (step S704), and initializes CTC and PIO (step S705).

  In this embodiment, one channel of the built-in CTC is used in the timer mode. Accordingly, in the built-in device register setting process in step S704 and the process in step S705, register setting for setting the channel to be used to timer mode, register setting for permitting interrupt generation, and setting an interrupt vector. The register is set. The interrupt by the channel is used as a timer interrupt. For example, when it is desired to generate a timer interrupt every 2 ms, a value corresponding to 2 ms is set as an initial value in a predetermined register (time constant register).

  The interrupt vector set for the channel set to the timer mode (channel 3 in this embodiment) corresponds to the start address of the timer interrupt process. Specifically, the start address of the timer interrupt process is specified by the value set in the I register and the interrupt vector. In the timer interruption process, a payout control process for controlling the payout means (including at least a process of driving the ball payout device 97 in response to a command signal related to award ball payout from the main board, and a ball payout device 97 in response to a ball lending request. A process for driving the program may be included.

  In this embodiment, the interruption mode 2 is also set in the payout control CPU 371. Therefore, an interrupt process based on counting up the built-in CTC can be used. Also, an interrupt processing start address can be set according to the interrupt vector sent by the CTC.

  The interrupt based on CTC channel 3 (CH3) count-up is an interrupt generated when the CPU internal clock (system clock) is counted down and the register value becomes “0”, and is used as a timer interrupt. . Specifically, a clock obtained by dividing the operation clock of the CPU 371 is given to the CTC, the register value is subtracted by the input of the clock, and when the register value becomes 0, a timer interrupt occurs. The process so far corresponds to a part of the initial setting process.

  Next, the payout control CPU 371 sets a value corresponding to a monitoring time for confirming that a payout start command is transmitted from the main board 31 in a general-purpose register (HL register or BC register) (step S720). .

  The payout control CPU 371 is an external register that is a register that reflects the state and is one of the specific registers when a signal having a level (in this example, low level) that causes an interrupt is input to the interrupt terminal. A CPU having an interrupt request register. In this embodiment, it is assumed that bit 7 of the external interrupt request register is set to “1” when a signal of a level that causes an interrupt is input to the interrupt terminal. That is, the value of the external interrupt request register is updated to 80 (H). The setting / resetting of the bits of the external interrupt request register cannot be executed by software, but is performed by an internal mechanism of the CPU. It is assumed that bits 0 to 6 of the external interrupt request register are always 0. In addition, bit 7 of the external interrupt request register is set to "1" when a level that causes an interrupt is input to the interrupt terminal regardless of whether the interrupt is disabled or not. The

  The payout control CPU 371 checks whether the bit 7 of the external interrupt request register is set to “1” while decrementing the value of the general-purpose register by 1 (steps S721 to S723). If bit 7 of the external interrupt request register is set before the value of the general-purpose register becomes 0, that is, before the monitoring time elapses, the process proceeds to step S725. If the monitoring time elapses before bit 7 of the external interrupt request register is set, after setting a predetermined bit (which can be arbitrarily determined) of a predetermined general-purpose register used as an unstartable flag (step S724), The process proceeds to step S706. In this embodiment, the prize ball REQ signal from the main board 31 is input to the interrupt terminal of the payout control CPU 371. Therefore, if the monitoring time has passed before bit 7 of the external interrupt request register is set, it means that the game control means could not confirm that the payout start command was transmitted within the predetermined monitoring time. To do. Therefore, an inactivation flag indicating that is set.

  The fact that bit 7 of the external interrupt request register is set before the monitoring time elapses means that the prize ball REQ signal is turned on. In other words, the game control means of the main board 31 means that the prize ball REQ signal is turned on in order to transmit the prize start command by the prize ball number signal. The prize ball number signal is input through 0 to 4 (step S725), and it is confirmed whether or not the input prize ball number signal is 10 (H) defined as the payout activation command (step S726). If it is 10 (H), it is determined that the payout activation command has been received, and the process proceeds to step S706. If it is not 10 (H), after setting a predetermined bit of a predetermined general-purpose register used as an activation disable flag (step S724), the process proceeds to step S706.

  In step S706, the RAM is set to an accessible state (step S706). Further, 0000 (H) is set as an initial value of the award ball unpaid number counter (step S707). Next, if the start disable flag (see step S724) is not set (step S727), the state of the output signal of the clear switch 921 input via the input port 2 is confirmed only once (step S708). In the confirmation, when the on is detected, the payout control CPU 371 executes an initialization process (steps S712 to S715). If the clear switch 921 is not in the on state, whether or not data protection processing of the backup RAM area (for example, power supply stop processing such as addition of parity data) has been performed when power supply to the gaming machine is stopped Confirmation is made (step S709). Whether or not the protection process has been performed depends on the value of the backup monitoring timer stored in the backup RAM area in the power supply stop process described later according to the execution of the data protection process in the backup RAM area (for example, It is confirmed by whether or not 10). Note that such a confirmation method is an example. For example, a flag indicating that data protection processing has been executed is set in the backup flag area in the power supply stop processing, and the flag is set in step S709. If it is confirmed that there is a backup, it may be determined that there is a backup.

  If it is determined that there is a backup, the payout control CPU 371 performs a data check (parity check in this example) in the backup RAM area (step S710). In this embodiment, clear data (00) is set in the checksum data area, and the checksum calculation start address is set in the pointer. Also, the number of checksum calculations corresponding to the number of data to be checksum is set. Then, the exclusive OR of the contents of the checksum data area and the contents of the RAM area pointed to by the pointer is calculated. The calculation result is stored in the checksum data area, the pointer value is incremented by 1, and the checksum calculation count value is decremented by 1. The above processing is repeated until the value of the checksum calculation count becomes zero. When the value of the checksum calculation count reaches 0, the CPU 56 inverts the value of each bit of the contents of the checksum data area and uses the inverted data as the checksum.

  In the power supply stop process, a checksum is calculated by the same process as described above, and the checksum is stored in the backup RAM area. In step S710, the calculated checksum is compared with the stored checksum. When the power supply is stopped after an unexpected power failure or the like, the data in the backup RAM area should be saved, so the check result (comparison result) is normal (matched). That the check result is not normal means that the data in the backup RAM area is different from the data when the power supply is stopped. In such a case, since the internal state cannot be returned to the state at the time of stopping the power supply, the payout control state restoration processing is not executed, and the initialization processing (steps S712 to S715) is executed.

  If the check result is normal, the payout control CPU 371 performs payout control state recovery processing. Specifically, the value of the award ball unpaid number counter formed in the backup RAM is set as the initial value of the award ball unpaid number counter (step S711). And then. The process after step S712 is executed.

  In the initialization process, the payout control CPU 371 first performs a RAM clear process (step S712). In addition, initial values are set in the flags and counters of the RAM area (step S713). The process of step S713 includes a process of setting an initial value of the award ball unpaid number counter in the award ball unpaid number counter. Therefore, when the payout control state recovery process (step S711) is executed, the value of the unsold prize ball number counter stored in the backup RAM is set again in the unsold prize ball number counter. In other words, the value of the award ball unpaid number counter stored in the backup RAM is used as it is. That is, when the process of steps S712 and S713 is executed without executing the process of step S711, the payout control process is started from the initial state. Further, when the process of step S711 is executed and the processes of steps S712 and S713 are executed, the execution state of the payout control process is returned to the state before the power supply is stopped.

  If the start disable flag is set in the process of step S724, the start error bit in the error flag formed in the RAM is set (steps S714 and S715). Next, a CTC register provided in the payout control CPU 371 is set so that a timer interrupt is periodically received (step S716). That is, a value corresponding to the timer interrupt generation interval is set as an initial value in a predetermined register (time constant register). Since interruption is prohibited in step S701 of the initial setting process, interruption is permitted before the initialization process is completed (step S717). Further, the command receivable state signal is turned on (step S718). Thereafter, a loop process for monitoring the occurrence of a timer interrupt is entered.

  As described above, when the payout control CPU 371 receives a payout activation command from the game control means of the main board 13, it executes the check process of the detection signal of the clear switch 921 in step S <b> 708. As described above, the game control means executes the detection signal check process of the clear switch 921 when the payout activation command is transmitted. Therefore, the check timing of the detection signal of the clear switch 921 of the game control means and the check timing of the detection signal of the clear switch 921 of the payout control means are substantially the same.

  As described above, the built-in CTC of the payout control CPU 371 is set to repeatedly generate a timer interrupt. When a timer interrupt occurs, the payout control CPU 371 executes a timer interrupt process after step S749.

  FIG. 41 is a flowchart showing an example of a timer interrupt process executed by the payout control unit. The payout control CPU 371 first executes a power-off process for monitoring whether or not a power-off signal has been output (step S749). Thereafter, a payout control process after step S750 is executed. In the payout control process, the payout control CPU 371 first performs an input determination process (step S751). In the input determination processing, the states of bit 5 of input port 0 and bits 3 to 7 (see FIG. 38) of input port 1 are detected, and the detection result is reflected in a predetermined 1 byte of RAM (referred to as an input state flag). It is processing to do. In the payout control process, when control is performed based on the state of bit 5 of input port 0 and bits 3 to 7 of input port 1, the state of the input state flag is not checked instead of directly checking the state of the input port. Check status. Further, the input determination processing includes processing for checking the status of bits 1 and 2 of the input port 1, that is, checking the status of the detection signals of the payout number count switch and the error release switch. Specifically, switch timers (launch control signal timer, payout number count switch timer, error release switch timer) corresponding to each of them are formed in the RAM, and it is detected in the switch check process that they are in the ON state. Then, the value of the corresponding switch timer is incremented by 1, and when it is detected that the switch is off, the value of the corresponding switch timer is cleared.

  Next, the payout control CPU 371 executes a payout motor control process (step S753). In the payout motor control process, when the payout motor 289 is to be driven, a process for outputting the patterns of the payout motors φ1 to φ4 to the output port 0 is performed.

  Further, the payout control CPU 371 executes a prepaid card unit control process for communicating with the card unit 50 (step S754). Next, the payout control CPU 371 executes main control communication processing for communicating with the game control means of the main board 31 (step S755). Further, a prize ball lending control process for performing a control for paying out a lending ball in response to a ball lending request from the card unit 50 and for performing a control for paying out the number of award balls indicated by a prize ball number signal from the main board. Is executed (step S756).

  Then, the payout control CPU 371 executes error processing for detecting various errors (step S757). Further, an information output process for outputting prize ball information and ball lending information output to the outside of the gaming machine is executed (step S758). Further, a predetermined display is performed on the error display LED 374 according to the result of the error processing, and a display control process for lighting the prize ball LED 51 and the ball out LED 52 is executed (step S759). In the display control process, the payout control CPU 371 performs control for lighting the prize ball LED 51 when the prize ball REQ signal is on. Further, when the prize ball REQ signal is turned off, control for turning off the prize ball LED 51 is performed.

  In this embodiment, a RAM area (output port 0 buffer, output port 1 buffer, output port 2 buffer) corresponding to the output state of the output port is provided. The contents of the port 0 buffer, output port 1 buffer, and output port 2 buffer are output to the output port (step S760: output processing). The output port 0 buffer, the output port 1 buffer, and the output port 2 buffer are a payout motor control process (step S753), a prepaid card control process (step S754), a main control communication process (step S755), and an information output process (step S758). And updated in the display control process (step S759).

  The power-off process is a process similar to the power-off process executed by the game control means (see FIGS. 20 and 21). That is, if the power-off signal from the power supply board 910 is in an on state continuously for a predetermined time counted by the backup monitoring timer (for example, when the value of the backup monitoring timer becomes 2 as the determination value (see step S453)). The power supply stop process is executed. In the process when power supply is stopped, the check code (specifically, checksum) is calculated for the RAM area that you want to save even when the power supply is stopped, the check code is stored in the backup RAM area, RAM access is prohibited, and the output port After clearing, loop processing starts. When it is detected that the power-off signal is turned off in the loop processing, the state of the payout control means is the same as when the game control means returns to the state of executing the game control processing (at least from the main board). This includes a process of driving the ball payout device 97 in response to a command signal related to award ball payout, and may include a process of driving the ball payout device 97 in response to a ball lending request. Specifically, for example, the process returns to step S701 of the main process shown in FIG.

  FIG. 42 is a flowchart showing the payout motor control process in step S753. In the payout motor control process, if the payout motor 289 is rotating (step S511), the payout control CPU 371 checks the detection output of the payout motor position sensor 295, and the detection output is turned on by the payout motor position sensor 295. If this is the case, the value of the payout operation counter is decremented by 1 (steps S512 and S513). Thereafter, any one of steps S521 to S526 is executed according to the value of the payout motor control code.

  For example, when the payout control CPU 371 detects that the value of the payout operation counter has reached a predetermined value (eg, 1) in the payout motor constant speed process in step S524, the payout motor in step S525 is used to stop the payout motor 289. Start the brake process. Further, in this embodiment, when the payout motor 289 is rotated 1/2, one game ball is paid out, and the payout motor position sensor 295 is turned on twice during one rotation. Take as an example. Accordingly, when paying out n game balls, the payout motor position sensor 295 is turned on n times.

  In the payout motor normal process (step S521) executed when the value of the payout motor control code is 0, the payout control CPU 371 sets the pointer at the head address of the table stored in the ROM. The payout motor normal process setting table stores a payout motor excitation pattern table in which data of excitation patterns (payout motors φ1 to φ4) of each step for rotating the payout motor 289 at the time of ball payout is sequentially set. Yes.

  In the payout motor start preparation process (step S522) executed when the value of the payout motor control code is 1, the payout control CPU 371 outputs the output port buffer corresponding to the output state of the output port that outputs the payout motors φ1 to φ4. Perform processing such as setting the initial value of the excitation pattern. Then, the value of the dispensing motor control code is changed to 2.

  In the payout motor slow-up process (step S523) executed when the value of the payout motor control code is 2, the payout control CPU 371 starts the rotation of the payout motor 289 more smoothly than in the case of the constant speed process. Corresponds to the output state of the output port that outputs the payout motors φ1 to φ4 by reading the contents of the payout motor excitation pattern table at a long interval and gradually approaching the time interval in the case of constant speed processing Set the output port buffer. At the time of reading, the contents of the payout motor excitation pattern table at the address pointed to by the pointer are read and the value of the pointer is incremented by one. If a predetermined time has elapsed since the value of the payout motor control code becomes 2, the value of the payout motor control code is changed to 3.

  In the payout motor constant speed process (step S524) executed when the value of the payout motor control code is 3, the payout control CPU 371 periodically reads the contents of the payout motor excitation pattern table and pays out the payout motors φ1 to φ4. Is set in the output port buffer corresponding to the output state of the output port that outputs. When a predetermined time comes before the time when the payout motor 289 should be stopped (the time when the payout of the game ball is finished), the value of the payout motor control code is changed to 4. Whether or not a predetermined time has passed is confirmed, for example, by the value of the payout operation counter having reached a predetermined value (for example, 1).

  In the payout motor brake process (step S525) executed when the value of the payout motor control code is 4, the payout control CPU 371 has a longer interval than in the case of the constant speed process in order to stop the payout motor 289 smoothly. In addition, the content of the payout motor excitation pattern table is read at a time interval that gradually moves away from the time interval in the case of constant speed processing, and the output corresponding to the output state of the output port that outputs the payout motors φ1 to φ4 Set to port buffer. When the dispensing motor 289 is finally stopped, the value of the dispensing motor control code is changed to zero. The payout control CPU 371 finally stops the payout motor 289 by stopping driving the payout motor 289 when the value of the payout operation counter reaches a value corresponding to the end of payout of the game ball (for example, 0). Stop.

  In the ball biting payout motor brake process (step S526) executed when the value of the payout motor control code is 5, the payout control CPU 371 smoothes the payout motor 289 in the case of rotation for releasing the ball biting. The payout motor excitation pattern is longer than the rotation of the payout motor 289 for releasing the ball biting, and gradually away from the time interval in the case of constant speed processing. The contents of the table are read out and set in the output port buffer corresponding to the output state of the output port that outputs the dispensing motors φ1 to φ4. Note that the contents of the output port buffer corresponding to the output state of the output port that outputs the payout motors φ1 to φ4 are output to the output port in the output process of step S760. The payout control CPU 371 changes the value of the payout motor control code to 5 when it detects a ball bite in steps S523 to S525.

  FIG. 43 is a flowchart showing the main control communication process in step S755. In the main control communication process, the payout control CPU 371 executes any one of steps S531 to S532 according to the value of the main control communication control code. If the value of the main control communication control code is 0 (waiting for reception of a prize ball number signal), the process ends without proceeding to step S531 or S532.

  FIG. 44 is an explanatory diagram showing conditions for inputting a prize ball control signal via an input port. As shown in FIG. 44, the main control unconnected error (connection confirmation signal is turned off) in the 1-byte error flag formed in the RAM, the prize ball REQ signal error (the prize ball REQ signal is turned on or off at an incorrect timing) ) Is not in the set state and the BRDY signal from the card unit 50 is not in the on state, the payout is made when the connection confirmation signal is in the on state and the prize ball REQ signal is in the on state. The control means inputs a prize ball control signal via the input port. The error bit is a bit in an error flag that is set when it is detected that various errors have occurred.

  FIG. 45 is a flowchart showing a prize ball REQ interrupt process activated in response to the prize ball REQ signal from the main board 31 introduced into the interrupt terminal being turned on (low level). In the prize ball REQ interrupt process, the payout control CPU 371 executes the subsequent processes when the error bit (main control unconnected error bit, prize ball REQ signal error bit or activation error bit) is on. The process is terminated (step S541). In step S541, if any one of the three bits in the error flag is set, it is determined that the error bit is set.

  If the BRDY signal is on, the payout control CPU 371 ends the process without executing the subsequent processes (step S542). That the BRDY signal is on means that a ball lending request is generated from the card unit 50 or that a ball lending process is in progress. That is, when a ball lending request is generated or a ball lending process is in progress, communication with the game control means of the main board 31 (communication relating to prize ball payout) does not proceed. That is, even when the prize ball REQ signal is turned on, the prize ball payout process is not executed.

  If the conditions of steps S541 to S542 are not satisfied and the connection confirmation signal is on, the payout control CPU 371 inputs the prize ball number signal via the input port 0, and the prize indicated by the prize ball number signal is shown. A process of adding the number of balls to the contents of the prize ball payout scheduled total counter (see FIG. 48) is performed (step S545). Then, after setting the prize ball REQ signal off monitoring time (24 in this example) to the main control communication control timer (step S546), the main control communication control code value is set to 1 (step S547), and the process ends. . The main control communication control timer is a timer used for monitoring the time related to communication with the game control means of the main board 31. At this stage, the award for setting the timing at which the prize ball REQ signal is turned off is set. A ball REQ signal off monitoring time (a time predetermined as a time shorter than the shortest time until the prize ball REQ signal is turned off) is set. The prize ball unpaid-out number counter is formed in a non-volatile (power-backed up in this example) RAM area. In this embodiment, when the prize ball REQ signal is transmitted (turned on), the prize ball number indicated by the prize ball number signal is added to the contents of the prize ball unpaid-out number counter.

  As described above, the prize ball number signal transmitted from the main board 31 is received by the interrupt process.

  FIG. 46 is a flowchart showing a main control communication process (step S531) executed when the value of the main control communication control code is 1. In the main control communication process, the payout control CPU 371 checks the state of the prize ball REQ signal if the connection confirmation signal is in the on state (step S551) (step S552). If the prize ball REQ signal is off, the prize ball REQ signal error bit in the error flag is set (step S553). This is because it is strange that the prize ball REQ signal immediately turns off at this stage.

  Next, the payout control CPU 371 checks the value of the main control communication control timer (step S554), and if not 0, subtracts 1 from the value of the main control communication control timer (step S555) and ends the process. If the value of the main control communication control timer is 0, the value of the main control communication control code is set to 2 (step S556), and the process ends.

  FIG. 47 is a flowchart showing a main control communication end process (step S532) executed when the value of the main control communication control code is 2. In the main control communication process, the payout control CPU 371 proceeds to step S564 when the error bit (main control unconnected error bit, prize ball REQ signal error bit or activation error bit) is on (step S564). S561). Moreover, also when a connection confirmation signal is an OFF state, it transfers to step S564 (step S562). If both error bits are off and the connection confirmation signal is on, it is checked whether or not the prize ball REQ signal is off (step S563). When it is turned off, the process proceeds to step S564.

  In step S564, the value of the main control communication control code is set to 0, and the process ends. If the prize ball REQ signal does not turn off even after a predetermined monitoring period has elapsed using the main control communication control timer, it is determined that the prize ball REQ signal has not been turned off within the monitoring time. Among them, a prize ball REQ signal error bit may be set.

  FIG. 48 is an explanatory view showing an example of a counter used by the payout control means in the payout control process. In this embodiment, a prize-ball-payout-scheduled total counter that stores the total number of prize-balls to be paid out, which is the number obtained by cumulatively adding the numbers specified in the prize-ball number command, and an addition process (addition process) described later are executed. A total number of previous winning ball payout totals counter that stores the total number of winning ball payouts that have been issued, a payout operation counter that is set to a value corresponding to the number of revolutions of the payout motor 289 when paying out the winning ball, A winning ball unpaid number counter in which the number of winning balls at the time of paying is set and a lending ball unpaid number counter in which the number of lending balls is set are used. These counters are formed in the RAM.

  The payout operation counter is used to determine the rotation speed of the payout motor 289. The values of the award ball unpaid number counter and the lending ball unpaid number counter are decremented by 1 when the payout number count switch 301 is turned on (the game ball passes the switch). Therefore, the award ball unpaid number counter and the lending ball unpaid number counter detect that the game ball finally paid out by the payout motor 289 passes through the payout number count switch 301 (the count value becomes 0). Used to determine that the award ball lending and ball lending have been completed.

  In order to determine the rotation speed of the payout motor 289, a payout operation timer that determines a rotation time according to the payout number may be used instead of the payout operation counter. When the payout operation timer is used, the data held in the drive amount data storage means (in this case, the timer value of the payout operation timer) corresponds to the drive amount of the payout drive means (in this example, the payout motor 289). The driving amount updating means for subtracting the minute amount corresponds to executing a process of reducing the timer value of the payout operation timer as time elapses.

  FIG. 49 is a flowchart showing the prize ball lending control processing in step S756. In the award ball lending control process, the payout control CPU 371 executes a later-described award ball payout amount addition control (step S600) and confirms that the detection signal of the payout number count switch 301 is turned on (step S600). In step S601), it is confirmed whether the paid out game ball is a prize ball or a rental ball (steps S602 and S603). In this example, whether or not the game ball is a prize ball is confirmed by whether or not the current payout control state is a prize ball. Whether or not a prize ball is in progress is confirmed, for example, by whether or not a prize ball operating flag in the payout control state flag formed in the RAM is set (step S602). Further, whether or not the game ball is a lending ball is confirmed by whether or not the current payout control state is lending the ball. Whether or not the ball is being lent is confirmed, for example, by whether or not the ball renting operation bit in the payout control state flag formed in the RAM is set (step S603).

  If it is during the winning ball, the value of the winning ball unpaid number counter is decremented by 1 (step S604). If it is not in the winning ball but in the ball lending, the value of the ball lending unpaid-out number counter is decreased by 1 (step S605). Further, if the winning ball is not being lent and not being lent, the value of the award ball unpaid-out counter is decremented by 1 assuming that the paid-out gaming ball is a winning ball (step S604).

  When the value of the winning ball unpaid-out counter is decremented by 1, the payout control CPU 371 turns on the winning ball count signal for a predetermined period (step S606). Thereafter, any one of steps S610 to S612 is executed according to the value of the payout control code.

  In the prize ball lending control process, an error bit is checked to determine whether or not to perform a payout operation (one prize ball payout or one ball lending). Only in the waiting for start process. That is, the confirmation process of the payout number count switch 301, the subtraction process of the non-payout number counter, the output process of the prize ball count signal, etc. shown in FIG. 49 are executed without checking the error bit. Therefore, even if an error occurs, the ball lending unpaid-out counter or the winning ball unpaid-out counter is subtracted in accordance with the detection output from the paid-out count switch 301, and the value of the award ball unpaid-out counter When is subtracted, a prize ball count signal is output. Therefore, the number of unpaid game balls can be managed even in an error state. Even if an error state is detected, a prize ball count signal can be output in response to the detection of a payout of a prize ball. Therefore, even in an error state, it is detected on the payout control board 37 side. Information indicating that the winning ball has been paid out can be transmitted to the main board 31 side.

  In the prize ball lending control processing, if there is a detection output from the number-of-payout count switch 301 when neither a prize ball nor a ball is lent, it is determined that the game ball that has been paid out is a prize ball, The value of the payout number counter is subtracted, and a prize ball count signal is output to the main board 31. Therefore, even when an illegal game ball is paid out, a prize ball count signal is transmitted to the game control means (specifically, the CPU 56) mounted on the main board 31. Since the game control means manages the number of prize balls to be paid out, if a prize ball count signal indicating the number of prize balls more than the number of prize balls to be originally paid out is received, illegal payout is performed. Can be determined. When it is determined that an illegal game ball has been paid out, the game control means performs the following appropriate processing.

  For example, the game control means performs a process for notifying a player, a game clerk, or the like of the occurrence of an error using the variable display device 9 or the like. Specifically, the game control means controls the variable display device 9 to display that the error has occurred in the display control means by transmitting a display control command for notifying the occurrence of the error to the display control means. Let it run. The game control means transmits a lamp control command and a sound control command for informing the error to the lamp control means and the sound control means via the display control means. You may make it perform lighting of the lamp and LED for alert | reporting generation | occurrence | production, and audio | voice output. In addition, the game control means performs a process for stopping the progress of the game. Specifically, the game control means saves the current control state, for example, the output state of the output port, in the RAM 55 before stopping the progress of the game, and then clears the output state of the output port so that the abnormal state is Stop playing until it is resolved. Further, the game control means performs a process (step S52) of outputting information indicating that an illegal game ball has been paid out to a hall computer or the like outside the game machine. The game control means sends information indicating the number of prize balls to be paid out and a signal indicating the number of prize balls actually paid out based on the prize ball count signal to a hall computer or the like outside the gaming machine by information output processing. By outputting, it is possible to make the hall computer or the like determine whether or not an illegal game ball has been paid out. In this case, the game control means sends a signal indicating that one prize ball has been paid out via the test terminal board every time a prize ball count signal is received, regardless of whether or not an illegal payment has been made. The prize ball information indicating that ten prize balls have been paid out is sent to the hall computer every time the prize ball count signal is received ten times, for example. Also good. Incidentally, all of the above processes may be executed, but at least one or more of the above processes are executed.

  FIG. 50 is a flowchart showing the award ball payout addition control (step S600). In the prize ball payout addition control, the payout control CPU 371 determines whether there is a bit indicating an error state in a set error flag in which various error states are reflected in each bit, and the error state. If there is a bit indicating, the processing is terminated without doing anything (step S691). Further, it is determined whether or not the ball lending operation flag is set. If it is set, the processing is terminated without doing anything (step S692). Since the winning ball lending control process is executed every 2 ms, the winning ball payout addition control is also executed every 2 ms. However, in the error state due to the process of step S691, the processes after step S694 are not executed. Further, even during the ball lending process based on the ball lending request from the prepaid card unit 50, the processes after step S694 are not executed.

  Furthermore, the payout control CPU 371 determines whether or not the value of the payout operation counter has reached a predetermined value (for example, 1) (step S693). When the predetermined value is reached, the processing after step S694 is executed. However, if the predetermined value is not reached, the processing after step S694 is not executed. Note that the processing after step S694 is executed at the timing when the value of the payout operation counter is updated to a predetermined value (for example, when the value is changed from 2 to 1), and is not always executed in a state where the predetermined value is reached. Absent.

  In step S694, the payout control CPU 371 checks whether or not the content of the planned winning ball payout counter (PA) is the same as the content of the previous winning ball payout total counter (PB). If they are not the same, a process for adding the number of prize balls to be paid after step S695 (hereinafter referred to as an addition process or an addition process) is executed. The previous prize ball payout total counter (PB) is set with the content of the prize ball payout total counter (PA) at the start of the prize ball payout process and when the extra process (previous addition process) is executed. Yes. Also, when a prize ball number command is received from the game control means, the number instructed by the prize ball number command is added to a prize ball payout scheduled total counter (PA). Accordingly, the fact that the content of the total number of winning ball payout counter (PA) is different from the content of the previous total number of paying ball counter (PB) means that a new winning ball number command has been received from the game control means. Therefore, if the conditions for prohibiting the addition of steps S691 to S693 are not satisfied, the addition process after step S695 is performed. The value of the payout operation counter is updated to a predetermined value when the payout motor 289 is rotating (see steps S511 and S513), that is, when a game ball is being paid out. According to the determination of 692, the process after step S695 is not executed during the non-execution of the prize ball payout.

  In step S695, the payout control CPU 371 adds, to the payout operation counter, a value corresponding to the difference between the content of the total prize ball payout total counter (PA) and the content of the previous prize ball payout total counter (PB). To update the payout operation counter (step S695). In addition, the difference between the contents of the total number of expected winning ball payout counter (PA) and the content of the total number of previous winning ball payout scheduled counter (PB) is added to the number of unpaid prize ball counter (step S696). Furthermore, the previous winning ball payout scheduled total counter (PB) is updated by setting the content of the expected winning ball payout total counter (PA) in the previous winning ball payout scheduled total counter (PB) (step S697). In this embodiment, when one game ball is paid out from the payout motor 289, the value of the payout operation counter is decremented by 1 (as described above, in this embodiment, the payout motor 289 is 1 / 1 game ball is paid out after 2 rotations, and the payout motor position sensor 295 is turned on twice during the period of 1 rotation), so the added value for the payout operation counter and the number of unpaid prize balls The added value for the counter is the same value.

  As described above, the addition process is executed only at the timing when the value of the payout operation counter is updated to a predetermined value. Therefore, it is possible to reduce the number of determinations as to whether or not the data has increased (the process of step S694), and to reduce the burden of the determination process.

  In step S697, instead of setting the content of the planned total payout ball counter (PA) in the previous total payout ball counter (PB), the planned total payout ball counter (PA) and the previous prize ball payout are set. The contents of the scheduled total counter (PB) may be cleared to zero. That is, when the increase determination means determines that the data has increased, the increase number specifying means moves the increase data stored in the prize game medium number data storage means to the payout operation counter (step S695). The stored contents of the prize game medium number data storage means (in this example, the prize ball payout scheduled total counter (PA)) and the previous prize game medium number data storage means (in this example, the previous prize ball payout scheduled total counter (PB)) are stored. It may be initialized. In such a case, it is possible to prevent the storage capacities of the premium game medium number data storage means and the previous premium game medium number data storage means from increasing.

  In the above example, it is configured to determine whether or not the value of the payout operation counter has reached a predetermined value in step S693, but without determining whether or not the value of the payout operation counter has reached a predetermined value. , It is determined whether or not the number of prize balls to be paid out has increased during the execution of the payout operation (specifically, it is determined whether or not the value of the total number of prize balls to be paid out has increased) and has increased. Then, the processing after step S694 may be performed. That is, each time the number of prize balls to be paid out increases during execution of the payout operation, the extra process may be performed.

  In this embodiment, since one game payout device 97 performs game ball payout based on the prize ball number command and game ball payout based on the loan request, when the ball lending process is executed, The prize ball payout process cannot be executed. Therefore, even if the extra process is performed while the ball lending process is being performed, the award ball payout is not performed, and therefore a meaningless process is performed. However, by prohibiting the extra process when performing the ball lending process, it is possible to improve the efficiency of the extra process so that the meaningless process is not executed.

  Similarly, the prize ball payout process cannot be executed in an error state. Therefore, even if the extra process is performed in an error state, the prize ball payout is not executed, and therefore a meaningless process is performed. However, by prohibiting the extra process in the error state, it is possible to improve the efficiency of the extra process so that the meaningless process is not executed. The addition process is executed collectively when the error state is canceled based on the operation signal from the error cancellation switch 375 (additions based on all prize ball number commands received in the error state are added. )

  FIG. 51 is a flowchart showing the payout start waiting process (step S610) executed when the payout control code is 0. In the payout start waiting process, the payout control CPU 371 does not execute the subsequent processes if the error bit is set (step S621).

  If the BRDY signal is not on (step S622), processing for paying out a prize ball after step S631 is executed. If the BRDY signal is on and the BRQ signal that is a ball lending request signal is on, a ball lending operation flag is set (steps S623 and S624). Then, “25” is set in the unpaid ball lending number counter (step S625), and “25” is set in the payout operation counter (step S626).

  The payout operation counter is referred to in the payout motor control process (step S768). That is, in the payout motor control process, control is performed to rotate the payout motor 289 by the number of rotations corresponding to the value set in the payout operation counter.

  Thereafter, the payout control CPU 371 sets a value (specifically “1”) corresponding to the payout motor activation preparation process (step S522) to the payout motor control code for selecting the process executed in the payout motor control process. It is set (step S627), the value of the payout control code is set to 1 (step S628), and the process is terminated.

  In step S631, the payout control CPU 371 checks whether or not the content of the winning ball payout scheduled total counter (PA) is 0 (step S631). If 0, the process ends. The prize ball payout total counter (PA) is a value other than 0 when the prize ball number command is received from the game control means of the main board 31 in the prize ball REQ interrupt process (the number indicated by the prize ball number command). Is added. If the content of the total number of paying ball counters (PA) is not 0, the content of the total number of paying ball counters (PA) is set in the payout operation counter (step S632), and the number of winning balls in the award ball unpaid number counter is set as a prize ball. The contents of the payout scheduled total counter (PA) are set (step S633). In addition, the content of the total number of winning ball payouts counter (PA) is set in the previous number of paying ball payouts total counter (PB) (step S634). Then, a winning ball moving flag is set (step S635), and the process proceeds to step S627.

  FIG. 52 is a flowchart showing a payout motor stop waiting process (step S611) executed when the payout control code is 1. In the payout motor stop waiting process, the payout control CPU 371 checks whether or not the payout operation of the payout motor 289 has ended (step S641). For example, the payout control CPU 371 sets a flag to that effect when the payout motor brake process (step S525) in the payout motor control process ends, and confirms the flag in step S641 so that the payout motor 289 pays out. It can be confirmed whether or not the operation is completed.

  When the payout operation of the payout motor 289 is completed, the payout control CPU 371 sets the payout passing monitoring time in the payout control monitoring timer (step S642). The payout passing monitoring time is a time that has a margin in the time from when the last payout ball is paid out by the payout motor 289 until it passes through the payout number count switch 301. Then, the value of the payout control code is set to 2 (step S643), and the process ends.

  53 and 54 are flowcharts showing the payout passing waiting process (step S612) executed when the value of the payout control code is 2. In the payout passing waiting process, when the prize ball is being paid out, it is determined that the payout has been completed normally if the value of the prize ball unpaid number counter is 0. Note that the value set in the payout operation counter for determining the rotation amount of the payout motor 289 corresponds to the value set in the award ball non-payout number counter at the start of the payout process, and the control here is performed. When executed, the value of the payout operation counter is 0 corresponding to the stop of the payout motor 289 (the payout motor 289 has been paid out). The payout motor 289 should have made a predetermined number of payouts, but the payout number count switch 301 provided at the bottom of the ball payout device 97 could only detect less than a predetermined number of payouts. Become. That is, the payout has not been completed normally.

  When the value of the award ball unpaid-out counter is not 0, if the error ball is not in an error state, a game ball re-payout operation is attempted. In the re-payout operation, when it is detected by the payout number count switch 301 that the game ball is actually paid out, it is determined that the payout has been completed normally.

  Further, when the ball lending is being paid out, it is determined that the payout has been completed normally if the value of the ball lending unpaid-out counter is 0. If the value of the ball lending unpaid number counter is not 0, if it is not an error state, a re-payout operation of the game ball or the remaining number of ball lending (corresponding to the value of the ball lending unpaid number counter) is attempted.

  As a specific process of the above description, in the payout passing waiting process, the payout control CPU 371 decrements the value of the payout control timer by 1 if the value of the payout control timer is not 0 (step S651). If the value of the payout control timer is not 0 (step S652), that is, if the payout control timer has not timed out, the process is terminated.

  If the payout control timer has timed out (step S652), it is determined whether or not a ball lending payout process (ball lending operation) has been executed (step S653). Whether or not the ball lending operation has been executed is confirmed by whether or not the ball lending operation in progress flag in the payout control state flag formed in the RAM is set. When the ball lending operation is not executed, that is, when the prize ball payout process (prize ball operation) is executed, the payout control CPU 371 checks the value of the award ball unpaid number counter (step S654). ). If the value of the prize ball unpaid number counter is 0, the following process is performed assuming that the prize ball payout process is normally completed.

  That is, the value set in the previous prize ball payout total counter (PB) is subtracted from the contents of the prize ball payout total counter (PA) (step S671). Then, the content of the previous winning ball payout scheduled total counter (PB) is cleared (initialized) to 0 (step S672).

  Further, the re-payout operation bit, the winning ball operation flag and the ball lending operation bit in the payout control state flag are reset (step S655), the payout control code is set to 0 (step S656), and the process is terminated. The re-payout operation bit is a control bit used when executing the re-payout process.

  In step S671, the content of the previous total number of payout balls counter (PB) is subtracted without clearing the content of the total number of payballs scheduled to be paid out (PA). In consideration of the fact that a new prize ball number command is received and the contents of the prize ball payout scheduled total counter (PA) may increase during the execution of.

  Further, although not explicitly shown in FIG. 53, the addition process is not executed while the payout passing waiting process is being executed. If executed, the initialization process of step S672 is executed in spite of the content of the previous winning ball payout scheduled total counter (PB) being updated, whereby the previous winning ball payout scheduled total counter (PB). This is because the number of prize balls paid out may not be accurate. Also, the value of the award ball unpaid out counter is increased (see step S696), and the check process in step S654 cannot be executed normally.

  The payout control CPU 371 determines that an error flag (specifically, a payout switch error error 1 bit, a payout switch error error 2 bit, and a payout case error bit when the value of the award ball unpaid number counter is not 0. The re-payout operation is executed on the condition that any one or a plurality of bits) is not set (step S659). If the error flag is set, the re-payout operation is not executed.

  In order to execute the re-payout process, the pay-out control CPU 371 first checks whether or not the re-payout operation in-progress bit is set (step S661). If not set, the re-payout operation in-progress bit is set (step S662), and a value corresponding to the value of the award ball unpaid number counter or the ball lending unpaid number counter is set in the payout operation counter (step S663). ). Thereafter, the payout control code is set to 1 (step S664), and the process is terminated.

  In step S661, when it is confirmed that the re-payout operation in-progress bit is set, the payout control CPU 371 does not pay out the game ball even when the re-payout process is executed (the payout number count switch 301 is set in the game ball). Is not detected), a payout case error bit in the error flag is set (step S666). At that time, the re-payout operation in-progress bit is reset (step S665). Then, the process ends.

  As described above, if the game ball is not paid out correctly even after performing the re-payout operation in the re-payout process (corrected payout process), the payout count switch non-passing error bit (payout) is assumed as a game ball payout operation failure. Case error bit) is set.

  Upon confirming that the ball lending / dispensing process (ball lending operation) has been executed in step S653, the payout control CPU 371 confirms whether or not the value of the unlapped ball lending number counter is 0 (step S657). . If it is 0, it is determined that the ball lending / dispensing process is normally completed, and the process proceeds to step S655.

  If the value of the ball lending unpaid number counter is not 0, an error flag (specifically, any one bit of the payout switch abnormal error 1 bit, the payout switch abnormal error 2 bit, and the payout case error bit) On the condition that (multiple bits) is not set (step S658), the re-payout process is executed. If the error flag is set, the re-payout process is not executed.

  FIG. 55 is a timing chart for explaining the ball biting detection process executed in the payout motor control process (step S768). In the payout motor constant speed process (step S524) in the payout motor control process, the payout control CPU 371 monitors the detection signal of the payout motor position sensor 295. The detection signal of the payout motor position sensor 295 is turned on twice, for example, every time the cam that rotates in conjunction with the payout motor 289 rotates once. In order for the detection signal to be output twice each time the cam rotates once, the cam has two locations in the portion that receives light from the light emitting portion in the payout motor position sensor 295 (positions symmetrical with respect to the axis). Is provided with a reflector. The output of the light receiving unit in the dispensing motor position sensor 295 is used as a detection signal.

  Therefore, even if the payout control CPU 371 gives an excitation pattern having a step number of 1/2 rotation or more to the payout motor 289, the detection signal of the payout motor position sensor 295 does not turn on. Actually, the payout motor 289 does not rotate due to foreign matter such as dust adhering to the cam portion and the like, and the game ball is clogged (ball biting has occurred). As a result, the cam rotates. It can be judged that it is not.

  In this embodiment, when the payout motor 289 receives an excitation pattern for 16 steps (2.087 ms per step), it makes one rotation and pays out two game balls. Then, for example, as shown in FIG. 55, the payout control CPU 371 checks the detection signal of the payout motor position sensor 295 every time the payout motor 371 gives an excitation pattern of 8 steps to the payout motor 289. Thus, it is determined whether or not the payout motor 289 is rotating. Then, if the same state is detected five times continuously (the detection signal of the dispensing motor position sensor 295 is turned off five times continuously or turned on five times continuously), it is determined that ball engagement has occurred. A ball biting release process is executed.

  As shown in FIG. 56, the payout control CPU 371 repeats a process of rotating the payout motor 289 at a high speed and a process of rotating it at a medium speed a predetermined number of times (for example, 9 times). Each time an excitation pattern for 8 steps is given to the payout motor 289, the detection signal of the payout motor position sensor 295 is checked to determine whether or not the payout motor 289 is rotating. If it is determined by the detection signal that the rotation of the payout motor 289 has been restored, the ball biting release process is terminated, and the normal ball payout process returns.

  If there is no change in the detection signal of the payout motor position sensor 295 even if the high speed rotation process and the medium speed rotation process are executed a predetermined number of times, the ball biting error bit (payout case error bit) of the error flag is displayed. ) Is set. When the payout case error bit is set, the payout control CPU 371 does not drive the payout motor 289. When the payout case error bit is reset (see step S807 in FIG. 58), the payout control CPU 371 returns to a state where the payout motor 289 can be driven.

  Thus, the payout control means includes a drive state monitoring means for monitoring the operating state of the payout means, and a drive stop means for stopping the driving of the payout means when the drive state monitoring means detects a malfunction of the payout means. Including.

  Next, error processing will be described. FIG. 57 is an explanatory diagram showing the relationship between the type of error and the display of the LED 374 for error display. As shown in FIG. 57, when the connection confirmation signal from the main board 31 is turned off, the payout control CPU 371 displays “1” on the error display LED 374 as a main board non-connection error. I do. When the disconnection of the payout count switch 301 or a ball clogging occurs at the payout count switch 301, the error display LED 374 is controlled to display “2” as the payout switch abnormality detection error 1. The disconnection of the payout number count switch 301 or the occurrence of ball clogging in the payout number count switch 301 is determined by the detection signal of the payout number count switch 301 not being turned off.

  When the detection signal of the payout number count switch 301 is turned on even though the game ball is not paying out, a control for displaying “3” on the error display LED 374 as a payout switch abnormality detection error 2 is performed. Do. If the detection signal of the payout count switch 301 does not turn on despite the rotation abnormality of the payout motor 289 or the game ball being paid out, “4” is displayed on the error display LED 374 as a payout case error. Control. The specific method for detecting that the detection signal of the payout number count switch 301 is not turned on is as described above. When the prize ball REQ signal is turned on at an improper timing or when the prize ball REQ signal is turned off at an improper timing, “5” is displayed in the error display LED 374 as a prize ball REQ signal error. Control to display. A specific method for detecting that the prize ball REQ signal is turned on or off at an incorrect timing is as described above.

  In addition, when the lower pan is full, that is, when the full switch 48 is turned on, control is performed to display “6” on the error display LED 374 as a full error. When the supply ball is insufficient, that is, when the ball break switch 187 is turned on, control is performed to display “7” on the error display LED 374 as a ball break error.

  Further, when the VL signal from the card unit 50 is turned off, control is performed to display “8” on the error display LED 374 as a prepaid card unit unconnected error. When communication with the card unit 50 is performed at an improper timing, control is performed to display “9” on the error display LED 374 as a prepaid card unit communication error. The prepaid card unit communication error is detected in the prepaid card unit control process (step S754).

  In addition, when the start error bit set due to not receiving the payout start command from the main board 31 at the start of power supply is set, control for displaying “A” on the error display LED 374. I do.

  Among the above errors, after a payout switch abnormality detection error 2, a payout case error, a prize ball REQ signal error or a start-up error occurs, the error release switch 375 is operated and an operation signal is output from the error release switch 375 (ON When the state is reached, the payout control means returns to the state before the error occurred.

  As for the startup error, even if an operation signal is output from the error release switch 375, it may be configured not to return to the state before the error occurred.

  FIG. 58 is a flowchart showing the error processing in step S757. In the error processing, the payout control CPU 371 checks the error flag, and the set bits are only the payout switch abnormality detection error 2, the payout case error, the winning ball REQ signal error, or the start error bit (out of four). It is confirmed whether or not only one of the two bits is, only two of the four bits, only three of the four bits, or only four of them (step S801). If only those bits are set, it is confirmed whether or not the operation signal is turned on from the error release switch 375 (step S802). The payout control CPU 371 does not turn on the operation signal from the error release switch 375 even if the payout number count switch 301 detects the payout of the game ball in the error state in which the payout case error bit is set. Unless this happens, the error bit of the payout case error is not reset (see steps S803 to S807). That is, even if the payout detecting means detects payout of a prize game medium that has not been paid out, the error state is continued. When the operation signal is turned on, the error recovery time is set in the pre-error recovery timer (step S803). The error recovery time is the time from when the error release switch 375 is operated until the actual return from the error state to the normal state.

  If the operation signal from the error release switch 375 is not on, the value of the timer before error recovery is confirmed (step S804). If the value of the timer before error recovery is 0, that is, if the timer before error recovery is not set, the process proceeds to step S808. If the pre-error recovery timer is set, the value of the pre-error recovery timer is decremented by -1 (step S805). If the pre-error recovery timer value becomes 0 (step S806), the payout switch of the error flags The bits of the abnormality detection error 2, the payout case error and the prize ball REQ signal error are reset (step S807), and the process proceeds to step S808.

  When the processing of step S807 is executed, there may be an error bit that is not in the set state among the bits of the payout switch abnormality detection error 2, the payout case error, and the prize ball REQ signal error. There is no problem resetting error bits that are not in the state. As described above, in this embodiment, when an error (see FIG. 57) that causes the setting of the payout switch abnormality detection error 2, the payout case error, or the prize ball REQ signal error bit occurs, an error occurs. The error is released when the release switch 375 is pressed.

  When the process of step S807 is executed and the payout case error bit is reset, the payout control code is “2” (corresponding to the execution of the payout passing waiting process shown in FIGS. 53 to 54), and the prize ball When the value of the unpaid-out number counter or the value of the ball-lending unpaid-out number counter is not 0, a retry operation for game ball payout is started. That is, when the award ball lending control process of step S766 is executed next, when the payout passing waiting process of step S612 is executed, the repayment process is performed again. For example, if a prize ball payout process has been performed and the value of the prize ball unpaid number counter is not 0, the process proceeds from step S654 to step S659, and it is confirmed in step S659 that the error bit is in a reset state. Therefore, the process for starting the re-payout process after step S662 is executed again, and the re-payout process is executed. In addition, regarding the payout case error bit reset by pressing the error release switch 375, when the bit is set (when step S666 is executed), the payout control timer has already expired. Therefore, when the process in step S807 is executed and the payout case error bit is reset, the payout control timer = 0 is determined in the determination in step S652 when the payout passage waiting process is executed next. When the payout case error bit is set, the re-payout operation in-progress bit is 0 (since the re-payout operation in-progress bit is set to 0 in step S665, step S666 is executed). Therefore, step S662 is always executed whenever it is confirmed in step S659 that the error bit is in the reset state. That is, the re-payout process is always executed.

  As described above, the payout control means is used to pay out a game ball when the payout number count switch 301 detects no game ball even though the ball payout device 97 pays out a game ball. After performing the correct payout control for causing the ball payout device 97 to execute the retry operation for a predetermined number of times (for example, twice) as a limit, the payout number count switch 301 has detected no game balls. When it is detected (see step S661 and after in FIG. 54), the control state related to the payout is shifted to the error state, and the correction payout control is performed again on the condition that the error release signal is output from the error release switch 375 in the error state. A correction payout control restart process for executing

  Further, even during re-payout processing in an error state (specifically, during re-payout processing before setting a payout case error and during re-payout processing after the error release switch 375 is pressed), steps S601 to S601 shown in FIG. The process of S604 is being executed. That is, even when an error relating to payout occurs, if the game ball passes the payout number count switch 301, the value of the award ball unpaid number counter or the ball lending unpaid number counter is subtracted. Therefore, the value of the award ball unpaid number counter or the ball lending unpaid number counter when returning from the error state is a value reflecting the number of game balls actually paid out. That is, even if an error related to payout occurs, the number of game balls actually paid out can be accurately managed.

  Also, in the payout passing waiting process shown in FIGS. 53 to 54, even when it is confirmed that the game ball has been paid out as a result of the re-payout process, the payout case error bit is not reset. The bit of the payout case error is reset only when the error release switch 375 is operated (specifically, when an error return time after operation has elapsed) (steps S802 and S807). That is, the state of the payout case error (payout shortage error) is not automatically canceled based on the fact that the game ball has passed the payout number count switch 301, etc. The error is not cleared. Therefore, the game store clerk and the like can surely recognize that a shortage of payout has occurred.

  When the error cancel switch 375 is operated so as to be reset in hardware (reset to the payout control CPU 371), the error cancel switch 375 is operated, for example, a prize ball has not been paid out. The value of the number counter is also cleared. However, in this embodiment, since the payout control means is configured to perform the re-payout operation again by operating the error release switch 375, the payout process is executed reliably, which is disadvantageous to the player. Can not be given.

  In step S808, the payout control CPU 371 checks the detection signal of the full tank switch 48. If the detection signal of the full tank switch 48 is output (if it is in the ON state), the full tank error bit in the error flag is set (step S809). If the detection signal of the full tank switch 48 is in the OFF state, the full tank error bit is reset (step S810).

  Also, the payout control CPU 371 checks the detection signal of the ball break switch 187 (step S811). If the detection signal of the ball break switch 187 is output (if it is on), the ball break error bit in the error flag is set (step S812). If the detection signal of the ball break switch 187 is OFF, the ball break error bit is reset (step S813). When the ball break error bit is set, the bit corresponding to the ball break LED 52 in the output port 1 buffer is set to a value corresponding to the lighting state in the display control processing in step S771.

  Further, as shown in FIG. 59, the payout control CPU 371 checks the state of the connection confirmation signal from the main board 31 (step S815). If the connection confirmation signal is not output (if it is in the off state), The main board unconnected error bit is set (step S816). If the connection confirmation signal is output (if it is on), the main board non-connection error bit is reset (step S817).

  Further, the payout control CPU 371 checks the value of the switch timer corresponding to the payout number count switch 301 among the switch timers in which the state of the detection signal of each switch is set, and the value is the switch on maximum time (for example, “ 240 ") (step S818), the bit of the payout switch abnormality detection error 1 is set in the error flag (step S819). If the value of the switch timer corresponding to the payout number count switch 301 is less than the switch-on maximum time, the bit of the payout switch abnormality detection error 1 is reset (step S820). Note that the value of each switch timer is incremented by 1 when the state of the input port to which the detection signal of each switch is input is switched on in the switch check process of step S761, and is cleared by 0 when it is off. Accordingly, the fact that the value of the switch timer corresponding to the payout number count switch 301 exceeds the maximum switch-on time means that the payout number count switch 301 is in the ON state beyond the maximum switch-on time. Then, it is determined that the game ball is clogged at the disconnection of the payout number count switch 301 or at the portion of the payout number count switch 301.

  Further, the payout control CPU 371, when the value of the switch timer corresponding to the payout number count switch 301 becomes a switch-on determination value (eg, “2”) (step S821), the ball lending operation flag and the winning ball operation If both the middle flags are in the reset state, the game ball has passed through the payout number count switch 301 even though the payout operation is not in progress, and the bit of the payout switch abnormality detection error 2 in the error flag is set (steps S822 and S823). . If the ball lending operation flag or the winning ball operation flag is set, the bit of the payout switch abnormality detection error 2 is reset (step S824).

  Further, the payout control CPU 371 checks the input state of the VL signal from the card unit 50 (step S825). If the VL signal is not input (if it is in the OFF state), the prepaid card unit not yet out of the error flags is displayed. A connection error bit is set (step S826). If the VL signal is input (if it is on), the prepaid card unit unconnected error bit is reset (step S827).

  Further, the payout control CPU 371 checks the state of predetermined error bits (in this example, full error bit, ball out error bit, main control unconnected error bit) in the error flag (step S828a), and the predetermined error If any of the error bits is set, the payout error signal is turned on (step S828b). If all the predetermined error bits are in the reset state, the payout error signal is turned off (step S828c).

  In the display control process in step S759, notification by display (numerical value display) corresponding to the error bit in the error flag is performed by the error display LED 374.

  In this embodiment, the main board unconnected error is automatically eliminated when the connection confirmation signal is turned on (see steps S815 and S817), but the condition that the error cancel switch 375 is further operated is added. Thus, the error state may be eliminated.

  In this embodiment, a communication error is reported so as to be distinguishable from a communication error with the card unit 50 (a prepaid card unit unconnected error and a prepaid card unit communication error) and other errors (see FIG. 57). ). Therefore, a communication error between the game control unit and the payout control unit is easily identified.

  In this embodiment, the error display LED 374 mounted on the payout control board 37 installed on the back side of the gaming machine is informed that an error relating to the payout has occurred. You may mount an alerting | reporting means in other locations (For example, the payout unit in which the ball payout apparatus 97 etc. were concentratedly arranged). Furthermore, you may make it alert | report by the indicator (for example, prize ball LED51) installed in the front side of the gaming machine. In the display control process, the payout control CPU 371 performs control for turning on the prize ball LED 51 when the prize ball REQ signal is on. When the prize ball REQ signal is off, the prize ball LED 51 is displayed. Control for turning off the light is performed. When an error relating to payout occurs, for example, the prize ball LED 51 is blinked to notify that an error related to payout has occurred. If an error is notified by a display device installed on the front side of the gaming machine, the game shop clerk can more easily recognize the occurrence of the error. Moreover, you may use together the alerting | reporting by error display LED374, and the alerting | reporting by the indicator installed in the front side of the gaming machine.

  FIG. 60A is a timing chart showing a state of occurrence of a payout case error (payout shortage error), and FIG. 60B is a timing chart showing a state when the error release switch 375 is operated.

  As shown in FIG. 60A, the payout motor 289 is rotated to pay out a predetermined number of game balls, and after the rotation stops, the game ball that should have been paid out last passes the payout number count switch 301. Later (after 402.087 ms in this example), it is confirmed whether or not there is an unpaid game ball (corresponding to the determination in step S654), and if there is an unpaid game ball, a re-payout operation is executed. FIG. 60A shows an example in which two re-payout operations are executed. When two re-payout operations are executed, it is determined as a payout case error (corresponding to the determination in step S661), and “4” is displayed on the error display LED 374 by the display control processing in step S759 (FIG. 57).

  As shown in FIG. 60B, when the error release switch 375 is operated, the re-payout operation is started again after the error release time has elapsed. As shown in FIG. 60B, when the re-payout operation is started again, the display of “4” on the error display LED 374 is erased. That is, when the corrected payout control is performed after the operation of the error release switch 375, a notification indicating an insufficient payout error is not performed.

  FIG. 61 is an explanatory diagram showing an example of changes in the contents of the counter used in the prize ball payout control. The prize ball payout scheduled total counter, the previous prize ball payout scheduled total counter, the payout operation counter, and the prize ball non-payout number counter are cleared to 0 in the initialization process (specifically, the process of step S712). Thereafter, for example, when 15 prize ball number commands are received, the value of the prize ball payout total counter is 15 in the prize ball REQ interrupt process. Then, when the prize ball payout process is started, 15 is set in the previous prize ball payout scheduled total counter, the payout operation counter, and the prize ball non-payout number counter (see steps S632 to S634). Thereafter, each time the payout motor position sensor 295 is turned on, the value of the payout operation counter is decremented by 1, and every time the payout number count switch 301 is turned on, the value of the award ball non-payout number counter is decremented by 1. In the meantime, for example, when 10 prize ball number commands are received, 10 is added to the prize ball payout scheduled total counter in the command analysis process to become 25.

  Then, a prize ball payout total counter (PA) is added by an addition process executed when the value of the payout operation counter reaches a predetermined value (in this example, “1”, but the predetermined value may not be 1). ) And the difference (10 in this example) between the contents of the previous award ball payout scheduled total counter (PB) are added to the payout operation counter and the award ball unpaid number counter. Accordingly, the value of the payout operation counter and the award ball non-payout number counter is 11. Further, the contents of the previous prize ball payout scheduled total counter (PB) are the same as the contents of the prize ball payout scheduled total counter (PA) (see steps S695 to S697).

  Thereafter, when the value of the unsuccessful prize ball counter reaches zero and the prize ball payout is completed, the previous prize ball payout total counter (PB) is determined from the content of the prize ball payout total counter (PA) (25 in this example). Is subtracted (the subtraction result is 0 in this example), and the previous award ball payout scheduled total counter (PB) is cleared.

  FIG. 62 is an explanatory diagram showing another example of changes in the contents of the counter used in the prize ball payout control. The contents of the total number of winning ball payout counter (PA) and the value of the previous winning ball payout total counter (PB) are 15, and 10 winning ball number commands are received during the paying out of the winning ball. And Then, in the prize ball REQ interrupt process, 10 is added to the prize ball payout scheduled total counter to 25.

  Then, by the addition process executed when the value of the payout operation counter reaches a predetermined value (for example, 1), the contents of the planned total payout ball counter (PA) and the total previous payball payout total counter (PB) (10 in this example) is added to the payout operation counter and the award ball non-payout number counter. Accordingly, the value of the payout operation counter and the award ball non-payout number counter is 11. Further, the contents of the previous winning ball payout scheduled total counter (PB) are the same as the contents of the winning ball payout scheduled total counter (PA).

  It is assumed that the prohibition condition for the extra process is satisfied when the winning ball payout process is continued (see steps S691 and S692). Therefore, it is assumed that the addition process is not executed, but 15 prize ball number commands and 10 prize ball number commands are received during that time. Then, in the command analysis process, 15 and 10 are added to the prize ball payout scheduled total counter to be 50.

  When the prohibition condition for the extra process is canceled, the contents of the total prize ball payout counter (PA) and the previous prize ball payout total counter are executed by the extra process executed when the value of the payout operation counter reaches a predetermined value. The difference between the contents of (PB) (25 in this example) is added to the payout operation counter and the award ball unpaid number counter, and the value of the payout operation counter and the award ball unpaid number counter becomes 26. Further, the contents of the previous winning ball payout scheduled total counter (PB) are the same as the contents of the winning ball payout scheduled total counter (PA).

  Thereafter, when the value of the award ball unpaid number counter becomes 0 and the award ball payout is completed, the previous award ball payout total counter (PB) is determined from the content of the award ball payout total counter (PA) (50 in this example). Is subtracted (the subtraction result is 0 in this example), and the previous award ball payout scheduled total counter (PB) is cleared.

  As described above, in this embodiment, in the command analysis process, the number based on the prize ball number command received from the game control means is used as a counter (for example, the control during the prize ball payout) (for example, Rather than immediately adding (adding) to the payout operation counter), it is used for the control during payout of a winning ball when a predetermined condition (for example, the value of the payout operation counter reaches a predetermined value) is satisfied. Add to the counter. Therefore, the number of executions of the extra process can be reduced as compared with the case where it is added to the counter used for the control during the payout of the prize ball every time the prize ball number command is received.

  In this embodiment, a method of using the previous award ball payout scheduled total counter is used to determine whether or not the number of prize balls to be paid out has increased, but such a method is an example, Other methods may be used. For example, a cumulative counter that cumulatively adds the number indicated by the prize ball number command received after the start of the prize ball payout process is provided, and in the addition process, the count value of the cumulative counter is added to the prize ball unpaid number counter and the payout operation counter. The contents of the cumulative counter may be cleared. In such a configuration, the cumulative counter corresponds to the prize game medium number data storage means to which the number instructed by the prize ball number command is added.

  Further, in this embodiment, the winning ball payout total number counter and the winning ball unpaid number counter are used together, but either one of the counters may be used. FIG. 63 is an explanatory diagram showing an example of changes in the contents of the counter used in the prize ball payout control when the prize ball unpaid number counter is not used. In this case, when the number-of-payout count switch 301 is turned on, 1 is subtracted from the values of the award winning ball payout total counter and the previous winning ball payout total counter.

  The winning ball payout total counter, the previous winning ball payout total counter and the payout operation counter are cleared to 0 in the initialization process in the main process. Thereafter, for example, when 15 prize ball number commands are received, the value of the prize ball payout total counter is 15 in the command analysis process. When the winning ball payout process is started, 15 is set in the previous winning ball payout scheduled total counter and the payout operation counter. Thereafter, each time the payout motor position sensor 295 is turned on, the value of the payout operation counter is decremented by 1, and every time the payout number count switch 301 is turned on, the values of the award ball payout scheduled total counter and the previous award ball payout scheduled total counter are 1. Subtracted. In the meantime, for example, when 10 prize ball number commands are received, 10 is added to the prize ball payout scheduled total counter in the command analysis process. At this time, if the value of the prize ball payout scheduled total counter is 6, it is updated to 16.

  Then, by the addition process executed when the value of the payout operation counter reaches a predetermined value, the difference between the contents of the award ball payout total counter (PA) and the content of the previous award ball payout total counter (PB) (this In the example, 10) is added to the payout operation counter. Therefore, the value of the payout operation counter is 11. Further, the contents of the previous winning ball payout scheduled total counter (PB) are the same as the contents of the winning ball payout scheduled total counter (PA). When the extra process is executed, the value of the prize ball payout scheduled total counter is reduced from 16 to 11 (because 5 payouts have been made).

  Thereafter, when the value of the prize ball payout scheduled total counter becomes 0 and the prize ball payout ends, the previous prize ball payout scheduled total counter (PB) is cleared. However, if the control is performed normally, the previous prize ball payout scheduled total counter (PB) is already zero.

  FIG. 64 is an explanatory diagram showing another example of changes in the contents of the counter used in the prize ball payout control. The contents of the total number of winning ball payout counters (PA) and the value of the total number of previous winning ball payouts total counter (PB) are 6, and 10 winning ball number commands are received during paying out the winning balls. And Then, in the command analysis process, 10 is added to the prize ball payout scheduled total counter to be 16.

  Then, by the addition process executed when the value of the payout operation counter reaches a predetermined value (for example, 1), the contents of the planned total payout ball counter (PA) and the total previous payball payout total counter (PB) (10 in this example) is added to the payout operation counter. Therefore, the value of the payout operation counter is 11. Further, the contents of the previous winning ball payout scheduled total counter (PB) are the same as the contents of the winning ball payout scheduled total counter (PA).

  It is assumed that the prohibition condition for the extra process is satisfied when the winning ball payout process is continued. Therefore, it is assumed that the addition process is not executed, but 15 prize ball number commands and 10 prize ball number commands are received during that time. Then, in the command analysis process, 15 and 10 are added to the prize ball payout scheduled total counter, for example, 28. At this time, the value of the total number of the previous winning ball payout scheduled total counter is 3.

  When the prohibition condition for the extra process is canceled, the contents of the total number of expected payout payout counter (PA) and the previous prize ball are obtained by the extra process executed when the value of the payout operation counter reaches a predetermined value (for example, 1). The difference (25 in this example) of the contents of the scheduled payout total counter (PB) is added to the payout operation counter, and the value of the payout operation counter becomes 26. Further, the contents of the previous winning ball payout scheduled total counter (PB) are the same as the contents of the winning ball payout scheduled total counter (PA).

  Thereafter, when the value of the prize ball payout scheduled total counter becomes 0 and the prize ball payout ends, the previous prize ball payout scheduled total counter (PB) is cleared.

  FIG. 65 is a flowchart showing a prize ball lending control process in an embodiment in which no prize ball unpaid number counter is used. In this embodiment, if the prize ball payout process is performed when the payout number count switch 301 is turned on, the values of the total prize ball payout total counter (PA) and the previous prize ball payout total counter (PB) are set. -1 (steps S604A and S604B). In addition, in the award ball payout amount addition control (step S600), the setting of the award ball unpaid number counter (step S696 in FIG. 50) is not executed.

  FIG. 66 is a flowchart showing a payout start waiting process in an embodiment in which no prize ball payout counter is used. In this embodiment, unlike the above-described embodiment, a process (step S633) of setting the contents of a prize ball payout total counter (PA) in the prize ball unpaid-out number counter at the start of the prize ball payout process is performed. Do not execute.

  FIG. 67 and FIG. 68 are flowcharts showing the payout passing waiting process in the embodiment that does not use the prize ball non-payout number counter. In this embodiment, the payout control means confirms that the award ball payout process continuously executed without dividing the payout of game balls according to a plurality of prize ball number commands for each prize ball number command is completed. The determination is made when the value of the total number of prize balls to be paid out counter (PA) becomes 0 (step S654A). In addition, when the re-payout operation is started, the contents of the total number of expected winning balls (PA) are set in the payout operation counter (step S663A).

  Note that the processes in the payout control process other than the processes described here are the same as those in the above-described embodiment.

  As described above, in each of the above embodiments, in the command analysis process, the number based on the prize ball number command received from the game control means is used as a counter used for the control during the prize ball payout at that time. Rather than immediately adding (adding) to (for example, a payout operation counter), it is used for control during payout of a winning ball when a predetermined condition (for example, the value of the payout operation counter has reached a predetermined value) is satisfied. Is added to the counter. Therefore, the number of executions of the extra process can be reduced as compared with the case where it is added to the counter used for the control during the payout of the prize ball every time the prize ball number command is received.

  In addition, as described above, the payout number count switch 301 for detecting the payout of the game ball without distinguishing between the winning ball and the lending ball is provided, and the detection output of the payout number count switch 301 is input only to the payout control means, and the payout control is performed. When the means inputs a detection signal from the payout number count switch 301, it determines whether it is a detection of a prize ball or a payout of a lending ball. Since the configuration is such that the ball count signal is transmitted to the game control means, the game control means can more reliably manage the number of unpaid prize balls and one payout number count switch 301 can be used. Since both the winning ball payout and the lending ball payout are detected, the number of parts is reduced, and the cost of the gaming machine can be reduced.

  Further, in the above-described embodiment, the payout control means detects the winning ball payout when the detection signal from the payout number count switch 301 is input even in an error state where the payout of the game ball is stopped. When it is determined that there is a prize ball, a prize ball count signal is transmitted to the game control means, so that a prize ball count signal indicating that a payout of the prize ball has been detected can be reliably transmitted to the game control means. .

  Further, in the above-described embodiment, the payout control means receives the detection signal from the payout number count switch 301 when the award ball is not paid out or the lending ball is not paid out. Since the award ball count signal is transmitted to the game control means as being a prize ball, the award ball count signal can be transmitted to the game control means even when an invalid gaming ball is paid out. Can be processed appropriately.

  In the above-described embodiment, when power supply to the gaming machine is started, the gaming control microcomputer 560 is operated with a predetermined delay from the timing at which the payout controlling microcomputer 370 becomes operable. Since the delay means (for example, the delay circuit 69 and the means for executing software delay processing) to enable the state is provided and the delay processing can be performed by hardware or software, the specification is changed. In addition, the versatility of delay processing by software can be left in preparation, and the delay processing by software can be simplified, and the data capacity of software for delay processing can be reduced. In addition, since the payout control microcomputer 370 becomes operable before the game control microcomputer 560, the payout control microcomputer 370 surely receives a command from the game control microcomputer 560. Will be able to.

  In the embodiment described above, after the payout command signal is transmitted, the signal indicating the completion of the payout process from the payout control board 37 side is stored in the total winning ball number storage buffer regardless of whether or not it is received. The winning ball number subtraction process is executed and the game control means does not accurately manage the number of unpaid prize balls. However, after the game control means transmits a payout command signal, In accordance with reception of the count signal, a subtraction process for subtracting the number of payouts confirmed to be actually paid out from the number of prize balls stored in the total prize ball number storage buffer may be performed. In this case, after transmitting the payout command signal, the game control means performs the subtraction process of the number of prize balls stored in the total prize ball number storage buffer regardless of whether or not a signal indicating the completion of the payout process is received. However, every time a prize ball count signal is received, it is sufficient to subtract one from the number of prize balls commanded by the payout command signal. If the configuration is such that the number of unpaid prize balls is managed by bidirectional communication between the game control means and the payout control means as described above, in the game control means based on the prize ball count signal from the payout control means. The number of unpaid prize balls can be managed accurately. In other words, if the management of the number of unpaid balls is not performed using the prize ball count signal, the management of the number of unpaid balls is performed by one-way communication. There is a problem that the number of unpaid prize balls ascertained in the means is not always accurate. As described above, if the configuration is such that the game control means manages the number of unpaid balls in the game control means as described above, the number of unpaid balls can be subtracted when the game is actually paid out. The number of unpaid prize balls can be managed accurately.

  Further, the payout control means transmits a command acceptance signal indicating that the payout command signal transmitted from the game control means has been received to the game control means, and the game control means accepts the command acceptance transmitted from the payout control means. When the signal is received, the winning ball number stored in the total winning ball number storage buffer may be subtracted. Here, the command acceptance signal corresponds to an acceptance confirmation signal for the payout command signal, and is in an output state for a predetermined period based on the receipt of the payout command signal. This command acceptance signal is also called a prize ball BUSY signal. Even in such a configuration, the number of unpaid prize balls can be centrally managed by the game control means.

  In the above-described embodiment, the game control means performs a process for lighting a predetermined lamp in order to notify that one prize ball has been paid out in response to reception of the prize ball count signal. Since it is configured to execute, even if the predetermined lamp is not controlled by the payout control means (that is, the control means for receiving the detection signal from the payout number count switch 301), the winning ball has been paid out or is paid out. It is possible to notify the player and the game store clerk that the played game ball is a prize ball. In the above example, as a process for turning on the predetermined lamp, a process of transmitting a prize ball payout confirmation designation command to the effect control board 80 is executed. When the prize ball payout confirmation designation command is received, the effect control board 80 outputs a control signal via the lamp driver board 35 and executes control for lighting a predetermined lamp for a predetermined period. However, the game control unit may control the predetermined lamp, and the game control unit may execute a driving process for lighting the predetermined lamp in response to receiving the prize ball count signal. Further, it may be notified that a prize ball has been paid out by a light emitter other than a predetermined lamp or a display device. In the embodiment described above, the payout control means controls the prize ball lamp 51. However, the prize control lamp 51 is controlled by the effect control means or the game control means, and the prize is given as the predetermined lamp. A ball lamp 51 may be used.

  In the above embodiment, the payout request is made by the prize ball REQ signal and the payout number is designated by the prize ball number signal. However, the payout request and the payout number are designated by the prize ball number signal. May be. In this case, the payout control means may determine that a payout request is made at the same time when the prize ball number signal is output. According to such a configuration, it is not necessary to use the prize ball REQ signal.

  In the above embodiment, the ball payout device 97 is configured to execute both ball lending and prize ball payout. However, even if the mechanism for lending the ball and the mechanism for paying the prize ball are independent, The invention can be applied.

  In the above-described embodiment, the payout is prohibited when the ball is out of the ball or the lower pan is full. However, when it is not preferable to perform another payout or when the payout cannot be performed, You may set it in a payout prohibition state. For example, the payout prohibition state may be set also when the glass door frame 2 is in an open state and a detection signal is output from a door opening switch for detecting this.

  In the above-described embodiments, different expressions such as transmission / reception and output / input are used for the exchange of various signals, but transmission and output or reception and input are used in substantially the same meaning. It goes without saying that these expressions are interchangeable. In addition, the transmission / reception of signals having many meanings such as control commands is made transmission / reception, and the transmission / reception and output / input are made of transmission / reception of signals for transmitting information by switching on / off. There are also cases where they are used properly. Even in this case, these expressions are interchangeable.

  In the above embodiment, a signal from the main board 31 to the peripheral board is output to each peripheral board via the central relay board 77. The main board 31 is provided with signal direction regulating means for preventing signal input from the centralized relay board 77. The central relay board 77 is provided with a signal direction regulating means for preventing signal input from the peripheral board. Furthermore, in an electrical component control board equipped with a microcomputer that inputs a signal from the main board 31 and does not send a signal to the main board 31, the signal is input from the central relay board 77 to the central relay board 77. Signal direction restricting means for preventing signal output is provided.

  Thus, the signal from the main board 31 to each peripheral board is concentrated on the central relay board 77, and the signal direction regulating means is provided for the signal output to the central relay board 77 in the main board 31. Therefore, it is possible to effectively prevent the input of an illegal signal that illegally pays out a prize ball to the main board 31 or illegally generates a big hit.

  In particular, among the peripheral boards, there is also provided a peripheral board (for example, an effect control board 80) for inputting signals from a board provided in a gaming machine other than the main board 31 or a gaming device provided in the gaming machine. However, it is possible to effectively prevent an illegal signal from being sent to the main board 31 via the peripheral board using a signal line from the board other than the main board 31 or the gaming device to the peripheral board. it can.

  In the above embodiment, the presentation control board 80 is exemplified as an electric component control board on which a microcomputer that inputs signals from the main board 31 and does not send signals to the main board 31 is used. If there is another electrical component control board on which a microcomputer that does not send signals to the main board 31 is input, the signal from the main board 31 also passes through the centralized relay board 77 for that board. In addition, a signal direction regulating means for preventing signal output to the central relay board 77 is provided at a portion where a signal is input from the central relay board 77.

  By adopting the configuration as described above, there is a suspicious point in the operation of the gaming machine, and a fraudulent act (a signal that illegally pays out a prize ball to the main board 31 or illegally generates a big hit is input. In the case where there is a suspicion of an act to be performed, for example, an act of connecting an unauthorized board to a peripheral board or a cable between boards, only the central relay board 77 needs to be examined except for the main board 31. Even if an illegal signal is sent to the central relay board 77 in order to send an illegal signal to the main board 31, the signal is sent to the main board 31 side by the signal direction regulating means mounted on the central relay board 77. This is because the signal transmission is blocked.

  In addition, since only one centralized relay board 77 needs to be investigated, compared to the case where a large number of relay boards are provided, in particular, compared to the case where a large number of relay boards are arranged in cascade. Survey time can be shortened.

  In the above embodiment, one central relay board 77 is provided for all peripheral boards, but a plurality of relay boards may be provided in parallel. For example, one relay board may be provided for each peripheral board or for several peripheral boards (not all peripheral boards). In such a case, there is a possibility that the investigation time for fraud may be longer, but there is a merit that it is easy to route the wiring inside the gaming machine.

  Further, as described above, in the above embodiment, the game control means transmits a payout start command to the payout control means when power supply to the gaming machine is started (step S11), and then clears. The check signal of the switch 921 is checked (step S13), and the payout control means checks the detection signal of the clear switch 921 when receiving a payout start command from the game control means (steps S726, S727, S708) Although the game control means executes the software delay processing, the game control means and the payout control means check the detection signal of the clear switch 921 almost simultaneously. Therefore, although one control means has performed the detection signal check processing of the clear switch 921, the other control means does not perform the detection signal check processing of the clear switch 921 and the backup storage contents in one control means. This prevents the situation in which the backup storage contents in the other control means are not cleared even though they are cleared.

  Further, the payout control means introduces a take-in signal (in the above embodiment, a prize ball REQ signal) instructing taking-in of the payout start command into the maskable interrupt terminal of the payout control microcomputer, and from the game control means. When confirming that the payout start command has been sent (the initial setting process is in progress), check the input of the capture signal by checking the bit in the external interrupt request register with interrupts disabled. (Steps S701 and S721). Therefore, even if it is configured to introduce the capture signal to the interrupt terminal, there is no possibility that the initial setting process is not correctly performed due to the occurrence of the interrupt. If an interrupt is allowed during the initial setting process, the internal state of the payout control microcomputer changes during the interrupt process, and the initial setting process may not be performed correctly.

  In the payout control process executed after executing the initial setting process and the initialization process, the payout control means is awarded with an interrupt process based on an input signal to the maskable interrupt terminal (external terminal interrupt). Since the prize ball number signal indicating the number of balls paid out is received, the number of prize balls paid out based on the prize ball number signal can be received quickly and accurately.

  In the above embodiment, when the game control means starts supplying power to the gaming machine, the execution state is restored (steps S16 and S17) or the stored contents are initialized (steps S21 to S23). From the payout control means after the preparation for execution of the game control process is completed (process that should be executed before starting the timer interrupt process (process excluding command transmission process by external interrupt)) In response to receiving the command receivable state signal, the game control process is started and the process for transmitting the prize ball control signal is executed in the game control process. It is possible to prevent the prize control signal from being transmitted by the game control means when the command reception process corresponding to the terminal interrupt is not yet executed, and the payout control The omission of prize balls control signal at stage can be reliably prevented.

  In the above embodiment, since the transmission process of the control command received by the external terminal interrupt is executed in the recovery process and the initialization process, “when the preparation for executing the game control process is completed” Means a state in which processing other than processing related to command transmission in the recovery processing and initialization processing has been completed. However, when the configuration is such that the transmission process of the control command received by the external terminal interrupt is not executed in the recovery process and the initialization process (for example, the control command transmission process is executed but the external interrupt is performed in the same manner as the payout start command) (In such a case, the request register may be used for transmission), and “when preparation for execution of the game control process is completed” means that the recovery process or the initialization process has been completed. means.

  Although not particularly mentioned in the above-described embodiment, when a command reception ready state signal is waiting to be received, a predetermined waiting time is measured and the command reception ready state signal is not received. When the standby time has elapsed, the control state of the game control means may be set to the control stop state. If comprised in this way, it can prevent that a game control process is started and a prize ball control signal is transmitted in the state where the payout control process may not be started in the payout control means.

  In the embodiment described above, the payout control means is configured not to perform the recovery process when the receipt of the payout start command from the game control means is not confirmed. However, the payout start command from the game control means is not used. The recovery process may be executed when the reception of the message is not confirmed. With this configuration, when the payout activation command is not received, the recovery process is executed without confirming the state of the clear switch 921. In this case, the error notification based on the setting of the error bit in step S715 is a notification indicating that the initialization process is not executed based on the fact that it cannot be normally determined whether to restore or initialize. Therefore, the game store clerk who has recognized the error notification can take a countermeasure such as turning on the power of the gaming machine again.

  Further, in the above embodiment, after the preparation for execution of the game control process is completed, the execution of the game control process is started in response to the reception of the command receivable state signal from the payout control means. When the preparation for execution of the game control process is completed, a signal indicating that (game control preparation completion signal) is transmitted as a signal received by the external terminal interrupt, and paid out in response to the reception of the game control preparation completion signal It is good also as a structure which starts execution of a game control process according to having received the signal (payout control preparation completion signal) transmitted by the control means.

  Hereinafter, an embodiment in which control is performed by exchanging a game control preparation completion signal and a payout control preparation completion signal will be described. In this embodiment, the process of transmitting the command receivable state signal (step S718) and the process of receiving (steps S18 and S24) are not executed, but the other processes are the same as those described above except for the processes specifically mentioned in the following description. It is the same as the embodiment.

  FIG. 69 is a flowchart showing a part of main processing executed by the CPU 56 in this embodiment. In this embodiment, when an initial value is set in the work area in the recovery process or the initialization process (steps S17 and S23), the CPU 56 is ready for game control indicating that preparation for starting the game control process is completed. After transmitting the signal to the payout control board 37 (steps S33a and S33b), it is checked whether or not a payout control preparation completion signal from the payout control CPU 371 has been received (steps S34a and S34b).

  That is, the CPU 56 repeatedly transmits a game control preparation completion signal until it confirms reception of the payout control preparation completion signal. In this example, the game control preparation completion signal is constituted by a prize ball number signal. Specifically, a signal having a configuration in which the lower 4 bits (bit 0 to bit 3) of the award ball number signal indicate a predetermined number (for example, “1”) that is not used as the award ball number is ready for game control. It shall be used as a signal. Here, a prize ball number signal in which bits 1 to 4 are “0” and bit 0 is “1” is used as a game control preparation completion signal.

  Accordingly, in steps S33a and S33b, the CPU 56 transmits a game control preparation completion signal in which only bit 0 of the award ball number signal is “1” and performs a process of turning on the award ball REQ signal.

  When the payout control preparation completion signal is received from the payout control CPU 371 (Y in step S34a, Y in S34b), the CPU 56 proceeds to the processes in steps S19 and S25.

  FIG. 70 is a flowchart showing a prize ball REQ interrupt process executed by the payout control CPU 371 in this embodiment. In the prize ball REQ interrupt process, the payout control CPU 371 checks whether or not the received signal is a game control preparation completion signal if the connection confirmation signal is on. That is, it is confirmed whether or not the state of the prize ball number signal is a state indicating a game control preparation completion signal (a state in which only bit 0 is “1”) (step S548). If it is a game control preparation completion signal, the payout control CPU 371 transmits to the main board 31 a payout control preparation completion signal indicating that command reception processing by external terminal interruption is possible (step S549). ). If it is not a game control preparation completion signal, the payout control CPU 371 proceeds to the processing of step S545 because the state of the prize ball number signal is a normal state indicating the number of prize balls to be paid out.

  As described above, in this embodiment, when the power supply to the gaming machine is started, the game control means returns the execution state (steps S16 and S17) or initializes the stored contents (steps S21 to S23). After completing the preparation for execution of the game control process (process that should be executed before starting the timer interrupt process (process excluding the command transmission process by external interrupt)), the game control process A game control preparation completion signal indicating that preparation for execution of the game has been completed, and in response to receiving a payout control preparation completion signal from the payout control means, the execution of the game control process is started and the game Since the process for transmitting the prize ball control signal is executed in the control process, the payout control means is still in a state where the command reception process corresponding to the external terminal interrupt cannot be executed. , Winning balls control signal by the game control means can be prevented from being transmitted, the omission of prize balls control signal in the payout control means it can be reliably prevented.

  Although not particularly mentioned in the above embodiment, as shown in FIG. 71, a standby time that is predetermined when the payout control preparation completion signal is waiting to be received (N in steps S34a and S34b). (Step S35), and when the standby time has passed without receiving the command receivable state signal (Y in step S35), the control state of the game control means may be set to the control stop state. If comprised in this way, it can prevent that a game control process is started and a prize ball control signal is transmitted in the state where the payout control process may not be started in the payout control means.

  In the above-described embodiment, when the payout activation command is waiting to be received (N in steps S721 to S723), a predetermined standby time is measured, and the standby time is received without receiving the payout activation command. When the time has elapsed (Y in step S723), the control state of the payout control means is set to the control stop state (for example, the operation is stopped without starting the payout control process. Specifically, it is determined as Y in step S714). When it is done, it is only necessary to enter a stop state without shifting to the process of step S716. With this configuration, it is possible to prevent the payout control process from being started in a state where the game control process may not be started in the game control means.

  In the above embodiment, after the control stop state as described above is entered, a game control preparation completion signal is transmitted again when a predetermined period has elapsed (for example, the control stop state shown in FIG. 71 continues for the predetermined period). When the payout control preparation completion signal is received (Y in Steps S34a and S34b), the game control process is resumed and execution of the game control process is started (Step S19, S33b). It is good also as a structure which transfers to S25 and starts game control processing after performing step S27). With this configuration, it is possible to prevent the game control process from being executed and the payout command signal being transmitted in a state where the payout control means may not have started the payout control process, and the payout control. It is determined that the payout control process has been started by the means, and the game control process can be started when it is confirmed that the payout control process has started. A configuration in which a game control preparation completion signal is transmitted every time a predetermined period elapses after the control is stopped, for example, up to a predetermined number of times until a payout control preparation completion signal is received (for example, the control shown in FIG. 71). When the stop state continues for a predetermined period, the process proceeds to steps S33a and S33b, and when the standby time has passed without receiving the payout control preparation completion signal (Y in step S35), a further predetermined period after returning to the control stop state When the process continues, the process of proceeding to steps S33a and S33b is repeated up to a predetermined number of times, and the control state is returned in response to receiving the payout control preparation completion signal before the standby time elapses (step S19, The game control process may be started after the process proceeds to S25 and step S27 is executed. And, if the payout control preparation completion signal is not received despite the fact that the game control preparation completion signal is repeatedly transmitted a predetermined number of times each time the predetermined period elapses, the control is completely stopped. Good.

  In each of the above embodiments, the payout start command (payout start command) and the winning ball number signal are transmitted through the same signal line, but the signal lines for transmitting them may be separated. In the above embodiment, the prize ball number signal is transmitted by one-way communication (the game control means does not take a response from the payout control means). A configuration may be adopted in which a prize ball acceptance signal indicating that a prize ball number signal has been accepted is transmitted in response to reception. That is, two-way communication may be performed for the winning ball number signal. Further, the form of the payout activation command and prize ball number signal used in the above embodiment may be changed to another form. For example, a 1-byte or 2-byte command may be transmitted via an 8-bit signal line. When a 2-byte command is used, a capture signal is transmitted for each byte.

  In each of the above-described embodiments, the recording medium used in the recording medium processing apparatus (card unit 50) is a magnetic card (prepaid card). However, the recording medium is not limited to a magnetic card, and is a non-contact type or a contact type. An IC card may be used. In addition, when the recording medium processing device is configured to be able to identify the recording information based on the identification code, the recording medium can be read at least by the recording medium processing device such as an identification code that can identify the recording information It may be something that can be recorded on. Further, the recording medium may be a medium on which a predetermined information recording symbol such as a barcode is printed so as to be readable. The shape of the recording medium is not limited to a card shape, and may be any shape such as a disk shape, a spherical shape, or a chip shape.

  Note that the pachinko gaming machine of each of the above embodiments mainly has a predetermined game value when the stop symbol of the special symbol variably displayed on the variable display portion 9 based on the start winning is a combination of the predetermined symbols. The first type pachinko gaming machine that can be granted to the player, but if there is a winning in a predetermined area of the electric game that is released based on the start winning, the second type that can be given a predetermined gaming value to the player A third type in which a predetermined right is generated or continued when there is a prize for a predetermined electric combination that is released when a stop symbol of a symbol that is variably displayed based on a start winning prize becomes a combination of a predetermined pattern The present invention can be applied even to a pachinko gaming machine. Furthermore, the present invention can be applied to a slot machine as long as it has a configuration including a main board and a payout control board.

  The present invention can be applied to games such as pachinko gaming machines, and in particular, can be applied to gaming machines in which game control means and payout control means are provided separately.

It is the front view which looked at the pachinko game machine from the front. It is a front view which shows the front surface of the game board in the state which removed the glass door frame. It is the rear view which looked at the gaming machine from the back. It is the front view and sectional drawing which show a ball dispensing apparatus. It is a block diagram which shows the circuit structural example of a game control board (main board). It is a block diagram which shows the circuit structural example of a payout control board. It is a block diagram which shows the example of a circuit structure for transmitting the signal transmitted / received by a card unit and a payment control board. It is a block diagram which shows the connection state of the main board | substrates provided in the gaming machine. It is explanatory drawing which shows the components mounted in the signal output part in a main board | substrate, and the concentrated relay board | substrate. FIG. 12 is a block diagram illustrating circuit configuration examples of an effect control board, a frame side lamp driver board, and a sound control board. It is a block diagram which shows the structural example of a power supply board. It is explanatory drawing which shows the example of bit allocation of the output port in a game control means. It is explanatory drawing which shows the example of bit allocation of the output port in a game control means. It is explanatory drawing which shows the bit allocation example of the input port in a game control means. It is a flowchart which shows the main process which CPU in a main board | substrate performs. It is a flowchart which shows the main process which CPU in a main board | substrate performs. It is a flowchart which shows payout starting command transmission processing. FIG. 6 is a timing chart showing how the microcomputer operates when power supply to the gaming machine is started and when power supply is stopped. It is a flowchart which shows a timer interruption process. It is a flowchart which shows a power-off process. It is a flowchart which shows a power-off process. It is a flowchart which shows a discharge motor control process. It is explanatory drawing which shows the buffer used by switch processing. It is a flowchart which shows an example of a switch process. It is explanatory drawing which shows an example of the content of a control signal. It is a block diagram which shows the signal line etc. which are used for transmission / reception of a control signal. It is a timing chart showing an example of how to output a prize ball number signal. It is a timing chart showing an example of how to output a prize ball count signal. It is a timing chart showing an example of how to output a payout error signal. It is a flowchart which shows a prize ball process. It is explanatory drawing which shows the structural example of a prize ball number table. It is a flowchart which shows a prize ball number addition process. It is a flowchart which shows a prize ball control process. It is a flowchart which shows prize ball waiting processing 1. It is a flowchart which shows a prize ball transmission process. It is a flowchart which shows the winning ball waiting process 2. FIG. It is explanatory drawing which shows the bit allocation example of the output port in a payout control means. It is explanatory drawing which shows the example of bit allocation of the input port in a payout control means. It is a timing diagram for demonstrating communication between a prepaid card unit and a game machine. It is a flowchart which shows the main process which CPU for payout control performs. It is a flowchart which shows the timer interruption process which CPU for payout control performs. It is a flowchart which shows a payout motor control process. It is a flowchart which shows a main control communication process. It is explanatory drawing which shows the conditions for inputting a prize ball control signal via an input port. It is a flowchart which shows a prize ball REQ interruption process. It is a flowchart which shows the process during main control communication. It is a flowchart which shows a main control communication end process. It is explanatory drawing which shows an example of the counter used in payout control processing. It is a flowchart which shows a prize ball lending control process. It is a flowchart which shows prize ball payout number addition control. It is a flowchart which shows the payout start waiting process. It is a flowchart which shows a payout motor stop waiting process. It is a flowchart which shows payout passage waiting processing. It is a flowchart which shows payout passage waiting processing. It is a timing diagram for explaining a ball biting detection process. It is a timing diagram for demonstrating a ball biting cancellation | release process. It is explanatory drawing which shows the relationship between the kind of error, and the display of LED for an error display. It is a flowchart which shows an error process. It is a flowchart which shows an error process. It is a timing diagram which shows the mode of occurrence of the payout case error. It is explanatory drawing which shows an example of the change of the content of the counter used in prize ball payout control. It is explanatory drawing which shows the other example of the change of the content of the counter used in prize ball payout control. It is explanatory drawing which shows the other example of the change of the content of the counter used in prize ball payout control. It is explanatory drawing which shows the other example of the change of the content of the counter used in prize ball payout control. It is a flowchart which shows the other example of a prize ball lending control process. It is a flowchart which shows the other example of the payout start waiting process. It is a flowchart which shows the other example of payout passage waiting processing. It is a flowchart which shows the other example of payout passage waiting processing. It is a flowchart which shows a part of main process which CPU in the main board | substrate in other embodiment performs. It is a flowchart which shows the prize ball REQ interruption process in other embodiment. It is a flowchart which shows a part of other example of the main process which CPU in the main board | substrate in other embodiment performs.

Explanation of symbols

1 Pachinko machine 31 Game control board (main board)
37 Dispensing control board 56 CPU
69 delay circuit 80 effect control board 97 ball payout device 301 payout number count switch 371 payout control CPU
374 LED for error display
375 Error release switch 917 Capacitor (backup power supply)
920 Power supply monitoring circuit

Claims (6)

A gaming machine in which a player can play a predetermined game using a game medium, and pays out a prize game medium as a prize based on the winning of the game medium in a predetermined prize area,
A game control process for controlling the progress of the game is executed, and a payout number signal for instructing the number of payout of the prize game medium based on the winning of the game medium in a predetermined prize area is instructed to take in the payout number signal. A game control board equipped with a game control microcomputer including a payout number signal output means for outputting together with a pay-in signal ;
A payout means for paying out the game medium;
Payout driving means for driving the payout means to pay out the game medium;
A payout control board equipped with a payout control microcomputer for executing a prize game medium payout control process for controlling the payout driving means in accordance with the payout number signal input from the game control microcomputer;
An operation means for outputting an operation signal according to the operation,
The game control microcomputer is:
A game control variation data storage unit that stores an execution state of the game control process and retains the stored content for a predetermined period even when power supply to the gaming machine is stopped.
A payout control start signal output means for outputting a payout control start signal to the payout control microcomputer together with an input signal for instructing to take in the payout control start signal when power supply to the gaming machine is started;
Delay processing means for executing a delay process for delaying a start time of the process of outputting the payout control start signal by the payout control start signal output means from a time when power supply to the gaming machine is started for a predetermined period;
After the payout control start signal output means outputs the payout control start signal, a game control operation signal check means for checking whether or not the operation signal is output from the operation means,
When the game control operation signal confirmation means confirms that the operation signal is not output, the game control process execution state is determined based on the stored contents held in the game control variation data storage means. An execution state return means for game control to be returned;
When the game control operation signal confirmation means confirms that the operation signal has been output, the game control process is initialized by initializing the stored contents held in the game control variation data storage means. Execution state initialization means for game control to start from the state,
The payout number signal output by the payout number signal output means and the payout control start signal output by the payout control start signal output means are the same signal lines from the game control board to the payout control board. Is a signal transmitted to
The take-in signal of the payout-number signal output by the payout-number signal output means and the take-in signal of the payout control activation signal output by the payout control activation signal output means are the same signal line. A signal transmitted from the board to the payout control board, input to the interrupt terminal of the payout control microcomputer,
The dispensing control microcomputer is:
A prize game medium number data storage means for storing data indicating a payout number of game media according to the payout number signal from the payout number signal output means;
A payout control variation that includes the prize game medium number data storage means, stores data that fluctuates in accordance with payout control, and can store the stored contents for at least a predetermined period when power supply to the gaming machine is stopped Data storage means;
In response to the input of the capture signal from the game control microcomputer to the interrupt terminal, the value of the specific register is updated to a predetermined value, and interrupt processing is executed by interrupting the payout control processing. Interrupt processing execution means;
And interrupt inhibit means for controlling the interrupt disabled state to prohibit the execution of the interrupt processing by the interrupt processing execution means,
The payout number signal from the payout number signal output means, a payout number signal input means for inputting in said interrupt process,
When power supply to the gaming machine is started, after controlling the interrupt disabled state by the interrupt disabled section, the initial setting means for initially setting the internal state of the payout control microcomputer,
Register confirmation means for confirming whether or not the value of the specific register is the predetermined value after the initial setting is performed by the initial setting means;
When the value of the specific register is confirmed to be the predetermined value by the register checking means within a predetermined time after being controlled to the interrupt disabled state by the interrupt prohibiting means , the game control micro A payout control start signal input means for inputting the payout control start signal output from the computer;
While being controlled to the interrupt prohibited state by the interrupt prohibiting means, even if the predetermined time has elapsed, the register value confirmation means has not confirmed that the value of the specific register is the predetermined value A non-startable information storage means for storing non-startable information indicating that the payout control start signal is not received from the game control microcomputer;
And the conditions, the payout controlling manipulation signal confirmation means for confirming whether or not the operation signal is output from the operation means that the payout control activation signal input means inputs the payout control activation signal,
When it is confirmed that the payout controlling manipulation signal confirmation means is not output before Symbol operation signal, the execution state of the payout control processing based on the storage contents stored in the payout control change data storing means An execution state return means for payout control to be returned;
When it is confirmed that the payout controlling manipulation signal confirmation means is output before Symbol operation signal, initially the payout control processes using the storage contents stored in the payout control change data storing means is initialized and a dispensing control execution state initialization means for starting from the state,
In the payout control microcomputer, if the start disable information storage means stores the start disable information, whether or not an operation signal is output from the operation means by the payout control operation signal confirmation means. Without executing confirmation, the storage content held in the payout control variation data storage means is initialized to start the payout control process from an initial state,
The dispensing control microcomputer is:
The execution of the interrupt process by the interrupt process execution unit is permitted after the execution state is returned by the payout control execution state return unit or the stored contents are initialized by the payout control execution state initialization unit. An interrupt permission means for controlling the interrupt permission state;
An input enable state signal indicating that the payout number signal can be input in the interrupt processing by the payout number signal input means in response to being controlled to an interrupt permission state by the interrupt permission means. An input enable state signal output means for outputting to the game control microcomputer ;
When the payout number signal input means inputs the payout number signal from the payout number signal output means, data of the number of payouts indicated by該払out number signal, the prize game medium count data storing means stores Adding means for adding to
A payout start means for starting driving of the payout means by the payout drive means when the data stored in the prize game medium number data storage means indicates that there is a game medium to be paid out;
An increase determination means for determining whether or not the data stored in the premium game medium number data storage means has increased when the payout driving means is driving the payout means;
An increase number specifying means for specifying an increase number when the increase determining means determines that the data is increasing; and
Drive amount data storage means for storing data capable of specifying the drive amount of the payout drive means until the payout means finishes paying out game media;
Drive amount subtraction means for subtracting the data stored in the drive amount data storage means by an amount corresponding to the drive amount of the payout drive means;
The data stored in the drive amount data storage means stores data indicating the drive amount according to the increase number specified by the increase number specifying means when the increase determination means determines that the data is increasing. Driving amount data adding means for adding to
After the payout starting means starts driving the payout means by the payout driving means, the payout is performed when the data stored in the drive amount data storage means becomes a value corresponding to the end of payout of the game medium. A payout stop means for stopping driving of the payout means by the drive means,
The game control microcomputer is prepared for execution of the game control process when the execution state is returned by the game control execution state return means or the stored contents are initialized by the game control execution state initialization means. After completion, in response to the input enabled state signal being input from the input enabled state signal output means, the game control process is started, and in the game control process, the payout number signal output means is used to output the payout number. A gaming machine characterized by executing a process of outputting a signal . The payout control microcomputer includes previous prize game medium number data storage means for holding data stored in the prize game medium number data storage means when the drive amount data addition means adds data,
The increase determination means determines whether the data has increased by comparing the data stored in the prize game medium number data storage means with the data stored in the previous prize game medium number data storage means. And
The increase number specifying means specifies the difference between the data stored in the prize game medium number data storage means and the data stored in the previous prize game medium number data storage means as an increase number. Gaming machine. When the increase determination means determines that the data has increased, the payout control microcomputer uses the data stored in the premium game medium number data storage means after the data is added by the addition means as the previous premium game medium number. The gaming machine according to claim 2, further comprising a prize game medium number data setting means set in the data storage means. The payout control microcomputer shifts to a stopped state in which the control is stopped when a predetermined waiting period has elapsed without inputting a payout control start signal from the payout control start signal output means. Item 4. A gaming machine according to any one of Items 3 to 3. The payout control microcomputer detects a communication abnormality detection means when a predetermined standby period has elapsed without inputting a payout control start signal from the payout control start signal output means. When,
The gaming machine according to any one of claims 1 to 4, further comprising: a communication abnormality notifying unit that notifies that when the communication abnormality detecting unit detects that an abnormality has occurred. An allowance signal output means for outputting an allowance signal that enables the game control microcomputer and the payout control microcomputer to be operable when power supply to the gaming machine is started;
When the payout control microcomputer and the game control microcomputer become operable based on the allowance signal from the allowance signal output means, the time is specified more than when the payout control microcomputer becomes operable. The gaming machine according to any one of claims 1 to 5, further comprising delay means for delaying a period to make the game control microcomputer operable.

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