JP4405355B2 - Data communication arbitration system and data communication arbitration circuit in imaging apparatus - Google Patents

Description

  The present invention relates to a data communication arbitration method and a data communication arbitration circuit in an imaging apparatus such as a television camera, and more specifically, uses an ultra-multi pixel CCD (Charge Coupled Device) sensor, and multi-CPU converts image information of each divided imaging area. The present invention relates to a data communication arbitration method and a data communication arbitration circuit for high-speed processing.

  In recent years, in a television camera, a super-multi-pixel CCD sensor has been used, and image processing such as suppression of noise mixed in a video output signal from the CCD sensor, correction of linear distortion, pixel interpolation, etc. is performed. An image of good image quality is obtained, and it takes time to correct or correct the image output signal, and one CPU is used to process the image output from the super-multi-pixel CCD sensor. The (processor) cannot output the output video signal at a predetermined transfer speed. (For example, see Patent Documents 1 and 2)

Japanese Patent Application No. 2003-115897 (full description, full drawing) Japanese Patent Application No. 2003-272183 (full description, full drawing)

  In a super-multi-pixel camera such as a studio camera at a broadcasting station, incident light from a lens is decomposed into four colors (R, G1, G2, B) by a prism, and each is received by a CCD sensor, and output from each CCD sensor. The signals are subjected to image processing for each of the R, G1, G2, and B channels, and finally integrated to obtain a high resolution image. Therefore, it is difficult for one CPU to cope with the processing speed or the information storage capacity of all these channels. Particularly, in recent years, a studio camera or the like compatible with a high-definition television has a large number of scanning lines and a horizontally long shape. The size is large and the amount of data processing is enormous.

  Conventionally, a sub CPU is provided for each channel, and the sub CPU performs signal processing of each channel by using an ASIC (Application Specific Integrated Circuit) or an FPGA (Field Programmable Gate Array). It is controlled to process by. The main CPU exchanges data with each sub CPU, controls the sub CPU of each channel, and operates these integrated circuits to control the entire TV camera. However, all channels are controlled by the main CPU and sub CPU. However, it is difficult to cope with the processing speed or the information storage capacity.

  The present invention has been made in view of the problems as described above. The super-multi-pixel CCD sensor is divided into a plurality of imaging areas, and a sub CPU is provided corresponding to each imaging area. It is an object of the present invention to provide a data communication arbitration method and its data communication arbitration circuit in an imaging apparatus capable of controlling a CPU and performing image processing at a predetermined operation rate.

The present invention solves the above-mentioned problems, and the invention according to claim 1 divides the imaging region into a plurality of parts, and provides a sub CPU corresponding to each divided imaging region, and the divided image data from each divided imaging region. In the data communication arbitration method in the imaging apparatus in which the sub CPU obtains the result of the image processing and the main CPU integrates the processed image data from the sub CPU, and the sub CPU is the main CPU. When the data is transmitted from the main CPU to any of the sub CPUs, the data reception is confirmed by the sub status signal indicating the reception status of the sub CPU, and the sub CPU receives the data. When transmitting processed image data to the main CPU, all transmission request signals from the sub CPU are received by the arbitration circuit, and the main transmission is performed from the arbitration circuit. The demand signal is sent to the main CPU, in the data communication arbitration scheme in the image pickup apparatus being characterized in that so as to integrate and transmit the data of the processed image sequentially the main CPU from the higher priority the sub CPU is there. The imaging area is an optical image formed on the photosensitive surface of a CCD sensor (solid-state imaging device), which is photoelectrically converted and output as an electrical signal. For example, if the photosensitive surface is divided into left and right parts, it corresponds to each divided photosensitive surface. An example of the imaging device is a television camera.

According to a second aspect of the present invention, in the data communication arbitration method in the imaging apparatus according to the first aspect, the sub CPU having a lower priority level receives the priority response signal in response to the transmission request signal. A data communication arbitration method for an imaging apparatus, characterized by holding transmission of a transmission request signal to a CPU.

  According to a third aspect of the present invention, in the data communication arbitration method in the imaging apparatus according to the first aspect, the sub CPU indicates that the main CPU has started receiving processed image data from the main CPU. This is a data communication arbitration method in an imaging apparatus, which is determined by a main status signal.

  According to a fourth aspect of the present invention, the imaging area is divided into a plurality of areas, a sub CPU corresponding to the divided imaging area is provided, and the sub CPU obtains a result of image processing of the divided image data from each of the divided imaging areas. A data communication arbitration circuit in an imaging apparatus in which the main CPU integrates processed image data from the sub CPU, wherein at least two sub CPUs are provided for the main CPU. When transmitting processed image data to the main CPU, all the transmission request signals of the sub CPU are received, the main transmission request signal is transmitted to the main CPU, and the processed images are sequentially processed from the sub CPU having a higher priority. The data communication arbitration circuit in the image pickup apparatus is provided with an arbitration circuit that transmits the data to the main CPU.

According to a fifth aspect of the present invention, the arbitration circuit includes: a holding circuit that holds a transmission request signal of the sub CPU;
An OR circuit that outputs a logical sum of outputs of the holding circuit;
A cancellation signal generating circuit for generating a cancellation signal of the transmission request signal;
A main request signal creation circuit for creating a main transmission request signal by the output of the OR circuit and the release signal of the release signal creation circuit;
A flag generating circuit that receives the output of the holding circuit, generates a flag signal according to the priority, and sends the flag signal to the sub CPU;
A main answer creating circuit for creating a priority response signal from a flag signal of the flag creating circuit and a response signal from the main CPU;
5. The data communication arbitration circuit according to claim 4, further comprising a data OR circuit that outputs a logical sum of processed image data of the sub CPU.

The present invention has the following effects. According to the first aspect of the present invention, the imaging area is divided into a plurality of areas, a sub CPU corresponding to each divided imaging area is provided, and the sub CPU obtains the result of image processing of the divided image data from each divided imaging area. A data communication arbitration method in an imaging apparatus in which a CPU integrates data of processed images from the sub CPU,
At least two sub CPUs are provided for the main CPU, and when data is transmitted from the main CPU to any of the sub CPUs, confirmation of the data reception is performed by a sub status signal indicating a reception state of the sub CPU. And when the processed image data is transmitted from the sub CPU to the main CPU, all transmission request signals from the sub CPU are received by the arbitration circuit, and the main transmission request signal is received from the arbitration circuit by the main CPU. Since the data communication arbitration method in the imaging apparatus is characterized in that the processed image data is sequentially transmitted from the sub CPU having a high priority to the main CPU to be integrated. The sub CPU obtains the result of processing the divided image data obtained by dividing the image data of the field, and the processed image processed by the sub CPU. When sending data to the main CPU, send the transmission request signal to the arbitration circuit, receive the transmission request signal from all sub CPUs, and send the main transmission request signal to the main CPU, processed according to the priority order Image data can be transmitted to the main CPU, and there is an advantage that image data of one frame can be easily integrated by the main CPU.

According to a second aspect of the present invention, in the data communication arbitration method in the imaging device according to the first aspect, the sub CPU having a lower priority level receives the priority response signal for the transmission request signal until the main CPU receives the priority response signal. Since the data communication arbitration method of the imaging apparatus is characterized by holding the transmission of the transmission request signal to the CPU , there is an advantage that a transmission timing delay or transmission error of processed image data does not occur.

  According to a third aspect of the present invention, in the data communication arbitration method in the imaging apparatus according to the first aspect, the sub CPU indicates that the main CPU has started receiving processed image data from the main CPU. Since the data communication arbitration method in the imaging apparatus is characterized in that the determination is based on the main status signal, there is an advantage that no transmission error occurs in the processed image data.

  In the invention of claim 4, the imaging area is divided into a plurality of areas, a sub CPU is provided for each of the divided imaging areas, and the sub CPU obtains the result of image processing of the divided image data from each of the divided imaging areas, A data communication arbitration circuit in an imaging apparatus in which a main CPU integrates processed image data from the sub CPU. The data communication arbitration circuit includes at least two sub CPUs for the main CPU. When transmitting processed image data to the CPU, it receives all the transmission request signals of the sub CPU, transmits a main transmission request signal to the main CPU, and sequentially processes the processed image data from the sub CPU having a higher priority. Since the data communication arbitration circuit in the image pickup apparatus is provided with an arbitration circuit that transmits the master CPU to the main CPU, the arbitration circuit After receiving the transmission request signal, the main transmission request signal is transmitted to the main CPU, the main CPU transmits a response signal to the arbitration circuit, and the arbitration circuit responds with priority to the sub CPU according to the priority order. A signal is transmitted to each sub CPU, processed image data is transmitted from each sub CPU to the main CPU according to the priority order, one frame of image data is integrated, and an arbitration circuit is configured by a logic circuit. There is an advantage that the processing order of the image data does not change, the data timing does not shift, and one frame of image data can be easily integrated.

In the invention of claim 5, the arbitration circuit includes a holding circuit that holds a transmission request signal of the sub CPU;
An OR circuit that outputs a logical sum of outputs of the holding circuit;
A cancellation signal generating circuit for generating a cancellation signal of the transmission request signal;
A main request signal creation circuit for creating a main transmission request signal by the output of the OR circuit and the release signal of the release signal creation circuit;
A flag generating circuit that receives the output of the holding circuit, generates a flag signal according to the priority, and sends the flag signal to the sub CPU;
A main answer creating circuit for creating a priority response signal from a flag signal of the flag creating circuit and a response signal from the main CPU;
5. The data communication arbitration circuit of the imaging apparatus according to claim 4, wherein the data communication circuit is a logic circuit that outputs a logical OR of data of processed images of the sub CPU. It has the advantage that it operates in accordance with the processing speed of the CPU and the processing speed is not delayed, has a higher processing speed than the data processing by the program, and has no fear of malfunctioning. There is an advantage that the processing time of data can be made sufficiently.

  DESCRIPTION OF EXEMPLARY EMBODIMENTS Hereinafter, a data communication arbitration method and a data communication arbitration circuit according to the present invention will be described with reference to the drawings. A typical imaging device is a television camera.

FIG. 1 is a block diagram showing an embodiment of the present invention.
The data communication arbitration circuit of the present embodiment includes a main CPU 1, a buffer circuit 2, a sub CPU 3, and an arbitration circuit 4. The main CPU 1 transmits the data to the sub CPU 3 (3 _{1 to} 3 n) as main data (MAIN_DAT (1, 2, 3,..., N)) via the buffer circuit 2 for each data. After the divided image data is subjected to signal processing such as noise removal processing or distortion correction, the processing result is received by the sub CPU 3 (3 _{1 to} 3n) as processed image data (SUB_DAT1, 2, 3,..., N). In accordance with a predetermined priority order, it is transmitted to the main CPU 1 via the arbitration circuit 4 at a predetermined timing. Data of each processed image transmitted to the main CPU 1 is integrated by the main CPU 1.

The sub CPU 3 is provided with a number corresponding to the number of the divided imaging areas of the CCD sensor, and the sub CPUs 3 _{1 to} 3n share the image processing result data from each divided imaging area of the image data of one frame. Transfer and send to the main CPU 1.

The arbitration circuit 4 is provided with a plurality of sub CPUs 3 ₁ to 3 n for the main CPU 1 and performs image processing with an FPGA (Function Setting IC), an ASIC (Application Specific IC) or the like, and the main CPU 1 and the sub CPUs 3 ₁ to 3. Processes according to the priority order of the sub CPUs 3 ₁ to 3n so that data can be transmitted to and received from 3n at a high speed, and data of each divided image processing result is sequentially transmitted corresponding to one image frame. A function of transmitting data of a completed image to the main CPU 1.

Next, an outline of the data communication arbitration method of the present embodiment will be briefly described with reference to FIG. The main CPU1 transmits to the sub CPU 3 ₁ 3n, receives data of the image processed processed image in the sub CPU 3 ₁ 3n, having the function of integration. First, the main CPU 1 to the sub CPUs 3 _{1 to} 3n When transmitting data to the main CPU 1, after confirming whether or not the main CPU 1 is in a busy state (BUSY), the main CPU 1 transmits data to all the sub CPUs _{1 to} n (3 _{1 to} 3n). Each of the sub CPUs _{1 to} n (3 _{1 to} 3n) checks whether or not the data from the main CPU 1 is its own data by checking the header. If any of the sub CPUs _{1 to} n (3 _{1 to} 3n) determines that the data is its own data, the sub status signal (any of the corresponding SUB_STATUS 1, 2, 3,. Output to CPU1. After reception ends, the sub status signal output is stopped.

When the processed image data is transmitted from the sub CPUs 3 _{1 to} 3n to the main CPU 1, priority is given to the transmission request signals (REQUEST1, 2, 3,..., N) from the sub CPUs 3 _{1 to} 3n. Data of processed images is sequentially transmitted from a higher sub CPU. At this time, the arbitration circuit 4 sends a transmission request signal (REQUEST1, 2, 3,..., N) from the sub CPUs 3 _{1 to} 3n to the main CPU 1, and receives transmission requests from all the sub CPUs 3 _{1 to} 3n. based on the main transmission request signal (MAIN_REQUEST) sent to the main CPU1, the main CPU1 is priority (sub CPU 3 ₁ most significant through the arbitration circuit _4, 3 2 3n are sequentially lower below Priority response signals 1 to n (ANSWER1, 2, 3,..., N) are sent to the sub CPU 3 having a higher position according to the priority order, and processed image data (SUB_STATUS1, 2, 3,..., N) Are sequentially transmitted to the main CPU 1 via the arbitration circuit 4, and it is confirmed that the transmission has been completed reliably.

Next, the arbitration circuit 4 of the present embodiment will be described with reference to FIG. Arbitration circuit 4, the sub CPU 3 ₁ 3n transmission request signal (REQUEST1,2,3, ..., n) and the holding circuit _{4 1} for holding, OR circuit outputs the logical sum of the output of the holding circuit _{4 1 4 2} When the transmission request signal (REQUEST1,2,3, ..., n) and the release signal generating circuit 4 ₃ to create a release signal, a release signal of the OR circuit 4 _second output (MAIN_REQUEST) and release signal generating circuit 4 ₃ and the main request signal generating circuit 4 ₄ to create a main request signal, the sub CPU 3 1 _3n to the priority provided in the output of the holding circuit 4 ₁ corresponding flag generating circuit for sending a flag signal according to the priority 4 ₅ a, the flag generating circuit _{4 5} and the output of the main response signal from the main CPU1 (MAIN_ANSWER) more sub CPU 3 ₁ 3n priority response signal (ANSWER1,2,3, ..., n) main answer to create a generating circuit _{4 6,} sub CPU 3 ₁ And a Detaoa circuit 4 ₇ for outputting the logical sum of 3n data signal (processed image data).

1 and 3 according to the present invention will be described with reference to the flowcharts of FIGS. First, the operation when the main CPU 1 transfers data (MAIN_DATA1, 2, 3,..., N) to the sub CPU 3 will be described with reference to FIG. In step M1, the main CPU 1 starts data transmission and proceeds to steps M2 and 3. If the main CPU 1 itself is not "busy state: BUSY", it is set to "busy state: BUSY". In step M5, Data (SUB_DAT) is transmitted to the sub CPU 3. In steps M6 to 9, the main CPU 1 detects the start flag and device code written by the sub CPU 3 in the data head, and the sub status (SUB_STATUS) of the sub CPU 3 changes from “L” to “H”. To detect that the transmission of data (SUB_DAT) has been completed. If the sub status (SUB_STATUS) is “L”, data transmission is repeated until “H”. In step M11, the “busy state: BUSY” of the main CPU 1 itself is canceled. By a similar control, data (MAIN_DATA1,2,3, ..., n) sends to the sub CPU 3 ₁ 3n, returns from the subroutine to the main routine (Idle state).

  On the other hand, the sub CPU 3 detects the start flag written in the data (MAIN_DATA1, 2, 3,..., N) from the main CPU 1 in step S14, detects the device code in step S15, and performs step S16. When the sub status (SUB_STATUS 1, 2, 3,..., N) of the sub CPU 3 is changed from “H” to “L”, the main data end flag is detected in step S17, and the main data end flag cannot be detected. Is a reception error (No), the process returns to step S14. If the reception is completed (Yes), the process proceeds to step S18, and the sub status (SUB_STATUS1, 2, 3,..., N) is changed from “L” to “S” in step S18. H "and the reception of data is terminated in step S19.

  Next, with reference to FIG. 5, processing steps when data is transmitted from the sub CPU 3 to the main CPU 1 will be described. In step S1, transmission of data (SUB_DATA1, 2, 3,..., N) by the sub CPU 3 is started. First, in steps S 2 and 3, the main CPU 1 detects that it is not “busy state: BUSY”, and proceeds to step S 4 to output a transmission request signal (REQUEST) “1” to the arbitration circuit 4.

Arbitration circuit 4 transmits a request signal from the sub _{CPU3 1 ~3n (REQUEST1,2,3, ...,} n) holding circuit (flip-flop) to "1" is received by 4 ₁ holds, the logical their output when input to the oR circuit _{4 4} to sum, any of the sub CPU 3 ₁ 3n becomes "1", the main request signal generating circuit (switch circuit) _{4 4} to the main CPU1 via the main transmission request signal (MAIN_REQUEST ) Send “1”. The main CPU1 is primarily a response signal "1" main answer generating circuit of the arbitration circuit 4 (switch circuits) 4 priority response signal ₆ in order of priority through the (answer1 that received the main transmission request signal "1", 2, 3, ..., n) are transmitted to the sub CPUs 3 _{1 to} 3n.

In step S5, the sub CPUs 3 _{1 to} 3n detect the priority response signal (ANSWER) “1”, and in step S6, the sub CPUs 3 _{1 to} 3n logically OR the data (SUB_DATA1, 2, 3,..., N). and it transmits to the main CPU1 in priority order through Detaoa circuit _{4 7.} The sub CPUs 3 _{1 to} 3 n confirm that the main CPU 1 has received the data and changed the main status (MAIN_STATUS) from “L” to “H”, confirms in steps S 6 to 11, and in step S 12. After confirming that the transmission request signal (REQUEST) of the sub CPUs 3 _{1 to} 3n is “0”, the transmission processing of data (SUB_DATA1, 2, 3,..., N) is terminated in step S13.

On the other hand, the main CPU 1 that receives the data receives the main transmission request signal (MAIN_REQUEST) from the arbitration circuit 4 in step M13, sets the main CPU 1 itself to “busy state: BUSY” in step M14, and proceeds to step M15. In step M15, a response signal (ANSWER) “1” is sent to the arbitration circuit 4, and in step M17 the start flag written in the data (SUB_DATA1, 2, 3,..., N) from the sub CPUs 3 _{1 to} 3n. When the main CPU 1 changes the main status (MAIN_STATUS) from “H” to “L” in step M19 and ends the transmission processing of data (SUB_DATA1, 2, 3,..., N) in step M20. In step M23, the main status (MAIN_STATUS) is changed from “L” to “H”, and it is confirmed from the arbitration circuit 4 that the main transmission request signal (MAIN_REQUEST) is not “1”. circuit (switch circuit) _{4 6} from the priority response signal (ANSWER1,2,3, ..., n) transmits "0" to the sub CPU 3 ₁ 3n, "busy: bUSY" in the main CPU itself to release the Stop receiving data.

Next, the operation of the arbitration circuit 4 in this embodiment will be described with reference to FIG. Transmission request signal from a plurality of _{sub-CPU3 1 ~3n (REQUEST1,2,3, ...,} n) to the holding state by the holding circuit 4 ₁ receives the output from the holding circuit 4 ₁ is input to an OR circuit 4 ₂ if any of the inputs are "1", via a main request signal generating circuit 4 ₄ transmits a main transmission request signal (MAIN_REQUEST) to the main CPU 1. Transmission request signal from the sub _{CPU3 1 ~3n (REQUEST1,2,3, ...,} n) detects the falling of the in release signal generating circuit 4 _3, creates a transmission request release signal indicating the end of communication, the main request the signal generating circuit 4 ₄ a transmission request release signal as a trigger, once released main transmission request signal from the main request signal generating circuit ₄ 4 (MAIN_REQUEST). Next, the main transmission request signal (MAIN_REQUEST) is output to the main CPU 1 again at the rising timing of the transmission request signal (REQUEST) transmitted according to the priority order of the sub CPUs 3 _{1 to} 3n. By such an operation, the main transmission request signal is input to the main CPU 1 in response to the transmission request signals from the sub CPUs 3 _{1 to} 3n. The main CPU 1 can confirm that transmission of transmission request signals from all the sub CPUs 3 ₁ to 3 n has been completed. The priority order of the sub CPUs 3 _{1 to} 3n is set by the main CPU 1.

Subsequently, the arbitration circuit 4, by the main response signal transmitted according to the priority of the _sub-CPU3 1 ~3n (MAIN_ANSWER) is input to the main Answer generating circuit 4 _6, each of the switching circuits Sa of the main Answer circuit 4 ₆ ~Sd is performed sequentially switching operation, the main answer circuit 4 ₆ priority response signal based on the flag signal "1" input from the flag generating circuit 4 ₅ to the input terminals of the switch circuits Sa~Sd of (ANSWER1,2, 3,..., N) are output in accordance with the priority order of the sub CPUs 3 _{1 to} 3n. Sub CPU 3 ₁ 3n are transmitted according to the priority to give transmission permission, the data of the processed image (SUB_DATA1,2,3, ..., n) via the Detaoa circuit _{4 7} arbitration circuit 4 to the main CPU1 .

Incidentally, the flag generating circuit _{4 5} arbitration circuit 4 is composed of AND circuit Ga~Gc an inverter Ia to Ic, among the output terminals of the holding circuits _{4 1} corresponding to the number of sub CPU 3, the lowest priority The one is connected to the input terminal of the AND circuit Ga, and the other output terminals are connected to the input terminal of the AND circuit Ga via the inverters Ia to Ic. Further, of the holding circuit 4 _1, the output terminal is low priority second is connected to the input terminal of the AND circuit Gb, another output terminal is connected to the input terminal of the inverter Ib, via Ic AND circuit Gb ing. The third lowest priority output terminal is connected to the input terminal of the AND circuit Gc, the other output terminal is connected to the input terminal of the AND circuit Gc via the inverter Ic, and the highest priority output terminal is It is connected to the input terminal of the switch circuit Sd. The flag generating circuit _{4 5} is configured to preferentially response signal in accordance with priority (ANSWERn, n + 1, ... ) is input to the sub CPU 3 ₁ 3n.

  As an application example of the present invention, it can be used for transmission control of image data having a multi-CPU of a television camera, and can be adopted for a transmission control system of image data of an ultra-high resolution television camera.

It is a block diagram which shows embodiment of this invention. It is a figure which shows an operation | movement flow simply about operation | movement of this embodiment. It is a circuit diagram which shows the arbitration circuit of this embodiment. It is a figure which shows the control flow from main CPU in this embodiment. It is a figure which shows the control flow from the sub CPU in this embodiment.

Explanation of symbols

1 Main CPU
2 Buffer circuit 3 (3 _{1 to} 3n) Sub CPU
4 Arbitration circuit 4 ₁ Holding circuit 4 ₂ OR circuit 4 ₃ Release signal creation circuit 4 ₄ Main request creation circuit 4 ₅ Flag creation circuit 4 ₆ Main answer creation circuit 4 ₇ Data OR circuit Ia to Ic Inverter Ga to Gc AND circuit Sa to Sd switch circuit

Claims (5)

The imaging area is divided into a plurality of areas, a sub CPU corresponding to each of the divided imaging areas is provided, the sub CPU obtains the result of image processing of the divided image data from each of the divided imaging areas, and the main CPU A data communication arbitration method in an imaging apparatus adapted to integrate processed image data,
At least two sub CPUs are provided for the main CPU, and when data is transmitted from the main CPU to any of the sub CPUs, confirmation of the data reception is performed by a sub status signal indicating a reception state of the sub CPU. And when the processed image data is transmitted from the sub CPU to the main CPU, all transmission request signals from the sub CPU are received by the arbitration circuit, and the main transmission request signal is received from the arbitration circuit by the main CPU. A data communication arbitration method in an imaging apparatus, wherein processed image data is sequentially transmitted from the sub CPU having a high priority to the main CPU and integrated . In the data communication arbitration method in the imaging apparatus according to claim 1,
The sub-CPU having a lower priority holds transmission of a transmission request signal to the main CPU until receiving a priority response signal for the transmission request signal. In the data communication arbitration method in the imaging apparatus according to claim 1,
A data communication arbitration method in an imaging apparatus, wherein the sub CPU determines that the main CPU starts receiving processed image data based on a main status signal from the main CPU. The imaging area is divided into a plurality of areas, a sub CPU corresponding to each of the divided imaging areas is provided, and the sub CPU obtains the result of image processing of the divided image data from each of the divided imaging areas. A data communication arbitration circuit in an imaging apparatus adapted to integrate processed image data,
At least two sub CPUs are provided for the main CPU, and when transmitting processed image data from the sub CPU to the main CPU, all the transmission request signals of the sub CPU are received and the main transmission request signal is sent. A data communication arbitration circuit in an imaging apparatus, comprising: an arbitration circuit that transmits to the main CPU and sequentially transmits processed image data from the sub CPU having a high priority to the main CPU. The arbitration circuit holds a transmission request signal of the sub CPU;
An OR circuit that outputs a logical sum of outputs of the holding circuit;
A cancellation signal generating circuit for generating a cancellation signal of the transmission request signal;
A main request signal creation circuit for creating a main transmission request signal by the output of the OR circuit and the release signal of the release signal creation circuit;
A flag generating circuit that receives the output of the holding circuit, generates a flag signal according to priority, and sends the flag signal to the sub CPU;
A main answer generation circuit for generating a priority response signal from a flag signal of the flag generation circuit and a response solicitation signal from the main CPU;
5. The data communication arbitration circuit according to claim 4, further comprising a data OR circuit that outputs a logical sum of data of processed images of the sub CPU.

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