JP4407860B2 - Semiconductor device and substrate - Google Patents

Description

[0001]
[Industrial application fields]
The present invention relates to a semiconductor device and a substrate, and more particularly to a semiconductor device packaged with, for example, a mold resin and a substrate used therefor.
[0002]
[Prior art]
An example of this type of semiconductor device is disclosed in Japanese Patent Application Laid-Open No. 10-135247 [H01L 21/52, H01L 21/60, H01L 23/12, H01L 23/29, H01L 23, filed on May 22, 1998. / 31].
[0003]
In this semiconductor device 1, as shown in FIG. 10A, a plurality of vent holes 3 are formed in the die bonding area 2 a of the substrate 2, a wiring pattern 4 is formed on the upper surface of the substrate 2, and the wiring pattern 4 is formed on the wiring pattern 4. The semiconductor chip 6 was die bonded via the die bonding sheet 5. Then, the semiconductor chip 6 was sealed with the mold resin 7, and air and water accumulated in the mold 7 a were discharged from the vent hole 3 to the outside.
[0004]
[Problems to be solved by the invention]
In the prior art, the occurrence of package cracks can be prevented to some extent by releasing air and water from the vent hole 3, but it is still not sufficient.
[0005]
That is, in the prior art, as shown in FIG. 10B, the vent hole 3 is merely formed between the wiring patterns 4, so that the vent is formed by the mold resin 7 that has entered under the die bonding sheet 5. There was a risk of the hole 3 being blocked. When the vent hole 3 is closed, the air and water in the mold 7a cannot be discharged to the outside, and the air and water are thermally expanded, which may cause package cracks.
[0006]
Therefore, a main object of the present invention is to provide a semiconductor device and a substrate that can more reliably prevent the occurrence of package cracks.
[0007]
[Means for Solving the Problems]
According to a first aspect of the present invention, there is provided a semiconductor device including a substrate, a vent hole formed in the chip area of the substrate, a semiconductor chip die-bonded to the chip area, and a mold resin for sealing the semiconductor chip. An inflow blocking portion that prevents the inflow of the gas into the vent hole is formed in an annular shape around the vent hole, and a notch that connects the inner region and the outer region is formed in the inflow blocking portion. is there.
[0009]
[Action]
In the semiconductor device of the first invention, the inflow of the mold resin into the vent hole is blocked by the inflow blocking portion. For example, since a die bonding sheet is disposed on the vent hole, the inflow prevention portion can be prevented from flowing into the vent hole by forming an inflow prevention portion around the vent hole. In addition, by forming a notch that connects the inner region and the outer region of the inflow blocking portion, air and water in the package can be guided to the vent hole. If at least two cutouts are formed, air or water can be led from the other cutout to the vent hole even if one cutout is blocked by the mold resin.
[0011]
【The invention's effect】
According to the present invention, since the vent hole can be prevented from being blocked by the mold resin, the occurrence of package cracks can be more reliably prevented.
[0012]
The above object, other objects, features and advantages of the present invention will become more apparent from the following detailed description of embodiments with reference to the drawings.
[0013]
【Example】
A semiconductor device 10 of this embodiment shown in FIG. 1 is obtained by die bonding a semiconductor chip 18 on a wiring pattern 14 formed on a substrate 12 via a die bonding sheet 16 and sealing it with a mold resin 20. There is a so-called BGA (Ball Grid Array) type.
[0014]
The substrate 12 is made of an insulating material such as polyimide, glass epoxy, or ceramic. A plurality of through holes 22 are formed in a matrix in the die bonding area 12a of the substrate 12, and a plurality of vents are formed in the chip area 12b. Holes 24 are formed in a matrix. Here, the “die bonding area (12a)” refers to a region where a plurality of semiconductor chips 18 of different sizes are selectively die bonded, and the “chip area (12b)” refers to the area within the die bonding area 12a. An area where the semiconductor chip 18 is actually die-bonded. When the substrate 12 is applied only to one semiconductor chip 18, the die bonding area 12a and the chip area 12b are assumed to coincide with each other.
[0015]
As shown in FIGS. 2 and 3, a plurality of wiring patterns 14 and a plurality of inflow blocking portions 26 are formed on the upper surface of the substrate 12. 2 shows the wiring pattern 14 with an intermediate portion omitted, and FIG. 3 shows an enlarged range of ¼ of FIG.
[0016]
The wiring pattern 14 is made of a conductive metal such as Cu, and one end of each wiring pattern 14 is disposed so as to close the upper end of the through hole 22, and the other end is disposed on the peripheral edge of the substrate 12. The end is a bonding pad 14a.
[0017]
When the semiconductor chip 18 is die-bonded on the wiring pattern 14, if the distance A between the wiring patterns 14 in the vicinity of the peripheral edge of the semiconductor chip 18 is too wide, the mold resin 20 enters the semiconductor chip 18 below the semiconductor chip 18. 18 may be peeled off. According to the experiment by the inventor, as shown in FIG. 4, it was found that a defect due to peeling occurred when the distance A was wider than 0.175 mm. Therefore, in this embodiment, in order to prevent the mold resin 20 from entering below the semiconductor chip 18, the distance A between the wiring patterns 14 in the die bonding area 12a is set to 0.175 mm or less. However, considering the safety factor, the interval A is desirably 0.170 mm or less.
[0018]
The inflow blocking portion 26 is for blocking the mold resin 20 from flowing into the vent hole 24 and guiding air and water in the mold 20a to the vent hole 24. As shown in FIG. 24 is formed in an annular shape around 24 with the same thickness as the wiring pattern 14. And in the inflow prevention part 26, the two notches 26a which connect the inner side area | region and an outer side area | region are formed in the part located in the center side of the chip area 12b, ie, the downstream of the flow of the mold resin 20. FIG. The formation position of the notch 26a is set according to the formation position of the inflow blocking portion 26 in consideration of the balance between the function of blocking the flow of the mold resin 20 and the function of releasing air and water. The width of the notch 26a is set to 0.1 mm or less, preferably 0.04 to 0.05 mm or less in consideration of the resin flow.
[0019]
The semiconductor chip 18 is die-bonded on the wiring pattern 14 and the inflow blocking portion 26 via the die bonding sheet 16, and the upper surface electrode 18a of the semiconductor chip 18 and the bonding pad 14a of the wiring pattern 14 are gold wires. The semiconductor chip 18 and each gold wire 28 are sealed with the mold resin 20 through wire bonding.
[0020]
Further, ball-like external terminals 30 are attached to the through holes 22 opened in the lower surface of the substrate 12, and the external terminals 30 and the wiring pattern 14 are electrically connected.
[0021]
When manufacturing the semiconductor device 10, first, as shown in FIG. 6, a band-shaped carrier film 32 made of polyimide or the like is prepared, and the wiring pattern 14 and the inflow blocking portion 26 are formed on the surface of the carrier film 32. That is, a Cu foil is formed on the surface of the carrier film 32, a resist is formed on the Cu foil in accordance with the shapes of the wiring pattern 14 and the inflow blocking portion 26, and unnecessary portions of the Cu foil are removed by etching.
[0022]
Then, the through hole 22 is formed in the die bonding area 12a of the carrier film 32, and the vent hole 24 is formed inside the inflow blocking portion 26 formed in the chip area 12b.
[0023]
Then, the semiconductor chip 12 is die-bonded to the chip area 12 b via the die bonding sheet 16, and the upper surface electrode 18 a of the semiconductor chip 18 and the bonding pad 14 a of the wiring pattern 14 are wire-bonded using a gold wire 28.
[0024]
Thereafter, the semiconductor chip 18, the gold wire 28, and the like are sealed with the mold resin 20, the external terminals 30 are attached to the respective through holes 22, and the carrier film 32 is cut and divided to obtain the semiconductor device 10.
[0025]
In the molding process, a gap corresponding to the thickness of the wiring pattern 14 is formed between the upper surface of the carrier film 32 (substrate 12) and the lower surface of the die bonding sheet 16, but as described above, the interval A of the wiring pattern 14 is Since it is set to 0.175 mm or less, there is no worry that the mold resin 20 enters the gap. Even if it enters, since the mold resin 20 is blocked by the inflow blocking portion 26, there is no fear that the vent hole 24 is blocked.
[0026]
According to this embodiment, the vent hole 24 can be prevented from being blocked by the mold resin 20. In addition, since the notch 26a is formed in the inflow blocking portion 26, even if one notch 26a is blocked by the mold resin 20, air or water in the mold is vented from the other notch 26a. 22 can be led. Therefore, generation of package cracks can be reliably prevented.
[0027]
In the above-described embodiment, two notches 26a are formed in each inflow blocking portion 26, but the number of the notches 26a may be one or three or more.
[0028]
The range of the chip area 12b can be appropriately changed according to the size of the semiconductor chip 18, and a narrower range may be set as the chip area 12b in correspondence with the smaller semiconductor chip 18.
[0029]
Further, the range in which the inflow blocking portion 26 is formed can be changed as appropriate. For example, as shown in FIGS. 7 and 8, the inflow blocking portion 26 may be formed in a wider range in the die bonding area 12a. When the chip area 12b is set in a range narrower than the range where the inflow blocking part 26 is formed, for example, as shown in FIG. 24 may be formed, and the inflow blocking portion 26 existing outside the chip area 12b may be left as a dummy pattern (a pattern not involved in inflow blocking).
[0030]
Further, in the above-described embodiment, the interval A between the wiring patterns 14 in the entire die bonding area 12a is set to 0.175 mm or less. It may be set to 175 mm or less.
[Brief description of the drawings]
FIG. 1 is an illustrative view showing one embodiment of the present invention;
FIG. 2 is an illustrative view showing a wiring pattern and an inflow blocking portion.
FIG. 3 is a partially enlarged view of FIG. 2;
FIG. 4 is a graph showing a relationship between a wiring pattern interval A and a defect occurrence rate.
FIG. 5 is an illustrative view showing an inflow blocking portion.
FIG. 6 is an illustrative view showing a method for manufacturing a semiconductor device;
FIG. 7 is an illustrative view showing another embodiment of the present invention.
FIG. 8 is a partially enlarged view of FIG. 7;
FIG. 9 is an illustrative view showing another embodiment of the present invention.
FIG. 10 is an illustrative view showing a conventional technique.
[Explanation of symbols]
DESCRIPTION OF SYMBOLS 10 ... Semiconductor device 12 ... Board | substrate 14 ... Wiring pattern 16 ... Die bonding sheet 18 ... Semiconductor chip 20 ... Mold resin 22 ... Through hole 24 ... Vent hole 26 ... Inflow prevention part

Claims (7)

In a semiconductor device including a substrate, a vent hole formed in a chip area of the substrate, a semiconductor chip die-bonded to the chip area, and a mold resin for sealing the semiconductor chip,
An inflow blocking portion for preventing the mold resin from flowing into the vent hole is formed in an annular shape around the vent hole on the upper surface of the substrate, and a notch communicating the inner region and the outer region is formed in the inflow blocking portion. A semiconductor device formed. The cut and at least two forming semiconductor device according to claim 1, wherein. The semiconductor device according to claim 1, wherein a width of the notch is 0.1 mm or less . The semiconductor device according to claim 3, wherein a width of the notch is 0.05 mm or less . 5. The semiconductor device according to claim 1, further comprising a plurality of wiring patterns formed on an upper surface of the substrate, wherein an interval between the wiring patterns is set to 0.175 mm or less. The semiconductor device according to claim 5, wherein the interval is 0.170 mm or less . A ball further comprising a through hole opened in the lower surface of the substrate, wherein the wiring pattern is disposed so as to close an upper end of the through hole, and further provided in the through hole and electrically connected to the wiring pattern The semiconductor device according to claim 1, further comprising a shaped external terminal.

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