Deprecated: The each() function is deprecated. This message will be suppressed on further calls in /home/zhenxiangba/zhenxiangba.com/public_html/phproxy-improved-master/index.php on line 456
JP4412640B2 - Substrate processing equipment - Google Patents
[go: Go Back, main page]

JP4412640B2 - Substrate processing equipment - Google Patents

Substrate processing equipment Download PDF

Info

Publication number
JP4412640B2
JP4412640B2 JP2003200989A JP2003200989A JP4412640B2 JP 4412640 B2 JP4412640 B2 JP 4412640B2 JP 2003200989 A JP2003200989 A JP 2003200989A JP 2003200989 A JP2003200989 A JP 2003200989A JP 4412640 B2 JP4412640 B2 JP 4412640B2
Authority
JP
Japan
Prior art keywords
pin
substrate
gas
reaction chamber
pin guide
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
JP2003200989A
Other languages
Japanese (ja)
Other versions
JP2005042141A (en
Inventor
永豊 陳
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Chi Mei Optoelectronics Corp
Original Assignee
Chi Mei Optoelectronics Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Chi Mei Optoelectronics Corp filed Critical Chi Mei Optoelectronics Corp
Priority to JP2003200989A priority Critical patent/JP4412640B2/en
Priority to TW93122227A priority patent/TWI297737B/en
Publication of JP2005042141A publication Critical patent/JP2005042141A/en
Application granted granted Critical
Publication of JP4412640B2 publication Critical patent/JP4412640B2/en
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Images

Landscapes

  • Chemical Vapour Deposition (AREA)
  • Container, Conveyance, Adherence, Positioning, Of Wafer (AREA)

Description

【0001】
【発明の属する技術分野】
本発明は、CVD(chemical vapor deposition)装置などの反応室内で基板を自動で昇降させる手段を設けた基板の処理装置に関する。
【0002】
【従来の技術】
LCD(liquid crystal display)のアレイ基板や半導体チップなどの製造における基板の成膜には、CVD装置などの成膜装置が使用される。周知のCVD装置は、真空または減圧された反応室内に基板を載置して、気相または化学反応によって基板上に材料を成膜する装置である。
【0003】
図2に示すように、CVD装置40は、基板42が収納され、CVDによる基板42の成膜をおこなったりするための反応室20と、反応室20において、基板42を下方から支えて昇降させる複数のピン32と、ピン32が挿入される筒状体で構成されたピンガイド34と、ピン32を下方から支えて昇降させるピンバー44と、を含む。反応室20の底部にはピン32が通るピン挿入穴が開いている。ピンガイド34を構成する筒状体の内周面35とピン32とは隙間を有する。ピン32の形状は例えば円柱状である。アレイ基板や半導体チップを自動で製造するために、反応室20への基板42の出し入れはロボットアーム46でおこなう。
【0004】
CVD装置40のピン32とピンガイド34の材料は成膜やクリーニング時に使用するガスの特性上、セラミックを使用している。そのために、ピン32を昇降させると、ピンガイド34の内周面35とピン32との隙間も真空または減圧下であるので、ピン32とピンガイド34の接触抵抗が大きい。図3に示すように、時にはピン32がピンガイド34にかじりつくことがある。
【0005】
ピン32やピンガイド34の表面を滑らかに加工しても、図4に示すように、反応室20からのプロセスガスがピン32とピンガイド34の隙間に入り込み、ピン32の表面やピンガイド34の内周面35にプロセスガスによるパーティクル36が付着し、ピン32が昇降しにくくなる。LCDのアレイ基板であれば、基板42はガラス基板であるため、ピン32がかじりつくことによって、ロボットアーム46にてガラス基板42を搬出時に、基板の受け渡しが上手くいかず、ガラス基板が割れてしまう恐れがある。
【0006】
また、一般的にLCDのアレイ基板の製造であれば、1枚のガラス基板から複数枚のアレイ基板が製造される。したがって、1枚のガラス基板が大きくなり、ガラス基板の重量および厚みによってはガラス基板がたわんでしまう。ガラス基板がたわむことによって、ガラス基板を支えるピン32が傾くことがある。ピン32が傾くことによって、ピン32がピンガイド34に引っ掛かり、ガラス基板を昇降できなくなる。
【0007】
例えば、ピン32の太さは約3mmである。ピン32の太さを太くすれば、基板34の昇降をスムーズにおこなうことができる。しかし、CVDによって基板42を成膜するためには、基板42の温度を上げる必要がある。成膜室20の底部のチャンバ壁21には基板42の温度を上げるためのヒーターが組み込まれている(図示せず)。ピン32が太くなると、チャンバ壁21に設けられるピン挿入穴22が大きくなり、その箇所に対応した基板42の温度を上げにくくなる。そのため基板42の温度が上がっていない箇所の成膜が不均一になる恐れがある。したがって、ピン32を太くすることはできない。
【0008】
基板42は高温で成膜されるため、一度搬送トラブルが発生すると、チャンバ壁21に組み込まれたヒーターをオフにして、基板42やチャンバ壁21などの温度を落とした後、トラブルの処理をおこなわなければならない。再び成膜をおこなうためには、CVD装置40の試運転などをおこなう必要がある。搬送トラブルが発生してから再び成膜をおこなうまで、2日間程度必要で、搬送トラブルは、アレイ基板などの生産性を落とす原因となっている。アレイ基板の生産性が落ちると、最終的な製品であるLCDの生産性も落ちてしまう。
【0009】
また、基板42が傾いたままの状態でプロセスガスを反応室20内に導入し、基板42上に材料を成膜したとき、基板42上で均一に材料が成膜されない恐れがある。
【0010】
【発明が解決しようとする課題】
本発明は、CVD装置などの真空または減圧された反応室内での基板の昇降時における基板の搬送トラブルを低減し、トラブルの低減によってLCDのアレイ基板などの生産性を落とさない処理装置を提供することを目的とする。
【0011】
【課題を解決するための手段】
本発明の処理装置の要旨は、基板の下面を支持して昇降させるピンと、底部の複数箇所に前記ピンを通すピン挿入穴を有し、該ピン挿入穴を含む底部上に基板が供給される反応室と、前記ピン挿入穴と同心配置されて、ピンが通される筒状体であり、該筒状体の内周面に複数の環状の凹部を軸方向に離隔して形成したピンガイドと、前記ピンガイド内にガスを導入するために、該ピンガイドにおいて軸方向中間部に貫通させたガス導入穴と、前記ピンガイドの端部から前記ガスを排出するガス排出穴と、を含む。ピンとピンガイドの内周面には隙間があり、隙間にガスが導入されることによって、ピンがピンガイドから浮き上がり、スムーズにピンが昇降する。
【0012】
前記ガスは不活性ガスである。反応室にガスが入り込んでも、窒素やアルゴンの不活性ガスであるので悪影響が少ない。
【0013】
【発明の実施の形態】
本発明の処理装置に係る実施の形態について、図面を用いて説明する。本発明の処理装置は、CVD装置などの反応室内で基板の昇降をおこなう装置である。本発明は、図2で示すCVD装置40の処理装置30を図1の処理装置10に変更する。
【0014】
図1に示すように、処理装置10は、基板42の下面を支えて基板42を昇降させるピン12と、基板42が外部より搬入されて基板42上に成膜がおこなわれる反応室20と、ピン12が通る筒状体であり、その筒状体の内周面15とピン12とで隙間17を有するピンガイド14と、ピンガイド14内にガスを導入するために、ピンガイド14の軸方向の中間部に貫通させたガス導入穴16と、ピンガイド14の端部からガスを排出するガス排出穴18と、を含む。
【0015】
ガス導入穴16はピンガイド14に設けられた貫通穴である。図1の矢印で示すように、ガス導入穴16を通して隙間17にガスを送ることによって、ピン12とピンガイド14の間にガスの流れる層ができる。したがって、ピン12とピンガイド14との摩擦が軽減され、ピン12がスムーズに昇降できる。ピン12の形状は、例えば円柱状である。例えば、ピン12の長さは42mm、ピン12の直径は3mm、隙間17の幅は10から100μm、ピン12のストロークは22mmである。ストロークは、反応室20内にピン12が伸び出す最大長である。ピン12やピンガイド14はセラミック等で形成する。1枚の基板42を複数のピン12で支えるため、1つのCVD装置40に複数の処理装置10が設けられる。
【0016】
反応室20はチャンバ壁21で構成され、反応室20の底部のチャンバ壁21にはピン12が通るピン挿入穴22を有する。ピン12とピン挿入穴22を形成する内壁は隙間を有する。反応室20の一の面は、基板42を出し入れするための扉を有する。
【0017】
ピンガイド14は、チャンバ壁21の下方に設けられ、ピンガイド14を形成する筒状体の中心軸は、ピン挿入穴22の中心軸と同軸となるように設けられる。ピンガイド14の内周面15に、その内周面15を一周する環状の凹部19が複数設けられている。ガス導入穴16からピンガイド14内に導入されたガスは、凹部19でガス圧が高められる。この凹部19でガス圧が高められることによって、隙間17をガスの層にすることができ、ピン12が内周面15から浮き上がった状態となる。
【0018】
ピンガイド14内に導入されたガスは、ピンガイド14の両端から排出される。反応室20内に全てのガスが入り込まないように、ピンガイド14の両端の内、反応室20側にガス排出穴18を設ける。隙間17を通ったガスの一部が反応室20に入り込む場合があるが、ガス排出穴18を通って排気される。ガスは不活性ガスであり、例えば窒素ガスやアルゴンガスである。基板42の成膜やエッチングに悪影響を与えないために、不活性ガスを使用する。
【0019】
成膜やエッチング時、反応室20にプロセスガスが導入されるが、反応室20からピン12とピンガイド14の隙間17にプロセスガスが入り込まないように不活性ガスを導入するときの圧力を制御する。不活性ガスが反応室20に少し入り込むように、不活性ガスの導入するときの圧力を制御しても良い。反応室20のピン挿入穴22とガス排出穴18の穴径との比率は、その形状や長さで値が変化する。そこで、ピン挿入穴22とガス排出穴18の穴径との比率は、不活性ガスとプロセスガスの圧力バランスとして、ピンガイド14上部の圧力が反応室20の圧力よりも高くなるように穴径を調節する。ガス圧の一例として、成膜時の反応室20への圧力は20から150Pa、ガス導入穴18への圧力は大気圧から1MPaの範囲にして、反応室20の穴径を調節する。この様にすることによって、プロセスガスがピン12とピンガイド14の隙間17に入り込むことはない。
【0020】
成膜室20の底面のチャンバ壁21には基板42の温度を上げるためのヒーターが組み込まれている。基板42の温度を上げるのは、CVDによって基板42を成膜するためである。ピン12の太さが上述したように3mmと細ければ、成膜室20の底面のピン挿入穴22はピン12の太さに対応して小さくなる。成膜時に基板42の温度を均一に上げることができ、成膜を確実におこなうことができる。本発明はピン12の太さを太くせずに、スムーズにピン12の昇降ができる。
【0021】
全てのピン12を同時に昇降させるためのピンバー44を備える。ピンバー44が全てのピン12の下端部を押し上げることによって、全てのピン12が同時に上昇する。ピンバー44を下げることによって、全てのピン12が同時に下降する。ピンバー44によってピン12が昇降され、基板42が昇降される。ピン12はピンバー44に固定されない。これは、基板42の成膜時、反応室20の温度を上げるため、ピンバー42とピン12が伸縮するのを考慮するためである。
【0022】
成膜室20への基板20の出し入れを自動でおこなうロボットアーム46が備えられる。ロボットアーム46とピン12との間の基板42の受け渡しは、ピン12が昇降することによっておこなう。
【0023】
少なくとも基板42の昇降時にガス導入穴16からピン12とピンガイド14との隙間17にガスを導入することによって隙間17にガスの層ができ、ピン12がスムーズに昇降する。反応室20からのプロセスガスがピン12とピンガイド14との隙間17に入り込まないため、ピン12やピンガイド14にプロセスガスのパーティクルが付着することもなく、ピン12がスムーズに昇降する。基板42の昇降時にトラブルが発生しにくいため、LCDのアレイ基板などの生産性を落とす恐れが少ない。ピン12の太さを太くせずに基板42の昇降をスムーズに行えるため、基板42の成膜も確実に行える。
【0024】
以上、本発明の実施形態について説明したが、本発明は上記の実施形態に限定されることはない。例えば、CVD装置40の反応室20内における基板42の昇降に本発明の処理装置10を使用したが、CVD装置40以外の蒸着装置などに使用しても良い。また、LCDのアレイ基板の製造以外に、半導体の製造などに本発明の処理装置10を使用しても良い。
【0025】
その他、本発明は、主旨を逸脱しない範囲で当業者の知識に基づき種々の改良、修正、変更を加えた態様で実施できるものである。
【0026】
【発明の効果】
本発明は、基板を昇降させるピンとピンガイドとの隙間にガスを導入する構成にすることによって、ピンがスムーズに昇降できる。反応室からのプロセスガスがピンとピンガイドとの隙間に入り込まないので、ピンやピンガイドにパーティクルが付着することはなく、ピンの昇降がスムーズに行える。ピンの昇降がスムーズに行えるため、基板昇降時のトラブルが低減され、LCDのアレイ基板などの生産性を落とす恐れが少ない。
【図面の簡単な説明】
【図1】本発明の処理装置の断面図である。
【図2】成膜室に入れられた基板をピンで上昇させる時の断面図である。
【図3】基板を下降させるときにピンが引っかかったときの断面図である。
【図4】処理装置のピンやピンガイドにパーティクルが付着してピンが引っかかった時の断面図である。
【符号の説明】
10,30:処理装置
12,32:ピン
14,34:ピンガイド
15,35:内周面
16:ガス導入穴
17:隙間
18:ガス排出穴
19:凹部
20:反応室
21:チャンバ壁
22:穴
36:パーティクル
40:CVD装置
42:基板
44:ピンバー
46:ロボットアーム
[0001]
BACKGROUND OF THE INVENTION
The present invention relates to a substrate processing apparatus provided with means for automatically raising and lowering a substrate in a reaction chamber such as a chemical vapor deposition (CVD) apparatus.
[0002]
[Prior art]
A film forming apparatus such as a CVD apparatus is used to form a substrate in manufacturing an LCD (liquid crystal display) array substrate or a semiconductor chip. A well-known CVD apparatus is an apparatus in which a substrate is placed in a vacuum or reduced pressure reaction chamber, and a material is deposited on the substrate by a gas phase or a chemical reaction.
[0003]
As shown in FIG. 2, the CVD apparatus 40 accommodates a substrate 42 and raises and lowers the substrate 42 from below in the reaction chamber 20 for depositing the substrate 42 by CVD. It includes a plurality of pins 32, a pin guide 34 formed of a cylindrical body into which the pins 32 are inserted, and a pin bar 44 that supports the pins 32 from below and moves them up and down. A pin insertion hole through which the pin 32 passes is opened at the bottom of the reaction chamber 20. The inner peripheral surface 35 of the cylindrical body constituting the pin guide 34 and the pin 32 have a gap. The pin 32 has a cylindrical shape, for example. In order to automatically manufacture the array substrate and the semiconductor chip, the robot arm 46 is used to put the substrate 42 into and out of the reaction chamber 20.
[0004]
The material of the pins 32 and the pin guides 34 of the CVD apparatus 40 uses ceramics due to the characteristics of the gas used during film formation and cleaning. Therefore, when the pin 32 is moved up and down, the clearance between the inner peripheral surface 35 of the pin guide 34 and the pin 32 is also under vacuum or reduced pressure, so that the contact resistance between the pin 32 and the pin guide 34 is large. As shown in FIG. 3, the pin 32 sometimes bites the pin guide 34.
[0005]
Even if the surface of the pin 32 or the pin guide 34 is processed smoothly, the process gas from the reaction chamber 20 enters the gap between the pin 32 and the pin guide 34 as shown in FIG. Particles 36 due to the process gas adhere to the inner peripheral surface 35 of the, and the pins 32 are difficult to move up and down. In the case of an LCD array substrate, since the substrate 42 is a glass substrate, when the glass substrate 42 is unloaded by the robot arm 46 when the pins 32 are gnawed, the substrate is not delivered well and the glass substrate is broken. There is a fear.
[0006]
In general, when manufacturing an array substrate for an LCD, a plurality of array substrates are manufactured from a single glass substrate. Accordingly, one glass substrate becomes large, and the glass substrate is bent depending on the weight and thickness of the glass substrate. When the glass substrate is bent, the pins 32 supporting the glass substrate may be inclined. When the pin 32 is tilted, the pin 32 is caught by the pin guide 34 and the glass substrate cannot be moved up and down.
[0007]
For example, the thickness of the pin 32 is about 3 mm. If the thickness of the pin 32 is increased, the substrate 34 can be raised and lowered smoothly. However, in order to form the substrate 42 by CVD, it is necessary to raise the temperature of the substrate 42. A heater for raising the temperature of the substrate 42 is incorporated in the chamber wall 21 at the bottom of the film forming chamber 20 (not shown). When the pin 32 becomes thicker, the pin insertion hole 22 provided in the chamber wall 21 becomes larger, and it becomes difficult to raise the temperature of the substrate 42 corresponding to the location. For this reason, there is a possibility that the film formation at the portion where the temperature of the substrate 42 is not increased becomes non-uniform. Therefore, the pin 32 cannot be thickened.
[0008]
Since the substrate 42 is formed at a high temperature, once a conveyance trouble occurs, the heater incorporated in the chamber wall 21 is turned off, and the temperature of the substrate 42 and the chamber wall 21 is lowered, and then the trouble is processed. There must be. In order to form a film again, it is necessary to perform a trial operation of the CVD apparatus 40 or the like. It takes about two days from the occurrence of the transport trouble to the re-deposition of the film, and the transport trouble causes a drop in productivity of the array substrate and the like. If the productivity of the array substrate decreases, the productivity of the final product LCD also decreases.
[0009]
Further, when the process gas is introduced into the reaction chamber 20 while the substrate 42 is tilted and a material is deposited on the substrate 42, the material may not be uniformly deposited on the substrate 42.
[0010]
[Problems to be solved by the invention]
The present invention provides a processing apparatus that reduces substrate transport troubles when raising and lowering a substrate in a vacuum or reduced pressure reaction chamber, such as a CVD apparatus, and does not reduce the productivity of LCD array substrates and the like by reducing the troubles. For the purpose.
[0011]
[Means for Solving the Problems]
The gist of the processing apparatus of the present invention is to have pins for supporting the lower surface of the substrate to be moved up and down, and pin insertion holes for passing the pins at a plurality of locations on the bottom, and the substrate is supplied onto the bottom including the pin insertion hole. A pin guide that is arranged concentrically with the reaction chamber and the pin insertion hole and through which the pin passes, and in which a plurality of annular recesses are formed on the inner peripheral surface of the cylindrical body so as to be spaced apart in the axial direction And in order to introduce gas into the pin guide, a gas introduction hole that penetrates the pin guide to an axially intermediate portion, and a gas discharge hole that discharges the gas from the end portion of the pin guide. . There is a gap between the pin and the inner peripheral surface of the pin guide, and when the gas is introduced into the gap, the pin floats up from the pin guide, and the pin moves up and down smoothly.
[0012]
The gas is an inert gas. Even if gas enters the reaction chamber, it is an inert gas such as nitrogen or argon, so there is little adverse effect.
[0013]
DETAILED DESCRIPTION OF THE INVENTION
Embodiments according to the processing apparatus of the present invention will be described with reference to the drawings. The processing apparatus of the present invention is an apparatus for raising and lowering a substrate in a reaction chamber such as a CVD apparatus. In the present invention, the processing apparatus 30 of the CVD apparatus 40 shown in FIG. 2 is changed to the processing apparatus 10 of FIG.
[0014]
As shown in FIG. 1, the processing apparatus 10 includes a pin 12 that supports the lower surface of the substrate 42 to raise and lower the substrate 42, a reaction chamber 20 in which the substrate 42 is loaded from the outside and a film is formed on the substrate 42, The pin guide 14 is a cylindrical body through which the pin 12 passes, the pin guide 14 has a gap 17 between the inner peripheral surface 15 of the cylindrical body and the pin 12, and the shaft of the pin guide 14 in order to introduce gas into the pin guide 14. The gas introduction hole 16 penetrated to the intermediate part of the direction and the gas discharge hole 18 which discharges | emits gas from the edge part of the pin guide 14 are included.
[0015]
The gas introduction hole 16 is a through hole provided in the pin guide 14. As shown by the arrows in FIG. 1, a gas flowing layer is formed between the pin 12 and the pin guide 14 by sending the gas to the gap 17 through the gas introduction hole 16. Therefore, friction between the pin 12 and the pin guide 14 is reduced, and the pin 12 can be raised and lowered smoothly. The shape of the pin 12 is, for example, a cylindrical shape. For example, the length of the pin 12 is 42 mm, the diameter of the pin 12 is 3 mm, the width of the gap 17 is 10 to 100 μm, and the stroke of the pin 12 is 22 mm. The stroke is the maximum length that the pin 12 extends into the reaction chamber 20. The pins 12 and the pin guides 14 are made of ceramic or the like. In order to support one substrate 42 with a plurality of pins 12, a plurality of processing apparatuses 10 are provided in one CVD apparatus 40.
[0016]
The reaction chamber 20 includes a chamber wall 21, and the chamber wall 21 at the bottom of the reaction chamber 20 has a pin insertion hole 22 through which the pin 12 passes. The inner wall that forms the pin 12 and the pin insertion hole 22 has a gap. One surface of the reaction chamber 20 has a door for taking in and out the substrate 42.
[0017]
The pin guide 14 is provided below the chamber wall 21, and the central axis of the cylindrical body forming the pin guide 14 is provided so as to be coaxial with the central axis of the pin insertion hole 22. A plurality of annular recesses 19 that go around the inner peripheral surface 15 are provided on the inner peripheral surface 15 of the pin guide 14. The gas introduced into the pin guide 14 from the gas introduction hole 16 is increased in gas pressure in the recess 19. By increasing the gas pressure at the recess 19, the gap 17 can be made a gas layer, and the pin 12 is lifted from the inner peripheral surface 15.
[0018]
The gas introduced into the pin guide 14 is discharged from both ends of the pin guide 14. Gas exhaust holes 18 are provided on the reaction chamber 20 side at both ends of the pin guide 14 so that all gases do not enter the reaction chamber 20. A part of the gas that has passed through the gap 17 may enter the reaction chamber 20, but is exhausted through the gas discharge hole 18. The gas is an inert gas, for example, nitrogen gas or argon gas. An inert gas is used so as not to adversely affect the film formation and etching of the substrate 42.
[0019]
The process gas is introduced into the reaction chamber 20 during film formation or etching, but the pressure when introducing the inert gas from the reaction chamber 20 so as not to enter the gap 17 between the pin 12 and the pin guide 14 is controlled. To do. The pressure when the inert gas is introduced may be controlled so that the inert gas slightly enters the reaction chamber 20. The value of the ratio between the pin insertion hole 22 of the reaction chamber 20 and the diameter of the gas discharge hole 18 varies depending on the shape and length thereof. Therefore, the ratio between the pin insertion hole 22 and the gas discharge hole 18 is such that the pressure above the pin guide 14 is higher than the pressure in the reaction chamber 20 as a pressure balance between the inert gas and the process gas. Adjust. As an example of the gas pressure, the hole diameter of the reaction chamber 20 is adjusted by adjusting the pressure to the reaction chamber 20 during film formation from 20 to 150 Pa and the pressure to the gas introduction hole 18 from atmospheric pressure to 1 MPa. By doing so, the process gas does not enter the gap 17 between the pin 12 and the pin guide 14.
[0020]
A heater for raising the temperature of the substrate 42 is incorporated in the chamber wall 21 on the bottom surface of the film forming chamber 20. The reason for raising the temperature of the substrate 42 is to form the substrate 42 by CVD. If the thickness of the pin 12 is as small as 3 mm as described above, the pin insertion hole 22 on the bottom surface of the film forming chamber 20 becomes smaller corresponding to the thickness of the pin 12. The temperature of the substrate 42 can be increased uniformly during film formation, and film formation can be performed reliably. In the present invention, the pins 12 can be raised and lowered smoothly without increasing the thickness of the pins 12.
[0021]
A pin bar 44 for raising and lowering all the pins 12 at the same time is provided. As the pin bar 44 pushes up the lower ends of all the pins 12, all the pins 12 rise simultaneously. By lowering the pin bar 44, all the pins 12 are lowered simultaneously. The pins 12 are moved up and down by the pin bar 44, and the substrate 42 is moved up and down. The pin 12 is not fixed to the pin bar 44. This is for considering the expansion and contraction of the pin bar 42 and the pin 12 in order to raise the temperature of the reaction chamber 20 when the substrate 42 is formed.
[0022]
A robot arm 46 for automatically taking the substrate 20 into and out of the film forming chamber 20 is provided. The substrate 42 is transferred between the robot arm 46 and the pin 12 by moving the pin 12 up and down.
[0023]
A gas layer is formed in the gap 17 by introducing gas into the gap 17 between the pin 12 and the pin guide 14 from the gas introduction hole 16 at least when the substrate 42 is raised and lowered, and the pin 12 moves up and down smoothly. Since the process gas from the reaction chamber 20 does not enter the gap 17 between the pin 12 and the pin guide 14, process gas particles do not adhere to the pin 12 and the pin guide 14, and the pin 12 moves up and down smoothly. Since troubles are unlikely to occur when the substrate 42 is raised and lowered, there is little risk of lowering the productivity of LCD array substrates and the like. Since the substrate 42 can be moved up and down smoothly without increasing the thickness of the pins 12, the film formation of the substrate 42 can be performed reliably.
[0024]
As mentioned above, although embodiment of this invention was described, this invention is not limited to said embodiment. For example, although the processing apparatus 10 of the present invention is used for raising and lowering the substrate 42 in the reaction chamber 20 of the CVD apparatus 40, it may be used for a vapor deposition apparatus other than the CVD apparatus 40. In addition to the manufacture of an LCD array substrate, the processing apparatus 10 of the present invention may be used for the manufacture of semiconductors.
[0025]
In addition, the present invention can be implemented in a mode in which various improvements, modifications, and changes are made based on the knowledge of those skilled in the art without departing from the spirit of the present invention.
[0026]
【The invention's effect】
According to the present invention, the pins can be moved up and down smoothly by adopting a configuration in which gas is introduced into the gap between the pins that raise and lower the substrate and the pin guide. Since the process gas from the reaction chamber does not enter the gap between the pin and the pin guide, particles do not adhere to the pin or the pin guide, and the pin can be moved up and down smoothly. Since the pins can be raised and lowered smoothly, troubles when raising and lowering the substrate are reduced, and there is little risk of reducing the productivity of LCD array substrates and the like.
[Brief description of the drawings]
FIG. 1 is a cross-sectional view of a processing apparatus of the present invention.
FIG. 2 is a cross-sectional view when a substrate placed in a film formation chamber is raised by a pin.
FIG. 3 is a cross-sectional view when a pin is caught when the substrate is lowered.
FIG. 4 is a cross-sectional view when particles are attached to a pin or a pin guide of the processing apparatus and the pin is caught.
[Explanation of symbols]
10, 30: Processing device 12, 32: Pin 14, 34: Pin guide 15, 35: Inner peripheral surface 16: Gas introduction hole 17: Gap 18: Gas discharge hole 19: Recess 20: Reaction chamber 21: Chamber wall 22: Hole 36: Particle 40: CVD apparatus 42: Substrate 44: Pin bar 46: Robot arm

Claims (1)

基板の下面を支持して昇降させるピンと、
底部の複数箇所に前記ピンを通すピン挿入穴を有し、該ピン挿入穴を含む底部上に基板が供給される反応室と、
前記ピン挿入穴と同心配置されて、ピンが通される筒状体であり、該筒状体の内周面を一周する複数の凹部を軸方向に離隔して形成したピンガイドと、
前記ピンガイド内に不活性ガスを導入するために、該ピンガイドにおいて軸方向中間部に貫通させたガス導入穴と、
前記ピンガイドの端部から前記不活性ガスを排出するガス排出穴と、
を含む基板の処理装置。
A pin that supports the lower surface of the substrate and moves up and down;
A reaction chamber having a pin insertion hole through which the pin is passed at a plurality of positions on the bottom, and a substrate is supplied onto the bottom including the pin insertion hole;
A pin guide that is arranged concentrically with the pin insertion hole and through which the pin is passed, and a pin guide formed by separating a plurality of recesses around the inner peripheral surface of the cylindrical body in the axial direction;
In order to introduce an inert gas into the pin guide, a gas introduction hole that penetrates the pin guide in an axially intermediate portion;
A gas discharge hole for discharging the inert gas from an end of the pin guide;
A substrate processing apparatus including:
JP2003200989A 2003-07-24 2003-07-24 Substrate processing equipment Expired - Fee Related JP4412640B2 (en)

Priority Applications (2)

Application Number Priority Date Filing Date Title
JP2003200989A JP4412640B2 (en) 2003-07-24 2003-07-24 Substrate processing equipment
TW93122227A TWI297737B (en) 2003-07-24 2004-07-23 Substrate processing apparatus

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2003200989A JP4412640B2 (en) 2003-07-24 2003-07-24 Substrate processing equipment

Publications (2)

Publication Number Publication Date
JP2005042141A JP2005042141A (en) 2005-02-17
JP4412640B2 true JP4412640B2 (en) 2010-02-10

Family

ID=34261205

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2003200989A Expired - Fee Related JP4412640B2 (en) 2003-07-24 2003-07-24 Substrate processing equipment

Country Status (2)

Country Link
JP (1) JP4412640B2 (en)
TW (1) TWI297737B (en)

Families Citing this family (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN100367485C (en) * 2003-04-21 2008-02-06 东京毅力科创株式会社 Apparatus for semiconductor processing of substrate to be processed
JP6451508B2 (en) * 2015-05-29 2019-01-16 株式会社Sumco Epitaxial growth apparatus, epitaxial wafer manufacturing method, and lift pin for epitaxial growth apparatus

Also Published As

Publication number Publication date
JP2005042141A (en) 2005-02-17
TW200512310A (en) 2005-04-01
TWI297737B (en) 2008-06-11

Similar Documents

Publication Publication Date Title
US11133210B2 (en) Dual temperature heater
US8673076B2 (en) Substrate processing apparatus and semiconductor device producing method
JP4759073B2 (en) Substrate support, substrate processing apparatus, substrate processing method, and semiconductor device manufacturing method
US6780251B2 (en) Substrate processing apparatus and method for fabricating semiconductor device
US6991684B2 (en) Heat-treating apparatus and heat-treating method
US20030136341A1 (en) Wafer lift pin for manufacturing a semiconductor device
JP2000208439A (en) Deposition apparatus
CN110970343A (en) Vapor phase growth apparatus and method for manufacturing epitaxial wafer
CN112992769A (en) Substrate processing apparatus and mounting table
JP2003197721A (en) Elevating/lowering pin for supporting substrate and multichamber film deposition device using it
JP4412640B2 (en) Substrate processing equipment
US20030175426A1 (en) Heat treatment apparatus and method for processing substrates
KR20040111389A (en) Lifting glass substrate without center lift pins
JP2000195927A (en) Vacuum chuck device
JP5358201B2 (en) Deposition method
US20050095826A1 (en) Heat-processing method and apparatus for semiconductor process
KR100317462B1 (en) Substrate processing apparatus
JPH08115883A (en) Film forming equipment
JP5436763B2 (en) Airtight module and exhaust method of the airtight module
KR101436059B1 (en) Apparatus and method for manufacturing semiconductor
CN222182428U (en) Vertical furnace tube device
JP2021068871A (en) Epitaxial growth device and method of manufacturing epitaxial wafer
JP3664193B2 (en) Heat treatment apparatus and heat treatment method
JP4394843B2 (en) Thin film formation method
JP2000252350A (en) Substrate delivery device

Legal Events

Date Code Title Description
A621 Written request for application examination

Free format text: JAPANESE INTERMEDIATE CODE: A621

Effective date: 20060721

A131 Notification of reasons for refusal

Free format text: JAPANESE INTERMEDIATE CODE: A131

Effective date: 20090601

A521 Written amendment

Free format text: JAPANESE INTERMEDIATE CODE: A523

Effective date: 20090821

TRDD Decision of grant or rejection written
A01 Written decision to grant a patent or to grant a registration (utility model)

Free format text: JAPANESE INTERMEDIATE CODE: A01

Effective date: 20091023

A01 Written decision to grant a patent or to grant a registration (utility model)

Free format text: JAPANESE INTERMEDIATE CODE: A01

A61 First payment of annual fees (during grant procedure)

Free format text: JAPANESE INTERMEDIATE CODE: A61

Effective date: 20091113

FPAY Renewal fee payment (event date is renewal date of database)

Free format text: PAYMENT UNTIL: 20121127

Year of fee payment: 3

R150 Certificate of patent or registration of utility model

Free format text: JAPANESE INTERMEDIATE CODE: R150

FPAY Renewal fee payment (event date is renewal date of database)

Free format text: PAYMENT UNTIL: 20131127

Year of fee payment: 4

R250 Receipt of annual fees

Free format text: JAPANESE INTERMEDIATE CODE: R250

R250 Receipt of annual fees

Free format text: JAPANESE INTERMEDIATE CODE: R250

LAPS Cancellation because of no payment of annual fees