JP4417974B2 - Manufacturing method of stacked semiconductor device - Google Patents

Description

The present invention relates to a process for producing a stacked semiconductor device.

  In order to realize miniaturization and high functionality of a semiconductor device, a package structure (COC (Chip on Chip) structure) in which a plurality of semiconductor elements are stacked and sealed in one package has been put into practical use. The COC package is applied to a structure in which a memory element and a logic element are stacked, and is practically used as a SIP (System in Package) type semiconductor device. Wire bonding has generally been applied to the connection between the stacked semiconductor elements (see Patent Document 1), but application of flip-chip connection is being studied in order to increase the data transmission speed and the like. (See Patent Document 2).

  When flip-chip connection is applied to the connection between the stacked semiconductor elements, first, the first semiconductor element (lower semiconductor element) is mounted on the wiring board having external connection terminals and the like with the electrode formation surface facing upward. To do. Next, a second semiconductor element (upper semiconductor element) is stacked on the first semiconductor element with the electrode formation surface facing downward. In this way, the first and second semiconductor elements stacked with the electrode formation surfaces facing each other are connected via the bump electrodes. Since the connection distance between the semiconductor elements is shortened by the flip-chip connection, for example, the data transmission speed between the memory element and the logic element can be increased.

  In general, since the size of the memory element is larger than that of the logic element, in the stacked SIP, the logic element is mounted on the memory element, and these elements are flip-chip connected. Wire bonding is applied to the connection between the memory element and the wiring board. For example, a semiconductor device used in a mobile phone, a digital home appliance, or the like may use a combination of a plurality of logic elements and memory elements. When a stacked structure is applied to such a configuration, a plurality of logic elements are stacked on the memory element. Therefore, depending on the size of each element, a sufficient connection area with the wiring substrate of the lower memory element is sufficient. May not be secured.

On the other hand, it is conceivable to stack memory elements on a plurality of logic elements. In this case, the upper semiconductor element is stacked across a plurality of lower semiconductor elements. It is necessary to apply wire bonding in connection accuracy between elements. In the stacked semiconductor device to which wire bonding is applied, the connection distance between the semiconductor elements becomes long, so that the data transmission rate is inevitably lowered. Furthermore, there is a problem that the number of connection electrodes cannot be increased because a connection region for each semiconductor element on the lower side of the upper semiconductor element cannot be sufficiently secured based on the stacked structure or the connection structure. Occurs.
JP 2000-114452 A JP 2006-024752 A

An object of the present invention is to provide a laminated production method of connection accuracy the connection distance shortened and stacked semiconductor device having both of between the semiconductor elements.

A manufacturing method of a stacked semiconductor device according to an aspect of the present invention includes a wiring board having an element mounting portion, and a lower semiconductor element group having a plurality of semiconductor elements mounted in parallel to the element mounting portion of the wiring board. And stacked on the lower semiconductor element group so as to straddle the plurality of semiconductor elements, and have a larger shape than the plurality of semiconductor elements of the lower semiconductor element group, and are flipped with respect to the plurality of semiconductor elements A method of manufacturing a stacked semiconductor device comprising a chip-connected upper semiconductor element, the step of forming a first solder pad on a positioning substrate, and the plurality of semiconductor elements constituting the lower semiconductor element group Forming a second solder pad having the same pattern as the first solder pad on a surface of the semiconductor element opposite to the surface on which the upper semiconductor element is stacked; A step of disposing the plurality of semiconductor elements on the positioning substrate such that the first solder pad and the second solder pad face each other; and a heat treatment on the first and second solder pads. A step of positioning the plurality of semiconductor elements based on the self-alignment effect of the solder pads, and the upper stage across the plurality of semiconductor elements on the lower-stage semiconductor element group on the positioning substrate. Stacking the side semiconductor elements, flip chip connecting the plurality of semiconductor elements and the upper stage semiconductor elements, and connecting the lower stage semiconductor element group and the upper stage semiconductor elements from the positioning substrate. And a step of mounting the connection body removed from the positioning substrate on the element mounting portion of the wiring board. That.

The method for manufacturing a stacked semiconductor device according to an aspect of the present invention increases the positional accuracy of a plurality of semiconductor elements constituting a lower-stage semiconductor element group, and then stacks the upper-stage semiconductor element across the plurality of semiconductor elements. Flip chip connection. Accordingly, it is possible to achieve both improvement in connection accuracy between the lower-stage side semiconductor element group and the upper-stage side semiconductor element and reduction in the connection distance.

  Hereinafter, embodiments for carrying out the present invention will be described with reference to the drawings. FIG. 1 shows a configuration of a stacked semiconductor device according to an embodiment of the present invention. A stacked semiconductor device 1 shown in FIG. 1 has a wiring board 2 that functions as an interposer. The wiring substrate 2 may be any substrate as long as it can mount a semiconductor element and has a wiring network, and a wiring network by inner layer wiring or surface wiring is provided on various insulating substrates such as a resin substrate, a ceramic substrate, and a glass substrate. A thing etc. are used. A printed wiring board is exemplified as the wiring board 2 to which the resin board is applied.

  On the lower surface side of the wiring board 2, solder bumps or the like are provided as the external connection terminals 3. Here, since the stacked semiconductor device 1 applied to a BGA package is shown, solder bumps are provided as external connection terminals 3 on the lower surface of the wiring board 2. The stacked semiconductor device 1 can also be applied to an LGA package or the like. In this case, the external connection terminal 3 is composed of a metal land. On the upper surface side of the wiring board 2, an element mounting portion 4 and a connection portion (connection pad) 5 are provided. The connection pads 5 are electrically connected to the external connection terminals 3 provided on the lower surface side via the wiring network of the wiring board 2. The connection pad 5 becomes a wire bonding part.

  A plurality of semiconductor elements (lower stage semiconductor elements) 6, 6... Constituting the lower stage semiconductor element group are arranged in parallel on the element mounting portion 4 of the wiring board 2. The lower semiconductor element 6 is bonded to the element mounting portion 4 of the wiring board 2 via the adhesive layer 7. The lower semiconductor element 6 is provided with an electrode pad 8 on the upper surface side, and is mounted on the wiring substrate 2 with the electrode pad 8 formation surface (electrode formation surface) facing upward. That is, the lower semiconductor element 6 is mounted on the wiring board 2 in a face-up state.

  The lower stage side semiconductor element group is composed of, for example, four semiconductor elements 6 as shown in FIG. The number of lower semiconductor elements 6 is not limited to two, but may be two as shown in FIG. Further, the number of lower semiconductor elements 6 may be three or five or more. As described above, the number of the lower semiconductor elements 6 constituting the lower semiconductor element group may be two or more, and is appropriately set according to, for example, the use of the stacked semiconductor device 1 constituting the SIP. Is. As will be described later, the lower semiconductor element 6 has a smaller element size than the upper semiconductor element. In such a case, the stacked semiconductor device 1 is suitable.

  The electrode pad 8 of the lower semiconductor element 6 has a first pad group 8a connected to the wiring substrate 2 and a second pad group 8b connected to an upper semiconductor element described later. The first pad group 8a constitutes a wire bonding part, and the second pad group 8b constitutes a flip chip connecting part. Of the electrode pads 8 of the lower semiconductor element 6, the first pad group 8 a is electrically connected to the connection pads 5 of the wiring board 2 through the conductive wires 9. As the conductive wire 9, a general fine metal wire such as an Au wire or a Cu wire is used.

  An upper semiconductor element 10 is stacked on a lower semiconductor element group including a plurality of semiconductor elements 6, 6. The upper semiconductor element 10 has a larger shape than the lower semiconductor element 6, and is stacked over a plurality of semiconductor elements 6, 6. The combination of the lower semiconductor element 6 and the upper semiconductor element 10 is not particularly limited. For example, the lower semiconductor element 6 is a logic element (logic LSI) and the upper semiconductor element 10 is a memory element (DRAM or the like). The combination of is illustrated. When the lower semiconductor element 6 is a logic element, for example, the lower semiconductor element group includes digital logic, analog logic, and the like.

  The upper semiconductor element 10 is provided with an electrode pad 11 on the lower surface side, and is laminated on the lower semiconductor element group with the formation surface of the electrode pad 11 facing downward. That is, the upper semiconductor element 10 is stacked on the lower semiconductor element group in a face-down state. In other words, the upper semiconductor element 10 is disposed with its electrode formation surface facing the electrode formation surface of the lower semiconductor element 6. The upper semiconductor element 10 is flip-chip connected to the lower semiconductor elements 6, 6.

  The second pad group 8 b of the lower semiconductor element 6 is electrically connected to the electrode pads 11 of the upper semiconductor element 10 via the bump electrodes 12. A gap between the lower semiconductor element 6 and the upper semiconductor element 10 is filled with a resin 13 as an underfill agent. For the underfill resin 13, for example, a thermosetting resin such as an epoxy resin, a phenol resin, or a silicone resin is used. The lower and upper semiconductor elements 6 and 10 stacked and arranged on the wiring board 2 are sealed together with the bonding wires 9 and the like with a sealing resin 14 such as an epoxy resin, for example. A semiconductor device 1 is configured.

  When the upper semiconductor element 10 is flip-chip connected to the plurality of lower semiconductor elements 6, 6... By simply mounting the lower semiconductor element 6 on the wiring board 2 by applying ordinary die bonding, the lower semiconductor element 10. The positional accuracy of the semiconductor element 6 cannot be increased to the same level as the pitch accuracy of the bump electrodes 12 used for flip chip connection. For this reason, when the upper semiconductor element 10 is flip-chip connected, the connection accuracy between the lower semiconductor element 6 and the upper semiconductor element 10 cannot be maintained. In other words, the lower semiconductor element 6 and the upper semiconductor element 10 cannot be reliably connected via the bump electrode 12.

  Therefore, in this embodiment, the self-alignment effect of solder, which will be described later, is used to increase the positional accuracy of the plurality of lower semiconductor elements 6 to be equal to or higher than the pitch accuracy of the bump electrodes. As described above, by increasing the positional accuracy of the lower semiconductor element 6 (positional accuracy between the adjacent lower semiconductor elements 6) to be equal to or higher than the pitch accuracy of the bump electrodes, the upper semiconductor element 10 can be divided into a plurality of lower semiconductor elements 10. It becomes possible to perform flip-chip connection to the side semiconductor element 6 with high accuracy. Furthermore, since the plurality of semiconductor elements 6 are arranged on the lower stage side, a sufficient connection area between the lower stage semiconductor element 6 and the wiring board 2 can be secured.

  For example, when a plurality of semiconductor elements are arranged in parallel on one semiconductor element, the planar arrangement is the reverse of FIG. 2, so that the connection region of the lower semiconductor element to the wiring board is sufficient. Cannot be secured. This cannot cope with an increase in the number of connection electrodes. In addition, as a structure in which one upper semiconductor element is stacked on a plurality of lower semiconductor elements, it is conceivable to stack each semiconductor element in a face-down state. In this case, all the semiconductor elements are stacked. It is necessary to apply a wire bonding connection to. For this reason, the connection distance between the semiconductor elements becomes long, and a decrease in data transmission speed is unavoidable.

  In the stacked semiconductor device 1 of this embodiment, a plurality of lower-stage semiconductor elements 6 and upper-stage semiconductor elements 10 are arranged with their electrode formation surfaces facing each other, and the positional accuracy of the lower-stage semiconductor elements 6 is determined as bump electrodes. The pitch accuracy is equal to or higher than the pitch accuracy. For this reason, it is possible to apply flip-chip connection capable of shortening the connection distance without reducing the connection accuracy between the plurality of lower semiconductor elements 6 and the upper semiconductor element 10. Furthermore, since the connection area | region with respect to the wiring board 2 of the lower stage side semiconductor element 6 is ensured, the number of connection electrodes can be multi-pinned. Therefore, it is possible to provide a stacked semiconductor device 1 that achieves both improvement in connection accuracy between stacked semiconductor elements 6 and 10 and reduction in connection distance.

  A manufacturing process of the stacked semiconductor device 1 described above will be described with reference to FIGS. First, as shown in FIG. 4, a positioning substrate 21 used for positioning a plurality of lower semiconductor elements 6 is prepared. A normal semiconductor wafer (Si wafer or the like) can be applied to the positioning substrate 21. The positioning substrate 21 is provided with an element arrangement region 22 having a shape corresponding to the arrangement position of the lower semiconductor element 6 on the wiring board 2. As shown in FIG. 5, the first solder pads 23 are formed in these element arrangement regions 22 by combining a thin film forming method such as a sputtering method and a plating method.

  On the other hand, as shown in FIG. 6, the semiconductor element 6 constituting the lower semiconductor element group has a surface (back surface) 6 b opposite to the surface (electrode formation surface) 6 a on which the upper semiconductor element 10 is stacked, Second solder pads 24 each having the same pattern as the first solder pads 23 are formed. Then, as shown in FIGS. 7 and 8, after the plurality of lower semiconductor elements 6 are arranged on the positioning substrate 21 so that the first solder pads 23 and the second solder pads 24 face each other, The first and second solder pads 23 and 24 are heat treated. The solder pads 23 and 24 are connected by this heat treatment. At this time, the plurality of lower semiconductor elements 6 are positioned with respect to the positioning substrate 21 based on the self-alignment effect of the solder pads 23 and 24.

  That is, when the first solder pad 23 provided on the positioning substrate 21 and the second solder pad 24 provided on the back surface 6b of the lower semiconductor element 6 are subjected to heat treatment and soldered, Based on the self-alignment effect of the solder, connection is made so that the centers coincide. The solder pads 23 and 24 are formed according to the arrangement position and the position accuracy of the lower semiconductor element 6, respectively. Therefore, by soldering the first solder pad 23 and the second solder pad 24, the plurality of lower-stage semiconductor elements 6 are placed on the positioning substrate 21 in a state where the positional accuracy in the stacked semiconductor device 1 is satisfied. Positioned. That is, the positioning is performed with an accuracy equal to or higher than the formation pitch of the bump electrodes 12 of the upper semiconductor element 10.

  The shape of the second solder pad 24 is not limited as long as it has the same pattern so as to face the first solder pad 23 when superposed, when using the self-alignment effect of the solder. In order to enhance the effect, it is preferable to have the same shape (same pattern (same size (width, diameter, etc.))). However, the self-alignment effect of the solder can be used even if they are not the same shape. The specific shape of the solder pads 23 and 24 is not particularly limited, and for example, dot-shaped or line-shaped solder pads 23 and 24 can be applied. 5 and 6 show the striped solder pads 23 and 24. FIG. Various shapes such as a dot shape, a cross shape, a polygonal shape, a linear shape, a curved shape, an equal pitch shape, and an unequal pitch shape can be applied to the solder pads 23 and 24.

  Furthermore, in order to increase the positioning accuracy of the lower semiconductor element 6, the formation pitch of the solder pads 23 and 24 is preferably equal to or less than the formation pitch of the bump electrodes 12 of the upper semiconductor element 10. The positioning accuracy of the lower semiconductor element 6 by soldering the solder pads 23 and 24 to each other is affected by the formation pitch of the solder pads 23 and 24. The lower the formation pitch and pattern width of the solder pads 23 and 24, the lower The positioning accuracy of the side semiconductor element 6 can be increased. Therefore, by making the formation pitch of the solder pads 23, 24 equal to or less than the formation pitch of the bump electrode 12, the connection accuracy of the upper semiconductor element 10 that is flip-chip connected to the lower semiconductor element 6 is more reproducible. It becomes possible to raise.

  Next, as shown in FIGS. 9 and 10, the upper semiconductor element 10 is stacked on the lower semiconductor element 6 connected to the positioning substrate 21 via the solder connection body 25, and the flip chip is formed between these elements. Connecting. For the connection between the plurality of lower semiconductor elements 6 and the upper semiconductor element 10, thermocompression bonding, reflow, or the like is applied. The upper semiconductor element 10 is stacked over the plurality of lower semiconductor elements 6 and is flip-chip connected to each semiconductor element 6. At this time, since the plurality of lower semiconductor elements 6 are positioned by the positioning substrate 21, the upper semiconductor elements 10 and the upper semiconductor elements 6 are connected to each other by stacking the upper semiconductor elements 10 thereon and performing flip chip connection. The connection accuracy with the side semiconductor element 10 can be maintained at a high level.

  Next, as shown in FIG. 11, a liquid underfill resin 13 is filled in the gap between the lower semiconductor element 6 and the upper semiconductor element 10 and cured, thereby making the upper semiconductor element 10 a lower semiconductor. Fixed to the element 6. In this manner, a connection body 26 is formed between the lower-stage side semiconductor element group composed of the plurality of semiconductor elements 6 and the upper-stage side semiconductor element 10. Then, as shown in FIG. 12, the connection body 26 is heat-treated and removed from the positioning substrate 21, and then mounted on the element mounting portion 4 of the wiring board 2 as shown in FIG. The laminated semiconductor device 1 is obtained through a resin sealing process or the like.

  In carrying out the step of removing the connection body 26 from the positioning substrate 21, the first and second solder pads 23 and 24 preferably have a melting point lower than that of the bump electrode 12. For example, when the bump electrode 12 is made of Au—Sn solder, a solder alloy having a lower melting point is applied to the first and second solder pads 23 and 24. Thus, the shape and connection structure of the connection body 26 are obtained by applying heat treatment to the connection body 26 in a temperature range in which the first and second solder pads 23 and 24 are melted and the bump electrode 12 can maintain the connection state. Can be easily removed from the positioning substrate 21 while maintaining a stable state.

  In addition, by fixing the lower semiconductor element 6 and the upper semiconductor element 10 with the underfill resin 13 in advance, the melting point difference between the first and second solder pads 23 and 24 and the bump electrode 12 can be reduced. Even if it is small, it can be removed from the positioning substrate 21 while maintaining the shape and connection structure of the connection body 26. In removing the connection body 26 from the positioning substrate 21, it is preferable to use both the melting point difference between the first and second solder pads 23, 24 and the bump electrode 12 and inter-element fixation with the underfill resin 13.

  As described above, the upper semiconductor element 10 is flip-chip connected to the plurality of lower semiconductor elements 6 positioned by using the positioning substrate 21 and the solder pads 23 and 24, whereby a plurality of lower semiconductor elements 6 are connected. The connection accuracy of the upper semiconductor element 10 stacked over the side semiconductor element 6 can be maintained. By removing the connection body 26 having such connection accuracy from the positioning substrate 21 and mounting it on the wiring substrate 2, the stacked semiconductor device 1 shown in FIG. 1 can be obtained. That is, the stacked semiconductor device 1 in which the connection accuracy between the plurality of lower semiconductor elements 6 and the upper semiconductor elements 10 is shortened and the connection accuracy is improved, and such a stacked semiconductor device 1 is practically used. It is possible to provide a simple manufacturing method.

  The present invention is not limited to the above-described embodiments, and can be applied to various stacked semiconductor devices in which a plurality of lower-stage semiconductor elements and upper-stage semiconductor elements are flip-chip connected. The number of lower semiconductor elements is not particularly limited, and the number of the lower semiconductor elements may be more than that. Such a stacked semiconductor device is also included in the present invention. Furthermore, the embodiments of the present invention can be expanded or modified within the scope of the technical idea of the present invention, and these expanded and modified embodiments are also included in the technical scope of the present invention.

It is sectional drawing which shows the structure of the laminated semiconductor device by embodiment of this invention. FIG. 2 is a plan view showing a combination of a lower stage semiconductor element group and an upper stage semiconductor element in the stacked semiconductor device shown in FIG. 1. FIG. 7 is a plan view showing another combination of a lower-stage side semiconductor element group and an upper-stage side semiconductor element in the stacked semiconductor device shown in FIG. 1. It is a figure which shows the manufacturing process of the laminated semiconductor device shown in FIG. 1, Comprising: It is a perspective view which shows the board | substrate for positioning. It is a figure which expands and shows the structure of the board | substrate for positioning shown in FIG. 4, Comprising: (a) is a top view, (b) is sectional drawing. It is a figure which expands and shows the lower stage side semiconductor element arrange | positioned on the board | substrate for positioning shown in FIG. 4, Comprising: (a) is sectional drawing, (b) is a bottom view. FIG. 2 is a diagram showing a manufacturing process of the stacked semiconductor device shown in FIG. 1 and is a perspective view showing a state where a lower semiconductor element is connected to a positioning substrate. It is sectional drawing which expands and shows the connection state of the board | substrate for positioning shown in FIG. 7, and a lower stage side semiconductor element. FIG. 2 is a diagram showing a manufacturing process of the stacked semiconductor device shown in FIG. 1 and is a perspective view showing a state where an upper semiconductor element is connected to a lower semiconductor element. FIG. 10 is an enlarged cross-sectional view illustrating a connection state between the lower semiconductor element and the upper semiconductor element illustrated in FIG. 9. It is sectional drawing which expands and shows the state which filled the underfill resin between the lower stage side semiconductor element shown in FIG. 10, and formed the connection body. It is a perspective view which shows the state which removed the connection body shown in FIG. 11 from the board | substrate for positioning.

Explanation of symbols

  DESCRIPTION OF SYMBOLS 1 ... Multilayer semiconductor device, 2 ... Wiring board, 4 ... Element mounting part, 5 ... Connection pad, 6 ... Lower side semiconductor element, 8, 11 ... Electrode pad, 10 ... Upper side semiconductor element, 12 ... Bump electrode, 13 ... underfill resin, 21 ... positioning substrate, 22 ... element arrangement region, 23 ... first solder pad, 24 ... second solder pad, 26 ... connector.

Claims (4)

A wiring board having an element mounting portion; a lower semiconductor element group having a plurality of semiconductor elements mounted in parallel with the element mounting portion of the wiring board; and the plurality of semiconductor elements on the lower semiconductor element group A stacked semiconductor device comprising: an upper semiconductor element that is stacked across the plurality of semiconductor elements and has a larger shape than the plurality of semiconductor elements of the lower semiconductor element group, and is flip-chip connected to the plurality of semiconductor elements A device manufacturing method comprising:
Forming a first solder pad on the positioning substrate;
Second solder pads each having the same pattern as the first solder pad on the surface opposite to the surface on which the upper semiconductor elements are stacked of the plurality of semiconductor elements constituting the lower semiconductor element group Forming a step;
Disposing the plurality of semiconductor elements on the positioning substrate such that the first solder pad and the second solder pad face each other;
Applying heat treatment to the first and second solder pads to position the plurality of semiconductor elements based on a self-alignment effect of the solder pads;
A step of stacking the upper semiconductor element across the plurality of semiconductor elements on the lower semiconductor element group on the positioning substrate, and flip-chip connecting the plurality of semiconductor elements and the upper semiconductor element. When,
Removing the connection body of the lower semiconductor element group and the upper semiconductor element from the positioning substrate;
Mounting the connection body removed from the positioning substrate on the element mounting portion of the wiring board. A method for manufacturing a stacked semiconductor device, comprising: The method for manufacturing a stacked semiconductor device according to claim 1 ,
The method of manufacturing a stacked semiconductor device, wherein the second solder pad has the same shape as the first solder pad. In the manufacturing method of the laminated semiconductor device according to claim 1 or 2 ,
The first and second solder pads have a melting point lower than that of a bump electrode for flip-chip connection of the upper semiconductor element, and a difference in melting point between the first and second solder pads and the bump electrode In accordance with the present invention, the connection body is removed from the positioning substrate. In the manufacturing method of the laminated semiconductor device according to claim 1 or 2 ,
After flip chip connecting the upper semiconductor element to the plurality of semiconductor elements, filling the resin between the plurality of semiconductor elements and the upper semiconductor element to solidify;
After solidifying the resin, a step of heat-treating the plurality of semiconductor elements connected to the positioning substrate via the first and second solder pads, and removing the connection body from the positioning substrate. A method for manufacturing a stacked semiconductor device, comprising:

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