JP4430485B2 - Method for detecting charge state of impurities in semiconductor - Google Patents

Description

The present invention relates to a method for detecting the charge state of an impurity in a semiconductor to enable control of the current flowing between the source and drain by controlling the charge state of the impurity introduced into the channel.

  In recent years, the development of new information processing technologies such as quantum computers based on the fundamental principles of quantum mechanics and so-called "spintronics" using spins of electrons or nuclei has been remarkable. Many of these techniques use elements utilizing the state of impurities in a semiconductor. For example, a quantum computer using an element made of silicon has been proposed that uses a nuclear spin or electron spin of phosphorus acting as a donor in silicon (see Non-Patent Documents 1 and 2).

In these techniques, spin is used for calculation (calculation), but the readout of the calculation result and the initialization of the calculation are performed through the electrons (donor electrons) captured by the phosphorus donor. Therefore, it is very important to control the state of electrons occupied by the phosphorus donor.
The applicant has not yet found prior art documents related to the present invention by the time of filing other than the prior art documents specified by the prior art document information described in this specification.
BEKane, "A silicon-based nuclear spin quantum computer" Nature, vol.393, pp.133-137, (1998). LCLHollenberg, et al. "Change-based quantum computing using single donors in semiconductors", Phys. Rev. B69, 113301, (2004).

Want only goods, in the prior art, it was not possible to control the occupancy of carriers such as electrons in the impurity such as phosphorus is introduced into the semiconductor layer.
The present invention has been made to solve the above-described problems, and it is an object of the present invention to control the occupation state of carriers such as electrons in impurities such as phosphorus introduced into a semiconductor layer. To do.

The method for detecting the charge state of an impurity in a semiconductor according to the present invention includes a channel region made of a semiconductor into which a first impurity is introduced, a source made of a semiconductor that is arranged so as to sandwich the channel region and into which a second impurity is introduced, and A drain and at least first and second gate electrodes arranged opposite to each other so as to sandwich the channel region in a direction different from the arrangement direction of the source and drain, and sandwiched between the first and second gate electrodes Using a transistor having a channel region thickness of 2 to 400 nm, the ionization energy of the first impurity is set to E, and the Boltzmann constant is set to k, the temperature is set to a temperature equal to or lower than the absolute temperature E / (10 k). The concentration of the ionized first impurity is obtained from the shift amount from the theoretical value of the threshold value of the transistor with respect to the change in the potential of the gate electrode .

In the above-described method for detecting the charged state of impurities in a semiconductor , when the ionization energy is 0.2 eV or less , the first impurity may have the same conductivity type as the second impurity.
On the other hand, when the ionization energy exceeds 0.2 eV , the first impurity may have a conductivity type different from that of the second impurity.

  As described above, according to the present invention, the neutral state and the ionized state of the first impurity introduced into the channel region are controlled by the potential applied to the two gate electrodes. An excellent effect is obtained in that the occupation state of carriers such as electrons in the introduced impurities such as phosphorus can be controlled.

Hereinafter, embodiments of the present invention will be described with reference to the drawings.
Figure 1 is a schematic sectional view showing a configuration example of a semiconductor device that is used to have your to the embodiment of the present invention (transistor). This semiconductor device includes a semiconductor layer 101 made of, for example, single crystal silicon, an n-type source 102 and drain 103 formed in the semiconductor layer 101, and a channel region 104 formed in the semiconductor layer 101 sandwiched between the source 102 and drain 103. Is provided.

Here, phosphorus is introduced into the channel region 104 as a donor at a lower concentration than the source 102 and the drain 103.
In addition, the semiconductor device illustrated in FIG. 1 includes two gate insulating films 105 and 106 formed so as to sandwich the channel region 104, and two gates provided so as to sandwich the channel region 104 via the gate insulating films 105 and 106. An electrode 107 and a gate electrode 108 are provided. In FIG. 1, black circles shown in the channel region 104 schematically indicate the state of the introduced impurity.

  For example, the semiconductor device shown in FIG. 1 can be formed by using an SOI (Silicon on Insulator) substrate. In this case, the channel region, the source / drain are formed on the silicon layer formed on the buried insulating layer of the SOI substrate, and one gate electrode is formed on the silicon layer via the insulating layer. The lower silicon portion may be used as the other gate electrode. The insulating layer on the silicon layer corresponds to the gate insulating film 105, and the buried insulating layer corresponds to the gate insulating film 106. In this case, the insulating layer can be formed by thermally oxidizing the surface of the silicon layer.

Further, impurities may be introduced into the source 102, the drain 103 and the channel region 104 by, for example, an ion implantation method. The impurity is not limited to phosphorus, but may be arsenic or antimony.
Further, the thickness of the semiconductor layer 101 may be about 2 to 400 nm.

Next, an operation example of the semiconductor device illustrated in FIG. 1 is described with reference to a band diagram in FIG.
First, FIG. 2A shows a band state when the voltage V _g1 applied to the gate electrode 107 and the voltage V _g2 applied to the gate electrode 108 are both zero volts. FIG. 2B shows a band state when the voltage V _g1 applied to the gate electrode 107 is positive and the voltage V _g2 applied to the gate electrode 108 is negative. FIG. 2C shows a band state when the voltage V _g1 applied to the gate electrode 107 is negative and the voltage V _g2 applied to the gate electrode 108 is positive.

  As shown in FIG. 2A, when the voltages of the gate electrode 107 and the gate electrode 108 are both about zero volts, the potential profile (state) of the silicon in the channel region 104 is flat and all donors are frozen. Out and neutralized. Here, according to the semiconductor device illustrated in FIG. 1, carriers are generated in the channel region 104 even in this state, and a current flows between the source 102 and the drain 103.

  On the other hand, when voltages of opposite signs are applied to both the gate electrode 107 and the gate electrode 108, an electric field is generated in the silicon in the channel region 104 as shown in FIGS. Ionization begins. As the electric field in the channel region 104 becomes stronger, the number of donors to be ionized increases and eventually becomes a constant value. As a result, in this state, the state of carriers generated in the channel region 104 changes and the state of current flowing between the source 102 and the drain 103 changes compared to the state shown in FIG.

  As described above, by using two gate electrodes arranged opposite to each other, the potential in the channel region 104 can be controlled, and the charge state of the impurity atoms introduced into the channel region 104 can be controlled. . In any state, since a current flows between the source 102 and the drain 103 and changes depending on the state, each state can be observed (observed).

  Note that when both the voltages of the gate electrode 107 and the gate electrode 108 are positive or when both voltages are negative, the characteristics of the MOS transistor are not in the vicinity of the threshold value. Further, by reducing the drain voltage to such an extent that pinch-off does not occur, the charge state of the impurity atoms can be controlled uniformly over the channel direction of the channel region. On the other hand, when the drain voltage is increased to such an extent that pinch-off occurs, all the impurity atoms are ionized in the region where pinch-off occurs, so that the impurity charge state only near the source in the channel region is ionized. Can be controlled.

Here, the thickness of the semiconductor layer 101 described above will be described.
The upper limit of the thickness of the semiconductor layer 101 depends on the impurity concentration. In the ionized state of the impurity, for example, when the impurity is a donor, the band bends downward, but when this amount of bending exceeds the band gap of the semiconductor, holes are generated at the interface, and silicon ( A voltage is not applied to the channel region 104).

In other words, the donor cannot be ionized by the electric field even if the gate voltage is applied to a certain value or more. This condition is expressed as “(1/2) × (q / ε) where t is the thickness of the semiconductor layer, N is the impurity concentration, q is the elementary charge, ε is the dielectric constant of the semiconductor, and Eg is the band gap of the semiconductor. Xt ² <Eg ”. When the semiconductor is silicon, about 400nm in a concentration of N = 1El6cm ^-3, a concentration of N = 1E18 cm ^-3, the following order of 40 nm.

  On the other hand, the lower limit of the semiconductor film thickness is limited by the spread of the wave function of channel electrons (or holes) when an electric field is applied to the semiconductor. This is because the position of the channel electrons cannot be controlled thinner than the spread of the wave function. The spread of the wave function when an electric field is applied to the semiconductor does not depend strongly on the type of semiconductor and is about 1 to 3 nm. Therefore, about twice this spread (2 to 6 nm) is the lower limit of the semiconductor film thickness.

Incidentally, the charge state of the impurity (donor) in the channel region 104 can be observed by examining the threshold value of the MOS transistor shown in FIG.
The change in threshold value of the semiconductor device shown in FIG. 1 is as shown in FIG.
Note that FIG. 3A shows the case where the channel region 104 does not contain an impurity (phosphorus), and FIG. 3B shows the case where the channel region 104 contains an impurity. In FIG. 3, the horizontal axis (V _g1 ) is the voltage of the gate electrode 107, and the vertical axis (ID) is the current flowing between the source and drain. Further, the voltage (V _g2 ) of the gate electrode 108 is used as a parameter. Each curve shown in FIG. 3 is a characteristic when the drain voltage is 10 mV.

  As shown in FIG. 3A, it can be seen that the MOS characteristics shift to the negative side by making the voltage of the gate electrode 108 positive. This shift is because electrons in the channel region 104 felt positive charges induced in the gate electrode 108. Conversely, when the voltage of the gate electrode 108 is negative, negative charges are induced and shift to the positive side. However, it can be seen that the shift amount is constant regardless of the polarity or value of the voltage of the gate electrode 108.

  On the other hand, when phosphorus is introduced into the channel region 104, the characteristics of the MOS shift due to a change in the voltage of the gate electrode 108, as shown in FIG. However, in this case, the shift amount is not constant and varies depending on the voltage value of the gate electrode 108. This indicates that charges other than those induced in the gate electrode 108 are generated or disappeared.

In order to consider this result quantitatively, FIG. 4 shows a plot of the threshold value (V _TH ) as a function of the gate electrode 108 voltage (V _g2 ). In FIG. 4, when the drain voltage is 10 mV, the gate voltage (V _g1 ) at which the drain current becomes lnA is used as the threshold value (V _TH ).
As indicated by white circles in FIG. 4, when the channel region 104 does not contain impurities (phosphorus), the shift amount is constant and becomes a straight line. On the other hand, when the channel region 104 contains phosphorus, it is not a straight line as shown by a white square.

However, when the voltage of the gate electrode 108 is near zero volts, the threshold values of both are substantially equal. This indicates that when the voltage of the gate electrode 108 is near zero volts, no positive charge exists, that is, all impurities (phosphor donors) are neutralized.
In addition, regardless of whether the voltage of the gate electrode 108 is changed to positive or negative, a shift toward the negative side gradually occurs with respect to the threshold value when the channel region does not contain impurities. This indicates that an electric field is generated in the silicon of the channel region 104 due to the voltage of the gate electrode 108, and impurities (phosphorus) are ionized due to this electric field.

  The concentration of ionized phosphorus donors in the channel region 104 can be calculated from the shift amount from the threshold value when the channel region does not contain phosphorus (shift amount from the theoretical value of the threshold value). Further, by comparing the potential profile in the channel region 104 and the calculation result of the channel wave function, the ionization rate of the impurity (donor) at a specific position can be calculated.

  The above is the result of the low temperature measurement of 23K. By performing at a low temperature, the influence of thermal noise can be reduced, and the reliability of the measurement results increases. What temperature is preferred depends on the ionization energy of the donor in question. The higher the ionization energy, the more reliable the results at higher temperatures. In order to obtain reliable data, the ionization energy of impurities must be E, the Boltzmann constant should be k, and it is necessary to carry out at a temperature of E / (10k) or less. In the case of phosphorus whose ionization energy is 45 meV, a temperature of about 50 K or less is required.

  Needless to say, the above-described observation technique can be applied to a donor having a shallow level other than phosphorus. Here, the donor having a shallow level is a donor having an ionization energy of 0.2 eV or less, and lithium, antimony, phosphorus, arsenic, bismuth, and tellurium when the semiconductor is silicon.

  By the way, it has been reported that the threshold value of an n-channel MOS transistor having a donor in the channel causes an abnormal behavior at a low temperature. This phenomenon was discovered in the 1970s, and it was found that donors frozen out at low temperatures were reionized due to substrate bias (Non-Patent Document: FHGaensslen and RCJaeger, "TEMPERATURE DEPENDENT THRESHOLD BEHAVIOR OF DEPLETION MODE MOSFETst, CHARACTERIZATION AND SIMULATION "Solid-State Electron. 22, (1979) 423.). It has been discovered from research with so-called cryoelectronics in mind, which operates circuits at low temperatures. This is a phenomenon that is difficult to control the threshold value due to an abnormal behavior, and is currently regarded as a defect of an n-channel MOS transistor having a donor.

  In addition, a phenomenon has been reported in which the center position of the wave function of channel electrons in a MOS transistor having two gate electrodes using an SOI substrate is changed by changing the voltage of the two gate electrodes (Seiji Horiguchi st al ., "Analysis of Back-Gate Voltage Dependence of Threshold Voltage of Thin Silicon-on-Insulator Metal-Oxide-Semiconductor Field-Effect Transistor and Its Application of Si Single-Electron Transistor" Jpn.J.Appl.Phys.43, ( 2004) 2036.).

The two phenomena described above will be described.
First, the behavior of the threshold value at a low temperature of an n-channel MOS transistor having a donor in the channel will be described.
FIG. 5 shows the relationship between the charge state of the donor and the Fermi level. When the energy of thermal noise (kT: k is Boltzmann constant, T is absolute temperature) is sufficiently smaller than the ionization energy of the donor, that is, when the temperature is sufficiently low, when the Fermi level is below the donor level, The donor level is positively charged with electrons empty. Conversely, when the Fermi level is above the donor level, electrons enter the donor level and become neutral.

The positional relationship between the Fermi level and the donor level can be controlled by the gate voltage, and the charge state of the donor can also be controlled by changing the voltage of the gate electrode. In general, the phenomenon described above with respect to a shallow level in silicon occurs below the temperature of liquid nitrogen.
FIG. 6 shows band diagrams of a p-channel MOS transistor and an n-channel MOS transistor including a donor. When the source and drain electrodes are p-type with respect to a channel including a donor, a p-channel transistor is formed, and carriers are holes.

  FIG. 6A shows a case where a voltage near the threshold (negative voltage) is applied to the gate electrode in the p-channel MOS transistor. In the case of FIG. 6A, when the hole channel is opened, the Fermi level is in the vicinity of the valence band edge. Therefore, the donor having the level in the vicinity of the conduction band edge is always in a state of emitting electrons. Therefore, even if the gate voltage changes near the threshold value, the donor in the channel does not change the charge state. Accordingly, there is no abnormality in the threshold value even at a low temperature.

  On the other hand, when the source / drain is n-type for a channel including a donor, a MOS threshold appears when the Fermi level is near the bottom of the conduction band, as shown in FIG. Therefore, in the case of an n-channel MOS, a change in the charge state of the donor in the channel is sensitively reflected on the threshold value of the MOS. Therefore, for example, when the substrate bias is changed, as shown in FIG. 6C, the charge state of a part of the donors in the channel changes, and an abnormal threshold change appears. This abnormal threshold change is presumed to be because the potential profile of silicon in the channel and the position of the wave function of the channel electrons flowing through the MOS transistor (between the source and drain) are not controlled.

Next, a phenomenon related to a change in the wave function of channel electrons in the SOI layer will be described.
The SOI is a silicon substrate in which a single crystal silicon layer (SOI layer) is formed on silicon dioxide (hereinafter referred to as a buried oxide film) which is an insulator. Therefore, by using the substrate portion made of silicon under the buried oxide film as one gate electrode, an SOI-MOS structure having gate electrodes on the upper and lower sides as shown in FIG. 1 can be obtained. Since the two gate electrodes work equivalently to the SOI layer, either one may be used as the gate electrode, or both may be used simultaneously. By changing the voltages of the two gate electrodes, the position of the wave function of the channel electrons in the silicon layer can be changed.

  For example, when a positive voltage is applied to the upper gate electrode formed on the SOI layer through the gate insulating film and a negative voltage is applied to the lower gate electrode made of silicon of the substrate, the potential of the SOI layer is The upper gate electrode side becomes lower. For this reason, the wave function of the channel electrons in the SOI layer has a shape that is in contact with (pressed against) the gate insulating film on the upper gate electrode side.

  On the other hand, when a negative voltage is applied to the upper gate electrode and a positive voltage is applied to the lower gate electrode, the potential of the SOI layer becomes lower on the lower gate electrode side. For this reason, the wave function of the channel electrons in the SOI layer has a shape that is in contact with (pressed against) the buried insulating film that is the gate insulating film on the lower electrode side.

At these intermediate voltages, the position of the wave function continuously changes from the interface on the upper electrode side to the interface on the lower electrode side. Accordingly, when the voltages of the two gate electrodes change, the distribution of the wave function continuously changes in the depth direction of the channel electrons in the silicon layer.
The above results can be regarded as an effective method for controlling the potential profile and the position of the wave function of silicon by using an SOI-MOS structure having two opposing gate electrodes.

  Therefore, by combining the two phenomena described above, in a field-effect transistor that includes an impurity of the same conductivity type as the source / drain in the channel, such as an n-channel MOS including a donor in the channel, the channel is disposed so as to hold the channel. The two gate electrodes can control the charge state of electrons (holes) in the channel, and can observe the charge state.

  In the above description, the two gate electrodes are arranged so that each layer sandwiches the channel layer in the stacking direction, but the present invention is not limited to this. For example, as shown in FIG. 7, two gate electrodes 707 and 708 may be disposed in the planar direction of the substrate 701 so as to sandwich a channel region 704 into which an impurity having the same conductivity type as that of the source and drain is introduced. Good.

  The semiconductor device illustrated in FIG. 7 is provided on an insulating substrate 701 so as to sandwich a source region 702 and a drain region 703, and a channel region 704 and a channel region 704 sandwiched in contact with the source region 702 and the drain region 703, respectively. The gate electrode 707 and the gate 708 are provided. The source region 702, the drain region 703, the channel region 704, the gate electrode 707, and the gate 708 are arranged on the same plane of the substrate 701.

Further, the gate electrode 707 and the gate electrode 708 are arranged to face each other with the channel region 704 interposed therebetween with the gate insulating layer 705 and the gate insulating layer 706 interposed in a direction different from the source region 702 and the drain region 703.
Similar to the semiconductor device shown in FIG. 1, in order to control the potential profile of the channel region 704, the two gate electrodes 707 and 708 need to be arranged to face each other. Note that a space may be formed between the gate electrode 707 and the gate electrode 708 and the channel region 704.

  In the above description, the case where the donor impurity is introduced into the source / drain and the channel region has been described. However, the present invention is not limited to this, and the same applies even when acceptor impurities having a shallow level are introduced. An acceptor having a shallow level is an acceptor having an ionization energy of 0.2 eV or less, and boron, aluminum, gallium, and indium when the semiconductor is silicon.

  In the case of an impurity that forms a so-called deep level having an energy level near the center of the silicon band gap, the polarity of the source and drain may be p-type or n-type. The elements other than the above-described donor and acceptor having a shallow level are regarded as deep levels.

  By the way, when an n-type impurity is introduced into the source / drain, even if a p-type impurity is introduced into the channel region, it is introduced into the channel region, for example, at a low temperature of 23K. The p-type impurity is in a neutral state. Further, voltages having different polarities are applied to the two gate electrodes, and part of the p-type impurity in the channel region is ionized. However, in this case, when the p-type impurity is in a neutral state, carriers are not generated between the n-type source and drain, and no current flows.

  On the other hand, according to the semiconductor device shown in FIG. 1, since n-type impurities are introduced into the source / drain and n-type impurities are introduced into the channel region, the n-type impurity introduced into the channel region. Even if the impurities are in a neutral state, carriers are generated in the channel region and current can flow.

  In other words, the feature of the semiconductor device shown in FIG. 1 is that it can be in a neutral state when no electric field is applied to the channel region without applying a potential to the two gate electrodes, and different potentials are applied to the two gate electrodes. As a result, an impurity that is partially ionized and in which the carrier is generated in the channel region in any state is introduced into the channel region.

  For example, phosphorus introduced into silicon is set to 23K or less, and becomes neutral when no electric field is applied. Thus, the impurities introduced into the semiconductor can be in a neutral state by setting the temperature range to be lower than a predetermined temperature. Further, when phosphorus is introduced, even in the neutral state, in the channel region between the n-type source and drain, carriers are generated and current can flow. Further, when the source / drain polarity is p-type, the same as described above, if acceptor impurities are introduced into the channel region.

Therefore, it is only necessary that a shallow level impurity having the same conductivity type as that of the source / drain is introduced into the channel region.
In addition, the above-described impurities that generate deep levels are in a state where carriers are generated in the channel region in a neutral state regardless of the polarity of the source and drain. Therefore, when a deep level impurity is introduced into the channel region, it does not have to have the same conductivity type as the source / drain.

According to the shape condition of the present embodiment described above, the charge state of the impurity in the channel it is possible control, since the state observation (reading) can be a transistor, a quantum computer, spintronics, fine MOS transistor integrated It can be used as an element such as a circuit.
Note that the semiconductor is not limited to silicon, and other semiconductors may be used. Further, unlike the junction FET, the gate insulating film is not necessarily required.

It is typical sectional drawing which shows the structural example of the semiconductor device in embodiment of this invention. FIG. 3 is a band diagram for explaining an operation example of the semiconductor device shown in FIG. 1. FIG. 2 is a characteristic diagram showing a change in threshold value of the semiconductor device shown in FIG. 1. FIG. ₂ is a characteristic diagram showing the threshold value (V _TH ) of the semiconductor device shown in FIG. 1 as a function of the gate electrode 108 voltage (V _g2 ). It is a band figure which shows the relationship between the electric charge state of a donor, and Fermi level. It is a band diagram which shows the band state of the p channel MOS transistor and n channel MOS transistor containing a donor. FIG. 6 is a schematic plan view (a) and cross-sectional views (b) and (c) showing another configuration example of the semiconductor device in the embodiment of the present invention.

Explanation of symbols

DESCRIPTION OF SYMBOLS 101 ... Semiconductor layer, 102 ... Source, 103 ... Drain, 104 ... Channel region, 105, 106 ... Gate insulating film, 107, 108 ... Gate electrode.

Claims (4)

A channel region made of a semiconductor doped with a first impurity;
A source and a drain made of a semiconductor which is arranged so as to sandwich the channel region and into which a second impurity is introduced;
And at least first and second gate electrodes arranged opposite to each other so as to sandwich the channel region in a direction different from the arrangement direction of the source and drain,
A transistor in which the thickness of the channel region sandwiched between the first and second gate electrodes is 2 to 400 nm;
When the ionization energy of the first impurity is E and the Boltzmann constant is k, it is set to a temperature equal to or lower than the absolute temperature E / (10k), and the threshold value of the transistor with respect to the potential change of the first gate electrode The concentration of the ionized first impurity is obtained from the shift amount from the theoretical value of
A method for detecting a charged state of impurities in a semiconductor . The method for detecting a charge state of an impurity in a semiconductor according to claim 1,
The first impurity has the same conductivity type as the second impurity. A method for detecting a charged state of an impurity in a semiconductor . The method for detecting a charge state of an impurity in a semiconductor according to claim 2,
The method for detecting a charged state of an impurity in a semiconductor, wherein the first impurity has an ionization energy of 0.2 eV or less . The method for detecting a charge state of an impurity in a semiconductor according to claim 1,
The method for detecting a charged state of an impurity in a semiconductor, wherein the first impurity has a conductivity type different from that of the second impurity, and ionization energy exceeds 0.2 eV .

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