JP4438739B2 - Image forming apparatus - Google Patents

Description

  The present invention relates to an image forming apparatus such as a printer, a copying machine, a facsimile machine, or a decoding machine that conveys a sheet to form an image on the sheet, and more particularly to an image forming apparatus suitable when a large-capacity memory is mounted. .

  In an image forming apparatus, the capacity of a memory to be mounted is increasing with the increase in resolution and color of a formed image and the cost of a memory.

  On the other hand, in the image forming apparatus, an error check is performed on all the bits of the mounted memory, and the system is activated after confirming that it is normal. For this reason, if a memory error is detected even with one bit, the system is not started. As the memory capacity increases, the probability that a memory error will be detected increases.

  Japanese Patent Application Laid-Open No. 2004-228561 discloses that a bank memory in which a memory error is detected cannot be used, and only a usable bank memory is used to enable print processing.

  However, there is no description at all about the configuration in which only usable bank memories are used.

The first program is regarded as data, and whether or not the instruction is a memory access instruction is determined by the second program. If it is a memory access, it is determined whether or not it is an access to an available bank memory If the bank memory cannot be used, the address in the instruction word can be changed. However, since the second program must perform such processing before executing the first program, the first program changed by this processing must be stored in another memory area and executed. There is a problem that the required memory area increases as the overhead increases.
JP-A-8-204926

  SUMMARY OF THE INVENTION In view of such problems, it is an object of the present invention to provide an image forming apparatus that can use only a block in which no memory error is detected with a simple configuration and has a small overhead.

In the first aspect of the image forming apparatus according to the present invention,
A processor;
Storage means coupled to the processor for storing programs;
Volatile memory coupled to the process;
A memory management unit coupled to or embedded in the processor;
The memory management unit comprises:
A table memory that converts a conversion source block address that is an input address into a conversion destination block address that is output data; and
A multiplexer that selects one of the conversion source block address and the conversion destination block address;
A plurality of registers; if the conversion source block address matches an error block address stored in any of the plurality of registers, the multiplexer selects the conversion destination block address; otherwise, A selection control circuit for causing the multiplexer to select the conversion source block address;
The program for the processor
Perform a memory error check on the volatile memory;
When a memory error is detected, the contents of the table memory are determined so that the block address of the block is converted to the block address of the block where the memory error is not detected, and the block in which the memory error is detected Are stored in any of the plurality of registers.

  In a second aspect of the image forming apparatus according to the present invention, in the first aspect, the program sequentially instructs the processor from the last block address side of the volatile memory as the block address of the block in which the memory error is not detected. The block address is assigned.

In the third aspect of the image forming apparatus according to the present invention, in the first or second aspect,
The volatile memory is composed of a plurality of semiconductor chips,
A decoder for decoding the upper bits of the address selected by the multiplexer to generate a plurality of chip selection signals;
The plurality of chip select signals are coupled to chip enable terminals of the plurality of semiconductor chips, respectively.

In a fourth aspect of the image forming apparatus according to the present invention, in any one of the first to third aspects,
The table memory stores information indicating whether the conversion source block address is valid or invalid corresponding to the conversion destination block address,
The output of the table memory corresponding to the information is coupled to the processor so that the processor is interrupted if the information indicates invalidity.

In a fifth aspect of the image forming apparatus according to the present invention, in any one of the first to fourth aspects,
The program for the processor
The memory error check for the volatile memory is sequentially performed from one end of the block row in block units,
Each time a memory error is detected, a memory error check for the volatile memory is sequentially performed in blocks from the other end of the block row until a block without a memory error appears,
The address value of the block without memory error that has appeared is stored in the address corresponding to the block in which the memory error is detected in the table memory.

  According to the configuration of the first aspect, the memory error check is performed on the volatile memory, and when a memory error is detected, the contents of the table memory are changed so that the block is converted into a block without a memory error. When the block address of the block in which the memory error is detected is stored in one of a plurality of registers, and the conversion source block address matches one of the error block addresses stored in the plurality of registers Causes the multiplexer to select the conversion destination block address, otherwise it selects the conversion source block address, so that even a block in which a memory error is detected can be used with a small overhead with a simple configuration. .

  Also, even if a memory error is detected in a part of the volatile memory, for the block without the memory error, since the multiplexer selects the conversion source block address, the volatile memory is used more than when the conversion destination block address is selected. High speed access is possible.

  According to the configuration of the second aspect, in order to correspond the conversion source block address to the conversion destination block address, a block address in order from the last block address side of the volatile memory is assigned as the conversion destination block address. Blocks whose block addresses are invalid are gathered on the last block side, and effective conversion source block addresses become continuous, improving the memory usage efficiency.

  According to the configuration of the third aspect, since the high-order bits of the address selected by the multiplexer are decoded by the decoder and the chip selection signal is generated, an appropriate chip can be selected according to the memory error.

  According to the configuration of the fourth aspect, information indicating whether the corresponding conversion source block address is valid or invalid is stored in the table memory together with the conversion destination block address, and this information is invalid. Since the processor is interrupted in the case shown, it is possible to cope with a memory overflow error caused by the storage area becoming narrow due to the presence of the memory error block.

  According to the configuration of the fifth aspect, the memory error check for the volatile memory is sequentially performed from the one end side of the block row in block units, and the memory error check for the volatile memory is performed in block units each time a memory error is detected. In order from the other end of the block row until a block without memory error appears, and the address value of the block without memory error that has appeared is set to the address corresponding to the block in the table memory where the memory error is detected. Since the data is stored, the contents of the plurality of registers and the table memory can be easily determined while performing a memory error check.

  Other objects, configurations and effects of the present invention will become apparent from the following description.

  FIG. 1 is a schematic block diagram illustrating a hardware configuration of an image forming apparatus according to Embodiment 1 of the present invention.

  The image forming apparatus 10 is, for example, a multifunction peripheral, and is configured by combining an operation / display unit 12 and an image forming apparatus main body 13 with a control device 11. The control device 11 processes a document image read by the image forming apparatus main body 13 based on information set by the operation / display unit 12 and default setting values, or is supplied from an external host computer 20. Based on the setting information and the image data, the image forming apparatus main body 13 is caused to form an image.

  In the control device 11, a nonvolatile memory 111, a volatile memory 112, and interfaces 113 to 115 are coupled to the MPU 110 through a bus, and the interfaces 113 to 115 are coupled to the operation / display unit 12, the image forming apparatus main body 13, and the host computer 20, respectively. Has been. The nonvolatile memory 111 stores data such as programs and initial values of the system.

  FIG. 2 is a block diagram showing a schematic configuration between the MPU 110 and the volatile memory 112.

  In this example, the output address of the MPU 110 is 28 bits, and the upper 8 bits are supplied to the address input terminal of the table RAM 301 as the conversion source block address SBA, and also supplied to one input terminal of the multiplexer 302 and the selection control circuit 303. Is done. These table RAM 301, multiplexer 302 and selection control circuit 303 constitute a memory management unit 30.

  Here, as shown in FIG. 5A, the volatile memory 112 is divided into logical blocks identified by the upper 8 bits. When a hexadecimal number is expressed with an initial 0x (the initial 0x is omitted in FIG. 5), for example, the memory block 0x00 is in the address range 0x0000000-0x00FFFFF, the memory block 0x01 is in the address range 0x0100000-0x01FFFFF, and the memory block 0xFE Is the address range 0xFE00000 to 0xFEFFFFF.

  As shown in the figure, when a memory error is detected in the memory blocks 0x01, 0x03, and 0xFD, a table as shown in FIG. 5D is created by the MPU 110 according to a program as will be described later. This table is stored in the RAM 301. When the 8-bit conversion source block address SBA is supplied to the input terminal of the RAM 301, the 8-bit conversion destination block address DBA and the 1-bit invalid flag Fn are output from the RAM 301. Is. For example, when the conversion source block address SBA is 0x03, DBA = 0xFC and Fn = ‘0’ are output from the table RAM 301.

  If there is no memory error, the entire range shown in FIG. 5A can be addressed. However, if there is a memory error, the block becomes unusable and the addressable range becomes narrow. Due to the block address conversion, the unusable conversion source block address SBA moves. Fn = '1' indicates that the conversion source block address SBA is invalid.

  The signal of the invalid flag Fn is supplied to the interrupt request input terminal IRQ of the MPU 110, the MPU 110 is interrupted when Fn = '1', and it is a memory overflow error due to the interrupt processing in FIG. It is displayed on the operation / display unit 12.

  FIG. 3 is a block diagram illustrating a schematic configuration of the selection control circuit 303.

  In the selection control circuit 303, the register file 40 includes eight registers REG0 to REG7, and a valid flag Fv is stored in each most significant bit. Fv = '1' indicates that the stored value of the register (block address where a memory error exists) is valid. The block addresses excluding the valid flag Fv stored in the register file 40 are respectively supplied to eight comparators constituting the comparison circuit 41 and compared with the conversion source block address SBA, and the result is passed through the OR gate 42. It is supplied to the selection control input terminal SEL of the multiplexer 302 in FIG.

  The corresponding valid flag Fv is supplied to the enable input terminal EN of the comparator corresponding to each of the registers REG0 to REG7. When Fv = '1', the output of the corresponding comparator is valid, and Fv = '0 When ', the output of the corresponding comparator becomes' 0' regardless of the comparison result.

  With this configuration, when the conversion source block address SBA does not match any of the valid (Fv = '1') memory error block addresses stored in the register file 40, the output of the selection control circuit 303 is' The conversion source block address SBA is selected by the multiplexer 302.

  Therefore, the conversion source block address SBA of the block having no memory error is selected by the multiplexer 302 without going through the table RAM 301 and is output from the memory management unit 30, thereby increasing the memory access speed.

  Even when the conversion source block address SBA is selected by the multiplexer 302, the output of the table RAM 301 is valid. If the invalid flag Fn is “1”, the MPU 110 is interrupted.

  When the conversion source block address SBA matches one of the valid memory error block addresses stored in the register file 40, the output of the selection control circuit 303 becomes “1”, and the multiplexer 302 outputs the conversion destination block address. DBA is selected. Accordingly, the table RAM 301 only needs to store the conversion address for only the block address where the memory error exists.

  Of the 8 bits selected by the multiplexer 302, the upper 4 bits are decoded by the decoder 31 and supplied to the chip enable input terminals CE of the 16 DRAMs 1120 to 112F constituting the volatile memory 112, respectively. The conventional MMU that converts a virtual address to a physical address is configured to supply the upper bits of the conversion source block address SBA to the decoder. In this embodiment, even if the same conversion source block address SBA is used, the memory Since the chip to be accessed may differ depending on the block in which an error exists, the upper bit of the output of the multiplexer 302 is supplied to the decoder 31 for chip selection.

  In order to halve the number of address signal lines of the DRAM, the lower 4 bits of the output of the multiplexer 302 and the 20 bits of the output address of the MPU 110 are supplied to the multiplexer 32, and the row address and the column address are sequentially time-shared. 112F is supplied to the address input terminal ADR.

  As shown in FIG. 6, a memory error check is performed in block units in ascending order from block 0x00, and if a memory error is detected, a memory error check is performed in block units in descending order from the end block eb, and a memory error is detected. The block that has not been assigned is assigned (replaced) to the block in which this memory error is detected.

  In this way, even if the conversion destination block address DBA is not arranged in ascending order, blocks where the conversion source block address SBA becomes invalid (blocks with Fn = '1') are gathered at the end side, and a valid conversion source block address is obtained. Since the SBA becomes continuous, the memory use efficiency is improved, and a block without a memory error is not subject to address conversion, and high-speed access is possible.

  FIG. 4 shows a flowchart of a program for performing such processing. This program is executed by the MPU 110 and is started when the image forming apparatus 10 is powered on.

  First, in steps S0 to S10, the contents of the table RAM 301 and the selection control circuit 303 are determined while performing a memory error check on a block basis, and then the system is activated in step S11.

  (S0) The contents of the table RAM 301 and the register file 40 are initialized. That is, as shown in FIG. 5B, the contents of the table RAM 301 are cleared to zero and the contents of the register file 40 are cleared to zero.

  (S1) The initial value 0 is substituted for the memory error check target block identification variable i, and the initial value 0xFE is substituted for the valid end block identification variable eb.

  (S2) The block i is checked for memory errors. In this check, for each of a plurality of check patterns stored in the non-volatile memory 111, for example, “01010101” and “10101010”, the check pattern is written to the memory block i of the volatile memory 112, and the contents are read and written. It is determined whether or not it matches the threshold value.

  (S3) If an error is detected in step S2, the process proceeds to step S4. Otherwise, the process proceeds to step S9.

  (S4) The value of i is stored in the register of Fv = '0' in the register file 40, and this valid flag Fv is set to '1'.

  (S5) A valid end block eb is checked for memory errors in the same manner as in step S2.

  (S6) If an error is detected in step S5, the process proceeds to step S7, and if not, the process proceeds to step S8.

  (S7) Fn (eb) is set to ‘1’ and eb is decremented by one. Here, Fn (eb) is an invalid flag Fn when SBA = eb. Next, the process returns to step S5.

  (S8) The value of eb is substituted for DBA (i). Here, DBA (i) is the conversion destination block address DBA when SBA = i.

  Also, the invalid flag Fn (eb) is set to ‘1’, and eb is decremented by one.

  (S9) Increment i by 1.

  (S10) If i> eb, the process proceeds to step S11; otherwise, the process returns to step S2.

  (S11) The operating system (OS) and a dedicated program operating on the OS are activated to put the image forming apparatus 10 into a ready state.

  Next, a specific example of the above processing will be described with reference to FIG.

  In FIG. 5C, when i = 0x01, a memory error is detected in step S2, and passes through steps S3 to S6. Next, in step S8, DBA (0x01) = 0xFE, Fn (0xFE) = '1', eb = 0xFD is shown.

  In FIG. 5D, when i = 0x03, a memory error is detected in step S2, a memory error of block 0xFD is detected in step S5 through steps S3 and S4, and Fn (0xFD) = '1' is detected in step S7. Eb = 0xFC, and then passes through steps S5 to S6, and DBA (0x03) = 0xFC, Fn (0xFC) = '1', and eb = 0xFB are shown in step S8.

  Thereafter, when i = 0xFB, a memory error is not detected in step S2, and the process proceeds from step S3 to step S9, i = 0xFC is established, i> eb is established in step S10, and the process proceeds to step S11.

  As described above, according to the first embodiment, a memory error check is performed on the volatile memory 112, and if a memory error is detected, the table is converted into a block without a memory error. The contents of the RAM 301 are determined, and the block address of the block in which the memory error is detected is stored in any register of the register file 40. The valid flag Fv is set to “1”, and the comparison output with the conversion source block address SBA is output. When the conversion source block address SBA matches one of the error block addresses stored in the register file 40, the multiplexer 302 selects the conversion destination block address DBA. Otherwise, the conversion source block address Easy selection of SBA In, the usable volatile memory 112 with less overhead in block memory error was detected.

  Further, even if a memory error is detected in a part of the volatile memory 112, since the conversion source block address SBA is selected by the multiplexer 302 for the block having no memory error, the conversion destination block address DBA is selected. The volatile memory 112 can be accessed at high speed.

  Further, in order to make the conversion source block address SBA correspond to the conversion destination block address DBA, a block address in order from the last block address side of the volatile memory 112 is assigned as the conversion destination block address DBA. Invalid blocks (Fn = '1' blocks) are gathered on the end side, and valid conversion source block addresses SBA become continuous, improving the memory usage efficiency.

  In addition, since the upper bits of the address selected by the multiplexer 32 are decoded by the decoder 31 to generate a chip selection signal, an appropriate chip can be selected according to a memory error.

  In addition to the conversion destination block address DBA, the table RAM 301 stores an invalid flag Fn indicating whether the corresponding conversion source block address SBA is valid or invalid, and indicates that this flag Fn is invalid. Since the MPU 110 is interrupted in some cases, it is possible to cope with a memory overflow error caused by the storage area becoming narrow due to the presence of the memory error block.

  Furthermore, the memory error check for the volatile memory 112 is performed in ascending order in units of blocks, and each time a memory error is detected, the block address of the block is stored in any register of the register file 40, and the valid flag Fv Next, a memory error check for the volatile memory 112 is performed in descending order from the block end side in block units until a memory error-free block appears, and the address value of the memory error-free block that appears appears in the table RAM 301. Thus, the contents of the register file 40 and the table RAM 301 can be easily determined while performing a memory error check.

  Note that the present invention includes various other modifications.

  For example, in the above embodiment, the case where the volatile memory 112 that is the address conversion target is a DRAM has been described, but the present invention can be applied to an SRAM without the multiplexer 32.

  Further, the memory management unit 30 may be built in the MPU 110.

  Further, the present invention is not limited to performing a memory error check at power-on. For example, a memory error check is performed before power-off and the result is stored in a nonvolatile storage means. The contents of the table RAM 301 may be determined by reading out. In this way, the system startup time can be shortened.

  In the above embodiment, the case where the program is stored in the nonvolatile memory 111 has been described. However, the program only needs to be stored in the nonvolatile storage device, and the program is stored in an external storage device such as a hard disk. May be.

1 is a schematic block diagram illustrating a hardware configuration of an image forming apparatus according to Embodiment 1 of the present invention. It is a block diagram which shows schematic structure between MPU and memory. FIG. 3 is a block diagram illustrating a schematic configuration of a selection control circuit 303 in FIG. 2. It is a schematic flowchart of the program started execution by power-on. FIG. 5 is an explanatory diagram of the processing of FIG. 4, where (A) shows a memory block, and (B) to (D) show how the contents of a table RAM are determined. FIG. 5 is a schematic explanatory diagram of the process of FIG. 4.

Explanation of symbols

DESCRIPTION OF SYMBOLS 10 Image forming apparatus 11 Control apparatus 110 MPU
111 Nonvolatile memory 112 Volatile memory 1120-112F DRAM
113 to 115 Interface 12 Operation / display unit 13 Image forming apparatus main body 20 Host computer 30 Memory management unit 301 Table RAM
302, 32 Multiplexer 303 Selection control circuit 31 Decoder 40 Register file 41 Comparison circuit 42 OR gate CE Chip enable input terminal EN Enable input terminal ADR address input terminal SBA conversion source block address DBA conversion destination block address SEL selection control input terminal Fv valid flag Fn Invalid flag

Claims (5)

A processor;
Storage means coupled to the processor for storing programs;
Volatile memory coupled to the process;
A memory management unit coupled to or embedded in the processor;
The memory management unit comprises:
A table memory that converts a conversion source block address that is an input address into a conversion destination block address that is output data; and
A multiplexer that selects one of the conversion source block address and the conversion destination block address;
A plurality of registers; if the conversion source block address matches an error block address stored in any of the plurality of registers, the multiplexer selects the conversion destination block address; otherwise, A selection control circuit for causing the multiplexer to select the conversion source block address;
The program for the processor
Perform a memory error check on the volatile memory;
When a memory error is detected, the contents of the table memory are determined so that the block address of the block is converted to the block address of the block where the memory error is not detected, and the block in which the memory error is detected To store the block address of one of the plurality of registers,
An image forming apparatus.   2. The program according to claim 1, wherein the program causes the processor to assign a block address in order from the last block address side of the volatile memory as a block address of a block in which the memory error is not detected. Image forming apparatus. The volatile memory is composed of a plurality of semiconductor chips,
A decoder for decoding the upper bits of the address selected by the multiplexer to generate a plurality of chip selection signals;
The plurality of chip select signals are respectively coupled to chip enable terminals of the plurality of semiconductor chips;
The image forming apparatus according to claim 1, wherein the image forming apparatus is an image forming apparatus. The table memory stores information indicating whether the conversion source block address is valid or invalid corresponding to the conversion destination block address,
The output of the table memory corresponding to the information is coupled to the processor so that the processor is interrupted if the information indicates invalidity;
The image forming apparatus according to claim 1, wherein the image forming apparatus is an image forming apparatus. The program for the processor
The memory error check for the volatile memory is sequentially performed from one end of the block row in block units,
Each time a memory error is detected, a memory error check for the volatile memory is sequentially performed in blocks from the other end of the block row until a block without a memory error appears,
Storing the address value of the block without memory error at the address corresponding to the block in which the memory error is detected in the table memory;
The image forming apparatus according to claim 1, wherein the image forming apparatus is an image forming apparatus.

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