JP4442199B2 - Asynchronous signal input device and sampling frequency converter - Google Patents

Description

  The present invention relates to an asynchronous signal input device used for reliably passing an asynchronous signal between devices, and a sampling frequency conversion device using the device.

  In digital audio equipment and the like, various sampling frequencies such as 32 kHz, 44.1 kHz, and 48 kHz are used. When devices with different sampling frequencies are connected, if the data sequence of the original signal waveform sent from the sending device is read as it is by the receiving device, the output signal waveform is distorted in the time direction. The signal waveform is not reproduced correctly. Therefore, a sampling frequency converter is used in the receiving device. The sampling frequency converter is an apparatus that receives an input data string having a first sampling frequency and generates an output data string having a second sampling frequency that draws the same signal waveform based on the input data string.

  As this type of sampling frequency converter, a device using a FIFO (First In First Out) has been proposed by the present applicant (see Patent Document 1). In this specification, the technique described in Patent Document 1 is referred to as a “conventional sampling frequency converter”.

JP-A-11-55075

  In the conventional sampling frequency converter, the input data string to be processed is sequentially written into the FIFO by the input clock having the same frequency as the first sampling frequency. On the other hand, in the sampling frequency conversion device, an output clock having the same frequency as the second sampling frequency is generated, and an output data string having the second sampling frequency is generated in synchronization with the output clock. Here, the output data string is the same signal waveform as that of the input data string, but each sampling frequency is different, so that the position occupied by each of the output data string and the input data string on the time axis ( Hereinafter, sampling points) are generally different. Therefore, in order to obtain individual output data constituting the output data string, interpolation processing using a predetermined number of input data before and after the sampling point of the output data (hereinafter referred to as interpolation input data string) is performed as an output clock. Done in sync with In this interpolation process, a process for obtaining phase information indicating the position of the sampling point of output data to be generated on the time axis, and an interpolation coefficient string prepared in association with this phase information are used as an input data string for interpolation. A convolution process is performed. The phase information is generated by accumulating some appropriate value of frequency control information each time an output clock is generated. By repeating the accumulation of the frequency control information, the phase information as the accumulation result sequentially increases, and the sampling point indicated by the phase information moves on the time axis. Then, when the sampling point indicated by the phase information exceeds the sampling point of the newest input data in the input data string for interpolation, a read clock is generated at a timing synchronized with the output clock, and is stored in the FIFO. The oldest input data string is read out. The read input data is added to the interpolation input data string, and the oldest input data in the interpolation input data string is discarded. By such processing, an output data string that draws the same signal waveform as the input data string is obtained.

  Here, the frequency of the input clock used for writing the input data string to the FIFO exactly matches the first sampling frequency, and the frequency of the output clock used for timing control of the interpolation processing is the second. If the sampling frequency exactly matches, a fixed value corresponding to the ratio between the first sampling frequency and the second sampling frequency may be used as the frequency control information. However, no matter how strict the frequency accuracy of the input clock and the frequency accuracy of the output clock are, there is a limit to exactly matching each of them with the first and second sampling frequencies. For this reason, if, for example, the frequency of the input clock is higher than the first sampling frequency or the frequency of the output clock is lower than the second sampling frequency, the remaining data amount in the FIFO (reading has not been completed). The number of input data) increases with time, and eventually the FIFO overflows. Conversely, when the frequency of the input clock is lower than the first sampling frequency, or the frequency of the output clock is higher than the second sampling frequency, the remaining data amount in the FIFO increases with time. It will decrease and eventually the FIFO will underflow.

In order to solve such a problem, the conventional sampling frequency converter has an asynchronous signal input device that prevents the overflow and underflow of the FIFO by increasing or decreasing the frequency control information according to the amount of remaining data in the FIFO. Is provided.
More specifically, in this asynchronous signal input device, the remaining data amount of the FIFO, that is, the phase difference between the last written data in the FIFO and the last read data from the FIFO is compared with the target phase difference. Then, a correction amount corresponding to the phase error between them is obtained, and this correction amount is averaged on the time axis to generate frequency control information. According to this configuration, when the amount of remaining data in the FIFO increases and a positive phase error occurs, the frequency control information increases. As a result, the time gradient of the phase information increases, the frequency of reading input data from the FIFO increases, and the remaining data amount of the FIFO decreases. On the other hand, if the amount of data remaining in the FIFO decreases and a negative phase error occurs, the frequency control information decreases. As a result, the time gradient of the phase information decreases, the frequency of reading input data from the FIFO decreases, and the amount of remaining data in the FIFO increases. As described above, in the asynchronous signal input device, an operation as a PLL (Phase Locked Loop) is performed so that the time average value of the phase difference between the input data written to the FIFO and the input data read from the FIFO is converged to an appropriate value. And FIFO overflow and underflow are prevented.

By the way, the above-described conventional asynchronous signal input device calculates a correction amount according to the difference between the remaining data amount of the FIFO and the target value in accordance with a conversion table prepared in advance. Here, if the correction amount is set small with respect to the difference between the remaining data amount of the FIFO and the target value, the time until the phase lock state is resumed when the phase lock of the PLL is released becomes longer. On the other hand, if the correction amount is set large with respect to the difference between the remaining data amount of the FIFO and the target value, the shift to the phase lock state is performed quickly, but the frequency of the read clock in the phase lock state varies. Becomes larger and the operation becomes unstable. As described above, the conventional asynchronous signal input device has a problem that it is difficult to achieve both the rapid transition to the phase locked state and the stabilization of the operation in the phase locked state.
The present invention has been made in view of the above-described circumstances. The phase difference between the data read from the FIFO and the data written to the FIFO is quickly converged to the target phase difference, and this converged state is An object of the present invention is to provide an asynchronous signal input device that can be stably maintained, and a sampling frequency conversion device using the same.

In order to solve the above-described problem, an asynchronous signal input device according to the present invention is stored in a storage unit, a write control unit that writes input data to the storage unit in accordance with an input clock of a first frequency, and the storage unit. The data amount measuring means for measuring the remaining amount of the input data that has not been read, and the first and second conversion means having different conversion characteristics, and by using any of these conversion means, A loop filter unit that converts an error between the remaining amount and the target value into a correction amount and generates frequency control information based on the correction amount, and determines whether or not the remaining amount has converged to the target value A determination means for instructing the loop filter unit to use one of the first or second conversion means based on the determination result, and a read signal synchronized with an output clock of a second frequency, Comprising a read signal generating means for generating a time density corresponding to the wave number control information, the and a read control means for reading out input data from said memory means by the read signal generated by the reading signal generating means, said first The conversion means is a conversion means whose correction amount is smaller than that of the second conversion means, and when the determination means determines that the remaining amount has converged to the target value, the first conversion means The loop filter unit is instructed to use, and when it is determined that the remaining amount has not converged to the target value, the loop filter unit is instructed to use the second conversion means . . According to such an asynchronous signal input device, a conversion characteristic suitable for the current amount of data in the storage unit is provided by the conversion characteristic selection unit among a plurality of conversion characteristics based on the determination result by the determination unit. Therefore, when the data amount of the storage means is greatly deviated from the target value, this data amount is quickly converged to the target value or a predetermined range including the target value, and when the data amount has once converged, The convergence state can be maintained, and extremely stable data delivery is provided.

Further, in a preferred embodiment, the determination means changes from a state where the remaining amount is not within a preset range including the target value and a state where the remaining amount is not within the range to a state within the range. If the remaining amount is determined not to have converged to the target value for a certain period of time and the remaining amount is changed to a state in the range, and the state is maintained for the certain period of time, It is determined that the remaining amount has converged to the target value.
In a preferred aspect, the first and second conversion means have conversion characteristics such that the relationship between the error and the correction amount is non-linear.

  The sampling frequency converter according to the present invention is a means for generating interpolation information every time the output clock is generated and the asynchronous signal input device described above, and the interpolation information is generated from the loop filter unit. Interpolation information generation means for controlling based on frequency control information, data corresponding to the generation timing of the output clock, data read by the read control means and interpolation information generated by the interpolation information generation means are used. Interpolating means obtained by the interpolation calculation.

  Hereinafter, a sampling frequency converter according to the best mode of the present invention will be described with reference to the drawings.

<Configuration of this embodiment>
FIG. 1 is a block diagram showing the configuration of the sampling frequency converter according to this embodiment.
The sampling frequency converter receives a sequence of input data Din having a _first sampling frequency f ₁ (44.1 kHz in this case), and generates a second signal waveform that draws the same signal waveform based on the sequence of input data Din. It is a device that generates a sequence of output data Dout having a sampling frequency f ₂ (here, 48 kHz). In this sampling frequency converter, an output clock CKout having the same frequency as the _second sampling frequency f2 is generated by a clock generation circuit (not shown) in order to control the timing of processing for generating and outputting an output data string. The

The sampling frequency converter is roughly composed of an asynchronous signal input device 100 and an interpolation unit 20. Here, the asynchronous signal input device 100 has three functions. The first function is to receive the first input data sequence of the sampling frequency f ₁ and stored, when the interpolation unit 20 requires a new input data, the interpolation section 20 at the timing synchronized with the output clock CKout this It is a function to supply to. The second function is a function for updating the interpolation ratio Δt representing the phase of the sampling point of the output data to be generated in the interpolation unit 20 every time the output clock CKout is generated, and supplying this to the interpolation unit 20. The third function is a function of controlling frequency control information that is an increment of the interpolation ratio Δt. The interpolation unit 20 stores the input data supplied via the asynchronous signal input device 100 as a past fixed number as an input data string for interpolation, and is determined by the interpolation ratio Δt at that time at the generation timing of the output clock CKout. It is a means for generating output data by convolving the interpolation count sequence with the interpolation input data sequence.

Next, the configuration of the asynchronous signal input device 100 will be described.
The FIFO 10 is a first-in first-out buffer configured by a RAM (Random Access Memory) or the like, and can store a maximum of four pieces of data. The FIFO 10 temporarily stores the input data Din supplied from the external transmission side device, and delivers it to the interpolation unit 20 in order from the oldest one.
The write control unit 30 generates a write address and a write enable signal WE according to the input clock Ckin having the same frequency as the sampling frequency f ₁ of the input data Din, and supplies it to the FIFO 10. Input data Din supplied to the FIFO 10 is written in an area designated by a write address in the FIFO 10 by a write enable signal WE.
When the read clock CKR that commands the supply of input data to the output interpolation unit 20 is generated in synchronization with the clock CKout, the read control unit 40 generates a read address and a read enable signal RE and supplies the read address and the read enable signal RE to the FIFO 10. Here, the read address is controlled so as to designate the oldest input data remaining in the FIFO 10 and not yet read. The input data designated by the read address is read from the FIFO 10 by the read enable signal RE and supplied to the interpolation unit 20. A circuit that generates the read clock CKR will be described later.

  The up / down counter 50 counts up by “1” every time the input clock Ckin is generated, and counts down by “1” every time the read clock CKR is generated. The count value ΔS of the up / down counter 50 represents the number of unread read input data remaining in the FIFO 10 at the present time, that is, the remaining data amount. As described above, in this embodiment, since the FIFO 10 can store a maximum of four pieces of data, the value of ΔS takes any value from “0” to “4”.

  ΔS which is the count value of the up / down counter 50 indicates the remaining data amount of the FIFO 10, and at the same time, the phase difference between the data Din written last by the input clock Ckin and the data Din read last by the read clock. It can be said that it shows. The up / down counter 50, the loop filter unit 60, and the variable frequency oscillating unit 70 constitute a PLL 80 that converges this phase difference to a predetermined target phase difference. Hereinafter, the configuration of the PLL 80 will be described.

The loop filter unit 60 includes a conversion unit 61, a first full adder 62, a first latch circuit 63, and a selector 64.
The conversion unit 61 is a circuit that performs non-linear conversion on the count value ΔS of the up / down counter 50 using a conversion table instructed by a phase lock determination circuit 51 described later, and outputs a correction amount Gain · ΔS. In the conversion table, the correction amount Gain · ΔS is determined in advance according to the value of ΔS, and the correction amount Gain · ΔS corresponding to the value of ΔS is supplied from the conversion unit 61 to the first full adder 62. The

  FIG. 2 is a conversion table in this embodiment. As shown in the figure, the conversion table includes a first conversion table and a second conversion table, and a different correction amount Gain · ΔS is determined in accordance with the count value ΔS of the up / down counter 50. The first conversion table has a smaller correction amount than the second conversion table, but in any conversion table, if the value of ΔS is “0” or “1”, the negative correction amount is Zero is given when it is “2”, and a positive correction amount is given when it is “3” or “4”.

The first full adder 62 is a 15-bit full adder. The first full adder 62 adds the correction amount Gain · ΔS and the value y (n) supplied from the selector 64, and performs the calculation shown in the following equation (1). The following y (n + 1), which is the output of the first full adder 62, is latched by the first latch circuit 63 at a timing synchronized with the output clock CKout, and the frequency control information that is the output of the loop filter unit 60 is variable frequency. It is supplied to the oscillation unit 70.
y (n + 1) = y (n) + Gain · ΔS (1)

Here, y (n + 1), which is frequency control information, is fed back to the selector 64 as y (n) in the equation (1). Accordingly, in the loop filter unit 60, the frequency control information is updated based on the remaining data amount of the FIFO 10 for each output clock CKout.
The selector 64 stores a value “4096 × 44.1 / 48” as an initial value y (0), and this y (0) is given to the first full adder 62 when the operation of the apparatus is started. Thereafter, the calculation shown in the equation (1) is performed.

  The variable frequency oscillating unit 70 includes a 12-bit second full adder 71 and a second latch circuit 72. The second latch circuit 72 latches the output data of the second full adder 71 in synchronization with the output clock CKout, and feeds it back to the second full adder 71 again. That is, the second full adder 71 accumulates the frequency control information y (n) supplied as output data of the loop filter unit 60 for each output clock CKout. The output of the second latch circuit 72 is fed back to the second full adder 71 while being supplied to the interpolation unit 20 as an interpolation ratio Δt.

Since the second full adder 71 has a 12-bit configuration, a carry-out occurs from the second full adder 71 every time the accumulated value becomes 2 ¹² , that is, “4096”. The time density at which this carry-out occurs depends on the value of the frequency control information y (n) output from the loop filter unit 60. This carry-out is supplied to the read control unit 40 and the up / down counter 50 as a read clock CKR which is an output of the variable frequency oscillating unit 70.

  The phase lock determination circuit 51 is connected to the up / down counter 50 and the conversion unit 61. The phase lock determination circuit 51 receives ΔS as a phase difference signal from the up / down counter 50, determines whether ΔS has converged, and performs conversion. This is a circuit for supplying a conversion table selection signal to the unit 61. In the present embodiment, two types of conversion tables have already been prepared as shown in FIG. 2, and the conversion unit 61 selects and selects one of the conversion tables based on the supplied conversion table selection signal. The nonlinear conversion described above is performed in accordance with the converted table, and the correction amount Gain · ΔS based on the current phase difference is supplied to the loop filter unit 60 of the PLL 80. The first conversion table is selected by the conversion unit 61 according to the first conversion table selection signal, and the second conversion table is selected according to the second conversion table selection signal.

The phase lock determination circuit 51 has a control unit and a clock counter (both not shown). The control unit takes ΔS input from the up / down counter 50 into the internal memory at a timing synchronized with the clock CKout, and stores the value. When the stored value is “0” or “4”, the control unit determines that the phase lock of the PLL 80 is released, and outputs the second conversion table selection signal to the conversion unit 61.
When the value of ΔS is in the range of “1” to “2” or “2” to “3” for a certain time (1 msec) or more, the phase lock determination circuit 51 determines that the PLL 80 is in the phase lock state, and One conversion table selection signal is supplied to the converter 61. This elapsed time is obtained by the clock counter counting the number of occurrences of the clock CKout. In other cases, for example, when the value of ΔS is switched between “1” and “3”, the currently selected conversion table is maintained.
In addition, although the said fixed time is set to 1 msec here, it is not limited to this, It can set freely according to a condition. For example, in the present embodiment, it is preferable to set within a range of several milliseconds to several seconds.

<Operation of this embodiment>
FIG. 3 is a timing chart showing the operation of the asynchronous signal input device according to this embodiment. As described above, the input data Din which is a sample of the signal waveform is supplied to the FIFO 10 in synchronization with the input clock Ckin having the same frequency as the sampling frequency f ₁ (44.1 kHz). Here, the FIFO 10 has areas corresponding to four addresses “A1” to “A4”. The write controller 30 supplies the write enable signal WE to the FIFO 10 every time the input clock Ckin is generated, and sequentially writes write addresses to be given to the FIFO 10 at that time, “A1”, “A2”, “A3”, “A4”. ”,“ A1 ”, and so on. In this way, each area corresponding to the addresses “A1” to “A4” in the FIFO 10 is cyclically designated as the write destination, and the input data Din is sequentially written. Hereinafter, the input data Din written to the address “Ax” (x = 1 to 4) in the FIFO 10 is expressed as Din (Ax), and when referring to the entire input data, simply “Din”, a specific Din is designated. In this case, it is expressed as “Din (Ax)”.

The read control unit 40 supplies the read enable signal RE and the read address to the FIFO 10 every time the read clock CKR is given. At this time, the read control unit 40 cyclically changes the read address supplied together with the read enable signal to “A1”, “A2”, “A3”, “A4”, “A1”, and so on.
The up / down counter 50 counts up every time the input clock CKin is given, and counts down every time the read clock CKR is given. The count value ΔS of the up / down counter 50 represents the amount of remaining data in the FIFO 10 and also represents the phase difference between the data Din written to the FIFO 10 and the data Din read from the FIFO 10.

Here, when the amount of remaining data in the FIFO 10 is large and the phase difference indicated by the count value ΔS is larger than the target phase difference (a phase difference corresponding to “2” in the example shown in FIG. 2), The correction amount Gain · ΔS is output. On the other hand, when the remaining data amount in the FIFO 10 is small and the phase difference indicated by the count value ΔS is smaller than the target phase difference, the conversion unit 61 outputs a negative correction amount Gain · ΔS. The loop composed of the first full adder 62, the first latch circuit 63, and the selector 64 averages the correction amount Gain · ΔS sequentially output from the conversion unit 61 in this way on the time axis, and the frequency control information y ( n). The variable frequency oscillating unit 70 accumulates the frequency control information y (n) every time the output clock CKout is given. Then, every time the full adder 71 overflows during the accumulation process, the carry-out CO generated at that time is output as the read clock CKR. The time density at which the read clock CKR is generated depends on the frequency control information y (n). If the frequency control information y (n) is large, the time density of the read clock CKR is large, and conversely, the frequency control information y (n ) Is small, the time density of the read clock CKR is small. When the time density of the read clock CKR becomes larger than that corresponding to the _first sampling frequency f1, the count value ΔS of the up / down counter 50 decreases and the negative correction amount Gain · ΔS is generated. Increasing the frequency control information y (n) decreases. As a result, the time density of the read clock CKR decreases. Conversely, when the time density of the read clock CKR becomes smaller than that corresponding to the _first sampling frequency f1, the frequency at which the count value ΔS of the up / down counter 50 increases and the positive correction amount Gain · ΔS is generated. And frequency control information y (n) increases. As a result, the time density of the read clock CKR increases. As a result of such an operation as a PLL, the read clock CKR is generated in synchronization with the output clock CKout having the same frequency as the _second sampling frequency f2, but the time density thereof is the first sampling frequency. It converges to f ₁ equivalent of thing.

In the example shown in FIG. 3, the output clock CKout is generated at times t ₁ , t ₂ , t ₃ , t ₄ , and t ₅ . At time t ₁ , t ₂ , t ₃ , t ₅ , the read clock CKR is generated in synchronization with the output clock CKout, but at time t ₄ , the read clock CKR is not generated. Thus, in the present embodiment, the read clock CKR having a time density corresponding to the _first sampling frequency f1 is generated in a manner in which the individual output clocks CKout are thinned out in some places. In accordance with the read clock CKR generated in this way, the input data Din in the FIFO 10 is read in order from the oldest and supplied to the interpolation unit 20. In the interpolation unit 20, an interpolation operation using the input data Din supplied in this way is executed every time the output clock CKout is given, and output data Dout which is sampling data of the _second sampling frequency f2 is generated. Is done.

FIG. 4 is a timing chart showing the operation of the sampling frequency converter according to the present embodiment. This figure shows the operation of the interpolation unit 20 added to FIG. Hereinafter, the operation of the interpolation unit 20 will be described with reference to FIG.
As already described, the interpolation frequency Δt is generated from the variable frequency oscillating unit 70 in synchronization with the output clock CKout and supplied to the interpolation unit 20. FIG. 4 shows how the interpolation ratio Δt is updated every time the clock CKout is generated.

FIG. 5 is a diagram illustrating an interpolation process performed by the interpolation unit 20. In the present embodiment, the interpolation unit 20 has a shift register that stores the latest two pieces of input data read from the FIFO 10. The interpolation unit 20 generates two pieces of input data Din (t) and Din (t + 1) stored in the shift register at the generation timing of the output clock CKout, and the interpolation ratio Δt supplied from the variable frequency oscillation unit 70 at that time. When, by using the sampling period T of the input data Din, performs interpolation calculation for obtaining a second output data Dout of the sampling frequency _{f 2} in the generation timing of the output clock CKout. Here, the interpolation ratio Δt is the generation timing of the output clock CKout, that is, the sampling point of the output data to be obtained by interpolation (marked with X in FIG. 5) and the sampling point of the input data Din (t) immediately before it. Shows the time between. Based on these, the interpolation unit 20 executes the interpolation calculation shown in the following equation (2).
Dout = Din (t) + (Din (t + 1) −Din (t)) × Δt / T (2)

FIG. 4 shows how such an interpolation process is sequentially executed. In the following description, the output interpolation ratio at time t _x and be expressed as Delta] t _x.
At time t ₂ , the interpolation unit 20 is supplied with the interpolation ratio Δt ₂ from the second latch circuit 72. On the other hand, the shift register of the interpolation section 20, since the Din (A3) is read anew on the basis of the read clock CKR, at time _{t 2,} Din (A2), and Din (A3) are stored. Interpolation unit 20, the Din (A2), Din (A3), and the Delta] t _2, performs interpolation calculation shown in the above (2) to calculate the output data Dout _{(t 2)} at time _{t 2.} At time t ₃ , similarly to time t ₂ , Din (A3) and Din (A4) are stored in the shift register of the interpolation unit 20, and Dout (t ₃ ) is calculated.
Then, at time t _4, since the read clock CKR is not generated, the storage contents of the shift register is not changed. Therefore, the interpolation section 20, Din (A3), Din ( A4), and performs interpolation calculation using interpolation ratio Delta] t _4, calculates the output data Dout _{(t 4)} at time _{t 4.} In the sampling frequency converter according to the present embodiment, the output data Dout is calculated in this way.

  In the operation described above, when the PLL 80 is in the phase lock state, it is desirable that the value of the correction amount Gain · ΔS output from the conversion unit 61 is small. This is because if a large correction amount Gain · ΔS is output, the time variation of the frequency control information y (n) increases, the frequency variation of the variable frequency oscillator 70 increases, and the phase lock may be released. Because there is. Also, if the value of the correction amount Gain · ΔS is large, the amplitude of the steady fluctuation of the frequency control information in the phase lock state is large, the period is shortened, and the distortion of the data after the sampling frequency conversion is large. . The reason for the latter will be described in some detail below. As described above, the frequency control information is corrected so that ΔS becomes “2” (that is, ΔS at which the correction amount = 0), with a value corresponding to “4096 × 44.1 / 48” as an initial value. Is repeated. For this reason, the frequency control information draws a curve close to a sine wave having a certain period and amplitude even in the phase lock state. FIG. 7 illustrates the steady fluctuation of the frequency control information. A thin line illustrates a case where the value of the correction amount Gain · ΔS is small, and a bold line illustrates a case where the value of the correction amount Gain · ΔS is large. ing. FIG. 8 illustrates a waveform represented by data after sampling frequency conversion. A thin line indicates a case where the value of the correction amount Gain · ΔS is small, and a thick line indicates a case where the value of the correction amount Gain · ΔS is large. Each is illustrated. These drawings are merely examples, and in order to prevent the illustration from becoming complicated, curves such as frequency control information when the correction amount Gain · ΔS is small and a case where the correction amount Gain · ΔS is large are shown. A difference from a curve such as frequency control information is shown in a prominent manner. As shown in FIG. 7, the greater the correction amount Gain · ΔS, the shorter the frequency control information fluctuation period and the larger the amplitude. When the frequency control information fluctuation period becomes shorter and the amplitude becomes larger, the phase error of the data after sampling frequency conversion becomes larger and the distortion becomes larger, as shown in FIG. In order to prevent such a situation from occurring, it is desirable that the value of the correction amount Gain · ΔS is small. On the other hand, when a disturbance occurs or when the device starts up, the loop gain of the PLL 80 is increased by increasing the value of the correction amount Gain · ΔS output from the conversion unit 61, and the PLL 80 is quickly phase-locked. Is preferred. For this reason, in this embodiment, two types of conversion tables are prepared, and the frequency variation of the variable frequency oscillating unit 70 is controlled by switching them at an appropriate timing. The phase lock determination circuit 51 performs this switching control.

FIG. 6 shows how two conversion tables are switched in this embodiment. In FIG. 6, the vertical axis represents ΔS which is the output of the up / down counter 50, and the horizontal axis represents time t (arbitrary unit).
At time t _A , the value of ΔS is “4”, and the second conversion table is selected for the conversion unit 61. During the period in which the second conversion table is selected, the fluctuation range of the correction amount Gain · ΔS is large, and the loop gain of the PLL 80 is large. Therefore, the PLL 80 quickly proceeds to the phase lock state. In FIG. 6, [Delta] S is "3" at time t _B, the value of [Delta] S at time t _C is the target value "2", i.e., reaches a value corresponding to the target phase difference.

When the value of ΔS becomes “2”, the correction amount Gain · ΔS that is the output of the conversion unit 61 becomes zero, so that the frequency control information for controlling the variable frequency oscillation unit 70 gradually converges to a constant value. When the PLL 80 enters a steady state, the frequency of the read clock CKR generated by the variable frequency oscillating unit 70 is substantially the same as the input clock Ckin of 44.1 kHz, and the remaining data amount ΔS of the FIFO 10 is “1” and “2”. To and from between. In this state, the long-term time average of the phase difference between the data Din written last in the FIFO 10 and the data Din read last from the FIFO 10 converges to a constant value. Therefore, the phase lock determination circuit 51 determines that the PLL 80 is in the phase lock state, and supplies the first conversion table selection signal to the conversion unit 61. At time t _D in FIG. 6, the signal is supplied.

  The conversion unit 61 changes the conversion table to the first conversion table based on the first conversion table selection signal, and outputs the correction amount Gain · ΔS based on the conversion table. Since the correction amount Gain · ΔS in the first conversion table has a smaller fluctuation range than the correction amount Gain · ΔS in the second conversion table, the fluctuation of the frequency control information of the loop filter unit 60 in the PLL 80 is also relatively small. Therefore, the frequency fluctuation of the read clock CKR of the variable frequency oscillating unit 70 is also small, and the PLL 80 can stably maintain the phase lock state.

On the other hand, due to sudden factors (disturbances), the amount of data remaining in the FIFO 10 may change greatly. At time t _E, by such a disturbance, ΔS has been shown condition that again "4". In this case, the phase lock determination circuit 51 determines that the phase lock by the PLL 80 has been released in the same manner as described above, and supplies the second conversion table selection signal to the conversion unit 61. When ΔS reaches the target value (target phase difference) again at time t _F and the phase lock determination circuit 51 determines that the PLL 80 is phase locked at time t _G , the first conversion table selection signal is sent to the conversion unit 61. Supplied. Thus, in the asynchronous signal input device 100 according to the present embodiment, the conversion table that gives the correction amount Gain · ΔS is appropriately selected by the phase lock determination circuit 51. Therefore, the PLL 80 can be quickly phase-locked and the phase-locked state can be maintained.

  The number of conversion tables is not limited to the aspect of this embodiment. By preparing three or more types of conversion tables, the amount of FIFO data may be controlled in more detail than in the present embodiment. Moreover, the content of the conversion table may be in any form as long as the gain of the loop filter unit 60 can be adjusted regardless of whether it is linear or non-linear.

  In the present embodiment, the interpolation unit 20 performs interpolation processing by linear interpolation between two points, but the mode of interpolation such as high-order interpolation and spline interpolation is not limited. These interpolations may be used.

It is a block diagram of the sampling frequency converter which concerns on embodiment of this invention. It is a figure which shows the conversion table in the same apparatus. It is a timing chart which shows operation | movement of the asynchronous signal input device in the apparatus. It is a timing chart which shows operation | movement of the sampling frequency converter which concerns on embodiment of this invention. It is a figure which shows the interpolation process of the interpolation part 20 in the same apparatus. It is a figure explaining operation | movement of the phase lock determination circuit 51 in the same apparatus. It is a figure which illustrates the steady fluctuation of the frequency control information in the same device. It is a figure which illustrates the waveform represented by the data after sampling frequency conversion in the same apparatus.

Explanation of symbols

  DESCRIPTION OF SYMBOLS 10 ... FIFO, 20 ... Interpolation part, 30 ... Write control part, 40 ... Read control part, 50 ... Counter, 51 ... Phase lock determination circuit, 60 ... Loop filter part, 61 ... Conversion part, 62 ... 1st all Adder, 63 ... first latch circuit, 64 ... selector, 70 ... variable frequency oscillator (voltage controlled oscillator), 71 ... second full adder, 72 ... second latch circuit, 80 ... PLL (phase locked loop).

Claims (4)

Storage means;
Write control means for writing input data into the storage means in accordance with an input clock of a first frequency;
Data amount measuring means for measuring the remaining amount of unread read input data stored in the storage means;
The first and second conversion means having different conversion characteristics are provided, and by using any of these conversion means, an error between the remaining amount and the target value is converted into a correction amount, and the correction is performed. A loop filter unit that generates frequency control information based on the quantity;
Determining whether or not the remaining amount has converged to the target value, and based on the determination result, determining means for instructing the loop filter unit to use one of the first or second conversion means;
A read signal generating means for generating a read signal synchronized with the output clock of the second frequency at a time density according to the frequency control information;
Read control means for reading input data from the storage means by a read signal generated by the read signal generating means ,
The first conversion means is a conversion means having a smaller correction amount than the second conversion means,
The determination means includes
When it is determined that the remaining amount has converged to the target value, the loop filter unit is instructed to use the first conversion means,
The asynchronous signal input device, wherein when it is determined that the remaining amount has not converged to the target value, the loop filter unit is instructed to use the second conversion means . The determination means includes
When the remaining amount is not in a preset range including the target value, and for a certain period of time after the remaining amount is changed from a state not in the range to a state in the range, the remaining amount is It is determined that the target value has not converged,
After the remaining amount is changed to the state within the range, when the state is maintained for the predetermined time, it is determined that the remaining amount has converged to the target value.
The asynchronous signal input device according to claim 1. The first and second conversion means are:
The asynchronous signal input device according to claim 1, wherein the asynchronous signal input device has a conversion characteristic such that a relationship between the error and the correction amount is nonlinear. An asynchronous signal input device according to any one of claims 1 to 3 ,
Interpolation information generating means for generating interpolation information every time the output clock is generated, and controlling the interpolation information based on frequency control information generated from the loop filter unit;
Interpolating means for obtaining data corresponding to the generation timing of the output clock by an interpolation operation using the data read by the read control means and the interpolation information generated by the interpolation information generating means, Sampling frequency converter.

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