JP4443085B2 - Playback device and decoding device - Google Patents

Description

[0001]
BACKGROUND OF THE INVENTION
  The present invention relates to a playback apparatus, and more particularly, to a playback apparatus having a waveform equalization circuit for waveform equalizing a run-length limited code reproduced from a recording medium such as an optical disk.And decoding apparatusAbout.
[0002]
[Prior art]
In a playback apparatus that plays back a run-length limit code from a recording medium such as an optical disc on which the run-length limit code is recorded at a high density, partial response (hereinafter also referred to as PR) equalization is performed to remove waveform distortion of the playback signal. A device using a waveform equalizing circuit having characteristics is conventionally known (Japanese Patent Laid-Open No. 10-106161).
FIG. 37 shows a block diagram of an example of this conventional reproducing apparatus. In the figure, the run length limited code reproduced from the optical disc 601 by the recording / reproducing system 602 is supplied to the transversal filter 603, and the tap coefficient input from the tap coefficient determiner 606 in the parameter setting unit 605 is converted into the tap coefficient. Based on this, PR equalization is performed.
[0003]
The X value selector 610 selects an X value that is an intersymbol interference value in, for example, PR (1, X, X, 1) equalization in the transversal filter 603 based on the characteristics of the reproduced waveform. Xi is sequentially obtained from the determination result of the rate determiner 609, and the value of X that finally satisfies the allowable error rate is selected. The post-equalization target waveform generator 608 includes binary data given from the parameter setting binary data memory 607 and the X value of the intersymbol interference imparting value in PR equalization selected by the X value selector 610. A target waveform after equalization is created from the above and given to the tap coefficient determiner 606.
[0004]
Bits corresponding to the parameter setting binary data memory 607 are recorded on the optical disc 601 in advance. The tap coefficient determiner 606 obtains a tap coefficient such that the reproduced waveform matches the equalized target waveform from the reproduced waveform corresponding to this bit and the equalized target waveform, and inputs the tap coefficient to the transversal filter 603. The discrimination point signal level determiner 611 obtains the discrimination point signal level based on the value of X given from the X value selector 610 and supplies this to the ML decoder 604. The ML decoder 604 decodes the equalized reproduction waveform extracted from the transversal filter 3 into binary data with reference to the discrimination point signal level and outputs the binary data.
[0005]
The decoded data extracted from the ML decoder 604 is supplied to an error rate determiner 609, where it is compared with the parameter setting binary data from the parameter setting binary data memory 607 to obtain an error rate. A determination result as to whether or not the error rate satisfies an allowable value is supplied to the X value selector 610. When the error rate determination unit 609 determines that the error rate satisfies the allowable value, the PR (1, X, X, 1) ML method using the tap coefficient and the discrimination point signal level at that time, PR, etc. And maximum likelihood decoding are performed.
[0006]
Conventionally, an optical disc signal reproduction method for performing maximum likelihood detection with a code inversion interval as a constraint condition after equalizing a reproduction signal by a run length limited code whose minimum code inversion interval is limited to a constant of 2 or more. Thus, a ternary equalization apparatus for only the amplitude excluding the point corresponding to the data string having the minimum code inversion interval among the points immediately before or after the code inversion position and only the amplitude of the code inversion position. Is also known (Japanese Patent Laid-Open No. 7-192270).
[0007]
[Problems to be solved by the invention]
However, the former reproducing apparatus of the above conventional reproducing apparatuses is premised on that bits corresponding to the parameter setting binary data memory 607 are recorded on the optical disk 601 in advance. If it is unclear whether the recording signal corresponds to the binary data stored in the parameter setting binary data memory 607, the waveform equalization cannot be adaptively performed.
[0008]
Therefore, the known pattern data corresponding to the binary data stored in the parameter setting binary data memory 607 is reproduced to determine the tap coefficient of the transversal filter 603 so that the waveform is equalized normally. Don't be. For this reason, when a reproduction signal is input with a reproduction characteristic different from that when the tap coefficient is determined, it cannot be handled.
[0009]
In the latter of the above conventional playback devices, the PR equalization performed by the playback device has multiple target values, so that a fine threshold comparison is required in the error rate determination unit 609, which is caused by noise and distortion. There is a problem that the judgment becomes difficult. Therefore, in devices to which a plurality of types of signals are input (for example, playback devices such as CDs and DVDs), run lengths and PR characteristics to be equalized differ depending on the characteristics of the signals to be played back, so control for adjusting the threshold is complicated. Thus, there is a possibility that it takes a long time for the waveform equalization to be performed stably.
[0010]
Further, in the conventional reproducing apparatus, the system clock needs to be equal to or higher than the data rate, and cannot cope with the increase in speed.
[0011]
The present invention has been made in view of the above points, and an object thereof is to provide a reproducing apparatus capable of performing waveform equalization by higher quality PR equalization without being affected by noise and distortion.
[0012]
Another object of the present invention is to provide a reproducing apparatus that can realize the expansion of the convergence range and the shortening of the convergence time.
[0013]
Furthermore, another object of the present invention is to provide a reproducing apparatus that can alleviate the speed limitation due to the IC device and reduce the power consumption.
[0014]
Furthermore, another object of the present invention is to realize a high-speed data rate process by paying attention to the fact that the signal band of the input signal is narrow and lowering the system clock frequency to half that of the prior art.
[0015]
Furthermore, another object of the present invention is to process an increase in parallel processing of a circuit by reducing the system clock frequency to half that of the prior art, independently processing odd number data and even number data, and target equalization processing. The purpose is to reduce the circuit scale by specializing in intersymbol interference between odd data and intersymbol interference between even data.
[0016]
[Means for Solving the Problems]
  In order to solve the above-described problems, the present invention provides a playback device and a decoding device having the following configurations (1) to (10).
(1) In a playback device that plays back a run-length limited code recorded on a recording medium, decodes the playback signal after performing partial response equalization using a transversal filter,
Sampling output means for sampling the reproduction signal, or a signal obtained by further resampling interpolation of the sampling signal, and dividing the even-numbered reproduction data signal and the odd-number reproduction data signal and outputting them in parallel;
An even filtering means for filtering the even-numbered reproduction data signal based on a first tap coefficient and outputting it as a first waveform-equalized reproduction signal;
An odd filtering means for filtering the odd-numbered reproduction data signal based on a second tap coefficient, and outputting the second waveform equalized reproduction signal;
An even provisional discrimination circuit that calculates a provisional discrimination value of the first waveform equalized reproduction signal and outputs a difference value between the provisional discrimination value and the first waveform equalization reproduction signal as an even error signal;
An odd temporary determination circuit that calculates a temporary determination value of the second waveform equalized reproduction signal and outputs a difference value between the temporary determination value and the second waveform equalized reproduction signal as an odd error signal;
Based on the even error signal and the even reproduction data signal from the even provisional discrimination circuit, the first tap coefficient of the even filtering means is variably generated so that the even error signal is minimized. 1 tap coefficient generating means;
Based on the odd error signal from the odd provisional discrimination circuit and the odd reproduction data signal, the second tap coefficient of the odd filtering means is variably generated so that the odd error signal is minimized. Two tap coefficient generation means;
Decoding means for decoding the first waveform-equalized reproduction signal output from the even filtering means and the second waveform-equalized reproduction signal output from the odd filtering means;
A playback apparatus comprising:
(2) n tap coefficients (n is an integer of 2 or more) output from the first tap coefficient generation unit and n tap coefficients output from the second tap coefficient generation unit correspond to each other. Coefficient averaging means for outputting n coefficients each averaged between tap coefficients,
2. The reproducing apparatus according to claim 1, wherein the even filtering means and the odd filtering means receive n coefficients from the coefficient averaging means as the first and second tap coefficients.
(3) The even-numbered temporary determination circuit and the odd-numbered temporary determination circuit detect whether or not the zero cross point is detected based on both the even-numbered reproduction data signal and the odd-numbered reproduction data signal, respectively, and obtain 0 point information. The detection means for outputting and the delay circuit for outputting at least three consecutive 0 point information among the 0 point information taken out in synchronization with the bit clock from the detection means in common,
PR mode signal indicating the type of partial response equalization, RLL mode signal indicating the type of run length limit code of the reproduction signal, a plurality of the 0 point information from the delay circuit, the first waveform, etc. Based on the state transitions determined by the PR mode signal and the RLL mode signal, and the patterns of the plurality of 0 point information, 3. The reproduction apparatus according to claim 1, further comprising temporary discrimination means for calculating temporary discrimination values of the first or second waveform-equalized reproduction signal.
(4) The even tentative discrimination circuit and the odd tentative discrimination circuit detect whether or not they are zero cross points based on the first and second waveform-equalized reproduction signals and output 0 point information, respectively. And a delay circuit that outputs at least three consecutive 0-point information among the 0-point information extracted in synchronization with the bit clock from the detection means,
PR mode signal indicating the type of partial response equalization, RLL mode signal indicating the type of run length limit code of the reproduction signal, a plurality of the 0 point information from the delay circuit, the first waveform, etc. Based on the state transitions determined by the PR mode signal and the RLL mode signal, and the patterns of the plurality of 0 point information, 3. The reproduction apparatus according to claim 1, further comprising temporary discrimination means for calculating temporary discrimination values of the first or second waveform-equalized reproduction signal.
(5) The temporary determination unit calculates a temporary determination value of the first or second waveform equalization reproduction signal with at least one of the PR mode signal and the RLL mode signal as a fixed value, and the temporary determination value 5. The reproduction apparatus according to claim 3, wherein a difference value between the first and second waveform-equalized reproduction signals is output as an error signal.
(6) The detecting means receives a digital signal obtained by sampling the run-length limited code with a system clock as an input signal, and re-samples the even-numbered reproduced data signal and the odd-numbered data at a desired bit rate. The reproduction data signal is generated and supplied to the even filtering means and the odd filtering means, and it is constituted by a resampling DPLL that detects whether or not it is a zero cross point and outputs the 0 point information. The playback apparatus according to any one of claims 3 to 5.
(7) When the partial response equalization characteristic designated by the PR mode signal is expressed by PR (a, b, b, a), the temporary determination means is the median value in the three consecutive 0 point information (A + b) * × G (where G is a predetermined gain and * is the median value (a + b) is zero) The value P is calculated by the following expression), and only the values of the 0 point information both before and after the median value in the three 0 point information indicate zero cross points, and the RLL When the minimum inversion interval of the recording signal indicated by the mode signal is 2, the value P is calculated by the equation (b−a) * × G, and 0 points before and after the median value in the three 0 point information. Only when the information value indicates the zero cross point, and the minimum inversion interval of the recording signal indicated by the RLL mode signal is not 2, or 0 before or after the median value in the three 0-point information When only the point information value indicates the zero cross point, the value P is calculated by the formula b * × G, and when the median value in the three zero point information indicates the zero cross point, the provisional discrimination value is calculated. It is calculated as 0, and the calculated value P is set to the polarity of the reproduced signal after equalization of the first or second waveform when the median 0 point information of the continuous three 0 point information is obtained. 6. The reproducing apparatus according to claim 3, wherein the provisional discrimination value having a corresponding polarity is calculated.
(8) When the partial response equalization characteristic designated by the PR mode signal is represented by PR (a, b, b, a), the temporary determination means is a median value in the five consecutive 0 point information. And the values of the 0 point information before and after that do not indicate a zero cross point (a + b) * × G (where G is a predetermined gain, * is an offset so that the median (a + b) is 0) The value P is calculated by the following equation), and only the value of the 0 point information both before and after the median value in the five 0 point information indicates the zero cross point, and the RLL When the minimum inversion interval of the recording signal indicated by the mode signal is 2, the value P is calculated by the equation (b−a) ** G, and 0 points both before and after the median value in the five 0 point information. Only the information value indicates a zero cross point, and the minimum inversion interval of the recording signal indicated by the RLL mode signal is not 2, or 0 before or after the median value in the five 0-point information When only the point information value indicates a zero cross point, or when only the first and fourth zero point information values in the five zero point information indicate the zero cross point, or the five zero point information When only the values of the second and fifth 0-point information at 0 indicate zero-cross points, the value P is calculated by the formula b * × G, and the values of the five 0-point information are any of the above. If not, the value P is calculated as 0, and the calculated value P is the first value when the median 0-point information of the continuous 5 0-point information is obtained. Or reproducing apparatus as claimed in any one of claims 3 to 5, and calculates, as the provisional determination value of polarity corresponding to the polarity of the second waveform equalization after regeneration signal.
(9) In a decoding device for reproducing a run-length limited code recorded on a recording medium and decoding a digital signal obtained by performing partial response equalization on the reproduced signal using a transversal filter,
Sampling output means for dividing the digital signal into even-numbered data signals and odd-numbered data signals or interpolating and outputting in parallel;
Means for decoding the even-numbered data based on the even-numbered data signal and the odd-numbered data signal, and outputting even-numbered decoded data;
Odd-number decoding means for decoding the odd-numbered data based on the even-numbered data signal and the odd-numbered data signal and outputting odd-numbered decoded data;
The even decoding means or the odd decoding means is:
An even-numbered branch metric calculation means for inputting the even-numbered data signal and outputting an even-numbered branch metric calculation result;
Odd branch metric calculation means for receiving the odd number data signal and outputting an odd branch metric calculation result;
Calculating the second path metric by adding the even branch metric operation result to the first path metric, and outputting an even path memory control signal based on the comparison / selection result generated in the process;
The odd path metric operation result is added to the second path metric to calculate the first path metric which is delayed by one data unit, and the odd path memory control based on the comparison / selection result generated in the process. Path metric calculation means for outputting a signal;
A decoding apparatus comprising: path memory calculation means for inputting the even-numbered path memory control signal and the odd-numbered path memory control signal and outputting even-numbered decoded data and odd-numbered decoded data.
(10) An even-numbered branch metric calculating means for inputting the reproduced signal after the first waveform equalization and outputting an even-numbered branch metric calculating result;
Odd branch metric calculation means for receiving the second waveform equalized reproduction signal as input and outputting an odd branch metric calculation result;
The even path metric calculation result is added to the first path metric to calculate a second path metric, and an even path memory control signal based on the comparison / selection result generated in the process is output, and the odd branch metric is output. The calculation result is added to the second path metric and delayed by one data unit to calculate the first path metric, and an odd path memory control signal based on the comparison / selection result generated in the process is output. Path metric calculation means to
9. The memory device according to claim 1, further comprising path memory calculation means for receiving the even-numbered path memory control signal and the odd-numbered path memory control signal and outputting even-numbered decoded data and odd-numbered decoded data. Playback device.
[0028]
DETAILED DESCRIPTION OF THE INVENTION
Next, embodiments of the present invention will be described with reference to the drawings. FIG. 1 shows a block diagram of a first embodiment of a reproducing apparatus according to the present invention. In the figure, a run-length limit code (digital signal) photoelectrically converted and amplified by a PD head amplifier 16 from an optical disk 15 on which a run-length limit code is recorded at high density is converted into a high-frequency band using a low-pass filter (LPF) 17. The (noise) component is blocked, and then passed through the A / D converter 18 and, if necessary, automatically gain controlled (AGC) so that the amplitude becomes constant by an AGC circuit (not shown) and then supplied to the resampling DPLL 19 Is done. The position where the A / D converter is provided may be anywhere before the resampling DPLL 19.
[0029]
The resampling DPLL 19 is a digital PLL circuit in which a loop is completed in its own block. The input signal sampled with a fixed system clock by the A / D converter 18 is resampled at a desired bit rate. Sampled digital data (that is, resampling data of 180 ° out of the phase of digital data of 0 ° and 180 °) is generated and supplied to an adaptive equalization circuit 20 (to be described later) constituting the main part of the present embodiment. .
[0030]
Here, resampling means obtaining the sampling data at the timing of the bit clock by performing decimation interpolation calculation from the data A / D converted at the timing of the system clock. At this time, the data is divided into odd-numbered data Ф 3 and even-numbered data Ф 4 and output to the adaptive equalization circuit 20.
[0031]
Further, the resampling DPLL 19 detects a zero cross of the resampling data of phase 0 °, and obtains the odd 0 point information ZDa corresponding to the odd data signal and the even 0 point information ZDb corresponding to the even data signal obtained thereby. This is supplied to the adaptive equalization circuit 20. FIG. 3 shows the relationship between the data Φ3 and Φ4 transferred from the resampling DPLL 19 to the adaptive equalization circuit 20, the 0 point information ZDa and ZDb, and the sample points D1 to D15 arranged along the time axis.
[0032]
As shown in FIG. 3, at the rising timing of the odd 0 point information ZDa, the odd data point sampling points D1 and D9 are at the zero cross point, and immediately after the rising time of the even 0 point information ZDb, the even data signal sample. Points D6 and D14 are at the zero cross point.
[0033]
The 0 point information ZDa and ZDb indicate the point at which the bit sampling data crosses the zero level in bit units. Further, the resampling DPLL 19 locks the resampling timing, that is, the frequency and the phase so that it becomes 0 based on the value of 180 ° phase resampling data corresponding to the zero cross point indicated by the 0 point information. Let
[0034]
Here, the resampling DPLL 19 will be described in more detail. FIG. 2 shows a block diagram of one embodiment of the resampling DPLL 19. As shown in the figure, the resampling DPLL 19 is a loop feedback loop circuit comprising an interpolator 41, a phase detector 42, a loop filter 43, and a timing generator 44. The interpolator 41 includes an A / D in FIG. The reproduction digital signal Φ0 from the converter 18, the data point phase information and the bit clock from the timing generator 44 are input, and the data value of the phase point data of the reproduction digital signal Φ0 is estimated by interpolation and output. At this time, the input reproduction digital signal may be estimated directly according to the data point phase information. However, after the reproduction digital signal is first interpolated to increase the information, it may be estimated according to the data point phase information. good. This is even more accurate.
[0035]
The output data values Φ1 and Φ2 of the interpolator 41 are supplied to the phase detector 42 as resampling data. The phase detector 42 outputs the odd reproduction data Φ3 and the even reproduction data Φ4 to the adaptive equalization circuit 20 shown in FIG. 1, while generating a phase error signal and supplying the phase error signal to the loop filter 43. To the container 44. The timing generator 44 estimates the next data point phase based on the input data of the loop filter 43 and outputs the generated bit clock to the interpolator 41 as well as this data point phase information.
[0036]
Since the phase detector 42 recognizes a point where the polarity of data changes, that is, a zero cross point, and outputs a phase error signal, the point is already recognized. Therefore, odd 0 point information ZDa indicating which data corresponds to the zero cross point among the odd reproduction data Φ3, and even 0 point information ZDb indicating which data corresponds to the zero cross point among the even reproduction data Φ4, Are respectively supplied to the adaptive equalization circuit 20.
[0037]
Returning to FIG. 1 again, the adaptive equalization circuit 20 receives the odd reproduction data Φ3, odd 0 point information ZDa, even reproduction data Φ4, and even 0 point information ZDb output from the resampling DPLL 19, respectively. And generate a post-equalization reproduced waveform (odd-equalized data Φ9 and even-equalized data Φ10) by giving a PR characteristic and supply the two equalized reproduced waveforms to the decoding circuit 38 in parallel. For example, Viterbi decoding is performed.
[0038]
The equalized reproduction waveform to which the PR characteristic is given by the adaptive equalization circuit 20 is supplied to the decoding circuit 38 and is subjected to, for example, Viterbi decoding. The specific circuit configuration of this Viterbi decoding will be described later. A branch metric calculation circuit that calculates a branch metric from the sample values of the equalized reproduction waveform and a path metric by accumulating the branch metrics for each clock. And a path memory for storing a signal for selecting the most probable data series having the smallest path metric. The path memory stores a plurality of candidate sequences, and outputs the candidate sequences selected according to the selection signal from the path metric calculation circuit as a decoded data sequence.
[0039]
The ECC circuit 39 uses the error correction code in the decoded data series from the decoding circuit 38 to correct the code error of the generation element of the error correction code, and outputs decoded data with greatly reduced errors. . In the above configuration, the present embodiment is characterized by the configuration of the adaptive equalization circuit 20, and the adaptive equalization circuit 20 will be described in more detail below.
[0040]
FIG. 4 shows a block diagram of the first embodiment of the adaptive equalization circuit 20 of the main part of the apparatus of the present invention. The adaptive equalization circuit 20a of the first embodiment of FIG. 4 corresponding to the adaptive equalization circuit 20 of FIG. 1 is a transversal that imparts PR equalization characteristics to the resampling data Φ3 from the resampling DPLL 19. A filter (TVF) 21a, a multiplier / low-pass filter (LPF) 22a that changes the coefficient of the transversal filter 21a according to an error signal, and a tap delay that delays 0-point information ZDa and ZDb from the resampling DPLL 19 A circuit 23, a provisional discrimination circuit 24a that generates the error signal based on the output signal of the transversal filter 21 and the delay signal from the tap delay circuit 23, and the polarity of the error signal is inverted and supplied to the multiplier / LPF 22a. Inverter (INV) 25a and resampling from resampling DPLL 19 A transversal filter (TVF) 21b that imparts PR equalization characteristics to the ring data Φ4; a multiplier / low-pass filter (LPF) 22b that varies a coefficient of the transversal filter 21b according to an error signal; A temporary discrimination circuit 24b that generates the error signal based on the output signal of the transversal filter 21 and the delay signal from the tap delay circuit 23, and an inverter (INV) that inverts the polarity of the error signal and supplies it to the multiplier / LPF 22b. ) 25b.
[0041]
The tap delay circuit 23 has a circuit configuration as shown in FIGS. 5 and 6, for example. Further, the temporary discrimination circuits 24a and 24b have a circuit configuration as shown in FIG. 7, for example. As shown in FIG. 5, the tap delay circuit 23 delays the 0-point information ZDa and ZDb from the resampling DPLL 19 by delay elements (Delay) 101a and 101b and outputs them as delay signals Za1 and Zb1, respectively. The signals are delayed through latch modules (LM) 102 to 105 cascaded in four stages, and delay signals Za2 and Zb2, Za3 and Zb3, Za4 and Zb4, Za5 and Zb5 are output from the latch modules (LM) 102 to 105, respectively.
[0042]
As shown in FIG. 6, the LMs 102 to 105 are circuits each including a delay circuit unit configured by a D-type flip-flop 106 and a non-delay circuit unit that outputs an input signal as it is. A bit clock is input to each enable terminal (not shown) of the D-type flip-flop in the tap delay circuit 23, and a system clock is input to each clock terminal via a terminal 45. Further, a reset signal is input to each clear terminal.
[0043]
Further, the temporary discriminating circuits 24a and 24b have the same configuration, and are each composed of a temporary discriminator 110a (or 110b) and a subtractor 111a (or 111b) as shown in FIG. Data from transversal filter 21a (or 21b), an output delay signal of tap delay circuit 23, a PR mode signal described later, and an RLL mode signal described later are input to provisional discriminator 110a (or 110b). The
[0044]
The temporary discriminator 110a (or 110b) is configured by a logic circuit, and performs a temporary discriminating operation skillfully using the characteristics of the partial response characteristics according to an algorithm described later based on the input signal. The subtractor 111a (or 111b) generates an error signal by subtracting the temporary discrimination result from the temporary discriminator 110a (or 110b) from the input data Ф3 (or Ф4). This is output to the multiplier / LPF 22a (or 22b) via the INV 25a (or 25b) of FIG. As described above, since both the tap delay circuit 23 and the provisional determination circuit 24a (or 24b) are configured by digital circuits, the tap delay circuit 23 and the provisional determination circuit 24a (or 24b) are not affected by time-dependent analog variations and parameter variations, and have high reliability. In addition, the circuit scale hardly increases.
[0045]
Next, the partial response (PR) characteristic will be described. For example, if the characteristic of PR (a, b, b, a) is applied to the isolated wave shown in FIG. As is well known, it is as shown in FIG. Further, in the continuous wave, this equalization waveform takes seven values of 0, a, a + b, 2a, 2b, a + 2b, and 2a + 2b. When these 7 values are input to the Viterbi decoder, the original data (input value) and the reproduction signal (output value) after PR equalization are subject to past signal constraints and input by this and (1, 7) RLL. It is known that if the signal “1” does not last more than twice, it can be represented by a state transition diagram as shown in FIG.
[0046]
In FIG. 8C, S0 to S5 indicate states determined by the immediately preceding output value. From this state transition diagram, for example, when in state S2, when the input value is a + 2b, the output value becomes 1 and transitions to state S3, and when the input value is 2b, the output value becomes 1 and transitions to state S4. However, it is understood that no other input value is input, and if it is input, it is understood that it is an error.
[0047]
FIG. 9 is a diagram showing the relationship between the characteristics of the PR (a, b, b, a), the run length restriction rule RLL mode, and the provisional determination value output from the provisional discriminator 110a (or 110b). In the figure, the PR mode in the top row indicates the value of the signal input to the temporary determination circuit 24a (or 24b), and the RLL mode in the leftmost column indicates the temporary determination circuit 24a (or 24b) shows a signal input to the temporary discriminator 110a (or 110b), and here, RLL (1, X) and RLL (2, X) are shown.
[0048]
The value of the PR mode has a partial response characteristic of PR (1, 1), PR (1, 1, 1), PR (1, 2, 2, 1), PR (1, 3, 3, 1), PR (2 , 3, 3, 2) and PR (3,4, 4, 3). RLL (1, X) has a minimum inversion interval of “2”, and the maximum inversion interval is a run length limiting rule of a predetermined value X that varies depending on the modulation method. RLL (2, X) has a minimum inversion interval of “ 3 ″ represents a run length limiting rule of a predetermined value X whose maximum inversion interval differs depending on the modulation method.
[0049]
In the case of RLL (1, X), as described in conjunction with FIG. 8, the equalized waveform has seven values of 0, a, a + b, 2a, 2b, a + 2b, 2a + 2b in PR (a, b, b, a). FIG. 9 shows provisional determination values in each partial response characteristic corresponding to these. Among the provisional determination values, the value on the right side of the arrow indicates the value when offset so that “a + b”, which is the median value of the seven values, becomes “0”. RLL (2, X) indicates a provisional determination value similar to RLL (1, X), but there is no value in two rows indicated by 2a and 2b of RLL (1, X). This is because the transitions S5 → S1 and S2 → S4 in the state transition diagram of FIG. 8C do not exist (because the values 2a and 2b are not taken).
[0050]
In FIG. 9, PR (1, 1) is a case where a = 0 and b = 1 of PR (a, b, b, a). Further, in FIG. 9, the gain G is a multiplication coefficient for normalizing the maximum value (a + b) * after the offset, and is represented by A / (a + b) * (where A is an arbitrary level) ).
[0051]
Next, returning to FIG. 7 again, the operation of the temporary discriminating circuit 24a (24b) shown in FIG. 7 will be described. The input waveform equalized reproduction signal from the transversal filter 21a (or 21b) is obtained at the current time. Treated as signal D3. On the other hand, the 0 point information ZDa (or ZDb) from the resampling DPLL 19 is supplied to the tap delay circuit 23, and the tap delay output is input to the temporary discriminator 110a (or 110b). The provisional discriminator 110a (or 110b) performs provisional discrimination (convergence target setting) on the premise of partial response equalization according to an algorithm described later.
[0052]
The subtractor 111a (or 111b) subtracts the discrimination result obtained by the temporary discriminator 110a (or 110b) from the current time signal D3 to calculate the error signal ERRa (or ERRb), and the inverter 25a (or The polarity is inverted in 25b) and then output to the multiplier / LPF 22a (or 22b). The error signal whose polarity is inverted by the inverter 25a (or 25b) is multiplied by the tap output from the transversal filter 21a (or 21b) by the multiplier / LPF 22a (or 22b), and then the high frequency component is removed. Is output to the transversal filter 21a (or 21b) as a tap coefficient (filter coefficient) that makes the error signal of 0.
[0053]
Next, the operation of the temporary discriminator 110a (or 110b) will be described in more detail with reference to the flowchart of FIG. Here, when the value Z of the 0 point information is “1”, it indicates a zero cross point, which is the state transition of PR (a, b, b, a) shown in FIG. In the figure, it is represented by a value “a + b”, which occurs in the process of transition from state S1 to S2 or from state S4 to S5.
[0054]
In this case, in the right half of FIG. 8C, the right half states S2, S3, and S4 are positive paths (a + 2b, 2a + 2b, 2b as described with FIG. 9 when normalized to a + b = 0). ) And the left half states S5, S0, and S1 follow a path of negative values (when normalized to a + b = 0, one of 0, a, and 2a as described with reference to FIG. 9). By referring to the value before or after the zero cross point, it is possible to determine whether the path is a positive path or a negative path.
[0055]
Moreover, if the interval from one zero cross point to the next zero cross point is known, that is, if the number of transitions from state S2 to state S5 or from state S5 to state S2 is known, the path can be determined and taken. The power value becomes clear for each sample point.
[0056]
In the state transition diagram, when the value other than “a + b” is not a zero cross point, the value Z of the above 0 point information is “0”. From this state transition diagram, two zero-crossing points (Z = 1) are not taken out consecutively, and in the case of RLL (1, X), at least one between adjacent Z = 1 " 0 ”exists (when the value Z of the 0 point information changes from 1 → 0 → 1, ie, when the state S2 → S4 → S5 or the state S5 → S1 → S2 transitions). In the case of RLL (2, X), there are at least two “0” s between adjacent Z = 1. This is because the values 2a and 2b do not exist.
[0057]
In the actual signal, it is fully expected that the detection of the zero cross point itself will be erroneous due to the influence of noise, etc., but in the case of feedback control, if the probability of correct determination exceeds the probability of error, it converges in the correct direction. In addition, it is considered that there is no practical problem with single noise because of sufficient integration processing.
[0058]
Paying attention to the above points, the temporary discriminator 110a (or 110b) first identifies the value Z of the 0 point information input for each cycle of the bit clock via the tap delay circuit 23a (or 23b), and continuously Whether the five values of the five clock cycles to be performed are all “0” (step 61 in FIG. 10) or only the last value among the above five values is “1” (step 62 in FIG. 10). Whether only the first value of the above five values is “1” (step 63 in FIG. 10), the first and last values of the above five values are “1”, and the remaining three values Is "0" (step 64 in FIG. 10).
[0059]
In these patterns, when the central value of the value Z of the 0 point information of interest is “0”, the values Z of the 0 point information on both the front and rear sides are all “0”. Since the waveform is sticking to the positive side or the negative side, when satisfying any of these patterns,
P = (a + b) * La G (1)
The large value P is calculated by the following equation (step 65 in FIG. 10). However, in equation (1) and equations (2) and (3) described later, G is the gain shown in FIG. 9, and a * and b * are the values of a and b in PR (a, b, b, a). Is a value after offset so that the median (a + b) becomes zero. These values of a *, b * and G are known values obtained from the PR mode signal and the RLL mode signal.
[0060]
If none of the above patterns is present, it is determined whether or not the values 0 of the five 0-point information in successive five clock cycles are “01010” (step 66 in FIG. 10). Based on the above, it is determined whether the partial response equalization of RLL (1, X) is performed (step 67 in FIG. 10). In this pattern, when the value Z of the 0-point information of the median value of interest is “0”, the values of two Z adjacent to both sides before and after the median value are “1”. As described above, since it may occur only when RLL (1, X), when it is RLL (1, X)
P = (b−a) * La G (2)
The value P is calculated by the following equation (step 68 in FIG. 10). At this time, since the polarity changes instantaneously at the second clock, a small value P is calculated by the equation (2).
[0061]
When the value Z of the five 0-point information of the continuous 5 clock cycles is not “01010”, the value Z of the five 0-point information is “01001”, “10010”, “00010”, and “01000”. It is determined whether the pattern is any pattern (steps 69 to 72 in FIG. 10). In these four patterns, when the median value does not indicate the zero-cross point among the five consecutive zero-point information, and one of the two adjacent zero-point information before and after the median value indicates the zero-cross point It is.
[0062]
When it is one of the above four patterns, or when it is determined in step 67 that the RLL mode is not (1, X),
P = b * La G (3)
The value P is calculated by the following equation (step 73 in FIG. 10). In this case, since the signal waveform maintains the same polarity for a short period, the intermediate level value P of the equations (1) and (2) is calculated by the equation (3).
[0063]
When the value P is calculated in any of the above steps 65, 68 and 73, it is determined whether or not the waveform equalization signal D3 at the current time taken out from the D-type flip-flop 47 is 0 or more (step in FIG. 10). 74). When the waveform equalization signal D3 at the current time is 0 or more, the final provisional determination level Q is a value of P (step 75 in FIG. 10), and when it is negative, the final provisional determination level Q is a value of −P. (Step 76 in FIG. 10).
[0064]
When it is determined in step 72 that the value Z of the 0 point information is not “01000”, the final provisional determination level Q is set to “0” (step 77 in FIG. 10). For example, the case where the median value of five consecutive 0 points Z is “1” corresponds to this case.
[0065]
The provisional determination level Q obtained by the above provisional determination processing is supplied to the subtractor 52a (or 52b) in FIG. 7, and is taken as a difference signal from the waveform equalization signal D3 at the current time to be an error signal. As described above, after being latched by the D-type flip-flop 53, it is output to the multiplier / LPF 22a (or 22b) of FIG. 4 via the INV 25a (or 25b) of FIG. Are removed and output to the transversal filter 21a (or 21b) as tap coefficients.
[0066]
In this way, the tap coefficient of the transversal filter 21a (or 21b) is variably controlled so that the error signal extracted from the subtractor 52a (or 52b) in FIG. The waveform equalization according to (or 21b) can be suitably performed by expanding the convergence range.
[0067]
Next, the waveform equalization by the provisional determination process will be described more specifically. For example, when the equalized reproduction signal having the waveform indicated by the solid line in FIG. 11A is extracted from the transversal filter 21a (or 21b) and input to the temporary determination circuit 24a (or 24b), the temporary determination circuit The zero point information of the value Z as shown in the lower part of the waveform of FIG.
[0068]
Here, in FIG. 11A, the ◯ marks indicate the original data points of the run-length limit code recorded on the recording medium. In addition, a cross indicates a sample point for equalization when partial response equalization is performed by the transversal filter 21a (or 21b), which is 180 ° shifted from the original data point (other FIG. 11B). -(D), FIG. 12, FIG. 13 is also the same).
[0069]
In FIG. 11A, when the value Z of five consecutive 0-point information is all “0”, “10000”, and “00001”, they are equalized based on the above equation (1) (FIG. 11A). 10 steps 61 to 63, 65), as shown in FIG. 11B, a reproduction signal is obtained in the same waveform as the original. Note that the waveform equalization based on the calculation results of the above expressions (1) to (3) is performed according to the polarity of the waveform equalization signal D3 at the third timing of the value Z of five consecutive 0-point information. It is as shown in FIG.
[0070]
FIG. 11C shows an example of an output equalized reproduction signal waveform of the transversal filter 21a (or 21b) when the value Z of five consecutive 0-point information extracted from the resampling DPLL 19 is “10001”. Indicates. In this case, since the value of the waveform equalization signal D3 at the third timing of the value Z of the five consecutive zero point information values is positive, the waveform equalization according to the equation (1) is performed at this time (see FIG. 10). Steps 64, 65, 74, 75) and the equalized reproduction signal shown in FIG. 11D are obtained from the transversal filter 21.
[0071]
FIG. 12A shows a case where the value Z of five consecutive 0 point information extracted from the resampling DPLL 19 is “01010” and RLL (1, X), and five consecutive 0 point information. An example of an output equalized reproduction signal waveform of the transversal filter 21 when the value Z is “01001” is shown. In this case, since the value of the waveform equalization signal D3 when the value Z of the five consecutive 0 point information is “01010” is positive, the waveform equalization of the positive value by the equation (2) is performed (FIG. 10 steps 66 to 68, 74, 75), and the value of the waveform equalization signal D3 at the time of “01001” is negative, the waveform equalization of the negative value by the equation (3) is performed (FIG. 4). Steps 69, 73, 74, 76) and the equalized reproduction signal shown in FIG. 12B are obtained from the transversal filter 21.
[0072]
FIG. 13A shows a case where the value Z of five consecutive 0-point information extracted from the resampling DPLL 19 is “01000” and a case where the value Z of five consecutive 0-point information is “00010”. An example of the output signal waveform after output equalization of the transversal filter 21 is shown. In this case, since the value of the waveform equalization signal D3 is positive when the values Z of the five consecutive 0 point information values are “01000” and “00010”, the waveform of the positive value according to the equation (3), etc. (Steps 71, 73 to 75, or Steps 72 to 75 in FIG. 10) are performed, and the equalized reproduction signal shown in FIG. 13B is obtained from the transversal filter 21.
[0073]
Further, in FIG. 13C, when the value Z of five consecutive 0-point information extracted from the resampling DPLL 19 is “01001”, the value Z of five consecutive 0-point information is “10010”. An example of the reproduced signal waveform after output equalization of the transversal filter 21 is shown. In this case, since the value of the waveform equalization signal D3 is positive when the values Z of the five consecutive 0 point information values are “01001” and “10010”, the waveform of the positive value according to the equation (3), etc. (Steps 69 and 73 to 75 in FIG. 10 or Steps 70 and 73 to 75 in FIG. 10), and an equalized reproduction signal shown in FIG. 13D is obtained from the transversal filter 21.
[0074]
As described above, in this embodiment, the value Z of the 0 point information is referred to and equalized to the value determined from the state transition diagram, so that it does not depend on the level of the current sample point (others (Even if it is close to the target value, it is not affected.) Accurate waveform equalization can be performed. In addition, it is possible to cope with different partial response equalization, and further, since the probability of erroneous determination is less than that of a conventional device with a fixed threshold, the convergence time can be shortened. Note that the present embodiment can be similarly applied to RLL (2, X). This is because, as described together with FIG. 9, the state transition is substantially the same as RLL (1, X).
[0075]
FIG. 14 shows an example of an eye pattern of the output signal of the adaptive equalization circuit 20a. In FIGS. 4A and 4B, the vertical axis indicates the level expressed in 2's complement display, and the horizontal axis indicates the time represented by the number of sample points. FIG. 14A shows the eye pattern of the odd-equalized data Φ9 output from the adaptive equalization circuit 20a, and FIG. 14B shows the eye pattern of the even-equalized data Φ10 output from the adaptive equalization circuit 20a. Indicates a pattern.
[0076]
As can be seen from FIGS. 14A and 14B, according to the present embodiment, when equalized to PR (1, 1, 1, 1) as an example, data after odd equalization Φ9 and even equalization It can be seen that all of the post-data Φ10 converges to each of the five target values of “0”, “32”, “64”, “−32”, and “−64”.
[0077]
Next, another embodiment of the present invention will be described. FIG. 15A shows a block diagram of a second embodiment of the adaptive equalization circuit of the main part of the apparatus of the present invention. In the figure, the same components as those in FIG. 4 are denoted by the same reference numerals, and the description thereof is omitted. The adaptive equalization circuit 20b according to the second embodiment shown in FIG. 15A uses the tap coefficients C1 to C5 input to the transversal filters 21a and 21b as multipliers and low-pass filters (LPFs) 22a. The coefficients Ca1 to Ca5 output from the above and the coefficients Cb1 to Cb5 output from the multiplier / low-pass filter (LPF) 22b are averaged by the coefficient averaging block 26.
[0078]
As shown in FIG. 15B, the coefficient averaging block 26 is composed of five averaging circuits (AVE) 261 to 265 that perform an averaging calculation process between corresponding coefficients. C1 to C5 are output and supplied to the transversal filters 21a and 21b. In this way, even when valid data is biased to even data or odd data, it is possible to control to the correct coefficient.
[0079]
Next, a second embodiment of the present invention will be described. FIG. 16 shows a block diagram of a second embodiment of a playback apparatus according to the present invention. In the figure, the same components as those in FIG. In FIG. 16, the adaptive equalization circuit 30 of the second embodiment corresponding to the adaptive equalization circuit 20 of FIG. 1 performs adaptive equalization processing on the resampling data Φ3 and Φ4 from the resampling DPLL 19a. Thus, the characteristic is that the reproduced signals Φ9 and Φ10 after waveform equalization are output to the decoding circuit 38.
[0080]
FIG. 17 shows a block diagram of a third embodiment of the adaptive equalization circuit of the main part of the apparatus of the present invention. In the figure, the same components as those in FIG. 4 are denoted by the same reference numerals, and description thereof is omitted. The adaptive equalization circuit 30a of the third embodiment shown in FIG. 17 is an embodiment of the adaptive equalization circuit 30 of FIG. 16, and PR equalization is performed on the resampling data Φ3 and Φ4 from the resampling DPLL 19a. Transversal filters 21a and 21b for imparting characteristics, multiplier / low-pass filters (LPF) 22a and 22b for changing coefficients of the transversal filters 21a and 21b according to an error signal, a tap delay circuit 23, a transformer A temporary discrimination circuit 24a that generates an error signal based on the output signal of the versatile filter 21a and the delay signal from the tap delay circuit 23 and supplies the error signal to the multiplier / LPF 22a, and the output signal of the transversal filter 21b and the tap delay circuit 23 An error signal is generated on the basis of the delayed signal from the signal to the multiplier / LPF 22b. It comprises a provisional discrimination circuit 24b to be supplied and a zero detector 31 which detects a zero cross point from the output signals of the transversal filters 21a and 21b and supplies it to the tap delay circuit 23.
[0081]
For example, when the polarity of the post-equalization reproduction signal that is continuous in time is inverted, the zero detector 31 supplies, to the tap delay circuit 23, as the zero point information, the closer to zero of the two neighboring sample points. To do. Accordingly, this embodiment also performs the same operation as that of the embodiment of FIG.
[0082]
Next, a description will be given of a fourth embodiment of the adaptive equalization circuit of the main part of the device of the present invention. FIG. 18A shows a block diagram of a fourth embodiment of the adaptive equalization circuit of the main part of the apparatus of the present invention. In the figure, the same components as those in FIG. The adaptive equalization circuit 30b of the fourth embodiment shown in FIG. 18A is another embodiment of the adaptive equalization circuit 30 of FIG. 16, and each tap input to the transversal filters 21a and 21b. The coefficients C1 to C5 are converted into coefficients Ca1 to Ca5 output from the multiplier / low pass filter (LPF) 22a and coefficients Cb1 to Cb5 output from the multiplier / low pass filter (LPF) 22b in the coefficient averaging block 27. It is an averaged value.
[0083]
As shown in FIG. 18B, the coefficient averaging block 27 is composed of five averaging circuits (AVE) 271 to 275 that perform an averaging calculation process between corresponding coefficients. C1 to C5 are output and supplied to the transversal filters 21a and 21b. In this way, even when valid data is biased to even data or odd data, it is possible to control to the correct coefficient.
[0084]
By the way, the resampling DPLL 19 is appropriately provided with an AGC circuit and an ATC circuit on its input side and adaptive equalization circuits 20a and 20b (30a and 30b) on its output side. Therefore, there is an advantage that reliable convergence can be expected, an external circuit is not required, the configuration is simple, and the digital circuit is highly reliable. However, the present invention is not limited to this, and can be applied to a configuration that does not use the resampling DPLL as in the following embodiments.
[0085]
Next, a third embodiment of the playback apparatus of the present invention will be described. FIG. 19 shows a block diagram of a third embodiment of a playback apparatus according to the present invention. In the figure, the same components as those in FIG. In the third embodiment of the reproducing apparatus shown in FIG. 19, the input reproduction signal of the LPF 17 is supplied to a phase locked loop (PLL) circuit 32, where a clock synchronized with the bit is generated, and the clock is A / D. It is supplied to the converter 18 and the IPF 33.
[0086]
The odd data (or even data) Φ1 output from the A / D converter 18 is directly supplied to the delay and zero detector 34, and is also supplied to the interpolation filter (IPF) 33. Sample point data Φ2 at an intermediate position between two adjacent odd data (or even data) Φ1 generated by performing decimation interpolation calculation from two odd data (or even data) Φ1 at the timing of the system clock is even data (or (Odd data) is supplied to the delay and zero detector 34.
[0087]
As a result, the delay and zero detector 34 is based on the input data Ф1 and と き に 2, and when the polarity of the input data Ф1 and Ф2 is inverted, the closer to zero of the two neighboring sample points is set to 0. By supplying to the delay circuit as point information and delaying, the odd-numbered data Ф3, the even-numbered data Ф4, and the odd-numbered 0 point information ZDa and the even-numbered data corresponding to the odd-numbered data Ф3, as in the resampling DPLL19 The even 0 point information ZDb corresponding to Ф4 is generated and output and supplied to the adaptive equalization circuit 35.
[0088]
The adaptive equalization circuit 35 has the same configuration as that of the adaptive equalization circuits 20a, 20b, 30a or 30b in the first to fourth embodiments, and receives the input data Ф3, Ф4 and 0 point information ZDa and ZDa. Then, an adaptive equalization process is performed to output odd-numbered data Ф9 and even-numbered data Ф10.
[0089]
Thus, in this embodiment, the adaptive equalization circuit 35 receives the A / D converted reproduction signal instead of the signal from the resampling DPLL 19 as an input signal, and outputs Φ3, Φ4 and ZDa, ZDb. And, it is characterized in that it operates using the output signal of the zero detector 34 as an input.
[0090]
Next, a fifth embodiment of the playback apparatus of the present invention will be described. FIG. 21 shows a block diagram of a fifth embodiment of a reproducing apparatus according to the present invention. In the figure, the same components as those in FIG. In the fifth embodiment of the reproducing apparatus shown in FIG. 21, the adaptive equalization circuit 50 uses the odd-numbered data Φ1 extracted from the A / D converter 18 instead of the signals Φ3 and Φ4 from the delay and zero detector 34. And even-numbered data Φ2 are used as inputs, and the zero-point information ZDa and ZDb, which are the outputs of the zero-crossing detector / phase comparator 51 to which the odd-numbered data Φ1 and even-numbered data Φ2 are supplied, are also used as adaptive equalization There is a feature in performing the operation.
[0091]
The zero-cross detection / phase comparator 51 performs zero-cross detection of the odd-numbered data Φ1 and the even-numbered data Φ2, and compares the phase of the detected zero-cross point with the phase of the bit clock from the voltage controlled oscillator (VCO) 53. A phase error signal is generated. This phase error signal is applied as a control voltage to the VCO 53 through the loop filter 52, and variably controls its output system clock frequency. The system clock output from the VCO 53 includes the above-described bit clock, and is applied to each block that requires the device clock.
[0092]
The loop filter 52 and the VCO 53 can be configured as either digital or analog. In the case of analog, an interface for performing D / A conversion is required. This embodiment also has the same features as the above embodiments.
[0093]
Next, a sixth embodiment of the playback apparatus of the present invention will be described. FIG. 22 shows a block diagram of a sixth embodiment of a playback apparatus according to the present invention. In the figure, the same components as those in FIG. 21 are denoted by the same reference numerals, and description thereof is omitted. In the sixth embodiment of the playback apparatus shown in FIG. 22, the playback signal output from the LPF 17 is supplied to two A / D converters 54 and 55, respectively.
[0094]
On the other hand, the system clock output from the VCO 53 includes the above-described bit clock, but system clocks having phases different from each other by 180 ° are output, and the system clock having a phase of 0 ° is supplied to the A / D converter 54 to generate a reproduction signal. A / D conversion is performed to generate odd data (or even data) Φ1, and the A / D converter 55 is supplied with a system clock having a phase of 180 ° to perform A / D conversion of the reproduction signal. Even data (or odd data) Φ2 is generated. These data Φ1 and Φ2 are supplied to the adaptive equalization circuit 50 and the zero cross detection / phase comparator 51, respectively.
[0095]
Next, a seventh embodiment of the reproducing apparatus of the present invention will be described. FIG. 23 shows a block diagram of a seventh embodiment of a playback apparatus according to the present invention. In the figure, the same components as those in FIG. 21 are denoted by the same reference numerals, and description thereof is omitted. In the seventh embodiment of the reproducing apparatus shown in FIG. 23, the zero cross detection / phase comparator 56 is not the data Φ1 and Φ2 input to the adaptive equalization circuit 50 but the data output from the adaptive equalization circuit 50. The zero cross detection operation and the phase comparison operation are performed with Φ9 and Φ10 as inputs.
[0096]
Next, an eighth embodiment of the playback apparatus of the present invention will be described. FIG. 24 shows a block diagram of an eighth embodiment of a reproducing apparatus according to the present invention. In the figure, the same components as those in FIG. 22 are denoted by the same reference numerals, and description thereof is omitted. In the eighth embodiment of the reproducing apparatus shown in FIG. 24, the zero cross detection / phase comparator 57 is not the data Φ1 and Φ2 input to the adaptive equalization circuit 50 but the data output from the adaptive equalization circuit 50. The difference from the playback apparatus of the sixth embodiment shown in FIG. 22 is that zero cross detection operation and phase comparison operation are performed using Φ9 and Φ10 as inputs.
[0097]
25 and 26 show internal block diagrams of each example of the adaptive equalization circuit 50. FIG. 25 shows the same configuration as the adaptive equalization circuits 20a and 30a, and FIG. 26 shows the same configuration as the adaptive equalization circuit 30b. It is.
[0098]
In the above embodiment, the provisional discriminator 110a (or 110b), as described with reference to the flowchart of FIG. 10, receives five consecutive bit clocks input via the tap delay circuit 23. Although the temporary determination result is obtained based on the value Z of the 0 point information, it is also possible to obtain the temporary determination result based on the three consecutive values 0 of the 0 point information. FIG. 27 shows a flowchart in this case. First, it is determined whether or not the three Z-point information values Z of three consecutive clock periods are all “0” (step 81 in FIG. 27). At this time, the signal waveform is stuck on the positive side or the negative side. Therefore, when this pattern is satisfied, a large value P is calculated by the above equation (1) (step 82 in FIG. 27).
[0099]
If it is not the above pattern, it is determined whether or not the three zero point information values Z of three consecutive clock cycles are “101” (step 83 in FIG. 27), and in this pattern, based on the RLL mode signal, It is determined whether the partial response equalization is RLL (1, X) (step 84 in FIG. 27). This pattern is a case where the Z value adjacent to both the front and rear sides is “1” when the value Z of the 0-point information of the median value of interest is “0”. As described above, this is the RLL. Since it may occur only when (1, X), the value P is calculated by the above equation (2) when RLL (1, X) (step 85 in FIG. 27).
[0100]
When the three Z-point information values Z of three consecutive clock periods are not “101”, whether the three zero-point information values Z are any of the patterns “100” and “001”. The determination is made (steps 87 and 88 in FIG. 27). In these patterns, when the central value of the 0-point information value Z of the median value of interest is “0”, one of the two 0-point information values adjacent to the front and rear sides is “1”. It is. If it is any of these patterns, or if it is determined in step 84 that the RLL mode is not (1, X), the value P is calculated by the above equation (3) (step 86 in FIG. 27).
[0101]
When the value P is calculated in any of the above steps 82, 85 and 86, it is determined whether or not the waveform equalization signal D3 at the current time is 0 or more (step 89 in FIG. 27). When the waveform equalization signal D3 at the current time is 0 or more, the final provisional determination level Q is a value of P (step 91 in FIG. 27), and when it is negative, the final provisional determination level Q is a value of −P. (Step 90 in FIG. 27). When it is determined in step 88 that the value Z of the 0 point information is not “001”, the final provisional determination level Q is set to “0” (step 92 in FIG. 27). For example, the case where the median value of three consecutive 0 points Z is “1” corresponds to this case.
[0102]
Next, a fifth embodiment of the adaptive equalization circuit of the main part of the device of the present invention will be described. FIG. 28 shows a block diagram of a fifth embodiment of the adaptive equalization circuit of the principal part of the apparatus of the present invention. In the figure, the same components as those in FIG. 4 are denoted by the same reference numerals, and description thereof is omitted. The adaptive equalization circuit 60 shown in FIG. 28 is characterized in that an error selection circuit 28a is provided between the temporary determination circuit 24a and the INV 25a, and an error selection circuit 28b is provided between the temporary determination circuit 24b and the INV 25b.
[0103]
For example, as shown in FIG. 29, the error selection circuits 28a and 28b receive the error signal output from the temporary determination circuit 24a (or 24b) at the first input terminal 281 and temporarily determine at the second input terminal 282. Temporary discrimination information, which is another output of the circuit 24a (or 24b), is input, and includes a selection circuit 283, a switch circuit 284, and a zero generator 285. The temporary determination information output from the temporary determination circuit 24a (or 24b) should be set to a target value for PR equalization, and a deviation from the target value is output as an error signal. 283 outputs “1” when the temporary determination circuit 24 outputs 0 * corresponding to the zero cross point as the target value.
[0104]
The selection circuit 283 also outputs “1” when the value of the provisional determination information is + b * or −b * when RLL (2, X). As described above, this b * is obtained by normalizing the value of b in PR (a, b, b, a) by the median value (a + b) of RLL (1, X) or RLL (2, X) (so-called offset). When the value is + b * or −b *, it is determined that the value is immediately before or after the zero cross point, and “1” is output. When the value of the temporary determination information is other than the above value, the selection circuit 283 outputs “0”. When RLL (1, X) is + (b−a) *, when − (b−a) *, it is determined that the value is immediately before or after the zero cross point, and “1” is set otherwise. Outputs “0”.
[0105]
The switch circuit 284 receives an error signal input to the terminal a and a fixed value 0 from the 0 generator 285 input to the terminal b as inputs, and an output signal of the selection circuit 283 is supplied as a switching signal. When the output signal of the selection circuit 283 is “1”, the effective component of the error signal input to the terminal a is selected, and when the output signal of the selection circuit 283 is “0”, the value 0 input to the terminal b is selected. select. The signal selected by the selection circuit 283 is supplied to the multiplier / LPF 22a (or 22b) via the output terminal 286 via the INV 25a (or 25b) in FIG. 28, and from the transversal filter 21a (or 22b). After being multiplied by the tap output, the high-frequency component is removed, and then the tap coefficient (filter coefficient) is set to zero so that the error signal is input to the transversal filter 21a (or 21b).
[0106]
Next, the operation of this embodiment will be described taking the case of RLL (2, X) as an example. In the adaptive equalization circuit 20 or the like that does not have the error selection circuit 28a (or 28b), the output signal of the adaptive equalization circuit 20 is a signal that is correctly PR equalized as indicated by I in FIG. The sample point when the target value is 0 (zero cross point) is a circle, the sample point when the target value is + b * or -b * is x, and the target value is (a + b) * or-(a + b) The sample points at the time of * are indicated by triangular marks, and the error signal output from the temporary discrimination circuit 24 at this time has a slight deviation from the target value as schematically shown in FIG. Correct waveform equalization is obtained.
[0107]
However, as seen in the reproduction signal from the optical disc, when the distortion is large in the reproduction signal, the output signal of the adaptive equalization circuit 20 is indicated by a circle due to the distortion, for example, as indicated by II in FIG. The sample point when the target value is 0 (zero cross point), the sample point when the target value indicated by x is + b * or -b *, and the target value indicated by a triangle is (a + b) * or-(a + b) Among the sample points at the time of *, a waveform portion III in which the sample point indicated by a triangle is deviated from the target value is generated, and an error signal output from the temporary discrimination circuit 24a or 24b is IV in FIG. 31 (B). As schematically shown, an error occurs with a large deviation from the target value. That is, inaccurate data appears at sample points that are not near the zero cross.
[0108]
Therefore, in this embodiment, the error selection circuits 28a and 28b having the configuration shown in FIG. 29 are provided on the output side of the temporary determination circuits 24a and 24b as shown in FIG. 28, and the target values 0 *, + b * or − An error signal is invalidated by outputting a fixed value 0 instead of outputting an error signal at a sample point other than the sample point near the zero cross in the case of b * (in the case of RLL (2, X)). Therefore, when the distortion is so large that a signal that is not correctly PR equalized as indicated by II in FIG. 32A (same as II in FIG. 31A) is output from the adaptive equalization circuit 20. Even in such a case, in the adaptive equalization circuit 60, the error signal output from the error selection circuit 28a (or 28b) is fixed as shown by a black triangle mark, as shown in FIG. Replaced by the value 0 The
[0109]
For this reason, even in the sample position where a large deviation from the target value occurs when the error selection circuits 28a and 28b do not exist, in this embodiment, as shown by V in FIG. Not to be. As described above, in this embodiment, an uncertain error signal among error signals is invalidated, and only the probable one is used as an effective component of the error signal, so that it can be converged to a correct target value. Can improve. Compared to the above-described embodiments, the efficiency is lowered because a part of the error signal is invalidated in this embodiment, but the reduction in efficiency is suppressed by increasing the loop gain of the adaptive equalization circuit 60. Can do.
[0110]
Next, a sixth embodiment of the adaptive equalization circuit of the main part of the apparatus of the present invention will be described. FIG. 33 shows a block diagram of a sixth embodiment of the adaptive equalization circuit of the principal part of the apparatus of the present invention. In the figure, the same components as those in FIG. 4 are denoted by the same reference numerals, and the description thereof is omitted. The adaptive equalization circuit shown in FIG. 33 is characterized in that an error selection circuit 29a is provided between the temporary determination circuit 24a and the INV 25a, and an error selection circuit 29b is provided between the temporary determination circuit 24b and the INV 25b.
[0111]
The error selection circuits 29a and 29b are different in configuration from the error selection circuits 28a and 28b shown in FIG. 28, and include, for example, a switch circuit 291 and a 0 generator 292 as shown in FIG. FIG. 34 shows a part of the circuit 23 a of the tap delay circuit 23.
[0112]
In FIG. 34, the even 0 point information (or odd 0 point information) from the resampling DPLL 19 is information indicating the timing at which sample points formed by resampling that correspond to the zero crossing points to be locked by the resampling DPLL 19 exist. (For example, only that point is “1”, and the others are “0”). The two latch circuits 231 and 232 connected in cascade in FIG. And supplied directly to the OR circuit 233.
[0113]
Therefore, “1” is output from the OR circuit 233 only when at least one of the three consecutive 0-point information is “1”, and is applied to the switch circuit 291 as a switching signal. When the output signal of the OR circuit 233 is “1”, the switch circuit 291 selects the error signal output from the temporary determination circuit 24 a (or 24 b) and outputs it to the output terminal 293, and the output of the OR circuit 233. When the signal is “0”, the fixed value “0” output from the 0 generator 292 is selected and output to the output terminal 293.
[0114]
Here, when at least one of the three 0-point information of three consecutive clock periods input to the OR circuit 233 is “1”, the digital reproduction signal input to the resampling DPLL 19 is the zero cross sample value and its value. This indicates that the sample value is any one of the three sample values of the immediately preceding sample value and the immediately following sample value. Therefore, the switch circuit 291 has only the error signal output from the temporary determination circuit 24a (or 24b) at this time. And the fixed value 0 from the 0 generator 292 is selected at the timing of other sample values.
[0115]
As a result, in the same manner as the error selection circuits 28a and 28b having the configuration shown in FIG. 29, the error selection circuits 29a and 29b invalidate the uncertain error signal that is not near the zero cross and selectively output only the probable error signal. The same effect as when the selection circuits 28a and 28b are used can be obtained.
[0116]
Next, the operation of another example of the temporary discriminator 110a (or 110b) shown in FIG. 7 in the temporary discriminating circuit 24a (or 24b) will be described with reference to the flowchart of FIG. In the figure, the same processing steps as those in FIG. 10 are denoted by the same reference numerals, and the description thereof is omitted. In FIG. 35, when the central value of the value Z of the 0 point information of interest is “0”, the values 0 of the 0 point information on both the front and rear sides are both “0” (that is, the signal waveform has a zero cross point). In the case of being away from the above, after calculating P by the calculation of the expression (1) in step 65, the temporary determination level Q is set to 0 (step 79), and the process is terminated.
[0117]
The provisional determination level Q is obtained as an error signal by taking the difference from the waveform equalization signal D3 at the current time. However, when calculating P by the equation (1), the sample value is a sample far from the zero cross sample. Since these values are shown, it is determined that the sample values are not accurate, and the temporary determination level Q is set to 0 to invalidate the error signal.
[0118]
FIG. 36 shows a flowchart for explaining the operation of still another example of the temporary discriminator 110a (or 110b) shown in FIG. 7 in the temporary discriminating circuit 24a (or 24b). In the figure, the same processing steps as those in FIG. In FIG. 36, when the value Z of the three 0-point information in three consecutive clock cycles is all “0”, the signal waveform is away from the zero cross point, so in step 82, the above equation (1) is used. After calculating the large value P, the temporary judgment level Q is set to 0 (step 97), and the process is terminated.
[0119]
The provisional determination level Q is obtained as an error signal by taking the difference from the waveform equalization signal D3 at the current time. However, when calculating P by the equation (1), the sample value is a sample far from the zero cross sample. Since these values are shown, it is determined that the sample values are not accurate, and the temporary determination level Q is set to 0 to invalidate the error signal.
[0120]
By the way, in the above embodiment, the resampling DPLL 19 and the adaptive equalization circuits 20, 20a, 20b, 30, 30a, 30b, 35, 50, 60 are full digital processing, and the effect is great. Since it is a system clock, all calculations must be performed within the system clock frequency, and depending on the system, there may be cases where it is not suitable in terms of speed limitation and power consumption by the IC device.
[0121]
In such a case, a memory element such as a FIFO is added to the resampling data and 0 point information input to the adaptive equalization circuit, and the resampling DPLL 19 is generated in synchronization with the system clock. Of course, writing at the timing of the bit clock, for example, reading at a timing of a new clock frequency corresponding to the average value of the frequencies generated by the bit clock, and subsequent operations may be performed using the new clock.
[0122]
The present invention is not limited to the above embodiment. For example, the provisional determination circuits 24a and 24b generate both error signals by changing both the PR mode signal and the RLL mode signal. One or both may be fixed to generate an error signal.
[0123]
The INVs 25a and 25b are inserted for the purpose of negative feedback (negative feedback) when updating the coefficients of the transversal filters 21a and 21b, and there are many other methods for achieving the purpose. A typical method that can be considered is as follows. (1) The tap output of the transversal filter 21a (or 21b) is inverted at INV. (2) The output of the multiplier / LPF 22a (or 22b) is inverted at INV. (3) Change the polarity of the main signal inside the transversal filter 21a (or 21b) to adjust the tension. (4) Polarity inversion is performed in any of the blocks in the lube. At this time, of course, the polarity of D3 and the error output polarity used in the flowcharts shown in FIGS. 10, 27, 35, and 36 must be taken into consideration. Further, as the memory element, it is also possible to use a RAM or other memory element other than the FIFO.
[0124]
Next, a specific embodiment of the decoding circuit 38 of the present invention will be described with reference to the drawings.
FIG. 38 shows a block diagram of an embodiment of a decoding circuit according to the present invention. In the figure, the equalized signals Φ9 and Φ10 output from the adaptive equalization circuit 20 are respectively input to the branch metric calculation circuits 381a and 381b, and the respective branch metrics (all possible states indicated by the state transitions). The difference from the value, that is, the square of the Euclidean distance or the negative polarity added thereto is calculated. As a result (in this case, bm_p3a, bm_p2a, bm_p1a, bm_0a, bm_m1a, bm_m2a, bm_m3a obtained from the branch metric arithmetic circuit 381a
And bm_p3b, bm_p2b, bm_p1b, bm_0b, bm_m1b, bm_m2b, bm_m3b obtained from the branch metric arithmetic circuit 381b)
Are supplied to the path metric 382, and path memory control signals (ctl1a, ctl2a, ctl3a, ctl4a and ctl1b, ctl2b, ctl3b, ctl4b) obtained in the process of the path metric calculation are supplied to the path memory calculation circuit 383. The path memory arithmetic circuit 383 outputs the decoded data Φ11 and Φ12 based on the path memory control signal.
[0125]
FIG. 39 shows an embodiment of each of the branch metric calculation circuits 381a and 381b. Assuming that the input values of the state transition diagram shown in FIG. 8C are assigned to aim_p3, aim_p2, aim_p1, aim_0, aim_m1, aim_m2, and aim_m3 as shown on the right of FIG. 39, the input signal and each value , And the result of calculating the square in the square calculation block is output as a branch metric.
[0126]
FIG. 40 shows an embodiment of the path metric calculation 382.
First, bm_p3a, bm_p2a, bm_p1a, bm_0a, bm_m1a, bm_m2a, bm_m3a obtained from the branch metric arithmetic circuit 381a follow the predetermined path shown in the state transition diagram shown in FIG. , L4a, L5a, L2a, L1a, and L0a, and then the comparison is made at the place where merging occurs (corresponding to S3, S4, S1, and S0 in the state transition diagram shown in FIG. 8C) and small Select The result is sent to the LM (see FIG. 6), and the second path metrics L3b, L4b, L5b, L2b, L1b, L0b
Is output as In this process, the information obtained by comparison and selection is transferred to the path memory control signals ctl1a, ctl2a, ctl3a, ctl4a.
Is output as
[0127]
Next, bm_p3b, bm_p1b, bm_0b, bm_m1b, bm_m2b, bm_m3b) obtained from the branch metric calculation circuit 381b follow the predetermined path shown in the state transition diagram shown in FIG. After adding L3b, L4b, L5b, L2b, L1b, and L0b, comparison is performed at the place where merging occurs (corresponding to S3, S4, S1, and S0 in the state transition diagram shown in FIG. 8C). Choose the smaller one. The result is sent to the LM, delayed by one data unit in the latch, and then the first path metric
L3a, L4a, L5a, L2a, L1a, L0a
Is output as
In this process, the information obtained by the comparison and selection is the path memory control signal ctl1b, ctl2b, ctl3b, ctl4b
Is output as
[0128]
That is, metric calculation for two steps is performed in one clock. Conventionally, when a metric for one step is performed with one clock, the time excluding the setup / hold period of the latch is an operation margin. In contrast, in the present application, metric calculation for two steps is performed with one clock, but the setup and hold period of the latch is not doubled, and is the same as in the past. Therefore, it is possible to earn a calculation margin accordingly.
Further, since the operations for two steps are configured only by combinational logic, it is advantageous for LSI placement and routing, and high-speed processing is possible even with only processing by a normal synthesis tool.
[0129]
FIG. 41 shows another embodiment of the path metric calculation 382 considering the offset calculation. In the Viterbi decoding path metric calculation, the path metric increases with time (decreases when the polarity is handled in the negative direction), so it is confirmed that the path metric for all states exceeds a certain threshold. A method called offset subtraction is used in which a value is subtracted (offset) from each path metric. However, this subtraction must be completed within one step, as is the operation required for each step (accumulation / comparison / selection). In FIG. 41, the first path metric
L3b, L4b, L5b, L2b, L1b, L0b
And the second path metric
L3b, L4b, L5b, L2b, L1b, L0b
Is a new path metric that is input to the offset calculation circuit and subtracts the common offset if necessary
L3b ', L4b', L5b ', L2b', L1b ', L0b' and L3b ', L4b', L5b ', L2b', L1b ', L0b'
Get. This is
bm_p3a, bm_p2a, bm_p1a, bm_0a, bm_m1a, bm_m2a, bm_m3a
as well as
bm_p3b, bm_p2b, bm_p1b, bm_0b, bm_m1b, bm_m2b, bm_m3b
Is added to
[0130]
FIG. 42 shows an embodiment of the offset calculation block.
The first path metrics L3a, L4a, L5a, L2a, L1a, and L0a are input to the offset calculation circuit and compared with a preset threshold level. If all the metrics exceed this value, the offset value fs1 Is set to that value, and 0 otherwise.
A new path metric is obtained by subtracting the offset value fs1 from the input path metric.
Second path metric
L3b, L4b, L5b, L2b, L1b, L0b
Is input to the offset calculation circuit and compared with a preset threshold level. If all the metrics exceed this value, the offset value fs2 is set to that value, otherwise it is set to zero.
A new path metric is obtained by subtracting the offset value fs1 from the input path metric.
You can use both of these or just one. Further, if there is a margin in the bit limit of the circuit, the relationship between the (first and second) path metrics and fs (1, 2) may be interchanged.
[0131]
FIG. 43 shows a specific embodiment of the path memory arithmetic circuit 383.
The path modules are connected in cascade as many as necessary. A fixed value is input to the first pass module, and each pass module has a pass memory control signal.
ctl1a, ctl2a, ctl3a, ctl4a
as well as
ctl1b, ctl2b, ctl3b, ctl4b
Controlled by. Finally, two majority voting circuits are prepared, determined to have the largest value, and output as decoded outputs Φ11 and Φ12.
[0132]
FIG. 44 shows a specific embodiment of the pass module.
Each input is output through a selection operation by SW and a latch and matrix operation by LM (see FIG. 6).
[0133]
Note that the present invention is not limited to the above-described embodiment, and the input of the decoding circuit may be interpolated immediately before. This embodiment is shown in FIGS.
A ninth embodiment of the device of the present invention will be described with reference to FIG. In the figure, the same components as those in FIG.
The resampling DPLL 300 has a function equivalent to 19 in FIG. 1, and supplies only the odd-numbered data Φ3 (or even-numbered data Φ4) output therefrom to the equalization circuit 301. At this time, the equalization circuit 301 is configured by a known transversal filter or the like.
[0134]
This output is supplied to the decoding circuit 38 as odd-numbered data Φ9 (or even-numbered data Φ10). Here, the odd-numbered data Φ9 (or even-numbered data Φ10) is also supplied to the IPF 302, and even-numbered data Φ10 (or odd-numbered data Φ9) is generated by interpolation and supplied to the decoding circuit 38. . With such a configuration, there is an advantage that the circuit scale can be reduced although the pulling performance and data accuracy are lowered.
[0135]
A tenth embodiment of the device of the present invention will be described with reference to FIG. In the figure, the same components as those in FIG. 19 are denoted by the same reference numerals, and the description thereof is omitted.
The odd-numbered data Φ1 (or even-numbered data Φ2) output from the A / D converter 18 is supplied to the equalizing circuit 303, and the odd-numbered data Φ9 (or even-numbered data Φ10) is supplied to the decoding circuit 38. Supplied. The odd-numbered data Φ9 (or even-numbered data Φ10) is also supplied to the IPF 304, and even-numbered data Φ10 (or odd-numbered data Φ9) is generated by interpolation and supplied to the decoding circuit 38. With such a configuration, there is an advantage that the circuit scale can be reduced although the pulling performance and data accuracy are lowered.
[0136]
【The invention's effect】
As described above, according to the present invention, the increase in the parallel processing of the circuit by reducing the system clock frequency to half that of the prior art is applied to the odd-numbered reproduced data signal and the even-numbered reproduced data signal, respectively. Independent processing and waveform equalization processing targets are specialized for intersymbol interference between odd-numbered reproduced data and inter-code interference between even-numbered reproduced data signals. Can be realized.
[0137]
Further, according to the present invention, an error signal that is an error from the convergence target value determined from the state transition is generated and output from the zero-cross sample without depending on the level of the current sample point. Based on variably controlling the tap coefficient of the transversal filter, the control is performed to minimize the error signal that deviates from the partial response waveform equalization characteristics. Can be expanded in comparison with the conventional waveform equalization circuit having a fixed tap coefficient. In addition, according to the present invention, since the probability of erroneous determination is low as compared with the conventional waveform equalization circuit with a fixed tap coefficient, the convergence time can be shortened as compared with the conventional case.
[0138]
According to the present invention, the even filtering unit and the odd filtering unit include n tap coefficients (n is an integer of 2 or more) output from the first tap coefficient generation unit, and the second tap coefficient generation unit. The n coefficients from the coefficient averaging means for outputting n coefficients obtained by averaging the n tap coefficients to be output with the corresponding tap coefficients are input as the first and second tap coefficients. Therefore, even when valid data is biased to even-numbered reproduction data or odd-numbered reproduction data, a correct tap coefficient can be generated.
[0139]
Furthermore, according to the present invention, it is possible to cope with any run-length limit code of the minimum inversion intervals 2 and 3, and since it can be constituted by a digital circuit, it is more reliable than an analog circuit and the circuit scale is almost increased. It can be configured without doing.
[0140]
In addition, according to the present invention, the resampling data and the 0 point information extracted from the resampling DPLL are once written in a memory element such as a FIFO at the timing of the bit clock in synchronization with the system clock, and then the bit clock is generated. By reading out at the timing of a new clock with a low frequency such as the average value of the frequency to be input and inputting it to the adaptive equalization circuit, the adaptive equalization circuit can perform an arithmetic operation based on the above new clock. The frequency is lower than that of a circuit that does not use a memory element, and the calculation time can be afforded. As a result, the number of latches is reduced, the circuit delay and the circuit scale are reduced, and as a result, the speed limit by the IC device is reduced. The problem can be solved, and the cost and power consumption can be reduced.
[0141]
Furthermore, according to the present invention, it is possible to realize high-speed data rate processing by paying attention to the fact that the signal band of the input signal is narrow and lowering the system clock frequency to half that of the prior art.
[0142]
In addition, according to the present invention, the system clock is lowered by parallel processing of the decoding device, and the calculation margin for the system clock of the decoding device is improved, so that the speed limitation problem due to the IC device can be solved, and the cost and consumption are also reduced. Electric power can be reduced.
[Brief description of the drawings]
FIG. 1 is a block diagram of a first embodiment of a playback apparatus according to the present invention.
FIG. 2 is a block diagram of an example of a resampling DPLL of a main part of the device of the present invention.
FIG. 3 is a diagram showing a data form of a main part of the device of the present invention.
FIG. 4 is a block diagram of a first embodiment of an adaptive equalization circuit as a main part of the device of the present invention;
5 is a circuit diagram of an embodiment of a tap delay circuit in FIG. 4. FIG.
6 is a circuit diagram of an example of an LM in FIG.
7 is a circuit diagram of an embodiment of a provisional discrimination circuit in FIG. 4. FIG.
FIG. 8 is an explanatory diagram of partial response characteristics.
FIG. 9 is a diagram illustrating the relationship among the characteristics of PR (a, b, b, a), the run length restriction rule RLL mode, and the provisional determination value of the provisional discriminator.
10 is a flowchart for explaining the operation of an example of a temporary discriminator in FIG. 7;
FIG. 11 is a diagram (part 1) illustrating an example of a waveform before and after waveform equalization according to the present invention.
FIG. 12 is a diagram (part 2) illustrating a waveform example before and after waveform equalization according to the present invention.
FIG. 13 is a diagram (No. 3) illustrating a waveform example before and after waveform equalization according to the present invention.
FIG. 14 is a diagram showing an example of an eye pattern of an output signal of an adaptive equalization circuit in a playback apparatus according to the present invention.
FIG. 15 is a block diagram of a second embodiment of the adaptive equalization circuit of the main part of the device of the present invention;
FIG. 16 is a block diagram of a second embodiment of the apparatus of the present invention.
FIG. 17 is a block diagram of a third embodiment of an adaptive equalization circuit as a main part of the device of the present invention;
FIG. 18 is a block diagram of a fourth embodiment of the adaptive equalization circuit of the main part of the device of the present invention;
FIG. 19 is a block diagram of a third embodiment of the apparatus of the present invention.
FIG. 20 is a block diagram of a fourth embodiment of the apparatus of the present invention.
FIG. 21 is a block diagram of a fifth embodiment of the apparatus of the present invention.
FIG. 22 is a block diagram of a sixth embodiment of the device of the present invention.
FIG. 23 is a block diagram of a seventh embodiment of the apparatus of the present invention.
FIG. 24 is a block diagram of an eighth embodiment of the apparatus of the present invention.
FIG. 25 is a block diagram of an example of an adaptive equalization circuit of a main part of the device of the present invention.
FIG. 26 is a block diagram of another example of the adaptive equalization circuit of the main part of the device of the present invention.
27 is a flowchart for explaining the operation of another example of the temporary discriminator in FIG. 3;
FIG. 28 is a block diagram of a fifth embodiment of the adaptive equalization circuit of the main part of the apparatus of the present invention;
29 is a block diagram of an example of an error selection circuit in FIG. 28. FIG.
FIG. 30 is a diagram illustrating a state of sample points and an extracted error component when PR is equalized correctly.
FIG. 31 is a diagram illustrating a state of sample points when PR is not correctly equalized and error components extracted without an error selection circuit;
32 is a diagram showing the state of sample points when the PR is not correctly equalized and error components extracted by the error selection circuit of FIG.
FIG. 33 is a block diagram of a sixth embodiment of the adaptive equalization circuit of the main part of the apparatus of the present invention;
34 is a block diagram of an example of an error selection circuit in FIG. 33. FIG.
FIG. 35 is a flowchart for explaining the operation of another example of the main part of the provisional determination circuit.
FIG. 36 is a flowchart for explaining the operation of still another example of the main part of the provisional determination circuit.
FIG. 37 is a block diagram illustrating an example of a conventional playback device.
FIG. 38 is a block diagram of an embodiment of a decoding circuit according to the present invention.
FIG. 39 is a diagram illustrating an example of each of the branch metric calculation circuits 381a and 381b.
FIG. 40 is a diagram illustrating an example of a path metric calculation 382. FIG.
FIG. 41 is a diagram showing another embodiment of the path metric calculation 382 taking account of the offset calculation.
FIG. 42 is a diagram illustrating an example of an offset calculation block.
FIG. 43 is a bell showing a specific embodiment of the path memory arithmetic circuit 383;
FIG. 44 is a diagram illustrating a specific example of the pass module.
FIG. 45 is a block diagram of a ninth embodiment of the apparatus of the present invention.
FIG. 46 is a block diagram of a tenth embodiment of the apparatus of the present invention.
[Explanation of symbols]
15 Optical disc
17 LPF
18, 43, 44 A / D converter
19 Resampling DPLL
20, 20a, 20b, 30, 30a, 30b, 35, 50, 60 Adaptive equalization circuit
21a, 21b Transversal filter
22a, 22b Multiplier and low-pass filter (LPF)
23 Tap delay circuit
23a Main part of tap delay circuit
24a, 24b provisional discrimination circuit
25a, 25b INV
26a, 26b, 26c, 26d, 26e Average calculator
27a, 27b, 27c, 27d, 27e Average calculator
28a, 28b, 29a, 29b Error selection circuit
31 Zero detector
32 Phase-locked loop (PLL) circuit
33 IPF
34 Delay and zero detector
38 Decoding circuit
39 ECC circuit
41 Interpolator
42, 55 Phase comparator
43 Loop filter
44 Timing generator
51, 56, 57 Zero-cross detection / phase comparator
53 Voltage Controlled Oscillator (VCO)
110a, 110b provisional discriminator
111a, 111b subtractor
231,232 Latch circuit
233 OR circuit
283 selection circuit
284, 291 Switch circuit
285, 292 0 generator
300 Resampling DPLL
301 equalization circuit
302 IPF
303 Equalizer
304 IPF

Claims (10)

In a playback device that plays back a run-length limited code recorded on a recording medium, decodes the playback signal after performing partial response equalization using a transversal filter,
Sampling output means for sampling the reproduction signal, or a signal obtained by further resampling interpolation of the sampling signal, and dividing the even-numbered reproduction data signal and the odd-number reproduction data signal and outputting them in parallel;
An even filtering means for filtering the even-numbered reproduction data signal based on a first tap coefficient and outputting it as a first waveform-equalized reproduction signal;
An odd filtering means for filtering the odd-numbered reproduction data signal based on a second tap coefficient, and outputting the second waveform equalized reproduction signal;
Calculating a temporary decision value of the first waveform equalization after regeneration signal, and the even temporary determination circuit for outputting a difference value between the tentative determination value and the first waveform equalization after regeneration signal as the even error signal,
Calculating a temporary decision value of the second waveform equalization after regeneration signal, and an odd provisional determination circuit for outputting a difference value between the tentative determination value and the second waveform equalization after regeneration signal as odd error signal,
Based on the even error signal and the even-numbered reproduced data signal from the even temporary determining circuit, first the even error signal the first tap coefficient of the even filtering means is generated by the variable so as to minimize 1 tap coefficient generating means;
Based on the odd error signal and the odd reproduced data signal from the odd provisional determination circuit, first the odd-error signal the second tap coefficient of the odd filtering means is generated by the variable so as to minimize Two tap coefficient generation means;
That it has a decoding means for decoding and said second waveform equalization after reproduction signal outputted from said first waveform equalization after the reproduction signal and the odd filtering means being outputted from the even number filtering means A playback device. And the tap coefficients output n number of the previous SL first tap coefficient generating means (n is an integer of 2 or more), and n tap coefficients output by the second tap coefficient generating means, corresponding tap coefficients Coefficient averaging means for outputting n coefficients averaged with each other ,
2. The reproducing apparatus according to claim 1, wherein the even filtering means and the odd filtering means receive n coefficients from the coefficient averaging means as the first and second tap coefficients. The even tentative discrimination circuit and the odd tentative discrimination circuit detect whether a zero cross point is detected and output 0 point information based on both the even reproduction data signal and the odd reproduction data signal, respectively. And a delay circuit that outputs at least three consecutive 0-point information among the 0-point information extracted in synchronization with the bit clock from the detection means,
PR mode signal indicating the type of partial response equalization, RLL mode signal indicating the type of run length limit code of the reproduction signal, a plurality of the 0 point information from the delay circuit, the first waveform, etc. receiving a reproduction signal or said second waveform equalization after reproduction signal after as input, and state transitions defined by the PR mode signal and the RLL mode signal, based on the pattern of the plurality of 0-point information, the 3. The reproduction apparatus according to claim 1, further comprising temporary determination means for calculating temporary determination values of the first or second waveform-equalized reproduction signal. The even-numbered temporary determination circuit and the odd-numbered temporary determination circuit each detect whether the zero cross point is detected based on the first and second waveform equalized reproduction signals and output 0 point information; and A delay circuit that outputs at least three consecutive 0-point information among the 0-point information extracted in synchronization with the bit clock from the detection means;
PR mode signal indicating the type of partial response equalization, RLL mode signal indicating the type of run length limit code of the reproduction signal, a plurality of the 0 point information from the delay circuit, the first waveform, etc. receiving a reproduction signal or said second waveform equalization after reproduction signal after as input, and state transitions defined by the PR mode signal and the RLL mode signal, based on the pattern of the plurality of 0-point information, the 3. The reproduction apparatus according to claim 1, further comprising temporary determination means for calculating temporary determination values of the first or second waveform-equalized reproduction signal. The temporary determination means, said calculating a temporary decision value of the PR mode signal and at least one said first or said second waveform equalizing reproduced signal as a fixed value of the RLL mode signal, the and the tentative determination value a 5. The reproducing apparatus according to claim 3 or 4, wherein a difference value with respect to one or the second waveform-equalized reproduced signal is output as an error signal. Said detection means, prior SL receives a digital signal obtained by sampling an input signal to run-length limited code by the system clock, the even-numbered reproduction data signal and the odd-numbered play resampled at a desired bit rate A data signal is generated and supplied to the even filtering means and the odd filtering means, and is constituted by a resampling DPLL that detects whether or not it is a zero cross point and outputs the zero point information. Item 6. The playback device according to any one of Items 3 to 5. When the partial response equalization characteristic designated by the PR mode signal is expressed by PR (a, b, b, a), the temporary discrimination means is the median value in the three consecutive 0-point information and its front and back When the values of both 0-point information do not indicate zero cross points (a + b) ** G (where G is a predetermined gain, * is after offset so that the median value (a + b) is 0) The value P is calculated by the following equation). Only the values of the 0 point information both before and after the median value in the three 0 point information indicate the zero cross point, and the RLL mode signal is minimum time inversion interval is 2 calculates the value P by (b-a) * × G becomes equation, 0 point information both before and after the central value in the three 0-point information of the recording signal shown Only the zero cross point indicates the zero cross point, and when the minimum inversion interval of the recording signal indicated by the RLL mode signal is not 2, or before or after the median value in the three 0 point information When only the information value indicates the zero cross point, the value P is calculated by the formula b ** G, and when the median value in the three 0 point information indicates the zero cross point, the provisional discrimination value is set to 0. And the calculated value P depends on the polarity of the reproduced signal after equalization of the first or second waveform when the median 0 point information of the continuous three 0 point information is obtained. 6. The reproducing apparatus according to claim 3, wherein the reproducing apparatus calculates the provisional discrimination value of the polarity. When the partial response equalization characteristic designated by the PR mode signal is expressed by PR (a, b, b, a), the temporary determination means is the median value of the five consecutive 0-point information and its front and back When both zero point information values do not indicate the zero cross point (a + b) ** G (where G is a predetermined gain, * is after offset so that the median value (a + b) becomes zero) The value P is calculated by the following equation). Only the values of the 0 point information both before and after the median value in the five 0 point information indicate zero cross points, and the RLL mode signal is minimum time inversion interval is 2 calculates the value P by (b-a) * × G becomes equation, 0-point information for both before and after the central value in the five 0-point information of the recording signal shown When only the value indicates the zero cross point and the minimum inversion interval of the recording signal indicated by the RLL mode signal is not 2, or before or after the median value in the five 0 point information When only the value of 0 indicates a zero-cross point, or when only the values of the first and fourth 0-point information in the five 0-point information indicate the zero-cross point, or 2 in the five 0-point information When only the values of the 0th and 5th 0-point information indicate the zero cross point, the value P is calculated by the formula b ** × G, and the values of the 5 0-point information do not apply to any of the above the value P calculated as 0 when the calculated the value P, the first when the 0-point information of the median of the five 0-point information which the successive obtained Reproducing apparatus of according any of claim 3 to 5, characterized in that calculated as the temporary determination value of polarity corresponding to the polarity of the second waveform equalization after regeneration signal. In a decoding device for reproducing a run-length limited code recorded on a recording medium and decoding a digital signal obtained by performing partial response equalization on the reproduced signal using a transversal filter ,
Sampling output means for dividing the digital signal into even-numbered data signals and odd-numbered data signals, or interpolating and outputting in parallel;
And even number decoding means for the even-numbered data signal and the based on the odd-numbered data signal by decoding the even-numbered data, and outputs the even-numbered decoded data,
Wherein decoding the odd-numbered data based on the even-numbered data signal and the odd-numbered data signal, and a odd number decoding means for outputting the odd-numbered decoded data,
The even decoding means or the odd decoding means is:
Enter the even-numbered data signal, and the even branch metric calculating means for outputting an even branch metric operation result,
Odd branch metric calculation means for receiving the odd data signal and outputting an odd branch metric calculation result;
Calculating the second path metric by adding the even branch metric calculation result to the first path metric, and outputting an even path memory control signal based on the comparison / selection result generated in the process;
The odd path metric operation result is added to the second path metric to calculate a first path metric which is delayed by one data unit, and the odd path memory control based on the comparison / selection result generated in the process. Path metric calculation means for outputting a signal;
The even path memory control signal and inputs the odd path memory control signal, decoding apparatus characterized by having a path memory operation means for outputting even-numbered decoded data and odd decoded data. An even-numbered branch metric calculation means for receiving the reproduced signal after the first waveform equalization and outputting an even-numbered branch metric calculation result;
Odd branch metric calculation means for receiving the second waveform equalized reproduction signal as input and outputting an odd branch metric calculation result;
The second branch metric is calculated by adding the even branch metric calculation result to the first path metric, and an even path memory control signal based on the comparison / selection result generated in the process is output. calculates a calculation result obtained by delaying said second added and path metric 1 data unit of a first path metric, it outputs the odd path memory control signal based on the comparison and selection result generated in the process Path metric calculation means to
The even path memory control signals and as input the odd path memory control signals, according to claim 1 to 8, characterized in that it has a path memory operation means for outputting the even-numbered decoded data and odd decoded data according to any one claim Playback device.

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