JP4443966B2 - Crossbar switch, operation control method thereof, and operation control program - Google Patents

Description

  The present invention relates to a crossbar switch mounted on, for example, a computer for image processing and related products.

There is a crossbar switch as one of system components that realizes node coupling in a multiprocessor with few restrictions.
The crossbar switch is generally configured by a two-dimensional grid-like parallel bus wiring in which a switch mechanism is arranged at each of a plurality of intersections (referred to as “cross points”) at which data paths intersect.
During operation, the switch mechanism controls the connection / disconnection of a plurality of crosspoints, whereby an input node line (bus wiring of an input node having a plurality of crosspoints, the same applies hereinafter) and an output node line (a plurality of crosspoints It is possible to selectively switch a plurality of data paths formed by a combination of cross points of output node bus wirings where cross points exist (hereinafter the same).
The crossbar switch is excellent in non-blocking property for preventing collision between data and has advantages such as relatively simple structure and control, and is used in many data processing apparatuses.

It is well known that a conventional crossbar switch requires a switch mechanism that is square times the number of nodes because of its structure.
In parallel bus wiring, additional circuit elements such as an arbiter (arbiter) and input buffer must be provided on each bus in order to avoid problems such as output line competition. It is difficult.
For example, in a crossbar switch configured to switch 256 to 1024 nodes, assuming that the number of cross points is 64 kilopoints to 1 megapoint and the bus width of the parallel bus is 32 bits wide, the maximum number of switches is 32. It is very difficult to configure and mount such a large-scale one in a small size with the current process rules.
In addition, the conventional crossbar switch configuration not only complicates the switch control when data path exchange processing is performed as the number of switches increases, but also dramatically increases the number of wires for switch control. End up.

  The present invention has been made to solve the above-described problems. Even when the number of switches is increased, the number of wires is not increased, and the switch control when performing the data path exchange process is performed. It is an object of the present invention to provide a crossbar switch and related products that are not complicated.

In the crossbar switch provided by the present invention, a node controller is provided in each of a plurality of cascade-connected nodes, and each node controller directly or indirectly indicates a relative position where the target node controller exists from the previous node. To determine whether the input address information represents a specific value, and to output data to a predetermined data output line when it is determined that the address information represents a specific value. And a switch for generating new address information obtained by changing the input address information in accordance with a predetermined rule, and an output interface for outputting the new address information to a subsequent node.
The “predetermined rule” means, for example, that the value represented by the address information is approximated to a specific value by a certain range each time a node passes, and changes to a value that does not make sense on the node line when the specific value is reached. For example.
According to the crossbar switch configured as described above, only by inputting address information, the corresponding node controller autonomously outputs data to the data output line.

For the address information, for example, circular numerical data can be used.
In this case, the output interface generates the new address information by increasing or decreasing the numerical data in the same change direction by a predetermined value.
By using numerical data, it becomes easy to determine whether the address information represents a specific value.
The address information may be serial data including a start bit and an end bit.
By using serial data, data lines can be saved, and by including a start bit and an end bit, there is an advantage that it is easy to specify numerical data.

A crossbar switch having a plurality of node lines each including a plurality of stages of nodes can also be used.
In this case, the node controller on each node line may operate asynchronously with the node controllers on other node lines, and at least operates at the same clock timing as the node controllers on other node lines operating in parallel. You may make it do.
In the former case, there is an advantage that the switch control is simplified, and in the latter case, there is an advantage that there is no difference in delay of data propagation between nodes.

Each of the plurality of nodes has a one-to-one correspondence with an output address of a predetermined data memory, and the switch of each node controller operates the data through the output address associated with the node when operating. Data output from the memory may be output to the data output line.
In this way, the desired data can be output from the data memory simply by inputting the address information.

In a crossbar switch having a plurality of node lines each including a plurality of nodes, and a node controller on each node line operating at least at the same clock timing as a node controller on another node line operating in parallel, Each node controller on each node line receives data from the previous node and outputs the data to the subsequent node of another node line, and the address information from the previous node and the new node. And a second path for outputting correct address information to a subsequent node of the same node line.
In the crossbar switch having such a configuration, the number of switchable data paths can be increased.

In the crossbar switch in which the first path and the second path are set, each node controller is arranged in a matrix matrix on a plurality of node lines, and the second path is arranged in the column direction of each node line. The first path may be set between the output end of the previous node controller and the input end of the node controller existing in a different column in the next row of the node controller. .
Thus, by arranging the node controllers in a matrix matrix, the structure of the crossbar switch can be standardized and multi-stage connection is facilitated.

  In the above crossbar switch in which each node controller is arranged in a matrix matrix, the first path and the second path in each node controller are set to have the same or substantially the same node length, thereby providing a multistage connection. In this case, the data delay amount can be reduced.

All the node controllers arranged at least in the same row direction may operate according to clock signals that define the same operation timing.
In this way, even when the node lines of each column are operated asynchronously, data can be output simultaneously from the respective output terminals.

The first path is set, for example, between the output end of the previous node controller and the input end of the node controller existing in the next row of the node controller and in the adjacent column.
Alternatively, for example, a part or all of the first path is a node controller that exists at the output end of the previous node controller and the next row of the node controller and at a position separated by a plurality of columns from the node controller. Is set between the input terminal and the input terminal.
In this case, the first path for the node controller located at the extreme end in the column direction is between the output end of the node controller and the input end of the node controller present at the adjacent position in the next row. Is set.

In another form, the crossbar switch is provided with address information generating means at each input end of the plurality of node lines, and the address information generating means identifies the line on which the address information generating means itself is provided. And a second line for identifying a node line to which data output from a switch provided at the last node of the line provided with the address information generating means is input. The address information is generated based on the identification data.
By this address information generating means, it becomes possible to designate an arbitrary node line and output data.

The crossbar switch of the present invention can be housed in a package that can be mounted on a computer.
At this time, an interface component for connecting a first device holding data input to the input terminals is provided at the input terminals of the plurality of node lines, and each node is provided at an output terminal of the plurality of node lines. By providing an interface component for connecting the second device having the operation pipeline corresponding to the line one-to-one, the connection with these devices is facilitated.
Further, by providing interface parts for connecting a plurality of node lines of other crossbar switches having the same configuration at the input ends and / or output ends of the plurality of node lines, it is easy to expand the scale after the fact. become.

The present invention also provides a method for controlling the operation of the crossbar switch.
This method is a method of controlling the operation of a crossbar switch including a plurality of nodes connected in cascade, a plurality of node lines through which input data flows, and a node controller arranged in each node. The device for controlling the crossbar switch generates address information from identification information of a node line for outputting data and information indicating a relative position of a node controller to be operated, and this address information is used as the first stage of the target node line. A step of inputting to the node, and a node controller existing in each node of the node line to which the address information is input determines whether the input address information represents a specific value, and determines that the specific value represents the specific value When this happens, the data on the node line is output and the input Les information generates new address information has been changed by a predetermined value amount, an operation control method of the crossbar switch and a step of outputting the new address information to the subsequent node.
According to this method, only by inputting address information, the corresponding node controller autonomously outputs data, so that the control of the crossbar switch can be easily performed for each node line.

The present invention further provides a computer program for controlling the operation of the crossbar switch in cooperation with computer hardware resources.
This program includes a computer comprising a plurality of nodes connected in cascade, a plurality of node lines through which input data flows, and a crossbar switch in which a node controller is provided in each node. A crossbar switch operation control program for operating each node controller as follows.
(1) Input address information for directly or indirectly specifying the relative position where the target node controller exists,
(2) It is determined whether or not the input address information represents a specific value. When it is determined that the input address information represents a specific value, the data on the node line is output,
(3) New address information is generated by changing the input address information by a predetermined value, and the new address information is output to a subsequent node.

  As is apparent from the above description, according to the present invention, even when the number of switches is increased, the number of wires is not increased, and the switch control when performing data path exchange processing is complicated. In addition, a small and low cost crossbar switch can be provided. Further, according to the present invention, it is possible to provide a crossbar switch that can be applied to a multistage pipeline.

<First Embodiment>
The crossbar switch of the present invention can be applied to data transfer control between a memory and a processor in a drawing apparatus that processes a large amount of drawing data, for example.
Hereinafter, an embodiment in this case will be described.
First, a drawing apparatus to which the present invention is applied will be described.
FIG. 1 is a block diagram of the main part of the drawing apparatus.
The drawing apparatus includes a buffer (memory buffer) 1 as an example of a semiconductor device, a pixel pipeline processor 2 having a serial operation pipeline, a buffer 1 and a pixel pipeline in order to secure data necessary for drawing processing. And a crossbar switch 3 connected to the processor 2 via an interface component.
The buffer 1 is a data memory in which the above data input to the crossbar switch is stored. In this embodiment, as an example, the texture and data such as CLUT (Color Look Up Table) for generating the overall color and pattern on the polygon are stored by mapping.
The CLUT includes three primary color tables of R (red), G (green), and B (blue), and a table of α values. The R, G, and B primary color tables are used to determine the color of each pixel in the texture, and the α value determines the proportion of image blending (α blending) for mapping the texture for each pixel. This is a coefficient value for representing translucency. An index for extracting R, G, B3 primary color values from the CLUT (a value for designating the table number of the CLUT) is set for each pixel represented by the XY coordinates of the texturer.

The pixel pipeline processor 2 reads data from the buffer 1 and performs texture mapping, Z coordinate comparison, pixel value calculation, and the like by a pipeline method.
The pixel pipeline processor 2 also performs processing for extracting the edge of the luminance of the image, processing for setting R, G, B3 primary color data from the CLUT according to the texture index and setting the color of each pixel, An α blend process using an α value (gradated α value) extracted from the CLUT with the byte value of the pixel as an index is also performed. Furthermore, processing such as scissoring, dithering, and color clamping is performed.
Scissoring is a process that removes data that protrudes from the screen, dithering is a process that involves intricately arranging colors to represent many colors with a small number of colors, and color clamp is a process that calculates color when calculating colors. This is a process of limiting the value so that it does not exceed 255 or become smaller than 0.

  The data obtained by performing the above-described processes in the pixel pipeline processor 2 is stored in a frame buffer (not shown), converted into frame data (two-dimensional image data) drawn on a two-dimensional monitor screen, Frame data is read from the frame buffer, output from the output terminal, and sent to the two-dimensional monitor device.

[Crossbar switch]
Next, the configuration and operation of the crossbar switch 3 will be described with reference to FIGS.
The crossbar switch 3 is housed in a package that can be mounted on a computer for realizing a drawing apparatus, and includes serial bus wirings 4 arranged in a grid as shown in FIG. The operation of the crossbar switch 3 is controlled by a controller (not shown) of the drawing apparatus during the drawing process in the drawing apparatus. This controller has functions for drawing processing and operation control of the crossbar switch 3 when the processor executes a predetermined program.
At the cross points that are nodes where the serial bus wiring 4 intersects, the serial bus wiring on the input side of the node (hereinafter referred to as “input node line” in this embodiment) and the serial bus wiring on the output side of the node (hereinafter referred to as “node node line”). In this embodiment, a node controller, for example, a switch circuit 5 is provided for switching connection / disconnection of the output node line.
Each of the input node lines is connected to the output address of the buffer 1 in a one-to-one correspondence via the interface component, and the output node line is connected to the pixel pipeline processor 2 via the interface component. Yes.

The switch circuit 5 is adjusted in advance by arbitration so that the relative position on the output node line can be distinguished from other switch circuits.
In this specification, information representing the relative position of each individual switch circuit 5 is referred to as an “address” of the switch circuit 5 for convenience. In addition, address information that is specified to directly or indirectly specify the address of one switch circuit 5 for connecting the input node line and the output node line is referred to as a “designated address”.
The address used in this embodiment is a bit (numerical data) representing the number of nodes on the output node line, that is, a numerical value corresponding to the number of cross points, and crosses in the direction from the address input end of the output node line to the data output end. Each time a point is passed, the value is decreased by, for example, 1 bit, and when a specific value, for example, zero value is reached, the maximum value, for example, the number of cross points is 8, 3, 2, 1, 0, 7 , 6,5,4.
Note that, instead of bits representing numerical values, cyclic character string data such as A, B, C,... Z, A,.
This character string data changes by one character each time a cross point is passed, and returns to the initial value when it reaches a specific value (value represented by the character).

An example of the address will be described with reference to FIG.
As shown in FIG. 5, when 256 input node lines are provided in order to reach 256-bit data to the output end of the output node line, the address has 256 kinds of circularity from “255” to “0”. It becomes the numerical data. That is, the address is decreased bit by bit, the address of the next stage of “0” is “255”, and the address of the next stage is “254”.

An address selection circuit 6 is connected to the address input terminal of the output node line.
The address selection circuit 6 inputs a designated address.
Each node line is provided in parallel with a clock line 7a for transmitting a common clock signal output from a clock signal source (not shown) of the controller.
The clock signal on the clock line 7a is configured to pass through the repeater 8 like each node line. Accordingly, each switch circuit 5 refers to the clock signal of the clock line 7a and starts operation at the same timing as the other switch circuits, thereby reducing the delay difference of data propagating between the nodes (switch circuits). Can be made.
Further, it is not necessary to consider the propagation delay (skew) between nodes, and the insertion restriction of the repeater 8 and the like can be relaxed.

A parallel / serial conversion circuit 9 for serial conversion of parallel data read from the buffer 1 is connected between the input end of the crossbar switch 3 and the interface component, and between the output end and the interface component, A serial / parallel conversion circuit 10 for converting serial data into parallel data is provided. The parallel / serial conversion circuit 9 is configured to be able to adjust the operation timing with reference to the clock signal of the clock line 7b.
The clock line 7b preferably transmits a common clock signal with the clock line 7a, but may transmit a different clock signal.

  If the buffer 1 and the pixel pipeline processor 2 are configured to input / output serial data, the parallel / serial conversion circuit 9 and the serial / parallel conversion circuit 10 are not necessary. In particular, when the pixel pipeline processor 2 includes a serial calculation pipeline, the input ends of the serial calculation pipeline and the output ends of the individual serial buses of the crossbar switch 3 need only correspond one-to-one. Since both can be wired, wiring work becomes easier.

The switch circuit 5 includes an input interface that receives a designated address sent from a preceding node (switch circuit) of the output node line, and an input node line and an output node when the received designated address represents a specific value (for example, “0”). By switching the data path by connecting the line, it is possible to output the data of the input node line to the output node line, and the received designated address is set to a single rule while maintaining a predetermined rule, for example, cyclic order. It has a function of generating a new designated address by decrementing by the crossing point passage and an output interface for sending out this new designated address to the subsequent node. Both the switching of the data path and the generation of a new designated address are autonomously performed in the switch circuit 5.
In addition, the reception of the specified address, the switching of the data path, the generation of a new specified address, and the output of the new specified address can be performed by the cooperation of the logic circuit and the software, but more simply Can be performed only by a logic circuit as shown in FIG.

The switch circuit 5 illustrated in FIG. 3 holds a decrement circuit 11 that decrements serial carry bits input through a plurality of cascaded nodes one bit at a time, such as an output node line, and holds all address bits. An OR circuit 12, an AND circuit 13 that outputs a select signal when the address bit is “0”, and a connection switching circuit 14 that switches connection / disconnection between the input node line and the output node line according to the output level of the select signal. It has.
Only by detecting that the input address bit is “0”, the switch circuit 5 can recognize that it has been designated, so that the designation form of the target switch circuit 5 is greatly simplified. There are advantages.

In the crossbar switch 3 of this embodiment, the clock line 7a is wired in parallel to the input node line and the output node line, and each switch circuit 5 refers to a common clock signal propagating through the clock line 7a, and the node (switch circuit Reducing the delay difference of the data propagating between them is a means for easily solving the above problem.
Such a configuration makes it easy to establish data synchronization in units of nodes, eliminates the need to consider propagation delay (skew) between nodes, and relaxes insertion restrictions of the repeater 8 and the like. Can do.

[Crossbar switch operation control method]
Next, an operation control method of the crossbar switch 3 when data is transferred from the buffer 1 to the pixel pipeline processor 2 will be described.
This method is basically performed by the controller of the drawing apparatus described above, but may be performed by the pixel pipeline processor 2 under the control of the controller, for example.
The outline of this operation control method is as follows.
That is, the controller inputs the specified address as serial data from the input end of any output node line.
This designated address is numerical data representing the number of the switch circuit from the input end of the output node line of the target switch circuit 5. In response to the input of the specified address, each switch circuit 5 of the output node line autonomously determines whether the input specified address is “0” or not, and when the zero value is expressed, the data on the input node line is received. Then, it is transferred to the subsequent node of the output node line. Further, the input designated address is decremented by “1” to generate a new designated address, and this new designated address is output as serial data to the subsequent node.

FIG. 4 is a processing procedure diagram of the switch circuit 5 when the above-described operation control is performed by the controller.
<Step S1>
The controller inputs the designated address to the address selection circuit 6 of the output node line having the target switch circuit 5, and the address selection circuit 6 initializes the designated address and inputs it to the output node line bit by bit.

<Step S2>
The decrement circuit 11 decrements the least significant bit (address bit received first) of the address bit received from the previous node and determines a value of a new designated address (address bit) to be output to the next node.
At the time of decrementing, if the address bit is “0”, lowering (carrying down) occurs, so the next address bit is also decremented.
In this process, the OR circuit 12 holds the address bits from the previous node in a predetermined memory area.

<Step S3>
The logical product circuit 13 determines whether or not the output of the address bits has been completed.
If completed, the process proceeds to step S4. If not completed, the process returns to step S1.

<Step S4>
The logical product circuit 13 determines whether or not the sum of the address bits is “0”.
If the sum of the address bits is “0”, the process proceeds to step S5.
<Step S5>
The AND circuit 13 of the switch circuit 5 asserts the select signal.
Then, the connection switching circuit 14 connects the input node line and the output node line according to the select signal.
FIG. 5 shows this state.
Thereby, data transfer from the input node line to the output node line is performed.
When the data transfer is completed, a series of control processing is completed.

Data control from the buffer 1 to the pixel pipeline processor 2 is appropriately performed when all the switch circuits 5 autonomously execute the control processing as described above.
By adopting such an operation control method, it is possible to share a control line for crosspoint switching (data transfer) and a data input line, and the number of bus lines can be greatly reduced.

As described above, in the crossbar switch 3 of this embodiment, the input node line and the output node line are configured by the serial bus, and the designated address is “0” simply by inputting the designated address to the output node line. Since the switch circuit 5 autonomously performs cross-point switching (data transfer), the number of wires can be remarkably reduced as compared with a parallel type crossbar switch, and downsizing can be realized. .
Furthermore, it is possible to suppress a decrease in performance due to serialization of the bus.

In addition, each input node line transmits serial data independently of other input node lines, and the output node line also transmits a specified address independently of other output node lines. Transmission is possible, and control is not complicated even when the number of node lines, nodes, and cross points is large.
Since each switch circuit 5 can operate at least according to the same clock signal as the clock signal that determines the operation timing of the switch circuit 5 on other node lines that operate in parallel, the difference in propagation delay between data nodes can be reduced. can do.

  In the crossbar switch 3 of the present embodiment, crosspoint switching is performed simply by inputting a designated address to a desired output node line, so that external operation control relating to data path switching is not required, and control There is an advantage that the operation itself is simplified.

Although the above description is an example in which the controller of the drawing apparatus performs the operation control of the crossbar switch 3 in an initiative, the operation control of the crossbar switch is equipped with a crossbar switch, but the drawing apparatus is It can also be realized by cooperation between an independently existing computer and a control processing program recorded on a computer-readable recording medium.
That is, by mounting a recording medium on which an operation control program is recorded in a computer, loading the operation control program into the storage unit of the computer, and the computer processor reads and executes the operation control program, Operation control is performed according to the procedure shown in FIG. Examples of the recording medium include a computer-readable recording medium that can record a program such as a semiconductor memory, a magnetic disk, an optical disk, a magneto-optical disk, and a magnetic tape.

<Second Embodiment>
Next, an embodiment of a crossbar switch applicable to a multistage pipeline will be described.
The crossbar switch of this embodiment has a plurality of node lines for transmitting serial data in the direction from the input end to the output end, and a plurality of node controllers are arranged at predetermined node intervals on each of these node lines. Are inserted and connected one by one.
Note that the node lines referred to in this embodiment are conceptual ones provided for the sake of convenience in order to match the description with the first embodiment.
Also in this embodiment, as in the case of the first embodiment, the node controller is referred to as a “switch circuit”.

FIG. 6 is a view for explaining characteristic components of the crossbar switch according to this embodiment and an outline of the operation thereof.
The crossbar switch according to this embodiment includes an address initialization unit 20 that is an example of an address information generation unit, and a path switching unit 21 that switches data paths.
Here, an example of a crossbar switch in which switch circuits (shown by rectangles in FIG. 6) in the path switching unit 21 are arranged in an 8 × 8 matrix matrix will be described.

The crossbar switch of this embodiment is different from the crossbar switch 3 of the first embodiment in that a first path and a second path are set between cascaded nodes, and the first path is set to the second path. And the number of nodes through which output data passes.
Note that the diagonal here means that in a crossbar switch in which switch circuits are arranged in a matrix matrix, when the first switch circuit is connected to the second switch circuit of the next stage by the second path, the first path is This means that the first switch circuit is connected to a second switch circuit provided in the same stage as the second switch circuit and different from the second switch circuit.
Since the switch circuits are arranged in a matrix matrix, the first path is inclined with respect to the second path. In addition, as shown in FIG. 6 and the like, the first path is not necessarily oblique to the second path, that is, not at an angle that is neither parallel nor perpendicular, but is parallel to the wiring and the second path perpendicular to the second path. You may comprise a 1st path | pass with wiring. As the switch circuit itself, the one of the crossbar switch 3 of the first embodiment can be used, but a different configuration can be used as will be described later.

As in the case of the first embodiment, the first path wired obliquely is a path that flows to the end so that data from each input end can be sent to all output ends.
This first path is set between the output end of the previous switch circuit and the input end of the switch circuit existing in a different column in the next row of the switch circuit.
In the example of FIG. 6, it exists in every other column in the next row, and the node at the extreme end of the column is between the input ends of the switch circuits existing in adjacent positions in the next row. Is set to
By setting in this way, the difference in data transmission delay can be reduced.
On the other hand, the second path is a path through which a designated address flows from the previous node, and is wired along the node line.

A point that can be accommodated in a computer-mountable package, a point that each switch circuit can be directly or indirectly specified by a designated address, for example, a point that its operation is controlled by a controller of a drawing apparatus, is described in the first embodiment. This is the same as the crossbar switch 3 of FIG.
In this embodiment, each node line is identified from other node lines by a line number that is binary identification data, and the designated address is expressed by binary address bits.
In order to simplify the description, in the following description, it is assumed that the line number and the designated address are each represented by 3 bits, but this numerical value is an example and is not intended to be limited to this example.

The address initialization unit 20 shown in FIG. 6 sets a designated address for the first-stage switch circuit for designating a target switch circuit.
As in the case of the first embodiment, the designated address is numerical data indicating, for example, which switch circuit the target switch circuit is from the first-stage switch circuit described above, and is decremented by “1” every time it passes through the node. (Decremented) to become a new designated address.
Therefore, “0” is input as the designated address to the target switch circuit from the previous-stage switch circuit. Based on this designated address, each switch circuit autonomously determines whether or not the inputted designated address is “0”. When “0” is represented, the switch circuit (a switch circuit identified by the designated address) is designated. The data on the connected first path is output from the node line on the subsequent stage side.
In the example of FIG. 6, it is shown that the designated address when data input to the line 7 is output from the output end of the line 6 is set to “001”, and this is set to the first switch circuit through the second path. Sent.

The switch circuit used in this embodiment is specifically configured as shown in FIG.
That is, the switch circuit 50 includes serial data a input from a first path input terminal INa that is an example of an input interface, serial data b that is input from a second path input terminal INb that is also an example of an input interface, The data c obtained by decrementing the serial data b by the decrement circuit 502 is selectively output by a selector 501 from a first path output terminal OUTa and a second path output terminal OUTb which are examples of an output interface.
The decrement circuit 502 is provided with a carry circuit 503 so that the logic level (“0” / “1”) of the carry bit is supplied to the input side of the decrement circuit 502 and the selector 501. .
Carry circuit 503 is reset by a control start bit described later.

Phase data output from an external controller is also input to the selector 501 and the carry circuit 503.
The phase data is used to form a crosspoint control phase and a data transfer phase, and either “0” or “1” is input.
When the phase data is “0”, the cross-point control phase when the address is input is the data transfer phase when the phase data is “1”.
As phase data, the same data is input to the selectors 501 and carry circuits 503 of all the switch circuits in each row. The transition from phase data “0” to phase data “1” is triggered by the flow of all address bits.
On the other hand, the transition from the phase data “1” to the phase data “0” is performed based on an instruction from the controller. For example, if it is necessary to change the connection relationship between the other output terminal and the input terminal while the input terminal of one node line and the output terminal of the other node line are connected through the first path, this phase data is used as the controller. To the selector 501 and carry circuit 503 of the corresponding switch circuit.

Carry circuit 503 carries carry bits when phase data is “0”, and carries carry bits when phase data is “1”.
As will be described later, the carry bit becomes important data at the time of phase switching. That is, when the phase data is “1” and the carry bit is “1”, it indicates that the designated address input in the crosspoint control phase is “0”, that is, this switch circuit is designated. .
The selector 501 performs serial data selection according to a predetermined rule.
For example, when the phase data is “0”, the data c output from the decrement circuit 502 is output from the second path output terminal OUTb.
When the phase data is “1” and the carry bit is “0”, the first path input terminal INa and the first path output terminal OUTa, the second path input terminal INb and the second path output terminal OUTb are respectively connected, and the phase data is When “1” and the carry bit is “1”, the first path input terminal INa and the first path output terminal OUTa, and the first path input terminal INa and the second path output terminal OUTb are connected to each other.
That is, when the phase data is “1”, from the output terminal OUTa of the first path of the switch circuit, always from the switch circuit (or address initialization unit) in the previous stage of the switch circuit, regardless of the value of the carry bit. The bit value input to the input terminal INa of the first path of the switch circuit is output as it is.
On the other hand, from the output terminal OUTb of the second path, when the carry bit is “0”, the bit value received by the switch circuit at the input terminal INb of the second path is when the carry bit is “1”. The bit value received by the switch circuit at the input terminal INa of the first path is output as it is.

  As described above, there is a case where it is necessary to change the connection relationship between the other output end and the input end in a state where the input end of one node line and the output end of another node line are connected through the first path. When it is necessary to change the output data only for the node line (flow the address again), when the phase data is “0”, the first path input terminal INa and the first path output terminal OUTa are connected, and the output of the decrement circuit 502 The second path input terminal 1Nb and the second path output terminal OUTb are connected.

Note that the control start bit and phase data for reset described above are supplied from the controller as an “instruction array” which is an instruction sequence.
In the following description, the node controller configured as shown in FIG. 7 is expressed as a switch circuit 50 in accordance with the first embodiment.

<Crossbar switch operation control method>
Next, a method for controlling the operation of the crossbar switch in this embodiment will be described with reference to FIGS. 6 and 8 to 25.
This method is also performed under the initiative of the controller of the drawing apparatus, but as described above, it can also be performed by the cooperation of a computer and a program that exist independently of the drawing apparatus.
Here, as a premise, there are 8 types of data (data 0 to data 7) as shown in the uppermost part of FIG. 6, and these data are assigned to the line numbers (line 0 to line 0) shown in the lowermost part of FIG. Let it be output from any node line identified by line 7). In this embodiment, data 0 to 7 are input to the lines 0 to 7, respectively, and data 4 is output from the final stage switch circuit of the path switching unit 21 of the line 0.
Similarly, data from line 1, data 1 from line 2, data 3 from line 3, data 4 from line 4, data 5 from line 5, data 7 from line 6, data from line 7 4 are respectively output from the switch circuit at the final stage.
In the following description, the line number is n (0 ≦ n ≦ 7), and for each data 0 to data 7, a line in which the data is input through the address initialization unit is described as an “input source line”. Since the line number to which the address initialization unit (AINI-1 to AINI-7) belongs and the data number input to the address initialization unit match, the line number n becomes the data number as it is.
For example, the input source line of data 5 is represented as line 5 using the data number “5” as it is.
Further, a line from which data n is output is referred to as “output destination line” of data n.
As described above, the data 4 input to the line 4 is output from each of the line 4, the line 7, and the line 0.
Therefore, the output destination lines of data 4 are line 4, line 7, and line 0.
On the other hand, since the data 2 is not output from anywhere, there is no output destination line. Further, the data output from the last-stage switch circuit of the path switching unit 21 in line n is defined as line n output data.
For example, as shown in FIG. 22 described later, the line output data in line 0, that is, the line 0 output data is data 4, and the line 1 output data is data 6.
It is assumed that cyclic addresses (numerical data) of 7, 6, 5, 4, 3, 2, 1, 0 are assigned to the switch circuits 50 of the respective node lines in descending order.

In order to designate the target switch circuit 50, the controller serially inputs a 3-bit address bit representing the line number of the input source line of the line n output data to the address initialization unit 20 of the line n. In this example, since the data number matches the line number to which the address initialization unit to which the data is input belongs, the data number of the line n output data is the number of the input source line of the line n output data. Match the line number.
Specifically, in line 0, the line 0 output data is data 4, and the input source line of this data 4 is line 4, so the address bit of line 0 is 4.
In line 1, since the output data of line 1 is data 6, the address bit of line 1 is 6.
Similarly, the address bits on lines 2, 3, 4, 5, 6, and 7 are 1, 3, 4, 5, 7, and 4, respectively.
In the present embodiment, the line n address bits determined as described above are serially input before data n is input to the address initialization unit of line n.
In the example of FIG. 6, the address bit “100” for identifying the line 4 that is the input source line of the data 4 that is the line 0 output data is input to the line 0 of the rightmost column, and then the data 0 is stored. Entered. In FIG. 6, this address bit is described as “address 4”. “Line 1 is serially inputted with an address bit“ 110 ”for identifying an input source line of data 6 that is line 1 output data.
Similarly, line 7 has an address bit “100” for identifying line 4, line 2 has an address bit “001” for identifying line 1, and line 6 has an address for identifying line 7. Bit “111”, line 3 has an address bit “011” for identifying line 3, line 5 has an address bit “101” for identifying line 5, and line 4 has a line 4 for identifying line 4. FIG. 6 shows that the address bits “100” are serially input. The address initialization unit 20 (AINI-0 to AINI-7) calculates a designated address from the line number of the line to which the address initialization unit belongs and the input address bits. In FIG. 6, the address bits are represented as “address 1” to “address 6”. The numerical value part of the address initialization units AINI-0 to AINI-7 represents the line number of the node line provided with the address initialization unit.

The first bit S of each address bit is a control start bit, and is input in synchronization with an LSB (Least Significant Bit).
When this control start bit is input to each switch circuit 50, carry circuit 503 is initialized, and selector 501 passes one address bit.
The second bit C of each address bit is a control bit and is input in synchronization with the middle data.
The third bit of each address bit is an end bit and is input in synchronization with MSB (Most Significant Bit). The switch circuit 50 in which the carry bit becomes “1” when the end bit is input is a target switch circuit for performing data transfer.

Each switch circuit of the path switching unit 21 of the crossbar switch in FIG. 6 is connected by the first path and the second path. The first path connects the m-th switch circuit of line n to the (m + 1) -th switch circuit of line (n−1) (1 ≦ m ≦ 8).
For example, in FIG. 6, the first-stage switch circuit of line 4 is connected to the second-stage switch circuit of line 3 through the first path. In line 0, the value of (n-1) is -1, but since 0≤n≤7, this value is set to 7. Therefore, line 0 is connected to line 7 through the first path. In this way, the value of n is circulated in a range of 0 to 7, 2, 1, 0, 7, 6,. Regarding m, 1 ≦ m ≦ 8, but the 8 + 1 = 9th stage means that data is output from the switch circuit in the final stage, so unlike n, m is a cyclic value. Don't be.
As will be described later, the connection form of the first path and the second path is the first path of line 0, the first path of line 1,... Line 7 as viewed from the input side of the second path of line 0. For example, it is specified by calculating the line number of the node line to which the line n output data is input and the line number of the node line to which the line n output data is output. An address can be generated.
However, in this example, since the designated address is numerical data having a cyclicity of 0 to 7, the address initialization unit 20 considers cyclicity such as 1 → 0 → 7 → 6. Perform the operation.

As described above, the transition from the phase data “0” to the phase data “1” is performed when all the address bits flow.
Therefore, in FIGS. 6 and 8 to 22, in each switch circuit of the path switching unit 21, the phase data is “0” while the address bits (3 bits in this embodiment) are flowing.
Further, since the data flows after all the address bits have flowed, the phase data is “1” when the data is flowing.
Here, as described above, when the phase data is “1”, the input from the input terminal INa of the first path is always output from the output terminal OUTa of the first path regardless of the value of the carry bit. .
Therefore, data input from the first path (input from the address initialization unit for the first-stage switch circuit) to the Z-stage switch circuit of the line n is at least from the input terminal INa of the first path. It is guaranteed that the current flows to the output terminal OUTa of one path and flows to the switch circuit of the (m + 1) th stage that is the next stage of the line (n−1) that is the next line (where 0 ≦ n ≦ 7, 1 ≦ m ≦ 8).

For example, in FIG. 6, data 4 is input to the first stage switch circuit of line 4 through the address initialization unit AINI-4.
In the first stage switch circuit of line 4, data 4 flows to the second stage switch circuit of line 3 through the first path. In the second-stage switch circuit of line 3, data 4 flows to the third-stage switch circuit of line 2 through the first path. Similarly, data 4 includes a fourth-stage switch circuit for line 1, a fifth-stage switch circuit for line 0, a sixth-stage switch circuit for line 7, a seventh-stage switch circuit for line 6, and a line 7 To the 8th stage switch circuit. Thus, the data 4 is guaranteed to flow through one switch circuit for each line through the first path.
Similarly, all of data 0-3, 5-7 flow through one switch circuit for each line.
The data flow through the first path of the crossbar switch is as described above.
Next, the second path of the crossbar switch will be described. The second path of the crossbar switch always connects switch circuits on the same line. Taking the line 4 in FIG. 6 as an example, the thick line extending in the direction of the arrow shown in the figure and going from AINI-4 to the description of “line 4” in the lower part of the figure is the second path. Therefore, when data flows through the second path, data flows through the switch circuits in the first stage, the second stage, the third stage,..., The eighth stage of the same line.

In the present embodiment, when it is desired to output the data x as the line n output data from the switch circuit at the eighth stage of the path switching unit 21 of the line n, the data x is actually output from the line n. The following processing is performed. First, the switch circuit that receives the data x from the first path is specified from the first to eighth switch circuits of the path switching unit 21 of the line n. The method of designating will be described later. In the designated switch circuit, the data x received from the first path flows to the switch circuit of the next stage on the same line through the second path. In the switch circuit of the stage subsequent to the designated switch circuit, the data x received through the second path flows to the switch circuit of the next stage through the second path.
This is repeated, and the switch circuit in the eighth stage receives the data x through the second path and outputs the received data x.
As a result, data x is actually output from the eighth-stage switch circuit as line n output data.
As shown in FIG. 7, the switch circuit is provided with two outputs, ie, a first path output terminal OUTa and a second path output terminal OUTb. Output data x only from the second path output terminal OUTb.
However, it is possible to arbitrarily determine which of the output terminals OUTa and OUTb outputs the data x to the eighth-stage switch circuit. For example, only the first path output terminal OUTa or both of the output terminals can output the data x. May be output.

Next, focusing on individual lines, the operation of the crossbar switch will be described.
In each line, eight switch circuits are arranged per line. The first-stage switch circuit of the path switching unit 21 of each line receives different data through each first path.
Hereinafter, for each stage of the line 4 in FIG. 6, which data among the data 0 to 7 is input through the first path will be described.
Data 4 is input to the first stage switch circuit of line 4 through AINI-4.
In this embodiment, the first path input terminal Ina of the first stage circuit receives data 4.
The second-stage switch circuit is connected to the first stage of the line 5 through the first path.
Therefore, the data 5 input from the address initialization unit of line 5 to the first stage switch circuit of line 5 is input to the second stage switch circuit of line 4 from the first stage of line 5 through this first path.
That is, the first pass input terminal INa in the second stage of the line 4 receives the data 5.
Similarly, the input terminal INa of the third-stage switch circuit on the line 4 receives the data 6.
Similarly, the first path input terminals Ina of the fourth, fifth, sixth, seventh, and eighth switch circuits of line 4 are data 7, data 0, data 1, and data 2, respectively. , Data 3 is received.
When attention is paid to each line in this way, the data received by the first path input terminal Ina of the switch circuit at each stage of the line n is data n at the first stage, that is, data n at the first stage, data (n + 1) at the second stage, and data at the third stage. Is the data (n + 2), the fourth row is the data (n + 3)... The mth row is the data {n + (m−1)}, the eighth row is the data (n + 7). However, since 0 ≦ n ≦ 7 and 1 ≦ m ≦ 8 as described above, the value of {(n + m−1)} is 7, 8, 1, 2, 3, 4, 5, 6, 7 , 8, 1, 2,...

Thus, in any line n, the data {n + (m−1)} is input to the m-th switch circuit.
On the contrary, when the data x is the line n output data of the line n, the relationship x = {n + (m−1)} is established, and therefore the number of stages m to which the data x is input is m = x Expressed as -n + 1.
For example, in the switch circuit of line 6 (ie, n = 6), if data 7 is line 6 output data (ie, x = 7), the stage number m = (7−6 + 1) = 2 indicates that the data 7 is input in the second stage. If the line 6 output data is data 5 (ie, x = 5), (5-6 + 1) = 0, but since the number of stages circulates in the range of 1 to 8 as described above, the 0th stage = 8th stage. As a result, the data 7 is input to the eighth stage. Actually, also in FIG. 6, this relationship is established in all lines and all stages.

Based on such a premise, in the present embodiment, when the phase data is “1”, line n output data should be output from the switch circuits at each stage of line n (for example, line 6 in FIG. 6). Data x (data 7 corresponding to line 6 output data as shown in FIG. 22 and x = 7 in line 6 in FIG. 6) is input from input terminal INa of the first path. The crossbar switch is configured so that the carry bit is always 1 in the switch circuit and the carry bit is always “0” in the switch circuit in which the data x is input from the input terminal of the second path. Yes.
In principle, the carry bit in the switch circuit not corresponding to these may be “0” or “1”. In the present embodiment, the value of the carry bit in the switch circuit not corresponding to these is “0”.

As will be described later, in the present embodiment, the above-described configuration is achieved by appropriately setting the designated address, phase data, and reset input using the switch circuit shown in FIG.
With this configuration, in each switch circuit of line n, when data x is input from the input end INa of the first path, the data received by the input end INb of the second path of the switch circuit Regardless, the data x is output from the output terminal OUTb of the second path and input to the input terminal INb of the second path of the switch circuit of the next stage on the same line.
In the switch circuit that has received the data x through the second path, the value of the carry bit is “0” as described above. Therefore, the data x is output to the output terminal OUTb of the second path, and the next line on the same line is further output. The signal is input to the input terminal INb of the second path of the stage switch circuit.
In this way, in the subsequent stage switch circuits, the data input from the second path is output as it is to the next stage switch circuit on the same line.
Therefore, data x is output as line n output data from the switch circuit in the eighth stage of line n.

From the above, the data input to the address initialization unit for any line can be the line n output data for line n.
Further, not only the line and the data are made to correspond one-to-one, but the same data can be output from a plurality of lines.
For example, as shown in FIG. 22, data 4 is output as line output data for all of line 4, line 7, and line 0.
Hereinafter, a configuration for setting the carry bit as described above will be described.
In the present embodiment, in order to realize the above configuration, the switch circuit shown in FIG. 7 is used, and the configuration of the specified address, the specification of phase data, the value of the carry bit are set as described above. And the input timing of the reset signal.

In this embodiment, phase data is set to 0 in the cross-point control phase where an address is input, and a specified address is sent to the switch circuit in each address initialization unit of each line.
Further, as described above, every time a node (switch circuit) is passed, the designated address is decremented (decremented) by “1” and output to the succeeding switch circuit as a new designated address.
In the address initialization unit, the designated address is input to the input terminal INb of the second path of the first-stage switch circuit, and the data is input to the input terminal INa of the first path of the first-stage switch circuit. When the phase data is “0”, the data c output from the decrement circuit 502 is output from the second path output terminal OUTb. As described above, when the phase data is “0”, carry bit propagation is performed in the switch circuit.

The operation of the switch circuit in carry bit propagation in which the designated address is input bit by bit will be described.
When the carry bit is 0, when the input from the second path input terminal INb is 0, the output of the second path output OUTb is maintained at 0 and the carry is maintained at 0.
When the carry bit is 0 and the input from the second path input terminal INb is 1, the output of the second path output OUTb is 1 and the carry is maintained at 0.
When the carry bit is 1, when the input from the second path input terminal INb is 0, the output of the second path output OUTb remains 1, and the carry remains 1.
When the carry bit is 1 and the input from the second path input terminal INb is 1, the output of the second path output OUTb is 0 and the carry is 0.
That is, in each switch circuit, for each bit of the designated address that is serially input bit by bit, when the carry is 1, the subtracted output is performed, and when the carry is 0, the subtraction is not performed. As a result, in each switch circuit, an operation of reducing the designated address serially input by 1 bit by 1 (1 decrement) is performed serially. With such a configuration, it is possible to serially input a designated address whose value is reduced by 1 by subtraction to the switch circuit at the subsequent stage.

Here, in the operation of the switch circuit described above, when the carry bit of the switch circuit is 0, the value of the carry bit is maintained at 0 regardless of whether 0 or 1 is input from the second path input terminal INb. .
On the other hand, when the carry bit of the switch circuit is 1, the carry bit remains 1 only when the input from the second pass input terminal INb is 0, and the input from the second pass input terminal INb is 1. Then, the carry bit is changed to 0.
Since the initial value of the carry bit is 1, if at least one of the bits (three bits in the present embodiment) of the designated address input bit by bit to the switch circuit is 1, The value of the carry bit is 0, and the value of the carry bit is never 1 after that.

If the value of the designated address input to the switch circuit is “0”, since all bits constituting the designated address are 0, the carry bit of the switch circuit remains at 1. Accordingly, the carry bit is maintained at 1 in the switch circuit to which the designated address is 0, that is, “000” is input.
On the other hand, if the designated address input to the switch circuit is other than “0”, the value of at least one of the bits constituting the designated address is “0”. Accordingly, in the switch circuit in which the input designated address is not 0, the value of the carry bit after the input of the 3-bit address is always “0”.
In this way, it is achieved that the value of the carry bit becomes “1” only in the switch circuit in which all the bits of the designated address sequentially input are “0”.
In other switch circuits, even if all three bits of the designated address pass and data is input (that is, even if the phase data becomes “1”), the value of the carry bit remains 0.
With this configuration, “in the data transfer phase (phase data =“ 1 ”), the switch circuit to which the data x is input from the first path is designated, the carry bit value of the designated switch circuit is set to 1, and the other switches The value of the carry bit of the circuit is set to “0”.

On the other hand, “in the data transfer phase, the data x that is the data to be the output data of line n among the switch circuits arranged in the first to eighth stages of line n is the first path (or address initialization unit). A configuration for designating a switch circuit input from is shown below.
In order to make such designation, the address initialization unit for line n receives the data x as the output data for line n from the first pass (address initialization unit in the first stage) to which stage of the switch circuit. Calculate whether it is input.
As described above, in the switch circuit of line n, the data x is input to the (x−n + 1) th stage.
Further, as described above, since the designated address is decremented by the decrement circuit 502 in FIG. 7 and then input to the switch circuit at the next stage, the designated address is (xn) at the (x−n + 1) stage. It will be decremented several times before being input.
From the above, the address initialization unit for line n calculates the designated address as (x−n).

For example, when attention is paid to the line 6, when the data 6 input to the line 6 is line 1 output data, n = 1 and x = 6. Therefore, the address initialization unit 1 sets the value of the designated address to (6 -1) = 5.
The designated address is decremented by “1” by the switch circuits in the first, second, third, fourth, fifth, and fifth path switching units 21 of line 1.
Therefore, in the switch circuit in the sixth row, the designated address is decremented five times to “0”, so that the switch circuit in the sixth row of line 1 The data 6 is recognized as a “switch circuit that is input from the first path”.
In line 7 (n = 7), data 4 (x = 4) input to line 4 becomes line 7 output data, so the value of (x−n) is 4-7 = −3.
However, the address initialization unit 7 outputs “5 (“ 101 ”)” obtained by adding 8 which is the cyclic cycle to “−3” which is the subtraction result from the above-described cyclicity. In this way, by performing a modulo operation modulo 8, an operation result in consideration of the circulation cycle can be obtained.

By serially performing binary subtraction using a serial subtractor or the like, the address initialization unit can be configured to output a designated address reflecting the above-described circularity.
Note that the address initialization unit can refer to the line number provided with the address initialization unit itself. For example, record the line number in a memory provided in the address initialization unit. The above-described phase data is also supplied to the address initialization unit. In the address initialization unit n, when the phase data is 0, the above-described subtraction is performed. When the phase data is 1, the input data n is directly passed through and the data flows to the first-stage switch circuit.
Next, the principle of the subtraction will be described. The operation when the phase data is 0 is serially performed bit by bit. For example, when the address initialization unit subtracts 7 (“111”), which is the line number of line 7, from 4 (“100”), which is the data number of line 7 output data, the following processing is performed. The
First, the first bit of the data number of the line n output data (“100” in the above example of the address initialization unit 7) is input to the address initialization unit n (this input is P).
On the other hand, the address initialization unit n provided in the line n reads the first bit of the line number n (“111” in the above example) of the line n (this read bit is set as Q). The address initialization unit n calculates PQR with R as the carry bit, and outputs the calculation result to the first-stage switch circuit.
However, in this calculation, the default value of the carry bit is 0. If the calculation result is negative, the carry bit is set to 1 regardless of the state before the calculation. As the output result, a result obtained by adding “2” to the operation result is output. Thereby, subtraction by serial input of 1 bit is performed.

FIG. 8 shows a state in which a control start bit S which is serial data (address) of the least significant bit is input to the address initialization unit 20 to start the crosspoint control phase, and FIG. 9 follows the least significant bit. The control bit C, which is the second bit serial data (address), is input to the address initialization unit 20, the least significant bit is input to the switch circuit 50 in the first row, and FIG. Control end bit E, which is data (address), is input to the address initialization unit 20, the first bit is input to the switch circuit 50 in the second row, and the second bit is input to the switch circuit 50 in the first row Is shown.
The numerical value at the time when all of these three bits have passed through the address initialization unit 20 represents the above-described subtraction result.

In FIG. 8, taking line 7 as an example, the output data of line 7 is data 4, so x = 4, and the line number is 7, so n = 7.
The least significant bit “0” of x = 4 (“100”) is input to the address initialization unit 7.
The address initialization unit 7 reads the least significant bit “1” of n = 7 (“111”) from the above memory, subtracts 1 from 0, and further subtracts the default value “0” of the carry bit.
The subtraction result is 0-1−0 = −1. As described above, “1”, which is a value obtained by adding 2 to this value, is supplied to the first-stage switch circuit as the least significant bit of the designated address (see FIG. 8 corresponds to “0 → 1” in AINI-7). At this time, although not shown, since the calculation result is negative, the carry bit is “1” based on the above-described principle.
In FIG. 9, the second bit “0” of x = “100” is input to the address initialization unit 7, and the second bit “1” of n = “111” is read from the memory and subtracted. .
At this time, since the carry bit is “1”, the subtraction result of this bit is 0−1-1 = −2. Based on the above principle, “0” obtained by adding 2 to the value of the operation result is supplied to the first stage switch circuit (corresponding to “0 → 0” in AINI-7 in FIG. 9). Further, since the calculation result is negative, the carry bit is “1”.
In FIG. 10, the most significant bit “1” with x = “100” is input to AINI-7, the most significant bit “1” with n = “111” is subtracted, and the carry bit value “1” is further subtracted. Is done.
The subtraction result is 1-1-1 = -1, but 2 is added from the above principle to output "1". As a result, the third bit of the designated address becomes “1” (corresponding to “1 → 1” in AINI-7 in FIG. 10).
By performing these processes, “101”, that is, 5 is obtained as the designated address. By using the carry bit in this way, a result obtained by subtracting the line number n from the data number x of the line n output data can be obtained.

Subsequently, when the fourth bit serial data (data to be transmitted) is input to the address initialization unit 20, the control end bit E is input to the switch circuit 50 in the first row of the path switching unit 21 as the designated address. The
FIG. 11 shows the state at this time.
In FIG. 11, the carry bit of the switch circuit 50 in the first row of line 4, line 5, and line 3 is “1”. Therefore, as described above, in these lines 4, 5, and 3, the switch circuit 50 in the first row is designated as the switch circuit that performs data transfer. The serial data flowing above is transferred onto the second path, and passes through the switch circuit 50 in the subsequent stage of the same node line (second path) as it is until the data reaches the output end.

FIG. 12 shows a state where the second-stage switch circuit 50 of the line 6 is selected as a switch circuit that performs data transfer.
Thereafter, serial data is transmitted step by step as shown in FIGS. 13 and 14, and the switch circuit 50 in the fifth row of line 0 is selected as a switch circuit for transferring data in the state of FIG. In the state of FIG. 16, the switch circuit 50 in the sixth row of line 1 and line 7 is further designated as a switch circuit that performs data transfer.
Further, after the state of FIG. 17, in the state of FIG. 18, the lowermost switch circuit of line 2 is designated as the switch circuit 50 that performs data transfer.

In this way, when the input of all the address bits of the designated address is finished in each switch circuit 50 in each node line, the data transfer phase starts from the next operation timing. Eventually, the data passes through each switch circuit 50 in the order of FIGS. 19 to 21, and is output one bit at a time from the output end of each node line.
FIG. 22 shows which path the serial data has been selected and passed through, and in what state it is finally output from the output terminal.

As described above, in the crossbar switch of the second embodiment, the data transfer phase and the crosspoint control phase are separated, and therefore, it is possible to share the control line and the data output line for performing the crosspoint control. Thus, the number of wires in the crossbar switch can be greatly reduced, and the crossbar switch can be downsized.
Further, for example, by wiring the nodes so that the distances between them are the same or substantially the same, it is easy to connect them in multiple stages via interface components and subsequently increase the scale of the crossbar switch. Furthermore, since the instruction array can perform the cross point control in almost the same time as the data transfer, it is possible to realize a higher speed data transfer process in the case of a process with a small ratio of the cross point control phase.

There are various ways of using the crossbar switch of the second embodiment.
For example, in addition to the general usage form of the crossbar switch as shown in FIG. 23, the multicast system as shown in FIG. 24 and the broadcast system as shown in FIG. 25 can be easily realized by this crossbar switch. Can do.
In these drawings, the numerical value of the area indicated by reference numeral 22 is the line number of the node line to which data desired to be output from the node line is input, and the numerical value in the path switching unit 21 is the switch circuit 50 of each node line. Address.
The numerical value described on each switch circuit 50 is the address decremented there. The numerical value in the address initialization unit 20 is a designated address, and is derived by subtracting the line number of the node line through which data flows from the line number of the node line to be output as described above.

  In the example of FIG. 24, data input from the input ends of the node lines identified by line number 0 from line 2, line 3, line 5, and line 6 are simultaneously output, and line numbers from line 4 and line 7 are output simultaneously. An example in which data input from the input end of the node line identified by 2 is output is shown. FIG. 25 shows an example in which data input from the input end of the node line identified by line number 3 is output from all of line 0 to line 7 simultaneously.

  In this manner, not only the switching pattern of the data path of the input N types (N is a natural number) versus the output N types but also the switching pattern of the data path of the input N types versus the output M (N <M) types can be realized. . In addition, a designated address is generated simply by specifying a line number, and the switch circuit 50 of each node line corresponding to the designated address performs data transfer autonomously, so that crosspoint control is performed as in the first embodiment. Is greatly simplified.

As a modification, the first path and the second path in the route switching unit 21 can be set as in the route switching unit 23 shown in FIG.
In FIG. 26, the first path is set between the output terminal of the switch circuit 50 in the previous stage and the input terminal of the switch circuit 50 present in the next column of the switch circuit 50 and in the adjacent column. An example of the case is shown. Further, the crossbar switch of the second embodiment described above is an example in the case of pipelining every row. However, in the crossbar switch shown in FIG. 26, a plurality of rows are combined into a pipeline. That is, the operation phase of each node line is switched in a plurality of rows as in phase 0 to phase 4.

  In FIG. 26, when the select path reaches the leftmost column, it returns to the input end of the switch circuit 50 in the rightmost column of the next row. You may make it return to 50 input terminals.

Although the present invention has been described by taking two embodiments as examples, these embodiments do not limit the scope of the present invention.
For example, in the first and second embodiments, the address and the designated address are numerical data in descending order, and data transfer is performed when the designated address is decremented to “0” every time a node passes. That is, the example in which the specific value represented by the node address is indirectly specified has been described, but the address and the designated address are numerical data in ascending order, and the value represented by the address increases as a result of passing through the node. When it is specified that the unique value assigned to the node has been reached in advance, that is, when the specific value represented by the node address is directly specified, the switch circuit 50 on the node operates to perform data transfer. You can also
If the address when the specific value is indirectly specified is a relative address, and the address when the specific value is directly specified is an absolute address, the crossbar switch example described above, particularly the crossbar of the second embodiment. In the example of the switch, the address after the address initialization unit 20 must be input as a value relative to its own address as to which line the data is taken from. The initialization unit 20 needs to convert the relative address to the absolute address. At this time, it is desirable from the viewpoint of speeding up the processing to prepare an address conversion table that preliminarily defines the relationship between the addresses when converting addresses.

  The crossbar switch according to the present invention includes a parallel computer, ATM (Asynchronous Transfer Mode), a case where a data path is selected between the buffer 1 and the pixel pipeline processor 2. In the case of data transfer in Ethernet (registered trademark) or the like and selection of a data path in data communication processing, it can be applied to other similar uses.

The principal part block diagram of the drawing apparatus with which this invention is applied. The internal block diagram of the crossbar switch by 1st Embodiment of this invention. The block diagram of the switch circuit by 1st Embodiment. Explanatory drawing of the procedure of operation control of the crossbar switch by a 1st embodiment. Explanatory drawing of crosspoint switching. The internal block diagram of the crossbar switch by 2nd Embodiment of this invention. The block diagram of the switch circuit by 2nd Embodiment. Operation explanatory diagram of the crossbar switch (crosspoint control phase). Operation explanatory diagram of the crossbar switch (crosspoint control phase). Operation explanatory diagram of the crossbar switch (crosspoint control phase). Operation explanatory diagram of the crossbar switch (crosspoint control phase). Operation explanatory diagram of the crossbar switch (crosspoint control phase). Operation explanatory diagram of the crossbar switch (crosspoint control phase). Operation explanatory diagram of the crossbar switch (crosspoint control phase). Operation explanatory diagram of the crossbar switch (crosspoint control phase). Operation explanatory diagram of the crossbar switch (crosspoint control phase). Operation explanatory diagram of the crossbar switch (crosspoint control phase). Operation explanatory diagram of the crossbar switch (crosspoint control phase). Crossbar switch operation explanatory diagram (data transfer phase). Crossbar switch operation explanatory diagram (data transfer phase). Crossbar switch operation explanatory diagram (data transfer phase). Explanatory drawing which showed the path | route in the state where data transfer control was complete | finished. The schematic diagram which showed the general operation | movement form of the crossbar switch. The schematic diagram which showed the operation | movement form of the multicast system. The schematic diagram which showed the operation | movement form of the broadcast system. The internal block diagram which showed the modification of the crossbar switch.

Explanation of symbols

1 ... buffer,
2 ... Pixel pipeline processor,
3 ... Crossbar switch
4 ... Serial bus wiring,
5, 50 ... switch circuit,
6 ... Address selection circuit,
7a, 7b ... clock lines,
8 ... repeater,
9: Parallel / serial conversion circuit,
10: Serial / parallel conversion circuit,
11: Decrement circuit,
12: OR circuit,
13 ... AND circuit,
14: Connection switching circuit,
20: Address initialization unit,
21, 23... Route switching unit,
22 ... Specified line number

Claims (15)

A node controller is deployed in each of the cascaded nodes.
Each node controller
An input interface for inputting address information for directly or indirectly specifying the relative position where the target node controller exists, from the previous node;
It is determined whether or not the input address information represents a specific value. When it is determined that the input address information represents a specific value, data can be output to a predetermined data output line. A switch for generating new address information changed according to the rules;
An output interface for outputting the new address information to a subsequent node;
A plurality of node lines each including the plurality of nodes;
Node controllers on each node line operate at least at the same clock timing as node controllers on other node lines operating in parallel,
Each node controller on each node line receives data from the previous node and outputs the data to the subsequent node of another node line, and the address information from the previous node and the new node. A second path for outputting correct address information to a subsequent node of the same node line, and
Each node controller is arranged in a matrix matrix on a plurality of node lines,
The second path is set in the column direction of each node line,
The first path is set between the output end of the previous node controller and the input end of the node controller that is in the next row and in a different column of the node controller.
Crossbar switch. The address information is circular numerical data,
The output interface generates the new address information by increasing or decreasing the numerical data in the same change direction by a predetermined value.
The crossbar switch according to claim 1. The address information is serial data including a start bit and an end bit.
The crossbar switch according to claim 2. A plurality of node lines each including the plurality of nodes;
Node controllers on each node line operate asynchronously with node controllers on other node lines,
The crossbar switch according to claim 1. Each of the plurality of nodes is associated with an output address of a predetermined data memory in a one-to-one relationship,
When the switch of each node controller is activated, it outputs the data output from the data memory through the output address associated with the node to the data output line.
The crossbar switch according to claim 1. The first path and the second path in each node controller have the same or substantially the same node length.
The crossbar switch according to claim 1 . All the node controllers arranged in at least the same row direction operate according to a clock signal that defines the same operation timing.
The crossbar switch according to claim 1 . The first path is set between the output end of the previous node controller and the input end of the node controller that is in the next row and adjacent column of the node controller.
The crossbar switch according to claim 1 . A part or all of the first path includes an output end of a previous node controller and an input end of a node controller that is a row of the next stage of the node controller and is located at a position separated from the node controller by a plurality of columns. Set between
The crossbar switch according to claim 1 . The first path for the node controller located at the extreme end in the column direction is set between the output end of the node controller and the input end of the node controller existing in the adjacent position in the next row. Yes,
The crossbar switch according to claim 9 . Address information generating means is provided at each input end of the plurality of node lines. The address information generating means includes first line identification data for identifying a line on which the address information generating means itself is provided, The address information is generated based on the second line identification data for identifying the node line to which the data output from the switch provided in the last node of the line provided with the address information generating means is input. To
The crossbar switch according to claim 1 . It is housed in a package that can be mounted on a computer.
At the input ends of the plurality of node lines, there is an interface component for connecting a first device that holds data input to the input ends,
At the output ends of the plurality of node lines, there are interface components for connecting a second device having an operation pipeline corresponding to each node line in a one-to-one relationship.
The crossbar switch according to claim 1 . It is housed in a package that can be mounted on a computer.
An interface component for connecting a plurality of node lines of another crossbar switch having the same configuration exists at the input end and / or the output end of the plurality of node lines.
The crossbar switch according to claim 1 . A method for controlling the operation of a crossbar switch, comprising a plurality of nodes connected in cascade, each having a plurality of node lines through which input data flows, and a node controller arranged in each node, Has a plurality of node lines each including the plurality of nodes, and a node controller on each node line operates at least at the same clock timing as a node controller on another node line operating in parallel. ,
Each node controller on each node line receives data from the previous node and outputs the data to the subsequent node of another node line, and the address information from the previous node and the new node. A second path for outputting correct address information to a subsequent node of the same node line, and
Furthermore, each node controller is arranged in a matrix matrix on a plurality of node lines,
The second path is set in the column direction of each node line,
The first path is set between the output end of the previous node controller and the input end of the node controller that is in the next row and in a different column of the node controller,
The device for controlling the crossbar switch generates address information based on identification information of a node line for outputting data and information indicating a relative position of a node controller to be operated, and this address information is used as the first node of the target node line. To enter
When the node controller existing in each node of the node line to which the address information is input determines whether the input address information represents a specific value, Generating new address information obtained by changing the input address information by a predetermined value, and outputting the new address information to a subsequent node,
Furthermore, the address information is for designating data output from the last stage of the column in which the address information is input.
Crossbar switch operation control method. A program to be executed by a computer comprising a plurality of nodes connected in cascade, a plurality of node lines through which input data flows, and a crossbar switch in which each node is provided with a node controller Because
The node controller has a plurality of node lines each including the plurality of nodes, and the node controllers on each node line operate at least at the same clock timing as node controllers on other node lines operating in parallel. Is,
Each node controller on each node line receives data from the previous node and outputs the data to the subsequent node of another node line, and the address information from the previous node and the new node. A second path for outputting correct address information to a subsequent node of the same node line, and
Furthermore, each node controller is arranged in a matrix matrix on a plurality of node lines,
The second path is set in the column direction of each node line,
The first path is set between the output end of the previous node controller and the input end of the node controller that is in the next row and in a different column of the node controller,
A crossbar switch operation control program for operating each node controller as in the following (1) to (3) .
(1) The address information for directly or indirectly specifying the relative position where the target node controller exists is input, and this address information is the data output from the last stage of the column in which the address information is input. It is what you specify,
(2) It is determined whether or not the input address information represents a specific value. When it is determined that the input address information represents a specific value, the data on the node line is output,
(3) New address information is generated by changing the input address information by a predetermined value, and the new address information is output to a subsequent node.

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