JP4450729B2 - Image forming apparatus - Google Patents

Description

  BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an image forming apparatus using a laser writing optical system, such as a printer, a copying machine, a facsimile, etc., and in an image forming apparatus using a PLL circuit as a clock source synchronized with an image signal, the PLL circuit More specifically, the power supply fluctuation of the power source supplied to the VCO (voltage controlled oscillator) of the PLL circuit is reduced, the jitter of the write clock is reduced, and the image quality is improved.

  FIG. 11 is a main part configuration diagram for explaining an example of an image forming apparatus having a laser beam scanning device. In FIG. 11, reference numeral 11 denotes a laser as a laser beam (light beam) generating means that is turned on in accordance with an image signal. A laser beam (light beam) 12 emitted from the LD 11 in a diode (hereinafter referred to as LD) unit is converted into a parallel beam by a collimator lens (not shown), passes through a cylinder lens, and is a polygon mirror as a deflecting unit. The light is deflected by the (rotating polygon mirror) 13 and passes through the fθ lens 14 and a BTL (barrel toroidal lens) (not shown) to scan the photosensitive member 15 as an image carrier. The polygon mirror 13 is rotated in the direction of arrow A about an axis perpendicular to the axis of the photoconductor 15 by a polygon motor as driving means (not shown) (with respect to the photoconductor 15 as shown in FIG. 12). Rotated).

  As the photoreceptor 15, a drum-shaped photoreceptor (illustrated example), a belt-shaped photoreceptor, or the like is used. The fθ lens 14 converts the speed so that the laser beam 12 scanned mainly at a constant angular speed by a polygon mirror (rotating polygon mirror) 13 is scanned at a constant speed in the axial direction (main scanning direction) on the photosensitive member 15. The BTL (barrel toroidal lens) mainly performs focusing in the sub-scanning direction (arrow B direction) (condensing function and position correction (surface tilt, etc.) in the sub-scanning direction).

  Around the photosensitive member 15, there are a charger 1 as a charging means, a developing device 2 as a developing means, a transfer device 3 as a transferring means, a fixing device 4 as a fixing means, a cleaning device 5 as a cleaning means, and a discharging means. And the like, and an image is formed on a recording paper 7 as a transfer material by a normal electrophotographic process. That is, the photosensitive member 15 is rotationally driven in the direction of arrow B by a driving mechanism (not shown), and the surface of the photosensitive member 15 is uniformly charged by the charger 1, and then scanned by the laser beam 12 from the laser beam scanning device. As a result, an electrostatic latent image is formed. The electrostatic latent image on the photoreceptor 15 formed in this manner is developed (visualized) by the developing device 2 to become a toner image, and the recording paper supplied from the paper feeding device by the transfer device 3. The transferred toner image is fixed on the recording paper 7 by the fixing device 4 and discharged to the outside. The photoreceptor 15 is cleaned by the cleaning device 5 after the toner image is transferred to remove the residual toner, and is neutralized by the static eliminator 6 to prepare for the next electrophotographic process.

  FIG. 12 is a diagram for explaining a control system around the laser beam scanning device as an image writing unit. As shown in FIG. 11, the laser beam 12 is scanned in the direction of arrow C on the photosensitive member 15. However, sensors 16 and 17 as light beam detecting means for detecting the laser beam 12 (light beam) are provided at both ends of the photosensitive drum 15, and the laser beam 12 transmitted through the fθ lens 14 is detected by the sensor. 16 and 17 so that the scanning start point and the scanning end point of the laser beam 12 are detected. In FIG. 12, only the fθ lens 14 is shown as a representative of a plurality of lenses. The sensor 16 also serves as a synchronization detection sensor for detecting a laser beam scanning synchronization signal that becomes a synchronization detection signal.

  When the laser beam 12 performs main scanning on the photoconductor 15 in the direction indicated by the arrow C, the sensors 16 and 17 detect the laser beam 12 and output laser beam detection signals DETP1 and DETP2, respectively. Detection signals DETP 1 and DETP 2 are sent to the time difference measuring unit 21.

  The time difference measuring unit 21 has an arithmetic function such as measuring and averaging the time difference between the output signal DETP1 of the sensor 16 and the output signal DETP2 of the sensor 17, and according to the set timing from the control device (CPU) 24. Measurement and calculation are performed, and the measurement and arithmetic results are sent to the magnification correction control unit 22.

  The magnification correction control unit 22 includes a storage unit that stores the initial setting value or / and the current setting value of the writing clock frequency and the phase adjustment value set by the control device (CPU) 24, and the writing clock frequency. By utilizing the fact that the image magnification in the main scanning direction is changed by the above, and by using the fact that the image magnification is changed by shifting the phase in a minute time that cannot be adjusted in the write clock adjustment unit, Based on a time difference meter and an arithmetic result, it has a function of calculating an optimum write clock frequency and phase adjustment value or / and fixing the write clock frequency and calculating an optimum phase adjustment value. It has the function of comparing the adjustment value with the reference value set by the control unit (CPU) 24, and the control signal for executing the write clock setting and phase adjustment is written according to the setting of the CPU 24. Send to the click generation unit 23.

  The write clock generation unit 23 includes a frequency modulation unit 23a and a phase control unit 23b. The frequency modulation unit 23a receives a clock from an oscillator (not shown) and generates a clock that is n times the write clock PCLK. The phase controller 23b divides the PLL oscillation clock by n in synchronization with the DETP1 (laser beam detection signal) as a synchronization detection signal, and generates a write clock PCLK synchronized with DETP1, and By adding or subtracting an integer multiple of the PLL transmission clock half cycle to a specific cycle of the write clock, the write clock cycle is shifted by one pixel unit. That is, the write clock generation unit 23 performs generation of the write clock and phase adjustment under the control of the control device (CPU) 24 and the magnification correction control unit 22.

  The write clock PCLK that has been subjected to the main scanning image magnification correction by the variable frequency and phase in the write clock generator 23 is sent to the LD modulator 10 as the light beam generator drive unit. The LD modulation device 10 controls the lighting of the LD 11 in the LD unit in the laser beam scanning device through the LD driver 60 according to the image signal synchronized with the write clock PCLK from the write clock generation unit 23. As a result, the laser beam 12 modulated in accordance with the image signal is emitted from the LD 11 in the LD unit, and the laser beam 12 is deflected by the polygon mirror 13 as described above and is passed through the fθ lens 14 on the photoconductor 15. Scan.

FIG. 13 is a diagram showing the PLL circuit and its peripheral circuits. The PLL circuit 30 is a circuit for generating a new signal synchronized with the phase of the input signal. Basically, the phase comparator 30 ₁ , The peripheral circuit includes a crystal oscillator 31, a 1 / M frequency divider 32, a 1 / N frequency divider 33, a power source 35, and the like. The power source 35 is composed of a loop filter 30 ₂ and a VCO (voltage controlled oscillator) 30 _3. more PLL circuit 30 and, and so as to supply power to a VCO (voltage-controlled oscillator) 30 _3.

In the circuit shown in FIG. 13, the write clock (f _out ), which is the output of the VCO (voltage controlled oscillator) 30 ₃ , is frequency-divided by 1 / N using the frequency divider 33. signal and a signal obtained by dividing the 1 / M with oscillated reference clock (f _in) of the frequency divider 32 from the crystal oscillator 31, compared with the phase comparator 30 _1, through the loop filter 30 ₂ It is supplied to a VCO (voltage-controlled oscillator) 30 _3, and outputs a write clock _{(f out)} from the VCO 30 _3. The reference clock _{(f in)} is an output signal of the crystal oscillator 31 and the write clock _{(f out)} is the output signal of the PLL circuit 30, the frequency division ratio N, between _{M, f out = f in ×} N The relationship / M is established.

  FIG. 14 is a schematic diagram of the write clock generation unit 23, and shows a configuration in which the PLL circuit 30 is arranged in the write clock generation unit 23. In FIG. It is arranged in the phase control unit 23 b constituting the clock generation unit 23. Note that the PLL circuit 30 may be disposed outside the phase control unit 23b.

  FIG. 15 is a configuration diagram showing the relationship between the PLL circuit 30 and the logic circuit (LD modulation device) 10 in the prior art. The PLL circuit 30 and the logic circuit (LD modulation device) 10 are arranged as shown in the figure. The write clock PCLK generated by 30 is sent to the logic circuit (LD modulator) 10, and the logic circuit 10 generates a data signal from the image signal synchronized with the write clock PCLK. The laser beam is sent to an LD (light beam generator) 11 through an LD driver 60.

In this case, in the prior art, the power source 35 is directly supplied to the PLL circuit 30 and the logic circuit (LD modulator) 10, but in the color image forming apparatus described in Patent Document 1, FIG. As shown, a ferrite bead inductor L is inserted between each PLL circuit 30 and the power supply 35 to make it difficult for high-frequency noise to enter the power supply of other PLL circuits, thereby reducing power supply interference between PLLs and reducing clock jitter. Further, a capacitor C is inserted into each PLL circuit to stabilize the power supply voltage of each PLL circuit.
JP 2003-118160 A

  Since power fluctuation (power ripple) to the VCO (Voltage Controlled Oscillator) of the PLL (Phase Lock Loop) circuit adversely affects the stable output of the PLL, a filter (RC) is conventionally used to suppress power fluctuation. A configuration through a filter, an LC filter, or the like is known. However, depending on the characteristics of the filter, fluctuations in the power supply may not be suppressed. Alternatively, in some cases, a larger power supply fluctuation may be given to the PLL. As a result, the write clock jitter (PLL oscillation frequency fluctuation) becomes large, and the image quality may deteriorate.

The purpose of the present invention is to supply power through the power regulating device only PLL circuit which need to reduce the clock jitter. When generating a write clock to be synchronized with image signals for a plurality of colors by a plurality of PLL circuits, even if the clock jitter (PLL oscillation frequency fluctuation) is likely to become very large, the VCO (voltage) of the PLL circuit If the power supplied to the control oscillator) is very stable, the fluctuation of the oscillation frequency becomes very small. Therefore, it is necessary to assemble a power supply adjusting device and a PLL circuit that satisfy the above conditions. Therefore, power is supplied through the power regulator only to the PLL circuit that needs to be supplied with power through the power regulator, and power is supplied through the power regulator without passing through the power regulator. I tried to do it.

The invention of claim 1 is provided corresponding to each of four LDs that generate light beams corresponding to each of Y (yellow), M (magenta), C (cyan), and K (black) . In an image forming apparatus having four PLL circuits and scanning one or a plurality of photosensitive members by modulating the light beam according to an image signal, a writing clock synchronized with the image signal for each of the four light beams Write clock generation means for generating a VCO in each write clock generation means, and for the VCO in the PLL circuit for M (magenta), C (cyan), K (black) Te compares the input voltage a reference voltage, when the input voltage is lower than the reference voltage serves to output voltage becomes higher, when the input voltage is higher than the reference voltage, output Supplying power through the power adjusting means is a voltage for suppressing the power fluctuation worked so as to be lower, for the VCO in the PLL circuit for Y (yellow), powered directly without going through the power adjusting means It was made to do.

  By supplying power to the VCO (Voltage Controlled Oscillator) of the PLL circuit through the power regulator, power supply fluctuation (power ripple) of the power supplied to the VCO (Voltage Controlled Oscillator) of the PLL circuit can be suppressed, and the write clock jitter (PLL) The fluctuation of the oscillation frequency of the image can be reduced, and the image quality can be improved.

  Further, by supplying power to the VCO (Voltage Controlled Oscillator) of the PLL circuit that generates a write clock that is synchronized with an image signal of a color whose image quality is conspicuously lowered, the power is supplied through a power supply regulator, thereby writing clock jitter (PLL oscillation frequency Fluctuations) and the overall image quality can be improved.

  In addition, even when the write clock jitter (PLL oscillation frequency fluctuation) is likely to become very large, by supplying power to the VCO (voltage controlled oscillator) of the PLL circuit through the power regulator, the PLL circuit Since the power supplied to the VCO (Voltage Controlled Oscillator) is further stabilized, the write clock jitter (PLL oscillation frequency fluctuation) becomes very small, and the image quality can be improved.

FIG. 1 is a schematic configuration diagram of a main part of an image forming apparatus 40 to which the present invention is applied . In FIG. 1, 41 is a PSU (power supply device), and the PSU 41 includes a PLL circuit 30 and a logic circuit (LD modulation device). ) Generate power to be supplied to 10. The power from the PSU 41 is supplied to the LD modulator (logic circuit) 10 as it is, and is supplied to a VCO (voltage controlled oscillator) (not shown) in the PLL circuit 30 through a power regulator 42 (regulator). Although not shown, power from the PSU 41 is directly supplied to the PLL circuit 30 as well. The write clock PCLK generated by the PLL circuit 30 is sent to the logic circuit (LD modulator) 10 as described above, and the logic circuit (LD modulator) 10 synchronizes with the write clock PCLK. A data signal is generated from the signal and sent to an LD (light beam generator) 11 through an LD driver 60.

Figure 2 is a connection relationship between a VCO (voltage-controlled oscillator) 30 ₃ of the power regulating device 42 (regulator) and PLL circuit 30, and the peripheral circuit (quartz oscillator 31 of the PLL circuit 30, a frequency divider 32, divider a constitutional view showing the vessel 33), and supplies the power supply 35 through the power regulating device 42 only a VCO (voltage-controlled oscillator) 30 ₃ in the PLL circuit 30 (regulator).

Figure 3 is a functional block diagram of a peripheral circuit in the power adjustment device shown in FIG. 1, FIG. 3, PLL circuit 30 for generating a write clock PCLK, the power regulating device 42 for reducing the write clock jitter, A logic circuit (LD modulation device) 10 that generates a data signal to be supplied to an LD (light beam generation device) 11 is arranged. The write clock PCLK generated by the PLL circuit 30 is sent to the logic circuit (LD modulation device) 10, and the logic circuit 10 generates a data signal from the image signal synchronized with the write clock PCLK, and the LD driver 60 And is sent to an LD (light beam generator) 11. A power supply 35 is supplied to a VCO (voltage controlled oscillator) (not shown) in the PLL circuit 30 through a power supply adjustment device 42 and directly supplied to the logic circuit (LD modulation device) 10 without going through the power supply adjustment device 42. It has come to be. Although not shown, the power supply 35 is directly supplied to the PLL circuit 30 without passing through the power supply adjustment device 42.

4 is a functional block diagram illustrating the configuration and peripheral circuits in the PLL circuit 30 in FIG. 3. In FIG. 4, the power supply adjustment device 42 is a series regulator, and the VCO (voltage) in the PLL circuit 30 is shown in FIG. The power source 35 is supplied to the controlled oscillator) 30 ₃ only through the power source adjusting device 42. A VCO (voltage-controlled oscillator) 30 ₃ are very susceptible to power fluctuations, several MHz frequency with power supply fluctuations 10~20mV with an oscillation frequency of about 500MHz fluctuates. Then, the influence of the variation appears directly on the image as image fluctuation. Therefore, using the power adjustment device 42 (regulator), there is a need in particular to suppress the power variation of a VCO (voltage-controlled oscillator) 30 _3.

5, the power adjustment device in the real施例of the present invention, as well as a functional block diagram of a peripheral circuit in the power supply adjusting device, FIG. 5, PLL circuit 30 for generating a write clock PCLK ₍₃₀ K, 30 _M , 30 _C , 30 _Y ), a power conditioner 42 (42 _K , 42 _M , 42 _C , 42 _Y ) that reduces write clock jitter, and K (black), M (magenta), C (cyan), A logic circuit 10 (10 _K , 10 _M , 10 _C , 10 _Y ) for generating data signals for four colors is arranged to form a color image in which four Y (yellow) color images are superimposed. ing.

The write clock PCLK generated by the PLL circuit 30 is sent to the logic circuit (LD modulator) 10 and the four logic circuits (LD modulator) 10 (10 _K , 10 _M , 10 _C , 10 _Y ) are written. generates a data signal from an image signal synchronized with the write clock PCLK, through the LD driver _{60 (60 K, 60 M,} 60 C, 60 Y), LD ( beam generating _{apparatus) 11 (11 K, 11 M} , 11 _C , _11Y ). The VCO (voltage controlled oscillator) (not shown) in the PLL circuit 30 (30 _K , 30 _M , 30 _C ) is supplied with power through a power supply adjustment device 42, but in this embodiment, three power supply adjustments are made. The device 42 (42 _K , 42 _M , 42 _C ) drives the VCO (voltage controlled oscillator) in the three PLL circuits 30 (30 _K , 30 _M , 30 _C ) in a one-to-one correspondence. . Although not shown, power is directly supplied to the PLL circuit 30 (30 _K , 30 _M , 30 _C ) without passing through the power supply adjustment device 42. A power supply adjustment device is not provided for the yellow (Y) PLL circuit. This is because yellow (Y) is a color in which the image quality deterioration due to clock jitter (PLL oscillation frequency fluctuation) is not conspicuous, and the influence of clock jitter can be sufficiently tolerated without a power supply adjustment device. The PLL circuit 30 _Y provided corresponding to the logic circuit 10 _Y and the VCO (voltage controlled oscillator) in the PLL circuit 30 _Y are supplied with power without passing through a power supply adjusting device .

Figure 6 is a functional block diagram showing a reference example of the peripheral circuit in the power adjustment device, FIG. 6, the four PLL circuit ₃₀ for generating a write clock _{PCLK (30 K, 30 M,} 30 C, 30 Y) Two power supply regulators 42 (42 _K , 42 _C ) are provided for a VCO (voltage controlled oscillator) (not shown). In other words , power is supplied to VCOs (voltage controlled oscillators) in the two PLL circuits 30 by one power supply adjustment device 42. That is, in the illustrated example, one power conditioner 42 _K drives two VCOs (voltage controlled oscillators) in the PLL circuits 30 _K and 30 _M , and another power conditioner 42 _C The VCO (voltage controlled oscillator) in the two PLL circuits 30 _C and 30 _Y is driven. Although not shown, power is directly supplied to the PLL circuit 30 (30 _K , 30 _M , 30 _C , 30 _Y ) without passing through the power supply adjustment device 42 .

Figure 7 is a functional block diagram of a peripheral circuit showing another reference example in power adjusting device, FIG. 7, all ₃₀ K of the PLL circuit 30 for generating a write clock _PCLK, 30 _M, 30 C, 30 _{For the} VCO (voltage controlled oscillator) (not shown) in _Y , power supply adjusting devices 42 _K , 42 _M , 42 _C , and 42 _Y that reduce write clock jitter correspond one-to-one, and four PLL circuits 30 _K , power adjustment device _{42 K, 42 M, 42 C} , 42 Y , respectively provided for _{30 M,} 30 C, 30 illustrated non VCO in _Y (voltage controlled oscillator). By doing so, power supply fluctuation can be suppressed with high reliability, clock jitter can be reduced, and image quality can be improved. Although not shown, power is directly supplied to the PLL circuit 30 (30 _K , 30 _M , 30 _C , 30 _Y ) without passing through the power supply adjustment device 42 .

8, in another functional block diagram showing a reference example, a diagram of a peripheral circuit in the power adjusting device, 50 is an IC package, the said IC package 50, a plurality of PLL circuits 30 ₍₃₀ K, 30 _M , _30C , _30Y ). In this way, even if a plurality of PLL circuits are enclosed in one package, the power supply fluctuation (power supply ripple) of the power supplied to the VCO of the PLL circuit is suppressed using the power supply adjustment device, so that the write jitter can be reduced. The image quality can be improved. Although not shown, power is directly supplied to the PLL circuit 30 (30 _K , 30 _M , 30 _C , 30 _Y ) without passing through the power supply adjustment device 42 .

Figure 9 is a functional block view showing another reference example of the peripheral circuit in the power adjustment device, the regulator 51 as a power supply regulation circuit to reduce the writing included clock jitter (power adjustment device) (51 K, _{51 M,} 51 _C , 51 _Y ). As the regulator, a series regulator, a three-terminal regulator, or the like is used. In FIG. 9, regulators 51 _K , 51 _M , 51 _C , 51 _Y are provided for VCOs (voltage controlled oscillators) not shown in the PLL circuits 30 _K , 30 _M , 30 _C , 30 _Y. and it has, but the PLL circuit 30 _K and 30 _M in one package 50 _1, PLL circuit 30 _C and 30 _Y is sealed in another package 50 _2. That is, two ASICs (Application Specific Integrated Circuits) 50 ₁ and 50 _{2 in} which two PLL circuits are enclosed in one package are arranged. One ASIC 50 ₁ is, K (black), and generates a data signal for M (magenta), the ASIC 50 ₂ on the other hand, C (cyan), and generates a data signal for Y (yellow), LD (light Beam generator 11) Although not shown, power is directly supplied to the PLL circuit 30 (30 _K , 30 _M , 30 _C , 30 _Y ) without passing through the regulator 51.

Here, the configuration of the regulator will be described.
Figure 10 is a block diagram of a regulator 51, in the figure, the regulator 51, pass transistor 52, the error amplifier 53, the reference voltage unit 54, and is configured from the detection unit 55. In FIG. 10, the unstable input voltage V _i is output to the load electronic circuit through the pass transistor unit 52, but the output voltage V _o is resistance-divided by the detection unit 55 and then output to the error amplifier 53. It is compared with the reference voltage of the reference voltage unit 54. In this case, if the reference voltage of the reference voltage portion 54 side is large act in the direction to increase the output voltage to increase the output current I _o of the pass transistor 52, when the output voltage of the detector 55 side is large path _-The output current Io of the transistor unit 52 is suppressed to lower the output voltage, thereby suppressing power supply fluctuations.

  In this way, by using a regulator as a power supply adjustment device, the cost can be kept low, it can be used with high reliability, and since there is little noise, power fluctuation can be suppressed and clock jitter can be reduced, improving image quality Can be planned. Furthermore, the regulator has a stable power supply (less power supply fluctuation) than the CL circuit, and is less likely to oscillate than the CL circuit.

1 is a schematic configuration diagram of a main part for explaining an embodiment of an image forming apparatus to which the present invention is applied ; It is the block diagram which showed the connection relation of a power supply adjustment apparatus and a voltage control oscillator. It is a functional block diagram of the peripheral circuit in a power supply adjustment apparatus . Diagrams revealed the structure of the P LL circuit. It is a main part configuration diagram for explaining the actual施例of the present invention. It is a principal part block diagram for demonstrating the circuit structure of the power supply adjustment device periphery used as a reference example with respect to this invention. It is a principal part block diagram for demonstrating the other circuit structure periphery of the power supply adjustment device used as a reference example with respect to this invention. It is a principal part block diagram for demonstrating the other circuit structure periphery of the power supply adjustment device used as a reference example with respect to this invention. It is a principal part block diagram for demonstrating the other circuit structure periphery of the power supply adjustment device used as a reference example with respect to this invention. It is a block diagram of a regulator. It is a principal part block diagram for demonstrating an example of the image forming apparatus which has a laser beam scanning apparatus. It is the figure which showed control of the laser beam scanning device as an image writing part, and a laser beam scanning device periphery. It is the figure which showed the PLL circuit and its peripheral circuit. It is the schematic of a write clock generation part. It is a block diagram of the PLL circuit and logic circuit in a prior art.

Explanation of symbols

DESCRIPTION OF SYMBOLS 1 ... Charging device, 2 ... Developing device, 3 ... Transfer device, 4 ... Fixing device, 5 ... Cleaning device, 6 ... Staticator, 7 ... Recording paper, 10 ... LD modulation device, 10 ( _10K , _10M , 10 _C , 10 _Y ): logic circuit, 11 (11 _K , 11 _M , 11 _C , 11 _Y ): LD (laser diode), 12: laser beam, 13: polygon mirror, 14: fθ lens, 15: photoconductor, DESCRIPTION OF SYMBOLS 16, 17 ... Sensor, 21 ... Time difference measurement part, 22 ... Magnification correction control part, 23 ... Write clock generation part, 23a ... Frequency modulation part, 23b ... Phase control part, 24 ... CPU, 30 ( _30K , _30M , 30 _C , 30 _Y ) ... PLL circuit, 30 ₁ ... phase comparator, 30 ₂ ... loop filter, 30 ₃ ... VCO (voltage controlled oscillator), 31 ... crystal oscillator, 32, 33 ... frequency divider, 35 ... Power supply, 40 ... Picture Forming apparatus, 41 ... PSU (power supply _{unit), 42,42 K, 42 M,} 42 C, 42 Y ... power adjusting device, 50 ... IC _{package, 50 1, 50 1 ... ASIC} (IC package), 51 (51 _{K, 51 M, 51 C,} 51 Y) ... regulator, 52 ... pass transistor unit, 53 ... error amplifier, 54 ... reference voltage unit, 55 ... detection _{unit, 60 (60 K, 60 M} , 60 C, 60 Y ) ... LD driver.

Claims (1)

It has four LDs that generate light beams corresponding to each of Y (yellow), M (magenta), C (cyan), and K (black) , and four PLL circuits provided corresponding to each LD. In an image forming apparatus that scans one or a plurality of photosensitive members by modulating the light beam according to an image signal, a write clock generation for generating a write clock synchronized with the image signal for each of the four light beams And the write clock generation means includes the PLL circuit including the VCO, and the input voltage is used as a reference for the VCO in the PLL circuit for M (magenta), C (cyan), and K (black) . If the input voltage is lower than the reference voltage, the output voltage will increase.If the input voltage is higher than the reference voltage, the output voltage will be lower. Working to supply power via the power adjustment means for suppressing the power fluctuation, for the VCO in the PLL circuit for Y (yellow), has directly the power to be supplied not via the power regulation means An image forming apparatus.