JP4451072B2 - Nonvolatile memory element, nonvolatile memory circuit, nonvolatile memory card, and recording / reproducing apparatus - Google Patents

Description

【０１４２】
状態１においては、Ｔｒ_i，Ｔｒ_jがともにＯＮ状態であり、Ｘ_i電位とＹ_j電位がともに＋Ｖとなるため、第３導電体Ｒ_ijには電流が流れず、第３導電体Ｒ_ijの溶断は発生しない。
【０１４３】
状態２においては、Ｔｒ_iがＯＮ、Ｔｒ_jがＯＦＦとなり、Ｘ_i電位が＋Ｖ、Ｙ_i電位が接地電位（０Ｖ）となって電位差Ｖが発生する。これによって、第３導電体Ｒ_ijとＹ_jに対する接地抵抗Ｒ_jとを通過する電流と、Ｘ_iに対する接地抵抗Ｒ_iを通過する電流とが流れることになる。ここで、Ｒ_ijとＲ_jとの直列抵抗よりもＲ_iを十分大きくしておくことにより、第１導電体Ｘ_iから第２導電体Ｙ_jへ向かって第３導電体Ｒ_ijに、より大きな電流が流れ、第３導電体Ｒ_ijが溶断される。
【０１４４】
状態３においては、Ｔｒ_iがＯＦＦ、Ｔｒ_jがＯＮとなり、Ｘ_i電位が＋Ｖ’、Ｙ_j電位が＋Ｖとなる。ここで、Ｘ_i電位（＋Ｖ’）は、Ｙ_j電位（＋Ｖ）を第３導電体Ｒ_ijとＲ_iとで分圧した電位である。この場合、Ｘ_iに対する接地抵抗Ｒ_iが、Ｙ_jに対する接地抵抗Ｒ_jよりも十分大きく成されているため、第３導電体Ｒ_ijに流れる電流が小さくなる。この結果、第３導電体Ｒ_ijの溶断は発生しない。
【０１４５】
状態４においては、Ｔｒ_i，Ｔｒ_jがともにＯＦＦ状態であり、Ｘ_i電位とＹ_j電位がともに接地電位（０Ｖ）となるため、第３導電体Ｒ_ijには電流が流れず、第３導電体Ｒ_ijの溶断は発生しない。
【０１４６】
このように、特定の第１導電体Ｘ_iを駆動するトランジスタＴｒ_iをＯＮ状態とし、それ以外の第１導電体３を駆動するトランジスタをＯＦＦ状態とし、第２導電体（Ｙ₁，Ｙ₂，・・・，Ｙ_M）を駆動するトランジスタを、記録情報に従って、ＯＮ状態、もしくは、ＯＦＦ状態とすることにより、特定の第１導電体Ｘ_iに接続されたＭ個の第３導電体６の溶断の有無を制御すること、すなわち、情報を記録することが可能となる。
【０１４７】
上記不揮発性記憶素子は、図６と図７に示す状態を判別することにより、記録された情報を再生することが可能である。例えば、特定の第２導電体Ｙ_jを駆動するトランジスタＴｒ_jをＯＮ状態として、第１導電体Ｘ₁〜Ｘ_Nを駆動するトランジスタＴｒ_iを順次ＯＦＦ状態としながら、第１導電体Ｘ_iの電位を順次測定することにより、特定の第２導電体Ｙ_jと第１導電体Ｘ₁〜Ｘ_Nとの交差位置に設けられたＮ個の第３導電体６の状態、すなわち、記録情報を再生することが可能である。
【０１４８】
図６の場合、第３導電体Ｒ_ijが接続状態にあるので、表１の状態３に示すように、第１導電体Ｘ_iの電位は＋Ｖ’となる。一方、図７の場合、第３導電体Ｒ_ijが溶断状態にあるので、第１導電体Ｘ_iの電位は接地電位（０Ｖ）となる。このように、第３導電体６の溶断の有無により、第１導電体２に誘起される電位が異なる。
【０１４９】
従って、第２導電体５に電圧を印加し、第１導電体３の電位を検出することにより、第３導電体６の溶断の有無、すなわち、記録された情報を再生することが可能となる。
【０１５０】
なお、上記の説明では、記録時に第２導電体Ｙ₁〜Ｙ_Mを順次選択すると共に、再生時に第１導電体Ｘ₁〜Ｘ_Nを順次選択する例を説明したが、第１導電体Ｘ₁〜Ｘ_Nおよび第２導電体Ｙ₁〜Ｙ_Mのいずれを順次選択するかについては、適宜変更可能である。
【０１５１】
また、図６及び図７に示すトランジスタや接地抵抗は、後述する不揮発性記憶回路の記録再生制御回路（例えば図８）の一部であるＸデコーダ１９内およびＹデコーダ２０により駆動されるデータ入力回路２２内に設けることが可能である。
【０１５２】
（不揮発性記憶回路の構成）
次に、本発明の不揮発性記憶素子１０を用いた不揮発性記憶回路１１について、図８に示す概略ブロック図を用いて説明する。
【０１５３】
不揮発性記憶回路１１は、半導体層（図示せず）上に設けられており、アドレス信号Ａ０〜Ａｉ（ｉ：自然数）を受けるアドレス入力端子１２と、外部から入力される、外部クロックＣＬＫ、Ｘアドレスストローブ信号ＸＡＳ、Ｙアドレスストローブ信号ＹＡＳ、ライトイネーブル信号ＷＥ、および素子セレクト信号ＣＳ等を受ける制御信号入力端子１３と、外部から電源電位ＶＣＣおよび接地電位ＶＳＳをそれぞれ受ける電源端子１４と、データＤ０〜Ｄｊ（ｊ：自然数）の入出力を行うデータ入出力端子１５とを備えている。
【０１５４】
不揮発性記憶回路１１は、さらに、アドレス入力端子１２からアドレス信号Ａ０〜Ａｉを受けて、ＸアドレスＸＡおよびＹアドレスＹＡを示す内部アドレス信号に変換するアドレスバッファ１６と、制御信号入力端子１３から制御信号群を受けてそれぞれに対応する内部制御信号を生成する制御信号バッファ１７と、制御信号バッファ１７から内部制御信号群を受けて不揮発性記憶回路１１全体の内部動作を制御する制御回路１８とを備えている。
【０１５５】
不揮発性記憶回路１１は、さらに、行列状に配置された複数の第１導電体３及び第２導電体５と、第１導電体３と第２導電体５とを接続する第３導電体６を有する不揮発性記憶素子１０を備えている。
【０１５６】
不揮発性記憶回路１１は、さらに、アドレスバッファ１６が生成するＸアドレスＸＡに従って不揮発性記憶素子１０の第１導電体３の選択を実行するＸデコーダ１９と、アドレスバッファ１６が出力するＹアドレスＹＡに応じて第２導電体５の選択を実行するＹデコーダ２０と、後述するセンス回路２１及びデータ入力回路２２とを備えている。
【０１５７】
Ｘデコーダ１９は、第１導電体３の選択時において、アドレスバッファ１６が出力するＸアドレスＸＡに応じて、不揮発性記憶素子１０中の第１導電体３のうちの少なくとも１本を記録再生のために選択的に活性化する。具体的には、記録再生方法について説明した図６において示した第１導電体Ｘ_iに接続されたトランジスタＴｒ_iと接地抵抗Ｒ_iとが、少なくともＸデコーダ１９内に設けられている。
【０１５８】
Ｙデコーダ２０は、第２導電体５の選択時において、アドレスバッファ１６が出力するＹアドレスＹＡに応じて、不揮発性記憶素子１０中の第２導電体５のうちの少なくとも１本を記録再生のために選択的に活性化する。具体的には、記録再生方法について説明した図６において示した第２導電体Ｙ_jに接続されたトランジスタＴｒ_jと接地抵抗Ｒ_jとが、少なくともＹデコーダ２０内に設けられている。
【０１５９】
不揮発性記憶回路１１は、さらに、データ入出力端子１５との間でデータ授受を実行するためのデータ出力バッファ２３およびデータ入力バッファ２４を備えている。データ出力バッファ２３およびデータ入力バッファ２４は、制御回路１８が生成するクロック信号に同期したタイミングでデータ入出力を実行する。
【０１６０】
データ入力バッファ２４から送出されたデータは、データ入力回路２２へと入力される。データ入力回路２２は、Ｘデコーダ１９とＹデコーダ２０の選択結果に対応して、第３導電体６に印加する電圧を入力されたデータに基づいて制御して、第３導電体６の溶断の実行、すなわち、不揮発性記憶素子の各交差位置に対する記録を行う。
【０１６１】
また、センス回路２１は、Ｘデコーダ１９とＹデコーダ２０の選択結果に対応して、個々の不揮発性記憶素子の記録状態、すなわち、第３導電体６の溶断の有無を検出し、記録データの再生を行う。例えば、Ｙデコーダ２０により選択された第２導電体Ｙ_jに電圧を印加して、第１導電体Ｘ₁〜Ｘ_Nに誘起される電圧をセンス回路２１により順次測定することにより、記録情報を再生することが可能である。そして、センス回路２１で検出された再生信号は、データ出力バッファ２３へと送出される。
【０１６２】
不揮発性記憶回路１１は、さらに、電源端子１３に入力された外部電源電位ＶＣＣおよび外部接地電位ＶＳＳに応じて、不揮発性記憶回路１１内部で使用される電源電位＋Ｖ、および、接地電位を生成する電源回路２５を備えている。電源電位＋Ｖおよび接地電位は、不揮発性記憶回路１１内部の各回路に供給される。
【０１６３】
なお、上記不揮発性記憶回路において、アドレス入力端子１２、制御信号入力端子１３、電源端子１４、及び、データ入出力端子１５を含んで構成された部分が回路入出力端子である。また、アドレスバッファ１６、制御信号バッファ１７、制御回路１８、Ｘデコーダ１９、Ｙデコーダ２０、センス回路２１、データ入力回路２２、データ出力バッファ２３、データ入力バッファ２４、及び、電源回路２５等の半導体回路を含んで構成された部分が記録再生制御回路である。
【０１６４】
従って、本発明の不揮発性記憶回路は、例えばＳｉ基板、ガラス基板などの半導体層上において、複数の第１導電体及び複数の第２導電体が、それぞれ、上述の記録再生制御回路に接続され、かつ、この記録再生制御回路が上述の回路入出力端子に接続された構成であると言える。
【０１６５】
本発明の上記不揮発性記憶回路を用いることにより、アドレスに対応して、本発明の不揮発性記憶素子に対する、情報の記録再生を実現することが可能となる。
【０１６６】
（不揮発性記憶素子の構成例２）
次に、図９、及び、図１０は、本発明の不揮発性記憶素子の他の構成を示す平面図と断面図である。
【０１６７】
図１、及び、図２に示す不揮発性記憶素子においては、第１導電体３と第２導電体５との各交差位置において、第１導電体３と第２導電体５とが、一箇所のみで第３導電体６によって接続されていた。これに対し、図９、及び、図１０に示す不揮発性記憶素子においては、第１導電体３と第２導電体５との各交差位置において、第１導電体３と第２導電体５とが、２箇所で、第３導電体６によって接続されている。
【０１６８】
このような構成の、不揮発性記憶素子は、図３、及び、図４に示す製造方法において、第３導電体６をエッチングする際のマスクであるフォトレジストパターン９を、図９に示す第３導電体６に対応するパターンとすることにより形成することができる。
【０１６９】
この構成においては、第１導電体３と第２導電体５とが、第２導電体５の両側で、第３導電体６により電気的に接続されていることにより、個々の不揮発性記憶素子の初期不良の数を低減することが可能となる。すなわち、不揮発性記憶素子の形成時に、塵埃等の欠陥が存在し、ある交差位置の一方の接続箇所における第３導電体６に電気的な接続が維持されないような事態が発生した場合においても、他方の接続箇所における第３導電体６において電気的な接続が維持されることにより、１箇所の接続不良のために不揮発性記憶素子全体が不良となることを回避することができる。
【０１７０】
なお、図９に示す構成の不揮発性記憶素子において、各交差位置において第２導電体５の両側に対して１箇所ずつ合計２箇所の接続箇所を設けるのみならず、片側に対して２箇所以上の接続箇所を設けてもよい。
【０１７１】
（不揮発性記憶回路の構成例１）
次に、本発明の不揮発性記憶回路のさらに具体的な実施形態について、図１１から図２０を用いて説明する。
【０１７２】
図１１は、本発明の不揮発性記憶回路の一部を示す斜視図であり、アドレス入力端子１２、制御信号入力端子１３、電源端子１４、及び、データ入出力端子１５等で構成された回路入出力端子２７と、アドレスバッファ１６、制御信号バッファ１７、制御回路１８、Ｘデコーダ１９、Ｙデコーダ２０、センス回路２１、データ入力回路２２、データ出力バッファ２３、データ入力バッファ２４、及び、電源回路２５等の半導体回路により構成された記録再生制御回路２８とが、単結晶シリコンウエハーからなるＳｉ基板２６（半導体層）上に形成された構成となっている。
【０１７３】
図１２は、図１１に示すＳｉ基板２６上に形成された上記記録再生制御回路２８の上に、本発明の不揮発性記憶素子２９（図８に示す不揮発性記憶素子１０に相当）を設けた構成の不揮発性記憶回路の斜視図である。ここで、記録再生制御回路２８のＸデコーダ１９、及び、データ入力回路２２等の入出力配線と、不揮発性記憶素子２９の複数の第１導電体３、及び複数の第２導電体５とは、それぞれ、図示しない絶縁膜を介して、立体配線技術を用いて配線されている。
【０１７４】
ここで、上記記録再生制御回路２８と上記不揮発性記憶素子２９とを重ならないように設け、水平配線により配線することも可能である。しかし、この場合、Ｓｉ基板２６上に、記録再生制御回路２８を形成する領域と不揮発性記憶素子２９を形成する領域とを別々に設けることが必要となり、記憶容量が減少することになる。大きな記憶容量を実現するためには、図１１、及び、図１２に示すように、記録再生制御回路２８と不揮発性記憶素子２９とを重ねて配置し、図示しない絶縁膜を介して、立体配線技術を用いて配線することが望ましい。
【０１７５】
なお、図示しない上記絶縁膜は、記録再生制御回路２８と不揮発性記憶素子２９との電気的な干渉を避けるために設けるものであり、記録再生制御回路２８と不揮発性記憶素子２９との間で、絶縁不良が発生しないように設けられることが望ましい。
【０１７６】
また、上記説明においては、記録再生制御回路２８として、Ｓｉ基板上に設けた半導体回路により構成された記録再生制御回路２８を用いたが、これに限られるものではない。
【０１７７】
例えば、図１３、及び、図１４に示すように、Ｓｉ基板以外の基板３０、例えば、ガラス基板やプラスチック基板上に半導体回路からなる記録再生制御回路３３と回路入出力端子３１とを設け、図１１、及び、図１２と同様にして、上記記録再生制御回路３３上に、不揮発性記憶素子２９を重ねて配置し、立体配線技術を用いて配線することが可能である。
【０１７８】
ここで、基板３０としてガラス基板やプラスチック基板を用いる場合、半導体回路からなる上記記録再生制御回路３３は、基板３０上にスパッタリング法やＣＶＤ法により形成された非晶質Ｓｉ薄膜３２（半導体層）を用いて構成することが可能である。非晶質Ｓｉ薄膜には、半導体回路を形成することが可能である必要があり、その膜厚を５０ｎｍ〜２００ｎｍとすることが望ましい。なお、左記の上限値、下限値はおよその目安である。
【０１７９】
しかし、半導体回路として非晶質Ｓｉ薄膜を用いた場合、非晶質Ｓｉ薄膜の電子移動度が小さいため、高速での記録再生制御が困難となる。本発明の不揮発性記憶回路に対して、映像情報等の情報を記録再生するためには、その記憶容量のみならず、高速での記録再生を実現することが重要な課題となる。
【０１８０】
従って、本発明の不揮発性記憶素子１０に用いる記録再生制御回路３３としては、上記非晶質Ｓｉ薄膜３２に対して、レーザビーム等のエネルギービームを照射して、上記非晶質Ｓｉ薄膜３２を多結晶化した領域に、上記記録再生制御回路３３を設けることが望ましい。上記非晶質Ｓｉ薄膜３２が多結晶化されることにより、半導体回路における電子移動度が大きくなる。従って、記録再生制御回路の高速動作が実現され、本発明の不揮発性記憶回路を、映像情報等の情報の高速記録再生に適用することができる。
【０１８１】
また、本実施例によれば、高価なＳｉ基板を用いず、安価なガラス基板やプラスチック基板を使用することができるため、低価格な不揮発性記憶回路を提供することが可能である。さらに、プラスチック基板を用いることにより、割れによる破損を防止することが可能であり、ガラス基板に比べて、携帯性に優れた不揮発性記憶回路を提供することが可能である。
【０１８２】
（不揮発性記憶回路の構成例２）
次に、図１５、及び、図１６は、一つの基板３０上に、複数の記録再生制御回路３４と、それぞれの記録再生制御回路３４に対応する複数の不揮発性記憶素子３５とが設けられた構成を示している。ここで、基板３０としては、図１１、及び、図１２に示すＳｉ基板であっても良いが、不揮発性記憶回路の低価格化を実現するためには、図１３、及び、図１４と同様に、Ｓｉ基板以外の基板を用いることが望ましい。
【０１８３】
また、図１３、及び、図１４の場合と同様に、レーザアニール処理により多結晶化された多結晶Ｓｉを用いて、記録再生制御回路３４を形成することにより、記録再生制御回路の高速動作が実現され、本発明の不揮発性記憶回路を、映像情報等の情報の高速記録再生に適用することができる。
【０１８４】
図１５、及び、図１６に示す不揮発性記憶回路においては、回路入出力端子３１と、それぞれの記録再生制御回路３４とが接続され、アドレス情報やデータ情報の授受が行われる。また、複数の上記記録再生制御回路３４のそれぞれに対して、不揮発性記憶素子３５が重ねて配置され、立体配線技術を用いて配線されている。
【０１８５】
図１３、及び、図１４に示す不揮発性記憶回路においては、基板上に一つの不揮発性記憶素子２９が設けられた構成となっている。従って、不揮発性記憶素子２９を構成する複数の第１導電体３及び複数の第２導電体５は、不揮発性記憶素子２９の長さとほぼ同程度の長さを有することになる。ここで、複数の上記第１導電体３、もしくは、複数の上記第２導電体５の一箇所に、欠陥による断線、もしくは、短絡が発生した場合、断線の発生した導電体に接続された個々の不揮発性記憶素子（個々の交差位置に対応；単位記憶素子と呼ぶ）は、すべて欠陥素子となってしまう。すなわち、一箇所の欠陥が、極めて多くの欠陥素子を発生させることになる。
【０１８６】
これに対して、図１５、及び、図１６に示す不揮発性記憶回路においては、複数の不揮発性記憶素子３５を、複数の記録再生制御回路３４にそれぞれ接続することにより、欠陥素子の数を低減することが可能である。例えば、基板３０のサイズが変わらないとすれば、図１６の場合、図１４の場合と比較して、不揮発性記憶素子３５の１つ分の容量は小さくなるものの、それぞれの不揮発性記憶素子３５が有する第１導電体３及び第２導電体５の長さを短くすることができる。このように、第１導電体３及び第２導電体５の長さが短くなると、一箇所の欠陥に起因する断線、もしくは、短絡により発生する欠陥素子の数を低減することが可能となる。
【０１８７】
（不揮発性記憶カードの構成例１）
図１１から図１６に示す本発明の不揮発性記憶回路を、回路基板上に配置し、回路入出力端子２７，３１を用いて、記録再生情報の入出力が可能な不揮発性記憶回路として用いることも可能であるが、大容量であり、かつ、低価格であるという特徴を生かして、可換型の不揮発性記憶回路とすることが可能である。
【０１８８】
すなわち、図１７に示すように、本発明の不揮発性記憶回路を、カード状基板３６の上に設け、不揮発性記憶カードとすることにより、大容量であり、かつ、低価格な記憶媒体を提供することができる。
【０１８９】
例えば、図１７に示す不揮発性記憶カードは、回路入出力端子３１に対して電気的に接触可能な接続ピンを有する記録再生装置に着脱可能に装着され、該記録再生装置が有する接続ピンを通じて、該不揮発性記憶カードと記録再生装置との間で、情報の記録再生が行われる。
【０１９０】
図１７は、カード状基板３６の上に、図１２、図１４、もしくは、図１６に示す不揮発性記憶回路を接着剤により貼り付けた構成であるが、カード状基板３６の上に、直接、記録再生制御回路３３，３４、及び、不揮発性記憶素子２９，３５を設けることも可能である。
【０１９１】
（不揮発性記憶カードの構成例２）
次に、図１８は、複数の不揮発性記憶回路がカード状基板３６の上に積層された構成の不揮発性記憶カードを示している。ここでは、複数の不揮発性記憶回路の回路入出力端子３１が積層方向に重ならないように、それぞれの不揮発性記憶回路が階段状に積層され、接着剤により張り合わせられている。
【０１９２】
該不揮発性記憶カードに対する記録再生は、記録再生装置に設けられた接続ピンを、露出した回路入出力端子３１に対して同時にまたは選択的に電気的に接触させ、記録再生情報の入出力を行うことにより実現される。
【０１９３】
このように、複数の不揮発性記憶回路を積層して設けることにより、さらに大容量の記憶容量を有する不揮発性記憶カードを提供することが可能となる。
【０１９４】
しかしながら、上記不揮発性記憶カードにおいては、複数の回路入出力端子３１のそれぞれに対して、アドレス情報や記録再生情報を入出力することが必要であり、記録再生装置の接続ピンの数が、不揮発性記憶回路の積層数に応じて増加し、かつ、記録再生装置の記録再生制御システムが複雑になるという問題が発生する。
【０１９５】
（不揮発性記憶カードの構成例３）
そこで、本構成例３では、入出力端子の数を増やすことなく、複数の不揮発記憶回路を積層することが可能な不揮発性記憶カードについて説明する。図１９及び図２０は、この不揮発性記憶カードについて説明する図である。
【０１９６】
本構成例３の不揮発性記憶カードは、図１９に示すように、カード状基板３６の上に、不揮発性記憶素子２９と、図示しない記録再生制御回路と、外部入出力端子４１と、上記外部入出力端子４１に接続された記憶回路選択回路３８とを有する第１の不揮発性記憶回路３７が、接着剤によりカード状基板３６の上に貼り付けられている。さらに、図２０に示すように、上記第１の不揮発性記憶回路３７及び記憶回路選択回路３８の上に、複数の第２の不揮発性記憶回路３９が、順次積層された構造となっている。
【０１９７】
上記複数の第２の不揮発性記憶回路３９は、それぞれ、入出力端子４０を有しており、該入出力端子４０は、それぞれ、該不揮発性記憶回路３９を貫通する孔を通じて、第１の不揮発性記憶回路３７が有する記憶回路選択回路３８に接続されている。
【０１９８】
記憶回路選択回路３８は、外部入出力端子４１から入力されたアドレス情報（第１の選択信号）に基づき、不揮発性記憶回路３７，３９から特定の不揮発性記憶回路を選択し、特定の不揮発性記憶回路に対する記録再生を実施することが可能である。
【０１９９】
さらに、記憶回路選択回路３８には、上記外部出力端子４１からもう一つのアドレス情報（第２の選択信号）が入力され、上記の選択された特定の不揮発性記憶回路において、活性化すべき（ＯＮすべき）第１導電体３および第２導電体５を選択し、不揮発性記憶素子に対して記録再生を実施することが可能である。
【０２００】
ここでは、第１の不揮発性記憶回路３７として、外部入出力端子４１と記憶回路選択回路３８と不揮発性記憶素子２９とを有する構成について記載しているが、第１の不揮発性記憶回路３７として、外部入出力端子４１と記憶回路選択回路３８とのみを有する構成とすることも可能である。
【０２０１】
図２１と図２２は、図２０に示す不揮発性記憶カードの記録再生を実施する不揮発性記憶回路の概略ブロック図を示している。
【０２０２】
図２１は、第１の不揮発性記憶回路３７を示し、アドレス信号Ａ０〜Ａｉ（ｉ：自然数）（第１の選択信号及び第２の選択信号）を受けるアドレス入力端子５０と、外部から入力される、外部クロックＣＬＫ、Ｘアドレスストローブ信号ＸＡＳ、Ｙアドレスストローブ信号ＹＡＳ、ライトイネーブル信号ＷＥ、及び素子セレクト信号ＣＳ等を受ける制御信号入力端子５１と、外部から電源電位ＶＣＣ及び接地電位ＶＳＳをそれぞれ受ける電源端子５２と、データＤ０〜Ｄｊ（ｊ：自然数）（記録再生の情報信号）の入出力を行なうデータ入出力端子５３とからなる上記外部入出力端子４１とが設けられている。
【０２０３】
次に、外部入出力端子４１は、記憶回路選択回路３８へと接続されており、記憶回路選択回路３８は、入力されたアドレス信号情報に応じて、選択すべき不揮発性記憶回路３７または３９を決定する。
【０２０４】
一方、図２１及び図２２に示すように、それぞれの不揮発性記憶回路３７，３９は、個々に、記憶回路選択回路３８から送出されるアドレス信号Ａ０〜Ａｉ（ｉ：自然数）を受けるアドレス入力端子６０と、外部クロックＣＬＫ、Ｘアドレスストローブ信号ＸＡＳ、Ｙアドレスストローブ信号ＹＡＳ、ライトイネーブル信号ＷＥ、及び素子セレクト信号ＣＳ等を受ける制御信号入力端子６１と、電源電位ＶＣＣ及び接地電位ＶＳＳをそれぞれ受ける電源端子６２と、データＤ０〜Ｄｊ（ｊ：自然数）の入出力を行なうデータ入出力端子６３とからなる上記入出力端子４０を備えており、記憶回路選択回路３８により決定された不揮発性記憶回路３７，３９の入出力端子４０と外部入出力端子４１との接続が、記憶回路選択回路３８により行われる。
【０２０５】
上記入出力端子４０から、それぞれの不揮発性記憶回路１０への記録再生動作については、図８の場合と同様にして行われる。
【０２０６】
上記構成の不揮発性記憶カードにおいては、複数の不揮発性記憶回路が積層され、大容量の記憶容量を実現可能であるとともに、不揮発性記憶カードが有する外部入出力端子の数を必要最小限（記憶回路選択回路３８の外部入出力端子４１の数）とすることが可能である。従って、記録再生装置の入出力システムを簡略化でき、低価格な記録再生装置を提供することができる。
【０２０７】
また、上記実施形態においては、アドレスバッファ１６、電源回路２５、制御信号バッファ１７、制御回路１８、データ入力バッファ２４、データ出力バッファ２３が、それぞれの不揮発性記憶回路３７，３９に設けられた構成について説明したが、これらの回路（不揮発性記憶素子１０のドライバ回路）を記憶回路選択回路３８にまとめて設けると、個々の不揮発性記憶回路に含まれる記録再生制御回路の規模が小さくなり、不揮発性記憶回路の形成プロセスの簡略化と低コスト化を実現することができる。
【０２０８】
【実施例】
〔実施例１〕
本発明の実施例１として、図１及び図２に示す構成の不揮発性記憶素子を作製した。
【０２０９】
実施例１の不揮発性記憶素子は、半導体回路が設けられた単結晶Ｓｉからなる基板１上に、膜厚１００ｎｍのＳｉＯ₂からなる絶縁膜２が形成され、その上に、幅が０．３μｍであり、膜厚が１００ｎｍのＡｌ配線からなる第１導電体３と第２導電体５とが、膜厚が１００ｎｍのＳｉＯ₂からなる絶縁膜４を介して積層されている。そして、第１導電体３と第２導電体５とを、１箇所（各交差部分の片側）で電気的に接続する第３導電体６が設けられている。
【０２１０】
第３導電体５としては、Ａｌ薄膜を用い、その膜厚を５０ｎｍとし、その接続幅（第２導電体５の延伸方向と平行方向の幅）を０．２μｍとした。
【０２１１】
次に、一本の第１導電体Ｘ₄に、２．５Ｖの電圧を印加し、一本の第２導電体Ｙ₃を抵抗を介して接地することにより、第１導電体Ｘ₄から第２導電体Ｙ₃へと電流を流した。その結果、第１導電体Ｘ₄と第２導電体Ｙ₃とを接続する第３導電体６のみを溶断することができた。また、同様にして、第１導電体Ｘ₇から第２導電体Ｙ₃へと電流を流すことにより、第１導電体Ｘ₇と第２導電体Ｙ₃とを接続する第３導電体６のみを溶断することができた。
【０２１２】
次に、第２導電体Ｙ₃に、１．５Ｖの電圧を印加することにより、第２導電体Ｙ₃に接続された第３導電体５に、溶断の発生していない第１導電体Ｘ₁，Ｘ₂，Ｘ₃，Ｘ₅，Ｘ₆，Ｘ₈には、約１．５Ｖの電圧が誘起され、第３導電体５に溶断の発生している第１導電体Ｘ₄，Ｘ₇には、電圧が誘起されなかった。
【０２１３】
以上のことから、実施例１の不揮発性記憶素子においては、選択された１つの第１導電体３と、選択された１つの第２導電体５との間に電位差を設け、該第１導電体３と該第２導電体５とを接続する第３導電体６を溶断することにより、情報を記録することが可能であることが確認された。さらに、上記第１導電体３、もしくは、上記第２導電体５のいずれか一方の導電体に、上記第３導電体６における溶断が発生しない程度の電圧を印加し、他方の導電体の電位を検出することにより、上記第３導電体６における溶断の有無を判断し、情報を再生することが可能であることが確認された。
【０２１４】
次に、上記実施例と同じ構成の不揮発性記憶素子における第３導電体６の寸法を変更して、溶断の発生の有無を調査した結果、第３導電体６の幅を狭くし、第３導電体６の膜厚を薄くする程、第３導電体５の溶断に必要な電圧が小さくなることが確認された。また、第３導電体６の幅と膜厚を、第１導電体３及び第２導電体５と同一にすると、第３導電体６の溶断に必要となる電圧が高くなりすぎ、第１導電体３もしくは第２導電体５における溶断の発生が確認された。
【０２１５】
従って、第３導電体６の幅及び膜厚を、少なくとも、第１導電体２もしくは第２導電体４の幅及び膜厚よりも小さくすれば、第１導電体３、及び、第２導電体５に溶断を発生させることなく、第３導電体６のみを溶断することが可能であると言える。
【０２１６】
また、低消費電力を実現するためには、低電圧での第３導電体６の溶断が望ましい。そのためには、第３導電体６の幅を０．２５μｍ以下または第３導電体６の膜厚を６０ｎｍ以下とすることが望ましく、第３導電体６の幅および膜厚を、それぞれ０．２５μｍ以下及び６０ｎｍ以下とすることがさらに望ましい。
【０２１７】
一方、第３導電体６の幅及び膜厚を小さくし過ぎると、塵埃等の欠陥により発生するピンホールに起因して、未記録状態の第３導電体６において断線が発生することになる。未記録状態における初期断線を避けるためには、第３導電体６の幅を０．１μｍ以上または第３導電体６の膜厚を１０ｎｍ以上とすることが望ましく、第３導電体６の幅及び膜厚を、それぞれ０．１μｍ以上及び１０ｎｍ以上とすることがさらに望ましい。この場合でも、１％から２％の初期断線が存在するが、不揮発性記憶回路のトータル記憶容量を著しく低下させることはない。
【０２１８】
さらに、未記録状態における第３導電体６の断線を完全に避けるためには、第３導電体６の幅０．１８μｍ以上または第３導電体６の膜厚を２０ｎｍ以上とすることが望ましく、第３導電体６の幅及び膜厚を、それぞれ０．１８μｍ以上及び２０ｎｍ以上とすることがさらに望ましい。
【０２１９】
〔実施例２〕
本発明の実施例２として、図９及び図１０に示す構成の不揮発性記憶素子を作製した。
【０２２０】
実施例２の不揮発性記憶素子は、実施例と同様に、幅が０．３μｍであり、膜厚が１００ｎｍのＡｌ配線からなる第１導電体３と第２導電体５とが、膜厚が１００ｎｍのＳｉＯ₂からなる絶縁膜３を介して積層され、第１導電体３と第２導電体５とが、第３導電体６により２箇所（各交差部分の両側）で電気的に接続されている。
【０２２１】
第３導電体６は、第１導電体３及び第２導電体５と同じＡｌを用い、膜厚を１５ｎｍとし、第１導電体２及び第２導電体４の端部と接触する部分の幅を０．１μｍとした。
【０２２２】
次に、一本の第１導電体Ｘ₅に、２Ｖの電圧を印加し、一本の第２導電体Ｙ₃を抵抗を介して接地することにより、第１導電体Ｘ₅から第２導電体Ｙ₃へと電流を流した。これによって、第１導電体Ｘ₅と第２導電体Ｙ₃とを接続する第３導電体５のみを溶断することができた。また、同様にして、第１導電体Ｘ₇から第２導電体Ｙ₃へと電流を流すことにより、第１導電体Ｘ₇と第２導電体Ｙ₃とを接続する第３導電体６のみを溶断することができた。
【０２２３】
次に、第２導電体Ｙ₃に、２Ｖの電圧を印加することにより、交差する位置の第３導電体６に溶断の発生していない第１導電体Ｘ₁，Ｘ₂，Ｘ₃，Ｘ₄，Ｘ₆，Ｘ₈には、約２Ｖの電圧が誘起され、交差する位置の第３導電体５に溶断の発生している第１導電体Ｘ₅，Ｘ₇には、電圧が誘起されなかった。
【０２２４】
以上のことから、実施例２の不揮発性記憶素子においても、選択された１つの第１導電体３と、選択された１つの第２導電体５との間に電位差を設け、該第１導電体３と該第２導電体５とを接続する上記第３導電体６を溶断することにより、情報を記録することが可能であり、さらに、上記第１導電体３、もしくは、上記第２導電体５のいずれか一方の導電体に、上記第３導電体６における溶断が発生しない程度の電圧を印加し、他方の導電体の電位を検出することにより、上記第３導電体６における溶断の有無を判断し、情報を再生することが可能であることがわかる。
【０２２５】
第１導電体３と第２導電体５とを、片側１箇所のみで接続した実施例１において、未記録状態における初期断線を完全に避けるためには、第３導電体６の幅を０．１８μｍ以上とし、第３導電体の膜厚を２０ｎｍ以上とすることが望ましいことを説明した。これに対して、第１導電体２及び第２導電体５の両側の端部を接続した実施例２においては、第３導電体５の幅を０．１５μｍとし、膜厚を１５ｎｍとした場合においても、未記録状態における初期断線を完全に避けることができた。これは、第２導電体５の両側で接続することにより、片側で初期断線が発生しても、他方で接続が維持されたことにより、初期断線を抑制することができたことによるものである。
【０２２６】
このように、第２実施例においては、第１導電体３と第２導電体５とが、第２導電体５の両側２箇所で、電気的に接続されていることにより、初期断線による不揮発性記憶素子の初期不良を低減することができる。また、第３導電体６の膜厚を薄くすることが可能となり、第３導電体６の形成プロセス（成膜、エッチング）を簡略化できる。
【０２２７】
〔実施例３〕
本発明の実施例３として、実施例１と同一の構成の不揮発性記憶素子を、第１導電体３及び第２導電体５を構成する材料の融点よりも、融点の低い材料で形成された第３導電体６を用いて作製した。
【０２２８】
ここでは、第１導電体３及び第２導電体５として、融点が６６０℃のＡｌを用い、第３導電体５として、Ａｌ，Ｚｎ，Ｓｎ，Ｂｉ，ＡｌＺｎ合金，ＡｌＳｎ合金を用いた実施例について説明する。Ｚｎ，Ｓｎ，Ｂｉ，ＡｌＺｎ合金，ＡｌＳｎ合金の融点は、それぞれ、４２０℃，２３２℃，２７４℃，５１０℃，３２０℃であった。
【０２２９】
第１導電体３及び第２導電体５は、実施例１と同じく、その幅を０．３μｍとし、その膜厚を１００ｎｍとした。また、各第３導電体６については、その幅を０．２μｍとし、その膜厚を４０ｎｍとした。
【０２３０】
一本の第１導電体Ｘ₄に、実施例１よりも低い１．８Ｖの電圧を印加し、一本の第２導電体Ｙ₃を抵抗を介して接地することにより、第１導電体Ｘ₄から第２導電体Ｙ₃へと電流を流した。このときの第３導電体６の溶断発生について調べた結果、第３導電体６としてＡｌを用いた場合、実施例１と比較して印加する電圧が低いため、第３導電体６の溶断が発生しなかった。これに対して、第３導電体６としてＺｎ，Ｓｎ，Ｂｉ，ＡｌＺｎ合金，ＡｌＳｎ合金を用いた場合、実施例１と比較して、印加する電圧が低いにもかかわらず、第３導電体６の溶断が発生した。
【０２３１】
従って、第３導電体６として、第１導電体３及び第２導電体５の融点よりも低い融点を有する材料を用いることにより、より低電圧での溶断、すなわち、記録が可能であることが確認された。
【０２３２】
また、同様な実験を、ＡｌＢｉ合金，ＺｎＳｎ合金を用いて行った結果、同様に、低電圧での溶断が可能であることが確認された。
【０２３３】
次に、第１導電体３及び第２導電体５として、幅が０．３μｍであり、膜厚が１００ｎｍのＣｕ配線を用いた場合について、同様な検討を行った。
【０２３４】
第３導電体６としては、幅が０．２μｍであり、膜厚が４０ｎｍであるＡｌ，Ｚｎ，Ｓｎ，Ｂｉ，ＡｌＺｎ合金，ＡｌＳｎ合金を用い、第３導電体６において、確実に溶断が発生する印加電圧を調べた結果、第３導電体６の融点が低いほど、低電圧での溶断が実現可能であることを確認した。
【０２３５】
本発明は上述した各実施形態および実施例に限定されるものではなく、請求項に示した範囲で種々の変更が可能であり、異なる実施形態および実施例にそれぞれ開示された技術的手段を適宜組み合わせて得られる実施形態および実施例についても本発明の技術的範囲に含まれる。
【０２３６】
【発明の効果】
本発明に係る不揮発性記憶素子は、以上のように、絶縁膜を間に挟んで絶縁された第１導電体と第２導電体とを有し、第１導電体と第２導電体とが、該第１導電体と該第２導電体との間に形成された電位差によって溶断される第３導電体により電気的に接続されていてもよい。
【０２３７】
それゆえ、各導電体を平面的ではなく、立体的に配置することができるので、第１導電体と第２導電体とを平面的に配置する構成と比較して、個々の不揮発性記憶素子の占有面積を小さくすることができる。従って、不揮発性記憶素子の単位面積あたりの記憶容量を増大させることができるので、記憶容量の大きなヒューズ型の不揮発性記憶素子を提供することができる。
【０２３８】
また、情報記録のために溶断される部分が第３導電体として、第１導電体および第２導電体とは別に設けられていることによって、第３導電体の素材選択や、パターン幅選択、あるいは膜厚選択の自由度が増すと共に、各導電体のパターン幅が互いに及ぼしあう制約が緩和される。また、第１導電体および第２導電体に積層構造を取らせたことにより、第１導電体および第２導電体の膜厚設定の自由度も増す。
【０２３９】
これにより、記憶容量をより増大させる設計や、不揮発性記憶素子の消費電力を下げる等の設計も容易になるという種々の効果を併せて奏する。
【０２４０】
また、本発明に係る不揮発性記憶素子は、以上のように、絶縁膜を間に挟んで絶縁された複数の第１導電体と複数の第２導電体と、第１導電体と第２導電体との間に与えた電位差によって溶断する第３導電体とを有し、該第１導電体と該第２導電体とがマトリクス状に互いに交差するように配置されており、第１導電体、絶縁膜および第２導電体からなる３層構造における、該第１導電体と該第２導電体との各交差位置において、該第１導電体及び該第２導電体の各外表面の少なくとも一部同士が、上記第３導電体により電気的に接続されていることを特徴としている。
【０２４１】
それゆえ、第１導電体と第２導電体とを特定することにより、記録再生を行うべき位置情報を特定することができるので、各交差位置に、１つの単位記憶素子が形成されているとみなせる。各交差位置では、第１導電体と第２導電体とに積層構造を取らせているので、単位記憶素子の占有面積を小さくすることができる。したがって、不揮発性記憶素子の記憶容量を上げることができる。
【０２４２】
また、第３導電体の素材選択や、各導電体のパターン幅または膜厚の設定に自由度が有るので、不揮発性記憶素子のさらなる大容量化と低消費電力化とを図ることができるという効果を併せて奏する。
【０２４３】
また、本発明に係る不揮発性記憶素子は、以上のように、上記の構成に加えて、上記各交差位置の少なくとも１箇所における第３導電体の切断により、情報が記録されていることを特徴としている。
【０２４４】
これにより、既に説明したとおり、大容量の情報を記録した不揮発性記憶素子を提供することができる。
【０２４５】
また、本発明に係る不揮発性記憶素子は、以上のように、上記の構成に加えて、上記第３導電体の幅が、上記第１導電体の幅、及び、上記第２導電体の幅よりも狭いことを特徴としている。
【０２４６】
それゆえ、配線パターンである第１導電体の幅と第２導電体の幅に対して、溶断部である第３導電体の幅を狭くして、第３導電体の抵抗を大きくすることが可能となる。従って、第１導電体と第２導電体との間に電位差を形成することにより、第１導電体と第２導電体とを接続する第３導電体に電流が流れ、抵抗の大きい第３導電体のみにおいて温度が上昇し、第３導電体のみを安定して溶断することが可能となり、不揮発性記憶素子の記録動作を安定化することができるというさらなる効果を奏する。
【０２４７】
また、本発明に係る不揮発性記憶素子は、以上のように、上記の構成に加えて、上記第３導電体の膜厚が、上記第１導電体の膜厚、及び、上記第２導電体の膜厚よりも薄いことを特徴としている。
【０２４８】
それゆえ、配線パターンである第１導電体の膜厚と第２導電体の膜厚に対して、切断部である第３導電体の膜厚を薄くして、第３導電体の抵抗を大きくすることが可能となる。従って、第１導電体と第２導電体との間に電位差を形成することにより、第１導電体と第２導電体とを接続する第３導電体に電流が流れ、抵抗の大きい第３導電体のみにおいて温度が上昇し、第３導電体のみを安定して溶断することが可能となり、不揮発性記憶素子の記録動作を安定化することができるというさらなる効果を奏する。
【０２４９】
また、本発明に係る不揮発性記憶素子は、以上のように、上記の構成に加えて、上記第３導電体の融点が、上記第１導電体の融点、及び、上記第２導電体の融点よりも低いことを特徴としている。
【０２５０】
それゆえ、より融点の低い材料を用いた第３導電体において、溶断が発生しやすくなり、第３導電体のみを安定して溶断することが可能となる。また、第３導電体を溶断するために、第１導電体及び第２導電体の間に設ける電位差を小さくすることもできる。この結果、安定した記録再生及び／または低消費電力を実現する不揮発性記憶素子を提供することができるというさらなる効果を奏する。
【０２５１】
また、本発明に係る不揮発性記憶素子は、以上のように、上記の構成に加えて、
上記第１導電体が、直線帯状であって互いに並列的に配置されており、上記第２導電体もまた、直線帯状であって互いに並列的に配置されていることを特徴としている。
【０２５２】
それゆえ、第１導電体及び第２導電体が、いずれも、直線帯状の導電体で構成され、屈曲部を有さないことにより、単位面積当たりにおける交差位置の数を、屈曲部を持つ構成に比べて増やすことができる。すなわち、交差位置に設けることが可能な第３導電体の数を増やすことができるので、不揮発性記憶素子の記憶容量をさらに増大させることができるというさらなる効果を奏する。
【０２５３】
また、本発明に係る不揮発性記憶素子は、以上のように、上記の構成に加えて、上記第１導電体と第２導電体の各外表面を上記第３導電体により接続する箇所は、各交差位置毎に少なくとも２箇所有ることを特徴としている。
【０２５４】
それゆえ、上記第１導電体と第２導電体とが各交差位置毎に２箇所以上の部分で、該接続体により接続されていれば、一方の接続体が断線を発生した場合においても、他方の接続体が、第１導電体と第２導電体とを接続しているため、断線による初期不良素子を大幅に低減することができるというさらなる効果を奏する。
【０２５５】
また、本発明に係る不揮発性記憶回路は、以上のように、上記の構成に加えて、上記の不揮発性記憶素子が記録再生制御回路を有する半導体層上に設けられており、複数の上記第１導電体、及び、複数の上記第２導電体が、それぞれ、該記録再生制御回路に接続され、かつ、該記録再生制御回路が回路入出力端子に接続されていることを特徴としている。
【０２５６】
それゆえ、回路入出力端子から入力されるアドレス情報、及び、記録情報に基づいて、記録再生制御回路が、第１導電体、及び、第２導電体を選択し、その結果として選択された第３導電体に対し、情報の記録再生を実施することが可能となる。
【０２５７】
すなわち、本発明の不揮発性記憶回路においては、それぞれの第１導電体、及び、第２導電体を直接選択することなく、回路入出力端子に対して、アドレス情報と記録情報だけを入力することにより、記録再生を行うことができるので、不揮発性記憶回路としての利便性が格段に改善されるというさらなる効果を奏する。
【０２５８】
また、本発明に係る不揮発性記憶回路は、以上のように、上記構成に加えて、複数の上記不揮発性記憶素子が上記半導体層上に設けられており、該不揮発性記憶素子毎に記録再生制御回路を設けたことを特徴としている。
【０２５９】
それゆえ、上記の効果に加えて、不揮発性記憶回路が、複数の不揮発性記憶素子に分割されることにより、個々の不揮発性記憶素子における配線長が、相対的に短くなり、一箇所の断線により失われる記録素子の数を低減することが可能となる。
【０２６０】
さらに、複数の不揮発性記憶素子が、それぞれに対応した記録再生制御回路を有する構成とすることで、それぞれの記録再生制御回路に対して、配線の幅を相対的に広げることができる。従って、配線欠陥による記憶素子の損失を低減することも可能となるというさらなる効果を併せて奏する。
【０２６１】
また、本発明に係る不揮発性記憶回路は、以上のように、上記の構成に加えて、上記記録再生制御回路を形成するための半導体層が、基板上に設けられた非晶質Ｓｉ層、基板上に設けられた多結晶Ｓｉ層、もしくは、基板上に設けられた非晶質Ｓｉ層を局所的に温度上昇させることにより作製された多結晶Ｓｉ層のいずれかであることを特徴としている。
【０２６２】
それゆえ、上記の効果に加えて、基板材料が限定されることがなくなり、低価格で、かつ、記憶容量の大きい不揮発性記憶回路を形成することが可能となるというさらなる効果を奏する。
【０２６３】
また、上記の効果に加えて、半導体層として上記多結晶Ｓｉ層を用いることにより、高速記録再生可能な不揮発性記憶回路とすることができるというさらなる効果を併せて奏する。
【０２６４】
また、本発明に係る不揮発性記憶回路は、以上のように、上記の構成に加えて、上記不揮発性記憶素子が、半導体層上に設けられた記録再生制御回路の上に、絶縁膜を介して設けられており、複数の上記第１導電体、及び、複数の上記第２導電体が、それぞれ、該記録再生制御回路に接続され、かつ、該記録再生制御回路が回路入出力端子に接続されていることを特徴としている。
【０２６５】
それゆえ、上記記録再生制御回路上に、不揮発性記憶素子を立体的に設けることにより、基板上の面を有効に活用することが可能となり、不揮発性記憶回路の記憶容量をさらに増大させることができるという効果を奏する。
【０２６６】
さらに、複数の不揮発性記憶素子のそれぞれに対して、記録再生制御回路を有する場合においても、該記録再生制御回路の上に絶縁膜を形成し、該絶縁膜上に、対応する不揮発性記憶素子を設けることによっても、同様に、不揮発性記憶回路の記憶容量を増大させることができるというさらなる効果を奏する。
【０２６７】
また、本発明に係る不揮発性記憶回路は、以上のように、上記の構成に加えて、複数の上記不揮発性記憶回路が、複数積層されて設けられていることを特徴としている。
【０２６８】
それゆえ、上記の効果に加えて、複数の不揮発性記憶回路が積層されることにより、積層数に応じて、その記憶容量を増大させることができるというさらなる効果を奏する。
【０２６９】
また、本発明に係る不揮発性記憶回路は、以上のように、上記の構成に加えて、複数の上記不揮発性記憶回路が有する回路入出力端子が、積層方向に重ならないように設けられていることを特徴としている。
【０２７０】
それゆえ、上記の効果に加えて、積層された複数の不揮発性記憶回路のそれぞれの素子入出力端子に対して、アドレス情報や記録情報を直接入出力することが可能となるので、高速な記録再生動作を実現することができるというさらなる効果を奏する。
【０２７１】
また、本発明に係る不揮発性記憶回路は、以上のように、上記の構成に加えて、外部入出力端子に接続された記憶回路選択回路を有し、複数の上記不揮発性記憶回路の回路入出力端子が、該記憶回路選択回路に接続され、該記憶回路選択回路には、記録再生を行う不揮発性記憶回路を選択する第１の選択信号と、選択された不揮発性記憶回路の活性化すべき第１導電体および第２導電体を選択する第２の選択信号と、記録再生すべき情報信号とが、外部入出力端子を介して入力されることを特徴としている。
【０２７２】
それゆえ、同じ外部入出力端子を介して、第１の選択信号、第２の選択信号および情報信号が記憶回路選択回路に入力され、これによって記録再生すべき不揮発性記憶回路中の記録再生すべき第３導電体を選択して、情報を記録することができる。従って、複数の不揮発性記憶回路が積層された不揮発性記憶回路において、外部入出力端子の数を低減することができる。すなわち、情報の記録再生を行うための入出力回路を簡素化することが可能となり、利便性に優れた不揮発性記憶回路を提供することができるというさらなる効果を奏する。
【０２７３】
また、本発明に係る不揮発性記憶カードは、以上のように、上記不揮発性記憶回路が、カード状基板上に設けられたことを特徴としている。
【０２７４】
それゆえ、大きな記憶容量の不揮発性記憶回路を有する可搬性及び利便性に優れた不揮発性記憶カードを実現することが可能であるという効果を奏する。
【０２７５】
また、本発明に係る記録再生装置は、以上のように、上記不揮発性記憶素子、もしくは、上記不揮発性記憶回路、もしくは、上記不揮発性記憶カードに対して、情報の記録再生を行うことを特徴としている。
【０２７６】
それゆえ、従来のハードディスク装置や光ディスク装置に必要な、ディスク回転機構やヘッドアクセス機構等の可動部を有さず、記録再生に固定的なコネクタ等を適用することができるので、極めて信頼性の高い記録再生装置を実現することができるという効果を奏する。
【０２７７】
さらに、従来の記録再生装置として、半導体回路で構成された記憶素子（フラッシュメモリー等）を用いた記録再生装置があるが、複雑な半導体回路をＳｉ基板上に形成することが必要であり、記録素子が高価なものとなり、動画等の情報を長時間にわたり記憶する素子としては不適格であった。これに対して、本発明の不揮発性記憶素子、及び、不揮発性記憶回路は、配線パターンである第１導電体と第２導電体の交差点において、第１導電体の端部と第２導電体の端部とを接続する第３導電体を有するという、極めて簡単な構成により、情報の記録再生が可能であり、低価格かつ大容量な不揮発性記憶素子、及び、不揮発性記憶回路を提供することが可能である。また、該不揮発性記憶素子、及び、該不揮発性記憶回路を積層して配置することにより、さらに大容量の不揮発性記憶素子を提供することが可能である。従って、本発明に係る上記不揮発性記憶素子、もしくは、上記不揮発性記憶回路、もしくは、上記不揮発性記憶カードを用いた記録再生装置においては、動画等の大容量の情報を安価な不揮発性記憶素子に記憶することが可能となるというさらなる効果を併せて奏する。
【図面の簡単な説明】
【図１】本発明の不揮発性記憶素子の平面構成例を示す説明図である。
【図２】図１に示す不揮発性記憶素子の断面の構成を、図１のＡ−Ａ’線に沿って示す説明図である。
【図３】（ａ）〜（ｃ）は、本発明の不揮発性記憶素子の形成方法を示す工程説明図である。
【図４】（ａ）〜（ｃ）は、図３（ａ）〜（ｃ）の工程に後続する工程を示す工程説明図である。
【図５】本発明の不揮発性記憶素子の等価回路図である。
【図６】本発明の不揮発性記憶素子の記録再生に使用する半導体回路の回路図である。
【図７】上記半導体回路の記録状態を示す回路図である。
【図８】本発明の不揮発性記憶回路の構成を示す概略ブロック図である。
【図９】本発明の不揮発性記憶素子の他の平面構成例を示す説明図である。
【図１０】図９に示す不揮発性記憶素子の断面の構成を、図９のＡ−Ａ’線に沿って示す説明図である。
【図１１】本発明の不揮発性記憶回路における基板面の構成を説明する模式的な斜視図である。
【図１２】本発明の不揮発性記憶回路の全体構成を示す模式的な斜視図である。
【図１３】本発明の不揮発性記憶回路における基板面の他の構成を説明する模式的な斜視図である。
【図１４】本発明の不揮発性記憶回路の他の全体構成を示す模式的な斜視図である。
【図１５】本発明の不揮発性記憶回路における基板面のさらに他の構成を説明する模式的な斜視図である。
【図１６】本発明の不揮発性記憶回路のさらに他の全体構成を示す模式的な斜視図である。
【図１７】本発明の不揮発性記憶カードの一構成例を示す模式的な斜視図である。
【図１８】本発明の不揮発性記憶カードの他の構成例を示す模式的な斜視図である。
【図１９】本発明の不揮発性記憶カードのさらに他の構成例の一部を示す模式的な斜視図である。
【図２０】本発明の不揮発性記憶カードのさらに他の全体構成を示す模式的な斜視図である。
【図２１】図２０に示す不揮発性記憶カードの最下層に搭載する不揮発性記憶回路の構成を示す概略ブロック図である。
【図２２】図２０に示す不揮発性記憶カードの下から２層目以上の層に搭載する不揮発性記憶回路の構成を示す概略ブロック図である。
【図２３】従来の不揮発性記憶素子の平面構成を示す説明図である。
【符号の説明】
１ 基板
３ 第１導電体
４ 絶縁膜
５ 第２導電体
６ 第３導電体
７、８ 絶縁体
９ フォトレジストパターン
１０、２９ 不揮発性記憶素子
１１、３７、３９ 不揮発性記憶回路
２６ Ｓｉ基板（半導体層）
２７、３１ 回路入出力端子
２８、３３、３４ 記録再生制御回路
３０ 基板
３２ 非晶質Ｓｉ薄膜（半導体層）
３６ カード状基板
３８ 記憶回路選択回路
４１ 外部入出力端子[0001]
BACKGROUND OF THE INVENTION
The present invention relates to a nonvolatile memory element.
[0002]
[Prior art]
As a conventional nonvolatile memory element, for example, a fuse element having a cut portion 101 in which a pattern width of a part of a conductor pattern 100 is narrowed as shown in FIG. 23 is known (for example, see Patent Document 1).
[0003]
The fuse element shown in FIG. 23 includes a conductor pattern 100 having a uniform film thickness and a cut portion 101, and a cut portion 101 having a width narrower than that of the conductor pattern 100 in accordance with recorded information. The information is recorded by forming a potential difference at both ends of the substrate and flowing a current I that can melt the cutting portion 101.
[0004]
Further, information is reproduced by confirming the presence or absence of conduction depending on whether or not the cutting part 101 is melted.
[0005]
[Patent Document 1]
JP 2002-197884 A (published July 12, 2002)
[0006]
[Problems to be solved by the invention]
However, in the above-described conventional configuration, due to the factors described below, the size of each nonvolatile memory element (fuse element) increases, and the number of elements that can be formed per unit area is limited. Has the problem.
[0007]
The first reason is that in the conductor pattern 100, a portion to which a positive voltage is applied and a portion to which a negative voltage is applied have a two-dimensional spread.
[0008]
The second reason is that the conductor pattern 100 becomes wider than the minimum line width that can be patterned.
[0009]
For example, in the fuse element shown in FIG. 23, since the element is provided in a plane, the film thickness of the conductor pattern 100 and the film thickness of the cutting portion 101 are equal. Here, in order to generate fusing only by the cutting portion 101 without causing the fusing of the conductor pattern 100, the width of the cutting portion 101 is made narrower than the width of the conductive pattern 100 as described above, and cutting is performed. It is necessary to increase the electrical resistance in the portion 101. As a result, the temperature of only the cutting part 101 rises, and no fusing occurs in the conductor pattern 100, so that only the cutting part 101 can be cut.
[0010]
By the way, the minimum line width that can be realized with respect to the pattern dimensions of conductors and the like is determined by the patterning process, and the minimum line width of about 0.1 μm to 0.5 μm is realized depending on the capability of the patterning device Is possible.
[0011]
Here, in the fuse element shown in FIG. 21, since the width of the cut portion 101 cannot be made smaller than the minimum line width, the minimum line width needs to be the pattern width of the cut portion 101. On the other hand, the width of the conductor pattern 100 needs to be wider than the width of the cut portion 101 so that the conductor pattern does not melt when the current I flows. Therefore, the width of the conductor pattern 100, which is the wiring of the fuse element, must be made wider than the minimum line width that can be formed by the patterning process, so that the increase in storage capacity is hindered.
[0012]
In the fuse element shown in FIG. 23, the conductor pattern 100 and the cut portion 101 are made of the same material and the same film thickness. Therefore, it is necessary to control the presence or absence of fusing by adjusting only these pattern widths, so that there is a problem that the degree of freedom in designing the fuse element is small.
[0013]
The present invention has been made to solve the above-described problems, and an object of the present invention is to provide a nonvolatile memory element having a large degree of freedom in element design and capable of increasing the capacity. Furthermore, the objective of this invention is providing the non-volatile memory circuit excellent in the convenience using this non-volatile memory element, a non-volatile memory card, and the recording / reproducing apparatus using them.
[0014]
[Means for Solving the Problems]
The nonvolatile memory element, nonvolatile memory circuit, nonvolatile memory card, and recording apparatus of the present invention that solve the above-described problems are as follows.
[0015]
  The nonvolatile memory element according to the present invention is, AbsolutelyA first conductor and a second conductor insulated with an edge film interposed therebetween, wherein the first conductor and the second conductor are between the first conductor and the second conductor. Electrically connected by a third conductor that is blown by the potential difference formed onMay be.
[0016]
With the above configuration, the first conductor and the second conductor provided via the insulating film are connected by the third conductor, and the third conductor is used as a fusing part, whereby each conductor is planar. It can be arranged in three dimensions, not the target. Accordingly, the area occupied by each nonvolatile memory element can be reduced as compared with the configuration in which the first conductor and the second conductor are arranged in a plane. Accordingly, since the storage capacity per unit area of the nonvolatile memory element can be increased, the present invention can provide a fuse-type nonvolatile memory element having a large storage capacity.
[0017]
In addition, since the portion to be melted for information recording is provided as the third conductor separately from the first conductor and the second conductor, the conventional conductor pattern and the planar portion of the cutting portion are provided. Compared with the arrangement, the degree of freedom in selecting the material of the third conductor, the pattern width, or the film thickness is increased, and the constraints that the pattern widths of the conductors exert on each other are relaxed. Further, since the first conductor and the second conductor have a laminated structure, the degree of freedom in setting the film thickness of the first conductor and the second conductor is also increased. Therefore, the degree of freedom can be increased in the design of each nonvolatile memory element.
[0018]
Furthermore, since the material and film thickness can be appropriately changed depending on each conductor (first conductor, second conductor, and third conductor), the storage capacity of each nonvolatile memory element can be further increased. Is also possible. In addition, for example, the third conductor can be formed of a material having a lower melting point than the first conductor and the second conductor and easily cut, so that the design for reducing the power consumption of the nonvolatile memory element can be easily performed. Become.
[0019]
In order to solve the above problems, a nonvolatile memory element according to the present invention includes a plurality of first conductors, a plurality of second conductors, a first conductor, and a first conductor insulated with an insulating film interposed therebetween. A third conductor fused by a potential difference applied between the two conductors, the first conductor and the second conductor are arranged so as to cross each other in a matrix, Each outer surface of the first conductor and the second conductor at each intersection position of the first conductor and the second conductor in a three-layer structure composed of a conductor, an insulating film, and a second conductor Are at least partially connected to each other by the third conductor.
[0020]
According to the above configuration, the first conductor and the second conductor are selected one by one from the plurality of first conductors and the plurality of second conductors, respectively, so that a potential difference is given, and thus the intersection exists. Recording and reproduction can be performed on the third conductor.
[0021]
That is, by specifying and selecting a third conductor to be blown (recording information) by one selected first conductor and one selected second conductor, or the third conductor It is possible to detect the connection / disconnection state (information reproduction). Therefore, by specifying the first conductor and the second conductor, it is possible to form a nonvolatile memory element that can specify position information to be recorded / reproduced.
[0022]
When recording information, a current capable of fusing the third conductor may be supplied by applying a potential difference between the selected first conductor and the second conductor. When information is reproduced, whether or not the third conductor is conductive is provided by giving a potential difference to the selected first conductor and the second conductor so as not to blow the third conductor. You can confirm. For example, by applying a voltage to the first conductor, a potential corresponding to the voltage applied to the first conductor is induced in the second conductor in which the third conductor is not melted, and the third conductor A potential corresponding to the voltage applied to the first conductor is not induced in the second conductor in which the conductor is melted. Therefore, by applying a voltage to the first conductor and examining the potential of each second conductor, it is possible to determine whether or not the third conductor is blown, that is, the recorded information.
[0023]
As described above, in the configuration of the nonvolatile memory element, it can be considered that one unit memory element is formed at each intersection position. Then, since the first conductor and the second conductor have a laminated structure at each crossing position, the area occupied by the unit memory element can be reduced. As a result, the storage capacity per unit area of the nonvolatile storage element in which a plurality of unit storage elements are integrated can be increased.
[0024]
In addition, as described above, there is a degree of freedom in selecting the material of the third conductor, and the third conductor is formed in a separate process from the formation of the first conductor and the second conductor. The restrictions imposed on the pattern width of the body from the pattern widths of the first conductor and the second conductor can be relaxed. That is, it is easy to increase the storage capacity and reduce the power consumption by setting the pattern width of each conductor as narrow as possible.
[0025]
As described above, the area occupied by the unit storage element can be reduced, and the design of each conductor has a degree of freedom, so that a large capacity and low power consumption nonvolatile storage element can be realized.
[0026]
Further, for example, when an insulating film is stacked on the strip-shaped first conductor array and an array of the strip-shaped second conductor is stacked thereon, the insulating film is etched using the second conductor as a mask. By doing so, it is possible to expose the connection portion between the first conductor and the second conductor at the intersection position simultaneously with the patterning of the insulating film. As a result, it is possible to reduce the cost by simplifying the nonvolatile memory element formation process.
[0027]
Furthermore, in this case, the non-volatile memory element regularly arranges the same shape pattern at the same interval and without the bent portion for each of the first conductor, the second conductor, and the third conductor. It is possible. Therefore, by optimizing the patterning process, a narrower minimum line width can be formed, and a nonvolatile memory element having a large storage capacity can be formed.
[0028]
In order to solve the above-described problems, the nonvolatile memory element according to the present invention records information by cutting the third conductor at at least one of the crossing positions in addition to the above-described configuration. It is characterized by.
[0029]
Thereby, as already explained, it is possible to provide a nonvolatile memory element in which a large amount of information is recorded.
[0030]
In order to solve the above-described problems, the nonvolatile memory element according to the present invention has a width of the third conductor, a width of the first conductor, and a second conductor in addition to the above configuration. It is characterized by being narrower than the width of.
[0031]
With the above configuration, in addition to the above-described effect, the width of the third conductor serving as the fusing portion is made narrower with respect to the width of the first conductor serving as the wiring pattern and the width of the second conductor. The resistance of the three conductors can be increased. Therefore, when a potential difference is formed between the first conductor and the second conductor, a current flows through the third conductor connecting the first conductor and the second conductor, and only the third conductor having a large resistance is used. The temperature can be increased at. As a result, only the third conductor can be stably melted, so that the recording operation of the nonvolatile memory element can be stabilized.
[0032]
Note that the width of the conductor here means the length in the direction perpendicular to the direction of current flow in each conductor. That is, it can also be said to be the width of the wiring formed by each conductor.
[0033]
Further, if the width of the first conductor and the width of the second conductor are substantially equal, disconnection of the first conductor and the second conductor can be suppressed, and the maximum storage capacity can be obtained. There is an effect. When the width of the first conductor is not substantially equal to the width of the second conductor, a disconnection failure is likely to occur in a thinner conductor. Accordingly, by making the widths of the two substantially equal to a width that does not cause disconnection failure, it is possible to suppress disconnection and to realize the maximum storage capacity.
[0034]
In addition, you may combine the structure described as this invention arbitrarily with each structure described as said invention as needed.
[0035]
In order to solve the above problems, the nonvolatile memory element according to the present invention has a thickness of the third conductor, a thickness of the first conductor, and a thickness of the second conductor in addition to the above configuration. It is characterized by being thinner than the thickness of the conductor.
[0036]
With the above configuration, in addition to the above effects, the thickness of the third conductor, which is the cut portion, is made thinner than the thickness of the first conductor, which is the wiring pattern, and the thickness of the second conductor. As a result, the resistance of the third conductor can be increased. Therefore, when a potential difference is formed between the first conductor and the second conductor, a current flows through the third conductor connecting the first conductor and the second conductor, and only the third conductor having a large resistance is used. The temperature can be increased at. As a result, only the third conductor can be stably melted, so that the recording operation of the nonvolatile memory element can be stabilized.
[0037]
In addition, the film thickness of a conductor said here means the thickness of the direction where each conductor is laminated | stacked.
[0038]
Further, when the film thickness of the first conductor and the film thickness of the second conductor are substantially equal, the disconnection of the first conductor and the second conductor is suppressed, and the maximum storage capacity is obtained. There is an effect that can be.
[0039]
In addition, you may combine the structure described as this invention arbitrarily with each structure described as said invention as needed. In particular, the fusing of only the third conductor can be further stabilized by combining the configuration described as the present invention with the configuration described as the invention with respect to the width of the third conductor.
[0040]
In order to solve the above problems, the nonvolatile memory element according to the present invention has a melting point of the third conductor, a melting point of the first conductor, and a second conductor in addition to the above-described configuration. It is characterized by being lower than the melting point of.
[0041]
With the above configuration, in addition to the above effects, the third conductor using a material having a lower melting point is likely to be melted, so that only the third conductor can be stably fused. . Further, in order to melt the third conductor, the potential difference provided between the first conductor and the second conductor can be reduced. As a result, it is possible to provide a nonvolatile memory element that realizes stable recording / reproduction and / or low power consumption.
[0042]
In addition, you may combine the structure described as this invention arbitrarily with each structure described as said invention as needed. In particular, the effects of the present invention can be further increased by combining the structure described as the present invention with each structure described as the invention with respect to the width or film thickness of the third conductor.
[0043]
In order to solve the above-described problem, the nonvolatile memory element according to the present invention has a linear strip shape and is arranged in parallel with each other in addition to the above-described configuration.
The second conductor is also a straight strip and is arranged in parallel with each other.
[0044]
With the above configuration, in addition to the above effects, the storage capacity of the nonvolatile memory element can be further increased. That is, each of the first conductor and the second conductor is formed of a linear strip-shaped conductor, and has no bent portion, so that the number of intersecting positions per unit area has the bent portion. It can be increased compared to the configuration. In other words, since the number of third conductors that can be provided at the intersection position can be increased, the storage capacity of the nonvolatile memory element can be further increased.
[0045]
In order to solve the above-described problem, the nonvolatile memory element according to the present invention is a portion where the outer surfaces of the first conductor and the second conductor are connected by the third conductor in addition to the above-described configuration. Is characterized in that there are at least two places for each intersection position.
[0046]
With the above configuration, in addition to the above effects, it is possible to reduce disconnection failure of the nonvolatile memory element.
[0047]
That is, when the first conductor and the second conductor are connected by the third conductor at only one place, the disconnection of the third conductor due to dust or the like existing in the formation process may occur. When this occurs, recording cannot be performed on the third conductor, and the nonvolatile memory element itself becomes a defective product. As a result, the number of initially defective elements increases in the nonvolatile memory element.
[0048]
On the other hand, when the first conductor and the second conductor are connected by the third conductor at two or more portions at each crossing position, one of the third conductors is disconnected. Even if it occurs, since the other third conductor connects the first conductor and the second conductor, initial defective elements due to disconnection can be greatly reduced.
[0049]
In addition, you may combine the structure described as this invention arbitrarily with each structure described as said invention as needed.
[0050]
In order to solve the above problems, a nonvolatile memory circuit according to the present invention includes the nonvolatile memory element provided on a semiconductor layer having a recording / reproducing control circuit, and a plurality of the first conductors, Each of the plurality of second conductors is connected to the recording / reproducing control circuit, and the recording / reproducing control circuit is connected to a circuit input / output terminal.
[0051]
With the above configuration, the recording / reproducing control circuit selects the first conductor and the second conductor based on the address information and the recording information input from the circuit input / output terminal, and the selected first conductor is selected. It is possible to select a third conductor that connects the conductor and the second conductor, and to record and reproduce information.
[0052]
That is, in the nonvolatile memory circuit of the present invention, only the address information and the recording information are input to the circuit input / output terminals without directly selecting the first conductor and the second conductor. Thus, the first conductor and the second conductor are selected, and recording / reproduction with respect to the third conductor is performed. Therefore, the convenience as a nonvolatile memory circuit is remarkably improved.
[0053]
In addition, you may combine arbitrarily the structure of the non-volatile memory element described in this invention with each structure of the non-volatile memory element described as said invention as needed.
[0054]
In order to solve the above problems, a nonvolatile memory circuit according to the present invention includes a plurality of the nonvolatile memory elements provided on the semiconductor layer in addition to the above-described configuration, and each nonvolatile memory element Is provided with a recording / reproduction control circuit.
[0055]
With the above configuration, in addition to the above effects, it is possible to suppress a decrease in storage capacity due to defects.
[0056]
When the nonvolatile memory element of the present invention is configured over a wide area, it is necessary to provide a first conductor and a second conductor having a long wiring length. Here, when one portion of the long wiring length is disconnected due to a defect, the plurality of third conductors connected to the disconnected conductor no longer operate as a memory element. In this case, a large number of storage elements are lost due to defects at one location.
[0057]
On the other hand, the nonvolatile memory circuit of the present invention has a plurality of nonvolatile memory elements on the nonvolatile memory circuit, and a recording / reproduction control circuit is provided for each nonvolatile memory element. The wiring length in the non-volatile memory element becomes relatively short. Thereby, it is possible to reduce the number of storage elements lost due to disconnection at one place.
[0058]
In addition, it is possible to provide a single recording / reproduction control circuit for a plurality of nonvolatile storage elements. In this case, however, the wiring length to the nonvolatile storage elements provided at positions away from the storage / reproduction control circuit is small. There is a problem that the number of storage elements is likely to be lost due to a long defect. Further, since wiring is made from a single recording / reproducing control circuit to a plurality of nonvolatile memory elements, the width of each wiring has to be reduced.
[0059]
Therefore, by adopting a configuration in which the plurality of nonvolatile memory elements have the corresponding recording / reproduction control circuits, the width of the wiring can be relatively increased with respect to each recording / reproduction control circuit. In other words, address information and recording information can be input with a wide width wiring, and recording / reproducing can be performed on a non-volatile memory element arranged near the recording / reproducing control circuit. It becomes possible to reduce.
[0060]
In order to solve the above problems, a nonvolatile memory circuit according to the present invention includes an amorphous Si in which a semiconductor layer for forming the recording / reproducing control circuit is provided on a substrate in addition to the above structure. Or a polycrystalline Si layer provided on the substrate, or a polycrystalline Si layer prepared by locally raising the temperature of the amorphous Si layer provided on the substrate. It is said.
[0061]
With the above structure, in addition to the above effects, the substrate material is not limited, and a nonvolatile memory circuit having a low cost and a large storage capacity can be formed.
[0062]
The recording / reproducing control circuit selects the first conductor and the second conductor according to the address information, and applies the voltage for recording / reproducing information to the first conductor and the second conductor. This is a circuit to be applied, and is generally composed of a semiconductor circuit formed on a Si single crystal substrate. However, since the Si single crystal substrate is expensive, the nonvolatile memory circuit formed on the Si single crystal substrate is also expensive.
[0063]
The nonvolatile memory circuit of the present invention can use, as its recording / reproduction control circuit, an amorphous Si layer provided on a plastic substrate or a semiconductor circuit formed on a polycrystalline Si layer. . In this case, the price of the nonvolatile memory circuit can be reduced.
[0064]
In addition, as a storage / reproduction control circuit of the nonvolatile memory circuit of the present invention, it is possible to use a semiconductor circuit provided in a polycrystalline Si layer formed by locally raising the temperature of the amorphous Si layer. is there. If a semiconductor circuit formed on an amorphous Si layer is used, since the electron mobility in the amorphous Si is small, the operation speed of the recording / reproducing control circuit is lowered, and the recording / reproducing speed is lowered. However, the polycrystalline Si has a large electron mobility, and can realize recording and reproduction at a higher speed than amorphous Si. Therefore, the nonvolatile memory circuit of the present invention can be a nonvolatile memory circuit that is inexpensive, has a large storage capacity, and can be recorded and reproduced at high speed.
[0065]
In addition, you may combine the structure described as this invention arbitrarily with each structure described as said invention as needed.
[0066]
In order to solve the above problems, a nonvolatile memory circuit according to the present invention includes an insulating film on the recording / reproducing control circuit provided on the semiconductor layer, in addition to the above-described configuration. The plurality of first conductors and the plurality of second conductors are respectively connected to the recording / reproducing control circuit, and the recording / reproducing control circuit is connected to a circuit input / output terminal. It is characterized by being connected to.
[0067]
With the above configuration, in addition to the above effects, the storage capacity of the nonvolatile memory circuit can be further increased.
[0068]
In the nonvolatile memory circuit of the present invention, since the nonvolatile memory element is three-dimensionally provided on the recording / reproducing control circuit via an insulating film, the surface on the substrate can be used effectively. . As a result, the storage capacity of the nonvolatile memory circuit can be increased, or the nonvolatile memory circuit can be reduced in size.
[0069]
In order to avoid interference of electrical wiring between the recording / reproducing control circuit and the nonvolatile memory element, the first conductor and the second conductor of the recording / reproducing control circuit and the nonvolatile memory element are vertically wired by via holes or the like. It is preferable to connect.
[0070]
Further, even when a recording / reproduction control circuit is provided for each of the plurality of nonvolatile memory elements, an insulating film is formed on each recording / reproduction control circuit, and the corresponding nonvolatile memory element is formed on the insulating film. By providing the above, the same effect can be obtained.
[0071]
In addition, you may combine arbitrarily the structure of the non-volatile memory element described in this invention with each structure of the non-volatile memory element described as said invention as needed.
[0072]
In order to solve the above problems, a nonvolatile memory circuit according to the present invention is characterized in that a plurality of the nonvolatile memory circuits are stacked in addition to the above structure.
[0073]
With the above structure, in addition to the above effects, a plurality of nonvolatile memory circuits are stacked, so that the storage capacity can be increased according to the number of stacked layers.
[0074]
In addition, you may combine the structure described as this invention arbitrarily with each structure described as said invention as needed.
[0075]
In order to solve the above problems, a nonvolatile memory circuit according to the present invention is provided so that circuit input / output terminals included in the plurality of nonvolatile memory circuits do not overlap in the stacking direction in addition to the above structure. It is characterized by having.
[0076]
According to the above configuration, in addition to the above effects, address information and recording information can be directly input / output to / from each circuit input / output terminal of the plurality of stacked nonvolatile memory circuits. That is, since the circuit input / output terminals of each nonvolatile memory circuit do not overlap in the stacking direction, all the circuit input / output terminals can be exposed. Therefore, for example, by connecting connection pins provided in the recording / reproducing apparatus to all exposed circuit input / output terminals, it becomes possible to perform recording / reproducing with respect to each nonvolatile memory circuit, and to perform high-speed recording. A reproduction operation can be realized.
[0077]
In order to solve the above problems, a nonvolatile memory circuit according to the present invention includes a memory circuit selection circuit connected to an external input / output terminal in addition to the above configuration, and includes a plurality of the nonvolatile memory circuits. A circuit input / output terminal is connected to the memory circuit selection circuit. The memory circuit selection circuit includes a first selection signal for selecting a nonvolatile memory circuit for recording and reproduction, and an activity of the selected nonvolatile memory circuit. A second selection signal for selecting the first conductor and the second conductor to be converted and an information signal to be recorded / reproduced are input via an external input / output terminal.
[0078]
With the above configuration, simple information input / output necessary for recording / reproducing information can be performed with a simple configuration with respect to a large-capacity nonvolatile memory circuit configured by a plurality of nonvolatile memory circuits. Is possible.
[0079]
That is, the first selection signal, the second selection signal, and the information signal are input to the storage circuit selection circuit via the same external input / output terminal, and should be recorded / reproduced in the non-volatile storage circuit to be recorded / reproduced thereby. A third conductor can be selected to record information. Therefore, for example, the recording / reproducing apparatus individually accesses the circuit input / output terminals included in each nonvolatile memory circuit, and transmits / receives a signal for selecting the third conductor to be recorded / reproduced and a recording / reproduction signal. Does not require configuration.
[0080]
Therefore, according to the nonvolatile memory circuit of the present invention, in addition to the above effects, the number of external input / output terminals can be reduced in the nonvolatile memory circuit in which a plurality of nonvolatile memory circuits are stacked. That is, an input / output circuit for recording / reproducing information can be simplified, and a nonvolatile memory circuit excellent in convenience can be provided.
[0081]
Note that the recording / reproduction control circuit of the nonvolatile memory circuit selected by the first selection signal causes the third conductor to melt with respect to the first conductor and the second conductor selected by the second selection signal. Recording is performed by generating and applying a voltage necessary for the recording based on the information signal.
[0082]
Similarly, when performing information reproduction, an information signal that detects whether or not the third conductor selected by the second selection signal is blown from the nonvolatile memory circuit selected by the first selection signal. Can be taken out from the circuit input / output terminal and output to the external input / output terminal by the memory circuit selection circuit.
[0083]
In addition, you may combine the structure described as this invention arbitrarily with each structure described as said invention as needed.
[0084]
In order to solve the above problems, the nonvolatile memory card according to the present invention is characterized in that the nonvolatile memory circuit is provided on a card-like substrate.
[0085]
With the above structure, it is possible to realize a non-volatile storage card having a non-volatile storage circuit having a large storage capacity and excellent in portability and convenience.
[0086]
Note that the configuration of the nonvolatile memory circuit described in the present invention may be arbitrarily combined with each configuration of the nonvolatile memory circuit described as the invention as necessary.
[0087]
In order to solve the above problems, a recording / reproducing apparatus according to the present invention records and reproduces information with respect to the nonvolatile memory element, the nonvolatile memory circuit, or the nonvolatile memory card. It is characterized by.
[0088]
With the above configuration, it is possible to realize a high-capacity recording / reproducing apparatus having no movable part and excellent in reliability. Conventional large-capacity recording / reproducing devices, like hard disks and optical discs, require moving parts such as a disc rotation mechanism and a head access mechanism, so there is a problem in the reliability of the device due to a drive mechanism failure such as a head crash. .
[0089]
In contrast, the recording / reproducing apparatus of the present invention can perform recording / reproduction by applying a recording voltage or a reproducing voltage to the first conductor and the second conductor of the nonvolatile memory element. Therefore, a fixed connector or the like can be applied to recording and reproduction. Therefore, it is possible to realize a recording / reproducing apparatus having no movable part and having extremely high reliability.
[0090]
Further, as a conventional recording / reproducing apparatus, there is a recording / reproducing apparatus using a storage element (flash memory or the like) composed of a semiconductor circuit, but it is necessary to form a complicated semiconductor circuit on a Si substrate. The element becomes expensive, and is unsuitable as an element for storing information such as a moving image for a long time.
[0091]
In contrast, the nonvolatile memory element and the nonvolatile memory circuit of the present invention connect the first conductor and the second conductor at the intersection of the first conductor and the second conductor, which are wiring patterns. In addition, it is possible to provide a low-cost and large-capacity non-volatile memory element and a non-volatile memory circuit with an extremely simple configuration having the third conductor. Further, by stacking the nonvolatile memory element and the nonvolatile memory circuit, it is possible to provide a nonvolatile memory element having a larger capacity.
[0092]
Therefore, in the recording / reproducing apparatus using the nonvolatile memory element, the nonvolatile memory circuit, or the nonvolatile memory card according to the present invention, a large amount of information such as a moving image is inexpensively stored. It becomes possible to memorize.
[0093]
Moreover, by making the recording / reproducing apparatus using the non-volatile memory element, the non-volatile memory circuit, or the non-volatile memory card according to the present invention a portable recording / reproducing apparatus, a large capacity such as a moving image Can be stored in an inexpensive non-volatile memory element with low power consumption, and a portable recording / reproducing apparatus can be realized.
[0094]
DETAILED DESCRIPTION OF THE INVENTION
Hereinafter, a nonvolatile memory element, a nonvolatile memory circuit, and a nonvolatile memory card of the present invention will be described in detail with reference to the drawings.
[0095]
(Technical idea of the present invention)
The nonvolatile memory element of the present invention has, for example, as shown in FIG. 2, a first conductor (3) and a second conductor (5) insulated with an insulating film (4) interposed therebetween, The third conductor in which the first conductor (3) and the second conductor (5) are fused by the potential difference formed between the first conductor (3) and the second conductor (5). It is characterized by recording information connected by the body (6).
[0096]
That is, in the nonvolatile memory element of the present invention, first, the first conductor and the second conductor have an insulating stacked structure, thereby reducing the occupied area of the nonvolatile memory element, Second, it is an important aim to increase the degree of freedom in designing the nonvolatile memory element by providing the third conductor separately from the stacked structure.
[0097]
The reason why the degree of freedom in designing the nonvolatile memory element can be increased is because the degree of freedom in selecting the material of the third conductor is increased, and there is a constraint that the pattern width or film thickness of each conductor influence each other. It is because it is eased.
[0098]
As described above, according to the present invention, the reliability of the third conductor being blown for information recording is increased, the third conductor is blown by applying a lower voltage, the material and the film of each conductor. By appropriately selecting the thickness, it is possible to increase the storage capacity in a nonvolatile memory element having a certain size.
[0099]
(Configuration Example 1 of Nonvolatile Memory Element)
FIG. 1 is a plan view of the nonvolatile memory element of the present invention, and FIG. 2 is a diagram for explaining a part of the A-A ′ cross section in FIG. 1.
[0100]
As shown in FIG. 2, the nonvolatile memory element of the present invention includes an insulating film 2 for avoiding electrical interference with a recording / reproduction control circuit, a first film on a substrate 1 provided with a recording / reproduction control circuit to be described later. A first conductor 3, an insulating film 4, and a second conductor 5 are sequentially stacked, and a third conductor 6 that electrically connects the first conductor 3 and the second conductor 5 is provided.
[0101]
Here, by forming a potential difference between the first conductor 3 and the second conductor 5, a portion of the third conductor that electrically connects the first conductor 3 and the second conductor 5. 6, a current corresponding to the potential difference flows, and the temperature of the third conductor 6 in the connection portion rises. If the potential difference is sufficiently large, the temperature rise causes the third conductor 6 to melt at the connection portion of the third conductor 6, and the electrical connection between the first conductor 3 and the second conductor 5 is broken. Be drunk.
[0102]
The nonvolatile memory element of the present invention records and reproduces information depending on whether or not the third conductor 6 is electrically connected.
[0103]
In this case, the factor related to the fusing of the third conductor 6 is the resistance value of the third conductor 6, and the resistance value is determined by the material of the third conductor 6 and the line width or thickness. Further, since the melting point determined by the material of the third conductor 6 is lower than that of the first conductor 3 and the second conductor 5, it is easy to blow out, which is advantageous in terms of power consumption.
[0104]
FIG. 1 shows an embodiment of the non-volatile memory element, and a plurality of first conductors 3 (X₁, X₂, ..., X₈) Are arranged in parallel to each other, and in a direction perpendicular to the first conductor 3, a plurality of linear strip-shaped second conductors 5 (Y₁, Y₂, ..., Y_Ten) Is arranged. That is, the 1st conductor 3 and the 2nd conductor 5 are arrange | positioned so that a non-contact state may be maintained and orthogonally crossed by the insulating film 4 provided in between.
[0105]
And the 3rd conductor 6 which electrically connects the 1st conductor 3 and the 2nd conductor 5 is provided in the part (intersection position) where the 1st conductor 3 and the 2nd conductor 5 cross | intersect. ing. Specifically, the third conductor 6 connects at least a part of the outer surfaces of the first conductor 3 and the second conductor 5 in the three-layer structure at the intersection position.
[0106]
In the above configuration, for example, the specific first conductor X_FourAnd a specific second conductor Y_ThreeBetween the first conductor X and the first conductor X_FourTo second conductor Y_ThreeThe first conductor X_FourAnd second conductor Y_ThreeThe third conductor 6 formed at the crossing position is melted and information is recorded in the form of melting of the third conductor 6.
[0107]
In addition, the first conductor X_FourOr the second conductor Y_ThreeBy applying a voltage so that the above-described potential difference is not formed and measuring the potential induced in the other conductor, the presence or absence of fusing of the third conductor 6 can be reproduced as recorded information. it can.
[0108]
That is, in the nonvolatile memory element of the present invention, a potential difference is provided between one selected first conductor 3 and one selected second conductor 5, and the first conductor 3 and the first conductor 3 Information recording is realized by fusing the third conductor 6 connecting the second conductor 5. In addition, a voltage that does not cause fusing in the third conductor 6 is applied to one of the first conductor 3 and the second conductor 5, and the potential of the other conductor is applied. By detecting this, the presence or absence of fusing of the third conductor 6 is determined, and information reproduction is realized.
[0109]
(Nonvolatile memory element manufacturing method)
Next, a method for forming a nonvolatile memory element of the present invention will be described with reference to FIGS.
[0110]
3A, 3 </ b> B, and 3 </ b> C are cross-sectional views illustrating a method for forming the first conductor 3 and the second conductor 5. FIGS. 3A and 3B show a manufacturing process at a certain point in time when viewed in a cross section perpendicular to AA ′ in FIG. 1 (the extending direction of the second conductor 5). (C) shows a manufacturing process at another time point as seen in the AA ′ cross section of FIG. 1. Therefore, the state of the first conductor 3 is different between (a) and (b) of FIG. 3 and (c) of FIG.
[0111]
First, as shown in FIG. 3A, after an insulating film 2 for avoiding electrical interference with the recording / reproducing control circuit is provided on a substrate 1 provided with a recording / reproducing control circuit to be described later, One conductor 3 is formed by a damascene method.
[0112]
Next, as shown in FIG. 3B, an insulating film 4 that electrically insulates the first conductor 3 and the second conductor 5 is formed.
[0113]
Finally, as shown in FIG. 3C, the second conductor 5 is formed by the damascene method.
[0114]
Here, as the first conductor 3 and the second conductor 5, Al or Al alloy (AlTi, AlCu, etc.) having a low electric resistance, or Cu or Cu alloy (CuTi, CuAl, etc.) is used. Is possible.
[0115]
As the insulating films 2 and 4, a Si oxide film (for example, SiO 2₂), Si nitride film (for example, Si_ThreeN_Four), Ta oxide film (for example, Ta₂O_Three) Or an organic insulating film such as a photo-curing resin or a thermosetting resin can also be used.
[0116]
Further, when the first conductor 3 and the second conductor 5 are formed by the damascene method, it is possible to use the same material as the insulating films 2 and 4 as the insulators 7 and 8.
[0117]
Although the method of forming the first conductor 3 and the second conductor 5 by the damascene method has been described here, the first conductor can be formed by patterning the conductive material using a masking process and an etching process. 3 and the second conductor 5 can also be formed.
[0118]
However, according to this method, the insulating film and the second conductor are formed on the first conductor formed in the uneven shape by patterning, and further, the second conductor is patterned. Concavities and convexities corresponding to the pattern shapes of the first conductor and the second conductor are formed on the surface. As the unevenness increases, a short circuit failure between the first conductor and the second conductor, a disconnection failure of the second conductor, and the like are likely to occur.
[0119]
In contrast, by providing the first conductor 3 and the second conductor 5 by the damascene method, the first conductor 3 and the second conductor 5 are planarly formed. It is possible to suppress the occurrence of disconnection failure. Accordingly, it is desirable that the first conductor 3 and the second conductor 5 be formed by a damascene method.
[0120]
Next, FIGS. 4A, 4B, and 4C are views for explaining a method of forming the third conductor 6 after the manufacturing process shown in FIG. 3C. (A), (b), and (c) of FIG. 4 show the manufacturing process as seen in the A-A ′ cross section of FIG. 1.
[0121]
First, in FIG. 4A, the insulator 8 and the unnecessary insulating film 4 are selectively removed by etching using the second conductor 5 as a mask. Here, the selective etching removal of the insulating film 4 needs to be performed at least until the first conductor 3 is exposed. Further, if the insulator 7 (see FIG. 3B) existing between the first conductors 3 is also removed by etching, the first conductor 3 and the second conductor 5 by the third conductor 6 The electrical connection can be ensured.
[0122]
For example, Cu is used as the first conductor 3 and the second conductor 5, and SiO is used as the insulator 8 and the insulating film 4.₂When CF is used, CF_FourBy performing dry etching using gas plasma, Cu is not etched and SiO 2 is not etched.₂Therefore, selective etching and removal of the insulator 8 and the insulating film 4 using the second conductor 5 as a mask is realized.
[0123]
Further, when an organic insulating film is used as the insulator 8 and the insulating film 4, O₂By performing ashing using gas plasma, etching of Cu is not performed, and only ashing removal of the organic insulating film proceeds. Therefore, the insulator 8 and the insulating film 4 are selectively used with the second conductor 5 as a mask. Etching removal is realized.
[0124]
Here, an organic insulating film is used as the insulator 8, and SiO 2 is used as the insulating film 4.₂Is used, it is necessary to use different reaction gases in removing the insulator 8 and the insulating film 4, which complicates the process. Therefore, it is desirable to use the same material for the insulator 8 and the insulating film 4 or a material that can be removed by etching with the same reaction gas.
[0125]
As described above, in the nonvolatile memory element of the present invention, it is possible to expose the first conductor 3 and the second conductor 5 without using an additional patterning process, and a simple formation process. It can be.
[0126]
Next, as shown in FIG. 4B, after forming the third conductor 6 so as to cover the exposed first conductor 3 and second conductor 5, the third conductor shown in FIG. A photoresist pattern 9 corresponding to the formation pattern 6 is formed.
[0127]
Here, since the surfaces of the first conductor 3 and the second conductor 5 are contaminated with an etching gas or the like by the process up to FIG. 4A, before forming the third conductor 6, Sputter etching is performed using an inert gas such as Ar gas, and the surface contamination layer is removed, so that the electrical connection between the first conductor 3 and the second conductor 5 and the third conductor 6 is ensured. Can be.
[0128]
Finally, as shown in FIG. 4C, the unnecessary third conductor 6 is removed by etching using the photoresist pattern 9 as a mask, and then the photoresist pattern 9 is removed, so that the insulating film 3 is interposed. Thus, the nonvolatile memory element in which the first conductor 3 and the second conductor 5 provided by the third conductor 6 are connected is completed.
[0129]
Here, the same material as the first conductor 3 and the second conductor 5 may be used as the third conductor 6. For example, when Cu is used for all the conductors, the film thickness of the third conductor 6 is made thinner than the film thicknesses of the first conductor 3 and the second conductor 5, and the pattern of the third conductor 6 The nonvolatile memory element may be designed so that the width (width) is narrower than the pattern width of the first conductor 3 and the second conductor 5 and the resistance value of the third conductor 6 is increased. The film thickness of each conductor and the pattern width (width) of each conductor are as defined above. Here, in particular, the pattern width of the third conductor 5 is It means the width in the direction parallel to the extending direction of the two conductors 5.
[0130]
As a result, the third conductor 6 can be easily melted and stable recording can be realized. In the nonvolatile memory element, the third conductor 6 is formed by a manufacturing process different from that of the first conductor 3 and the second conductor 5, and the first conductor 3 and the second conductor 5 are Since it is a structure laminated | stacked one by one, it becomes possible to set easily the film thickness and width | variety of each conductor 3,5,6.
[0131]
As the material of the third conductor 6, the same material as the first conductor 3 and the third conductor 5 may be used as described above, but from the material of the first conductor 3 and the second conductor 5. However, it is desirable to use a material having a low melting point. With the above configuration, the third conductor 6 can be blown out more reliably.
[0132]
For example, when Cu is used as the first conductor 3 and the second conductor 5 and Al is used as the third conductor 6, the melting point of Cu is 1085 ° C., and the melting point of Al is 660 ° C. In addition, fusing in the third conductor 6 can be generated. Further, the thickness of the third conductor 6 made of Al is made thinner than that of the first conductor 3 and the second conductor 5, and the pattern width of the third conductor 6 is made smaller than that of the first conductor 3 and the second conductor 6. By making the conductor 5 narrower, more reliable recording can be realized.
[0133]
When a high melting point conductive material such as Cu is used as the first conductor 3 and the second conductor 5, the third conductor 6 is made of Zn, Sn, Bi as a low melting point material other than Al. Etc. can be used. Furthermore, these alloys, that is, AlZn alloy, AlSn alloy, AlBi alloy, ZnSn alloy and the like can also be used. Further, as will be described later, since each melting point of Zn, Sn, Bi is lower than that of Al, Al is used for the first conductor 3 and the second conductor 5, and Zn, Sn, Bi is used for the third conductor 6. Either of these can also be used.
[0134]
(Recording / reproducing method of nonvolatile memory element)
Next, the recording / reproducing method for the nonvolatile memory element of the present invention will be described with reference to FIG. 5, FIG. 6, FIG. 7, and FIG.
[0135]
FIG. 5 is a circuit diagram of the nonvolatile memory element shown in FIG. 1, and the N first conductors 3 (hereinafter referred to as the first conductor X) in a non-contact state.₁~ X_NAnd M second conductors 5 (hereinafter referred to as second conductor Y).₁~ Y_MIn the crossing position, the third conductor 6 (hereinafter referred to as the third conductor R)._ijWill be described in other words).
[0136]
FIG. 6 shows a recording circuit that realizes a recording operation for the nonvolatile memory element. Here, the first conductor X_iAnd second conductor Y_jThe third conductor R selected by_ijWill be described.
[0137]
Element selection transistor (Tr) included in a recording / reproduction control circuit to be described later_i, Tr_j) Are respectively connected to the power supply voltage (+ V). Next, an element selection transistor (hereinafter simply referred to as Tr_iOr Tr_jGate voltage (Vg) applied to the gate (G) of_i, Vg_j)_i, Tr_jON / OFF is selected and Tr_iThe first conductor X connected to_iAnd Tr_jSecond conductor Y connected to_jIs determined. And the first conductor X_iAnd second conductor Y_jBased on the potential difference of the third conductor R_ijIs controlled.
[0138]
The third conductor R_ijIs connected to the first conductor X_iHas a grounding resistance R_iIs connected to the second conductor Y_jTr connected to_jThe drain (D) has a ground resistance R_jIs connected.
[0139]
Thus, the third conductor R_ijCurrent is passed through the third conductor R_ijThe information is recorded by cutting. FIG. 7 shows the third conductor R_ijShows a state in which information is recorded by fusing.
[0140]
Table 1 below shows the transistor (Tr in the circuit shown in FIG._i, Tr_j) And the first conductor X_iAnd second conductor Y_jIt shows the relationship with the potential at.
[0141]
[Table 1]

[0142]
In state 1, Tr_i, Tr_jAre both ON and X_iPotential and Y_jSince both potentials are + V, the third conductor R_ijNo current flows through the third conductor R_ijNo fusing occurs.
[0143]
In state 2, Tr_iIs ON, Tr_jBecomes OFF and X_iPotential is + V, Y_iThe potential becomes the ground potential (0 V) and a potential difference V is generated. Thereby, the third conductor R_ijAnd Y_jResistance to ground R_jCurrent passing through and X_iResistance to ground R_iCurrent passing through the current flows. Where R_ijAnd R_jR rather than series resistance with_iIs sufficiently large, the first conductor X_iTo second conductor Y_jTowards the third conductor R_ijA larger current flows through the third conductor R_ijIs blown out.
[0144]
In state 3, Tr_iIs OFF, Tr_jBecomes ON and X_iPotential is + V ', Y_jThe potential becomes + V. Where X_iThe potential (+ V ′) is Y_jThe potential (+ V) is set to the third conductor R_ijAnd R_iThis is the potential divided by. In this case, X_iResistance to ground R_iBut Y_jResistance to ground R_jThe third conductor R is made sufficiently larger than the third conductor R._ijThe current that flows through becomes smaller. As a result, the third conductor R_ijNo fusing occurs.
[0145]
In state 4, Tr_i, Tr_jAre both OFF and X_iPotential and Y_jSince both potentials are ground potential (0V), the third conductor R_ijNo current flows through the third conductor R_ijNo fusing occurs.
[0146]
Thus, the specific first conductor X_iTransistor Tr for driving_iIs turned on, the other transistors that drive the first conductor 3 are turned off, and the second conductor (Y₁, Y₂, ..., Y_M) Is turned on or off according to the recorded information, so that the specific first conductor X_iIt is possible to control the presence or absence of fusing of the M third conductors 6 connected to each other, that is, to record information.
[0147]
The nonvolatile memory element can reproduce the recorded information by determining the states shown in FIGS. For example, a specific second conductor Y_jTransistor Tr for driving_jIn the ON state, the first conductor X₁~ X_NTransistor Tr for driving_iAre sequentially turned OFF, and the first conductor X_iThe specific second conductor Y is measured by sequentially measuring the potential of_jAnd first conductor X₁~ X_NIt is possible to reproduce the state of the N third conductors 6 provided at the crossing position, that is, the recorded information.
[0148]
In the case of FIG. 6, the third conductor R_ijIs in the connected state, as shown in state 3 of Table 1, the first conductor X_iBecomes + V ′. On the other hand, in the case of FIG. 7, the third conductor R_ijIs in a fusing state, the first conductor X_iBecomes the ground potential (0 V). Thus, the potential induced in the first conductor 2 varies depending on whether the third conductor 6 is fused or not.
[0149]
Therefore, by applying a voltage to the second conductor 5 and detecting the potential of the first conductor 3, it is possible to reproduce the recorded information, that is, whether or not the third conductor 6 is blown. .
[0150]
In the above description, the second conductor Y is used during recording.₁~ Y_MAre sequentially selected and the first conductor X is reproduced during reproduction.₁~ X_NHas been described, the first conductor X₁~ X_NAnd second conductor Y₁~ Y_MWhich of these is sequentially selected can be appropriately changed.
[0151]
The transistors and ground resistors shown in FIGS. 6 and 7 are data inputs driven in the X decoder 19 and the Y decoder 20 which are part of a recording / reproduction control circuit (for example, FIG. 8) of a nonvolatile memory circuit described later. It can be provided in the circuit 22.
[0152]
(Configuration of non-volatile memory circuit)
Next, a nonvolatile memory circuit 11 using the nonvolatile memory element 10 of the present invention will be described with reference to a schematic block diagram shown in FIG.
[0153]
The nonvolatile memory circuit 11 is provided on a semiconductor layer (not shown), receives an address signal A0 to Ai (i: natural number), and an external clock CLK, X input from the outside. Control signal input terminal 13 for receiving address strobe signal XAS, Y address strobe signal YAS, write enable signal WE, element select signal CS, and the like, power supply terminal 14 for receiving power supply potential VCC and ground potential VSS from the outside, and data D0 To Dj (j: natural number).
[0154]
The nonvolatile memory circuit 11 further receives an address signal A0 to Ai from the address input terminal 12 and converts it into an internal address signal indicating the X address XA and the Y address YA, and the control signal input terminal 13 performs control. A control signal buffer 17 that receives the signal group and generates a corresponding internal control signal, and a control circuit 18 that receives the internal control signal group from the control signal buffer 17 and controls the internal operation of the entire nonvolatile memory circuit 11. I have.
[0155]
The nonvolatile memory circuit 11 further includes a plurality of first conductors 3 and second conductors 5 arranged in a matrix, and a third conductor 6 that connects the first conductor 3 and the second conductor 5. The non-volatile memory element 10 which has is provided.
[0156]
The nonvolatile memory circuit 11 further includes an X decoder 19 that performs selection of the first conductor 3 of the nonvolatile memory element 10 in accordance with the X address XA generated by the address buffer 16, and a Y address YA output by the address buffer 16. Accordingly, a Y decoder 20 for selecting the second conductor 5 and a sense circuit 21 and a data input circuit 22 to be described later are provided.
[0157]
The X decoder 19 records and reproduces at least one of the first conductors 3 in the nonvolatile memory element 10 in accordance with the X address XA output from the address buffer 16 when the first conductor 3 is selected. To selectively activate. Specifically, the first conductor X shown in FIG. 6 explaining the recording / reproducing method._iTransistor Tr connected to_iAnd ground resistance R_iAre provided in at least the X decoder 19.
[0158]
The Y decoder 20 records and reproduces at least one of the second conductors 5 in the nonvolatile memory element 10 according to the Y address YA output from the address buffer 16 when the second conductor 5 is selected. To selectively activate. Specifically, the second conductor Y shown in FIG._jTransistor Tr connected to_jAnd ground resistance R_jAre provided in at least the Y decoder 20.
[0159]
The nonvolatile memory circuit 11 further includes a data output buffer 23 and a data input buffer 24 for executing data exchange with the data input / output terminal 15. The data output buffer 23 and the data input buffer 24 execute data input / output at a timing synchronized with the clock signal generated by the control circuit 18.
[0160]
Data sent from the data input buffer 24 is input to the data input circuit 22. The data input circuit 22 controls the voltage applied to the third conductor 6 based on the input data in accordance with the selection results of the X decoder 19 and the Y decoder 20, so that the third conductor 6 is melted. Execution, that is, recording for each crossing position of the nonvolatile memory element is performed.
[0161]
In addition, the sense circuit 21 detects the recording state of each nonvolatile memory element, that is, the presence or absence of fusing of the third conductor 6 in accordance with the selection result of the X decoder 19 and the Y decoder 20, and records data Perform playback. For example, the second conductor Y selected by the Y decoder 20_jA voltage is applied to the first conductor X₁~ X_NThe recorded information can be reproduced by sequentially measuring the voltage induced by the sense circuit 21. Then, the reproduction signal detected by the sense circuit 21 is sent to the data output buffer 23.
[0162]
The nonvolatile memory circuit 11 further generates a power supply potential + V and a ground potential used in the nonvolatile memory circuit 11 according to the external power supply potential VCC and the external ground potential VSS input to the power supply terminal 13. A power supply circuit 25 is provided. The power supply potential + V and the ground potential are supplied to each circuit in the nonvolatile memory circuit 11.
[0163]
In the nonvolatile memory circuit, a portion including the address input terminal 12, the control signal input terminal 13, the power supply terminal 14, and the data input / output terminal 15 is a circuit input / output terminal. Also, semiconductors such as an address buffer 16, a control signal buffer 17, a control circuit 18, an X decoder 19, a Y decoder 20, a sense circuit 21, a data input circuit 22, a data output buffer 23, a data input buffer 24, and a power supply circuit 25. A portion including the circuit is a recording / reproducing control circuit.
[0164]
Therefore, in the nonvolatile memory circuit of the present invention, a plurality of first conductors and a plurality of second conductors are connected to the above-described recording / reproducing control circuit on a semiconductor layer such as a Si substrate or a glass substrate, for example. In addition, it can be said that the recording / reproducing control circuit is connected to the circuit input / output terminal described above.
[0165]
By using the non-volatile memory circuit of the present invention, it is possible to realize information recording / reproduction with respect to the non-volatile memory element of the present invention corresponding to an address.
[0166]
(Configuration example 2 of nonvolatile memory element)
Next, FIGS. 9 and 10 are a plan view and a cross-sectional view showing another configuration of the nonvolatile memory element of the present invention.
[0167]
In the nonvolatile memory element shown in FIG. 1 and FIG. 2, the first conductor 3 and the second conductor 5 are located at one location at each intersection position of the first conductor 3 and the second conductor 5. Only connected by the third conductor 6. On the other hand, in the nonvolatile memory element shown in FIGS. 9 and 10, the first conductor 3 and the second conductor 5 are arranged at each intersection position of the first conductor 3 and the second conductor 5. Are connected by the third conductor 6 at two places.
[0168]
The non-volatile memory element having such a structure has a photoresist pattern 9 as a mask for etching the third conductor 6 in the manufacturing method shown in FIGS. A pattern corresponding to the conductor 6 can be formed.
[0169]
In this configuration, the first conductor 3 and the second conductor 5 are electrically connected to each other by the third conductor 6 on both sides of the second conductor 5. It is possible to reduce the number of initial defects. That is, when a non-volatile memory element is formed and a defect such as dust is present and an electrical connection is not maintained with the third conductor 6 at one connection location at a certain crossing position, By maintaining the electrical connection in the third conductor 6 at the other connection location, it is possible to avoid the entire nonvolatile memory element from being defective due to a connection failure at one location.
[0170]
In addition, in the nonvolatile memory element having the configuration shown in FIG. 9, in addition to providing a total of two connection points on each side of the second conductor 5 at each crossing position, two or more points on one side are provided. May be provided.
[0171]
(Configuration example 1 of nonvolatile memory circuit)
Next, more specific embodiments of the nonvolatile memory circuit of the present invention will be described with reference to FIGS.
[0172]
FIG. 11 is a perspective view showing a part of the nonvolatile memory circuit according to the present invention. The circuit input circuit includes an address input terminal 12, a control signal input terminal 13, a power supply terminal 14, a data input / output terminal 15, and the like. Output terminal 27, address buffer 16, control signal buffer 17, control circuit 18, X decoder 19, Y decoder 20, sense circuit 21, data input circuit 22, data output buffer 23, data input buffer 24, and power supply circuit 25 The recording / reproducing control circuit 28 composed of a semiconductor circuit such as the above is formed on a Si substrate 26 (semiconductor layer) made of a single crystal silicon wafer.
[0173]
12 is provided with the nonvolatile memory element 29 of the present invention (corresponding to the nonvolatile memory element 10 shown in FIG. 8) on the recording / reproducing control circuit 28 formed on the Si substrate 26 shown in FIG. It is a perspective view of the non-volatile memory circuit of a structure. Here, the input / output wirings such as the X decoder 19 and the data input circuit 22 of the recording / reproduction control circuit 28, and the plurality of first conductors 3 and the plurality of second conductors 5 of the nonvolatile memory element 29 are These are wired using a three-dimensional wiring technique through an insulating film (not shown).
[0174]
Here, the recording / reproducing control circuit 28 and the nonvolatile memory element 29 may be provided so as not to overlap with each other and wired by horizontal wiring. However, in this case, it is necessary to separately provide a region for forming the recording / reproducing control circuit 28 and a region for forming the nonvolatile storage element 29 on the Si substrate 26, and the storage capacity is reduced. In order to realize a large storage capacity, as shown in FIG. 11 and FIG. 12, a recording / reproduction control circuit 28 and a nonvolatile storage element 29 are arranged so as to overlap each other and a three-dimensional wiring is interposed via an insulating film (not shown). Wiring using technology is desirable.
[0175]
The insulating film (not shown) is provided to avoid electrical interference between the recording / reproducing control circuit 28 and the nonvolatile memory element 29, and is provided between the recording / reproducing control circuit 28 and the nonvolatile memory element 29. It is desirable that it be provided so as not to cause insulation failure.
[0176]
In the above description, the recording / reproduction control circuit 28 is formed of a semiconductor circuit provided on a Si substrate as the recording / reproduction control circuit 28. However, the present invention is not limited to this.
[0177]
For example, as shown in FIGS. 13 and 14, a recording / reproduction control circuit 33 and a circuit input / output terminal 31 made of a semiconductor circuit are provided on a substrate 30 other than a Si substrate, for example, a glass substrate or a plastic substrate. 11 and FIG. 12, the nonvolatile memory element 29 can be placed on the recording / reproducing control circuit 33 so as to be wired using a three-dimensional wiring technique.
[0178]
Here, when a glass substrate or a plastic substrate is used as the substrate 30, the recording / reproducing control circuit 33 made of a semiconductor circuit has an amorphous Si thin film 32 (semiconductor layer) formed on the substrate 30 by a sputtering method or a CVD method. It is possible to configure using The amorphous Si thin film needs to be capable of forming a semiconductor circuit, and the film thickness is desirably 50 nm to 200 nm. In addition, the upper limit value and the lower limit value shown on the left are approximate guidelines.
[0179]
However, when an amorphous Si thin film is used as a semiconductor circuit, since the electron mobility of the amorphous Si thin film is small, it is difficult to control recording and reproduction at high speed. In order to record / reproduce information such as video information with respect to the nonvolatile memory circuit of the present invention, it is important to realize not only the storage capacity but also high-speed recording / reproduction.
[0180]
Therefore, as the recording / reproducing control circuit 33 used in the nonvolatile memory element 10 of the present invention, the amorphous Si thin film 32 is irradiated with an energy beam such as a laser beam, so that the amorphous Si thin film 32 is formed. It is desirable to provide the recording / reproducing control circuit 33 in the polycrystalline region. When the amorphous Si thin film 32 is polycrystallized, the electron mobility in the semiconductor circuit is increased. Accordingly, high-speed operation of the recording / reproduction control circuit is realized, and the nonvolatile memory circuit of the present invention can be applied to high-speed recording / reproduction of information such as video information.
[0181]
Further, according to this embodiment, since an inexpensive glass substrate or plastic substrate can be used without using an expensive Si substrate, a low-cost nonvolatile memory circuit can be provided. Further, by using a plastic substrate, breakage due to cracking can be prevented, and a nonvolatile memory circuit that is more portable than a glass substrate can be provided.
[0182]
(Configuration example 2 of nonvolatile memory circuit)
Next, in FIGS. 15 and 16, a plurality of recording / reproduction control circuits 34 and a plurality of nonvolatile storage elements 35 corresponding to the respective recording / reproduction control circuits 34 are provided on one substrate 30. The configuration is shown. Here, the substrate 30 may be the Si substrate shown in FIG. 11 and FIG. 12, but in order to realize a low price of the nonvolatile memory circuit, it is the same as in FIG. 13 and FIG. In addition, it is desirable to use a substrate other than the Si substrate.
[0183]
Similarly to the case of FIG. 13 and FIG. 14, the recording / reproduction control circuit 34 is formed by using polycrystalline Si that has been polycrystallized by laser annealing, so that the recording / reproduction control circuit can operate at high speed. The nonvolatile memory circuit of the present invention can be applied to high-speed recording / reproduction of information such as video information.
[0184]
In the nonvolatile memory circuits shown in FIG. 15 and FIG. 16, the circuit input / output terminal 31 and each recording / reproduction control circuit 34 are connected, and address information and data information are exchanged. In addition, a non-volatile storage element 35 is placed on each of the plurality of recording / reproduction control circuits 34 and wired using a three-dimensional wiring technique.
[0185]
The nonvolatile memory circuit shown in FIGS. 13 and 14 has a configuration in which one nonvolatile memory element 29 is provided on a substrate. Therefore, the plurality of first conductors 3 and the plurality of second conductors 5 constituting the nonvolatile memory element 29 have a length substantially the same as the length of the nonvolatile memory element 29. Here, when a disconnection due to a defect or a short circuit occurs in one place of the plurality of first conductors 3 or the plurality of second conductors 5, the individual conductors connected to the conductors in which the disconnection has occurred All of the non-volatile memory elements (corresponding to individual crossing positions; called unit memory elements) are all defective elements. That is, a single defect will generate an extremely large number of defective elements.
[0186]
On the other hand, in the nonvolatile memory circuits shown in FIGS. 15 and 16, the number of defective elements is reduced by connecting a plurality of nonvolatile memory elements 35 to a plurality of recording / reproducing control circuits 34, respectively. Is possible. For example, if the size of the substrate 30 does not change, the capacity of one nonvolatile memory element 35 is smaller in the case of FIG. 16 than in the case of FIG. The lengths of the first conductor 3 and the second conductor 5 included in can be shortened. As described above, when the lengths of the first conductor 3 and the second conductor 5 are shortened, it is possible to reduce the number of defective elements caused by a disconnection or a short circuit caused by a single defect.
[0187]
(Configuration example 1 of nonvolatile storage card)
The nonvolatile memory circuit of the present invention shown in FIGS. 11 to 16 is disposed on a circuit board and used as a nonvolatile memory circuit capable of inputting / outputting recording / reproducing information using circuit input / output terminals 27 and 31. However, taking advantage of the features of large capacity and low price, a replaceable nonvolatile memory circuit can be obtained.
[0188]
That is, as shown in FIG. 17, the nonvolatile memory circuit of the present invention is provided on a card-like substrate 36 to provide a nonvolatile memory card, thereby providing a large capacity and low cost storage medium. can do.
[0189]
For example, the non-volatile storage card shown in FIG. 17 is detachably attached to a recording / reproducing device having a connection pin that can be electrically contacted with the circuit input / output terminal 31, and the recording / reproducing device has a connection pin. Information is recorded and reproduced between the nonvolatile storage card and the recording / reproducing apparatus.
[0190]
FIG. 17 shows a configuration in which the nonvolatile memory circuit shown in FIG. 12, FIG. 14, or FIG. 16 is pasted on the card-like substrate 36 with an adhesive, but directly on the card-like substrate 36, Recording / reproduction control circuits 33 and 34 and nonvolatile storage elements 29 and 35 can be provided.
[0191]
(Configuration example 2 of nonvolatile memory card)
Next, FIG. 18 shows a nonvolatile memory card having a configuration in which a plurality of nonvolatile memory circuits are stacked on a card-like substrate 36. Here, the respective nonvolatile memory circuits are stacked in a stepped manner and bonded together with an adhesive so that the circuit input / output terminals 31 of the plurality of nonvolatile memory circuits do not overlap in the stacking direction.
[0192]
For recording / reproduction with respect to the non-volatile storage card, connection pins provided in the recording / reproduction device are simultaneously or selectively electrically contacted to the exposed circuit input / output terminals 31 to input / output recording / reproduction information. Is realized.
[0193]
Thus, by providing a plurality of non-volatile storage circuits in a stacked manner, it is possible to provide a non-volatile storage card having a larger storage capacity.
[0194]
However, in the nonvolatile memory card, it is necessary to input / output address information and recording / reproducing information to / from each of the plurality of circuit input / output terminals 31, and the number of connection pins of the recording / reproducing device is nonvolatile. There arises a problem that the number increases depending on the number of layers of the volatile memory circuit and the recording / reproducing control system of the recording / reproducing apparatus becomes complicated.
[0195]
(Configuration example 3 of nonvolatile memory card)
Therefore, in the third configuration example, a nonvolatile memory card capable of stacking a plurality of nonvolatile memory circuits without increasing the number of input / output terminals will be described. 19 and 20 are diagrams for explaining this nonvolatile storage card.
[0196]
As shown in FIG. 19, the non-volatile memory card of Configuration Example 3 includes a non-volatile memory element 29, a recording / reproduction control circuit (not shown), an external input / output terminal 41, and the external memory. A first nonvolatile memory circuit 37 having a memory circuit selection circuit 38 connected to the input / output terminal 41 is attached to the card-like substrate 36 with an adhesive. Further, as shown in FIG. 20, a plurality of second nonvolatile memory circuits 39 are sequentially stacked on the first nonvolatile memory circuit 37 and the memory circuit selection circuit 38.
[0197]
Each of the plurality of second non-volatile memory circuits 39 has an input / output terminal 40, and each of the input / output terminals 40 passes through a hole penetrating the non-volatile memory circuit 39. Is connected to a memory circuit selection circuit 38 included in the memory circuit 37.
[0198]
The memory circuit selection circuit 38 selects a specific non-volatile memory circuit from the non-volatile memory circuits 37 and 39 based on the address information (first selection signal) input from the external input / output terminal 41, and the specific non-volatile Recording and reproduction with respect to the storage circuit can be performed.
[0199]
Further, another address information (second selection signal) is input to the memory circuit selection circuit 38 from the external output terminal 41, and the memory circuit selection circuit 38 should be activated (ON) in the selected specific nonvolatile memory circuit. It is possible to select the first conductor 3 and the second conductor 5 and perform recording / reproduction with respect to the nonvolatile memory element.
[0200]
Here, a configuration having the external input / output terminal 41, the memory circuit selection circuit 38, and the nonvolatile memory element 29 is described as the first nonvolatile memory circuit 37, but as the first nonvolatile memory circuit 37, A configuration having only the external input / output terminal 41 and the memory circuit selection circuit 38 is also possible.
[0201]
21 and 22 are schematic block diagrams of a nonvolatile memory circuit that performs recording and reproduction of the nonvolatile memory card shown in FIG.
[0202]
FIG. 21 shows a first nonvolatile memory circuit 37, which receives an address signal A0 to Ai (i: natural number) (first selection signal and second selection signal), and is input from the outside. Control signal input terminal 51 that receives external clock CLK, X address strobe signal XAS, Y address strobe signal YAS, write enable signal WE, element select signal CS, and the like, and receives power supply potential VCC and ground potential VSS from the outside, respectively. The external input / output terminal 41 comprising a power supply terminal 52 and a data input / output terminal 53 for inputting / outputting data D0 to Dj (j: natural number) (information signal for recording / reproduction) is provided.
[0203]
Next, the external input / output terminal 41 is connected to the memory circuit selection circuit 38, and the memory circuit selection circuit 38 selects the nonvolatile memory circuit 37 or 39 to be selected according to the input address signal information. decide.
[0204]
On the other hand, as shown in FIGS. 21 and 22, each of the nonvolatile memory circuits 37 and 39 individually receives an address signal A0 to Ai (i: natural number) sent from the memory circuit selection circuit 38. 60, a control signal input terminal 61 that receives an external clock CLK, an X address strobe signal XAS, a Y address strobe signal YAS, a write enable signal WE, an element select signal CS, and the like, and a power supply that receives a power supply potential VCC and a ground potential VSS, respectively. The non-volatile memory circuit 37 is provided with the input / output terminal 40 composed of a terminal 62 and a data input / output terminal 63 for inputting / outputting data D0 to Dj (j: natural number). , 39 is connected to the external input / output terminal 41 by the memory circuit selection circuit 38. That.
[0205]
The recording / reproducing operation from the input / output terminal 40 to each nonvolatile memory circuit 10 is performed in the same manner as in FIG.
[0206]
In the nonvolatile memory card having the above-described configuration, a plurality of nonvolatile memory circuits are stacked to realize a large storage capacity, and the number of external input / output terminals of the nonvolatile storage card is minimized (memory). The number of external input / output terminals 41 of the circuit selection circuit 38). Therefore, the input / output system of the recording / reproducing apparatus can be simplified, and an inexpensive recording / reproducing apparatus can be provided.
[0207]
In the above embodiment, the address buffer 16, the power supply circuit 25, the control signal buffer 17, the control circuit 18, the data input buffer 24, and the data output buffer 23 are provided in the respective nonvolatile storage circuits 37 and 39. However, if these circuits (the driver circuit for the nonvolatile memory element 10) are collectively provided in the memory circuit selection circuit 38, the scale of the recording / reproduction control circuit included in each nonvolatile memory circuit is reduced. Simplification of the formation process of the volatile memory circuit and cost reduction can be realized.
[0208]
【Example】
[Example 1]
As Example 1 of the present invention, a nonvolatile memory element having the configuration shown in FIGS. 1 and 2 was produced.
[0209]
The non-volatile memory element of Example 1 has a thickness of 100 nm on a substrate 1 made of single crystal Si provided with a semiconductor circuit.₂The first conductor 3 and the second conductor 5 made of Al wiring having a width of 0.3 μm and a film thickness of 100 nm are formed on the insulating film 2 made of₂Are laminated via an insulating film 4 made of And the 3rd conductor 6 which electrically connects the 1st conductor 3 and the 2nd conductor 5 in one place (one side of each cross | intersection part) is provided.
[0210]
As the third conductor 5, an Al thin film was used, its film thickness was 50 nm, and its connection width (width in the direction parallel to the extending direction of the second conductor 5) was 0.2 μm.
[0211]
Next, one first conductor X_FourA voltage of 2.5 V is applied to the second conductor Y_ThreeIs grounded through a resistor, thereby the first conductor X_FourTo second conductor Y_ThreeA current was passed through. As a result, the first conductor X_FourAnd second conductor Y_ThreeOnly the third conductor 6 that connects the two can be fused. Similarly, the first conductor X₇To second conductor Y_ThreeCurrent to the first conductor X₇And second conductor Y_ThreeOnly the third conductor 6 that connects the two can be fused.
[0212]
Next, the second conductor Y_ThreeBy applying a voltage of 1.5 V to the second conductor Y_ThreeThe third conductor 5 connected to the first conductor X is not melted.₁, X₂, X_Three, X_Five, X₆, X₈In the first conductor X, a voltage of about 1.5 V is induced and the third conductor 5 is blown out._Four, X₇No voltage was induced.
[0213]
From the above, in the nonvolatile memory element of Example 1, a potential difference is provided between one selected first conductor 3 and one selected second conductor 5, and the first conductivity It was confirmed that information can be recorded by fusing the third conductor 6 connecting the body 3 and the second conductor 5. Furthermore, a voltage that does not cause fusing in the third conductor 6 is applied to one of the first conductor 3 and the second conductor 5, and the potential of the other conductor is applied. By detecting this, it was confirmed that it was possible to determine the presence or absence of fusing in the third conductor 6 and reproduce the information.
[0214]
Next, as a result of investigating the occurrence of fusing by changing the size of the third conductor 6 in the non-volatile memory element having the same configuration as that of the above embodiment, the width of the third conductor 6 is reduced. It was confirmed that the voltage required for fusing the third conductor 5 was smaller as the thickness of the conductor 6 was reduced. Further, if the width and film thickness of the third conductor 6 are the same as those of the first conductor 3 and the second conductor 5, the voltage required for fusing the third conductor 6 becomes too high, and the first conductor The occurrence of fusing in the body 3 or the second conductor 5 was confirmed.
[0215]
Therefore, if the width and film thickness of the third conductor 6 are at least smaller than the width and film thickness of the first conductor 2 or the second conductor 4, the first conductor 3 and the second conductor It can be said that it is possible to melt only the third conductor 6 without causing the melt to melt.
[0216]
In order to realize low power consumption, it is desirable to blow the third conductor 6 at a low voltage. For that purpose, it is desirable that the width of the third conductor 6 is 0.25 μm or less or the film thickness of the third conductor 6 is 60 nm or less, and the width and film thickness of the third conductor 6 are 0.25 μm, respectively. More preferably, the thickness is less than 60 nm or less.
[0217]
On the other hand, if the width and film thickness of the third conductor 6 are made too small, disconnection occurs in the unrecorded third conductor 6 due to pinholes caused by defects such as dust. In order to avoid initial disconnection in an unrecorded state, it is desirable that the width of the third conductor 6 is 0.1 μm or more, or the film thickness of the third conductor 6 is 10 nm or more. It is further desirable that the film thickness be 0.1 μm or more and 10 nm or more, respectively. Even in this case, there is an initial disconnection of 1% to 2%, but the total storage capacity of the nonvolatile storage circuit is not significantly reduced.
[0218]
Furthermore, in order to completely avoid the disconnection of the third conductor 6 in the unrecorded state, it is desirable that the width of the third conductor 6 is 0.18 μm or more or the thickness of the third conductor 6 is 20 nm or more. It is further desirable that the width and film thickness of the third conductor 6 be 0.18 μm or more and 20 nm or more, respectively.
[0219]
[Example 2]
As Example 2 of the present invention, a nonvolatile memory element having the configuration shown in FIGS. 9 and 10 was produced.
[0220]
As in the example, the nonvolatile memory element of Example 2 has a width of 0.3 μm, and the first conductor 3 and the second conductor 5 made of Al wiring with a film thickness of 100 nm have a film thickness of 100 nm SiO₂The first conductor 3 and the second conductor 5 are electrically connected to each other at two locations (on both sides of each intersection) by the third conductor 6.
[0221]
The third conductor 6 uses the same Al as the first conductor 3 and the second conductor 5, has a film thickness of 15 nm, and the width of the portion in contact with the end portions of the first conductor 2 and the second conductor 4 Was 0.1 μm.
[0222]
Next, one first conductor X_FiveA voltage of 2 V is applied to one second conductor Y_ThreeIs grounded through a resistor, thereby the first conductor X_FiveTo second conductor Y_ThreeA current was passed through. Thereby, the first conductor X_FiveAnd second conductor Y_ThreeOnly the third conductor 5 connecting the two can be fused. Similarly, the first conductor X₇To second conductor Y_ThreeCurrent to the first conductor X₇And second conductor Y_ThreeOnly the third conductor 6 that connects the two can be fused.
[0223]
Next, the second conductor Y_ThreeIn addition, by applying a voltage of 2 V, the first conductor X in which no fusing occurs in the third conductor 6 at the intersecting position₁, X₂, X_Three, X_Four, X₆, X₈Includes a first conductor X in which a voltage of about 2 V is induced and fusing occurs in the third conductor 5 at the intersecting position._Five, X₇No voltage was induced.
[0224]
From the above, also in the nonvolatile memory element of Example 2, a potential difference is provided between one selected first conductor 3 and one selected second conductor 5, and the first conductivity Information can be recorded by fusing the third conductor 6 that connects the body 3 and the second conductor 5, and further, the first conductor 3 or the second conductor can be recorded. By applying a voltage that does not cause fusing in the third conductor 6 to any one of the conductors 5 and detecting the potential of the other conductor, the fusing of the third conductor 6 is detected. It can be seen that information can be reproduced by determining the presence or absence.
[0225]
In Example 1 in which the first conductor 3 and the second conductor 5 are connected to only one place on one side, in order to completely avoid the initial disconnection in the unrecorded state, the width of the third conductor 6 is set to 0. It has been described that it is desirable that the thickness is 18 μm or more and the thickness of the third conductor is 20 nm or more. On the other hand, in Example 2 where both ends of the first conductor 2 and the second conductor 5 are connected, the width of the third conductor 5 is 0.15 μm and the film thickness is 15 nm. The initial disconnection in the unrecorded state was completely avoided. This is because, even if an initial disconnection occurs on one side by connecting on both sides of the second conductor 5, the initial disconnection can be suppressed by maintaining the connection on the other side. .
[0226]
Thus, in the second embodiment, the first conductor 3 and the second conductor 5 are electrically connected to each other at two locations on both sides of the second conductor 5, so that the non-volatile due to the initial disconnection is caused. The initial failure of the volatile memory element can be reduced. In addition, the thickness of the third conductor 6 can be reduced, and the formation process (film formation and etching) of the third conductor 6 can be simplified.
[0227]
Example 3
As Example 3 of the present invention, a nonvolatile memory element having the same configuration as that of Example 1 was formed with a material having a lower melting point than the melting points of the materials constituting the first conductor 3 and the second conductor 5. The third conductor 6 was used for production.
[0228]
Here, an example in which Al having a melting point of 660 ° C. is used as the first conductor 3 and the second conductor 5, and Al, Zn, Sn, Bi, AlZn alloy, AlSn alloy is used as the third conductor 5. Will be described. The melting points of Zn, Sn, Bi, AlZn alloy, and AlSn alloy were 420 ° C., 232 ° C., 274 ° C., 510 ° C., and 320 ° C., respectively.
[0229]
As in Example 1, the first conductor 3 and the second conductor 5 had a width of 0.3 μm and a film thickness of 100 nm. Moreover, about each 3rd conductor 6, the width | variety was 0.2 micrometer and the film thickness was 40 nm.
[0230]
One first conductor X_FourA voltage of 1.8 V lower than that in Example 1 was applied to the second conductor Y_ThreeIs grounded through a resistor, thereby the first conductor X_FourTo second conductor Y_ThreeA current was passed through. As a result of investigating the occurrence of fusing of the third conductor 6 at this time, when Al is used as the third conductor 6, the voltage applied is lower than that of Example 1, so Did not occur. On the other hand, when Zn, Sn, Bi, an AlZn alloy, or an AlSn alloy is used as the third conductor 6, the third conductor 6 is applied although the applied voltage is lower than that of the first embodiment. Fusing occurred.
[0231]
Therefore, by using a material having a melting point lower than the melting points of the first conductor 3 and the second conductor 5 as the third conductor 6, it is possible to perform fusing at a lower voltage, that is, recording. confirmed.
[0232]
Moreover, as a result of conducting a similar experiment using an AlBi alloy and a ZnSn alloy, it was confirmed that fusing at a low voltage was possible.
[0233]
Next, the same examination was performed when Cu wiring having a width of 0.3 μm and a film thickness of 100 nm was used as the first conductor 3 and the second conductor 5.
[0234]
As the third conductor 6, Al, Zn, Sn, Bi, AlZn alloy, AlSn alloy having a width of 0.2 μm and a film thickness of 40 nm is used, and the third conductor 6 is surely blown out. As a result of investigating the applied voltage, it was confirmed that the lower the melting point of the third conductor 6 is, the lower the fusing can be realized.
[0235]
The present invention is not limited to the above-described embodiments and examples, and various modifications are possible within the scope shown in the claims, and technical means disclosed in different embodiments and examples are appropriately used. Embodiments and examples obtained in combination are also included in the technical scope of the present invention.
[0236]
【The invention's effect】
  As described above, the nonvolatile memory element according to the present invention includes the first conductor and the second conductor insulated with the insulating film interposed therebetween, and the first conductor and the second conductor are Electrically connected by a third conductor that is fused by a potential difference formed between the first conductor and the second conductor.May be.
[0237]
Therefore, since each conductor can be arranged three-dimensionally rather than planarly, each nonvolatile memory element is compared with a configuration in which the first conductor and the second conductor are arranged planarly. Occupying area can be reduced. Therefore, since the storage capacity per unit area of the nonvolatile memory element can be increased, a fuse-type nonvolatile memory element having a large storage capacity can be provided.
[0238]
In addition, since the portion to be cut for information recording is provided as the third conductor separately from the first conductor and the second conductor, the material selection of the third conductor, the pattern width selection, Alternatively, the degree of freedom in selecting the film thickness increases, and the constraint that the pattern widths of the respective conductors exert on each other is eased. Further, since the first conductor and the second conductor have a laminated structure, the degree of freedom in setting the film thickness of the first conductor and the second conductor is also increased.
[0239]
Accordingly, various effects such as a design for further increasing the storage capacity and a design for reducing the power consumption of the nonvolatile memory element can be achieved.
[0240]
In addition, as described above, the nonvolatile memory element according to the present invention includes a plurality of first conductors, a plurality of second conductors, a first conductor, and a second conductor that are insulated with an insulating film interposed therebetween. A third conductor that melts by a potential difference applied to the body, the first conductor and the second conductor are arranged so as to cross each other in a matrix, and the first conductor , At least each of the outer surfaces of the first conductor and the second conductor at each intersection position of the first conductor and the second conductor in the three-layer structure including the insulating film and the second conductor. Part of them is electrically connected by the third conductor.
[0241]
Therefore, by specifying the first conductor and the second conductor, the position information to be recorded / reproduced can be specified, so that one unit storage element is formed at each intersection position. It can be considered. At each crossing position, the first conductor and the second conductor have a laminated structure, so that the area occupied by the unit storage element can be reduced. Therefore, the storage capacity of the nonvolatile memory element can be increased.
[0242]
Further, since there is a degree of freedom in selecting the material of the third conductor and setting the pattern width or film thickness of each conductor, it is possible to further increase the capacity and reduce the power consumption of the nonvolatile memory element. Combines effects.
[0243]
Further, as described above, the nonvolatile memory element according to the present invention is characterized in that information is recorded by cutting the third conductor at at least one of the crossing positions in addition to the above configuration. It is said.
[0244]
Thereby, as already explained, it is possible to provide a nonvolatile memory element in which a large amount of information is recorded.
[0245]
In addition to the above configuration, the nonvolatile memory element according to the present invention has a width of the third conductor, a width of the first conductor, and a width of the second conductor, as described above. It is characterized by being narrower than.
[0246]
Therefore, it is possible to increase the resistance of the third conductor by narrowing the width of the third conductor serving as the fusing portion with respect to the width of the first conductor serving as the wiring pattern and the width of the second conductor. It becomes possible. Therefore, when a potential difference is formed between the first conductor and the second conductor, a current flows through the third conductor connecting the first conductor and the second conductor, and the third conductor having a large resistance. Only in the body, the temperature rises, and only the third conductor can be stably melted, so that the recording operation of the nonvolatile memory element can be stabilized.
[0247]
In addition to the above-described configuration, the nonvolatile memory element according to the present invention has a thickness of the third conductor, a thickness of the first conductor, and a second conductor. It is characterized by being thinner than the film thickness.
[0248]
Therefore, the thickness of the third conductor, which is the cut portion, is reduced with respect to the thickness of the first conductor, which is the wiring pattern, and the thickness of the second conductor, thereby increasing the resistance of the third conductor. It becomes possible to do. Therefore, when a potential difference is formed between the first conductor and the second conductor, a current flows through the third conductor connecting the first conductor and the second conductor, and the third conductor having a large resistance. Only in the body, the temperature rises, and only the third conductor can be stably melted, so that the recording operation of the nonvolatile memory element can be stabilized.
[0249]
In addition to the above configuration, the nonvolatile memory element according to the present invention has a melting point of the third conductor, a melting point of the first conductor, and a melting point of the second conductor. It is characterized by being lower than.
[0250]
Therefore, in the third conductor using a material having a lower melting point, fusing is likely to occur, and only the third conductor can be stably fused. Further, in order to melt the third conductor, the potential difference provided between the first conductor and the second conductor can be reduced. As a result, it is possible to provide a nonvolatile memory element that realizes stable recording / reproduction and / or low power consumption.
[0251]
Further, the nonvolatile memory element according to the present invention, as described above, in addition to the above configuration,
The first conductors are linear strips arranged in parallel with each other, and the second conductors are also linear strips arranged in parallel with each other.
[0252]
Therefore, each of the first conductor and the second conductor is composed of a linear strip-shaped conductor, and has no bent portion, so that the number of crossing positions per unit area is determined with the bent portion. Can be increased compared to In other words, since the number of third conductors that can be provided at the crossing position can be increased, the storage capacity of the nonvolatile memory element can be further increased.
[0253]
In addition to the above-described configuration, the nonvolatile memory element according to the present invention, in addition to the above-described configuration, a location where the outer surfaces of the first conductor and the second conductor are connected by the third conductor, It is characterized in that there are at least two places at each intersection position.
[0254]
Therefore, if the first conductor and the second conductor are connected by the connecting body at two or more portions at each crossing position, even when one of the connecting bodies generates a disconnection, Since the other connection body connects the first conductor and the second conductor, there is an additional effect that initial defective elements due to disconnection can be greatly reduced.
[0255]
Further, as described above, the nonvolatile memory circuit according to the present invention is provided with the nonvolatile memory element on a semiconductor layer having a recording / reproducing control circuit in addition to the above-described configuration. One conductor and the plurality of second conductors are each connected to the recording / reproducing control circuit, and the recording / reproducing control circuit is connected to a circuit input / output terminal.
[0256]
Therefore, the recording / reproducing control circuit selects the first conductor and the second conductor based on the address information and the recording information input from the circuit input / output terminal, and the selected second conductor is selected as a result. Information recording / reproduction can be performed on the three conductors.
[0257]
That is, in the nonvolatile memory circuit of the present invention, only the address information and the recording information are input to the circuit input / output terminals without directly selecting the first conductor and the second conductor. As a result, recording / reproduction can be performed, so that the convenience of the nonvolatile memory circuit is greatly improved.
[0258]
Further, as described above, the nonvolatile memory circuit according to the present invention includes a plurality of the nonvolatile memory elements provided on the semiconductor layer in addition to the above-described configuration, and performs recording / reproduction for each nonvolatile memory element. A control circuit is provided.
[0259]
Therefore, in addition to the above-described effects, the nonvolatile memory circuit is divided into a plurality of nonvolatile memory elements, so that the wiring length in each nonvolatile memory element becomes relatively short, and disconnection occurs at one place. This makes it possible to reduce the number of recording elements lost.
[0260]
Further, by adopting a configuration in which the plurality of nonvolatile memory elements have the corresponding recording / reproduction control circuits, the width of the wiring can be relatively increased with respect to each recording / reproduction control circuit. Therefore, there is another effect that the loss of the memory element due to the wiring defect can be reduced.
[0261]
Further, as described above, the nonvolatile memory circuit according to the present invention includes an amorphous Si layer provided on a substrate, in addition to the above configuration, a semiconductor layer for forming the recording / reproducing control circuit, It is characterized in that it is either a polycrystalline Si layer provided on the substrate or a polycrystalline Si layer produced by locally raising the temperature of the amorphous Si layer provided on the substrate. .
[0262]
Therefore, in addition to the above effects, the substrate material is not limited, and it is possible to form a nonvolatile memory circuit having a low cost and a large storage capacity.
[0263]
In addition to the above effect, the use of the polycrystalline Si layer as the semiconductor layer also provides a further effect that a nonvolatile memory circuit capable of high-speed recording / reproduction can be obtained.
[0264]
Further, as described above, in addition to the above configuration, the nonvolatile memory circuit according to the present invention includes the nonvolatile memory element on the recording / reproducing control circuit provided on the semiconductor layer via an insulating film. The plurality of first conductors and the plurality of second conductors are respectively connected to the recording / reproducing control circuit, and the recording / reproducing control circuit is connected to a circuit input / output terminal. It is characterized by being.
[0265]
Therefore, by providing a three-dimensional non-volatile memory element on the recording / reproducing control circuit, it is possible to effectively use the surface on the substrate and further increase the memory capacity of the non-volatile memory circuit. There is an effect that can be done.
[0266]
Furthermore, even when each of the plurality of nonvolatile memory elements has a recording / reproducing control circuit, an insulating film is formed on the recording / reproducing control circuit, and the corresponding nonvolatile memory element is formed on the insulating film. Similarly, there is another effect that the storage capacity of the nonvolatile memory circuit can be increased.
[0267]
As described above, the nonvolatile memory circuit according to the present invention is characterized in that a plurality of the nonvolatile memory circuits are stacked in addition to the above structure.
[0268]
Therefore, in addition to the above-described effect, the storage capacity can be increased according to the number of stacked layers by stacking a plurality of nonvolatile storage circuits.
[0269]
In addition to the above configuration, the nonvolatile memory circuit according to the present invention is provided so that circuit input / output terminals of the plurality of nonvolatile memory circuits do not overlap in the stacking direction. It is characterized by that.
[0270]
Therefore, in addition to the above effects, address information and recording information can be directly input / output to / from the respective element input / output terminals of the plurality of stacked nonvolatile memory circuits. There is an additional effect that the reproduction operation can be realized.
[0271]
Further, as described above, the nonvolatile memory circuit according to the present invention includes a memory circuit selection circuit connected to the external input / output terminal in addition to the above configuration, and includes a plurality of nonvolatile memory circuits. An output terminal is connected to the memory circuit selection circuit. The memory circuit selection circuit should activate a first selection signal for selecting a nonvolatile memory circuit for recording and reproduction, and the selected nonvolatile memory circuit. A second selection signal for selecting the first conductor and the second conductor and an information signal to be recorded / reproduced are input via an external input / output terminal.
[0272]
Therefore, the first selection signal, the second selection signal, and the information signal are input to the storage circuit selection circuit via the same external input / output terminal, thereby recording and reproducing in the nonvolatile storage circuit to be recorded and reproduced. The third conductor to be selected can be selected to record information. Therefore, in the nonvolatile memory circuit in which a plurality of nonvolatile memory circuits are stacked, the number of external input / output terminals can be reduced. That is, it is possible to simplify the input / output circuit for recording and reproducing information, and there is a further effect that a nonvolatile memory circuit excellent in convenience can be provided.
[0273]
The nonvolatile memory card according to the present invention is characterized in that the nonvolatile memory circuit is provided on a card-like substrate as described above.
[0274]
Therefore, there is an effect that it is possible to realize a non-volatile memory card having a non-volatile memory circuit having a large storage capacity and excellent in portability and convenience.
[0275]
Further, as described above, the recording / reproducing apparatus according to the present invention records and reproduces information with respect to the nonvolatile memory element, the nonvolatile memory circuit, or the nonvolatile memory card. It is said.
[0276]
Therefore, since there are no movable parts such as a disk rotation mechanism and a head access mechanism necessary for conventional hard disk devices and optical disk devices, a fixed connector or the like can be applied to recording and reproduction, so that it is extremely reliable. There is an effect that a high recording / reproducing apparatus can be realized.
[0277]
Furthermore, as a conventional recording / reproducing apparatus, there is a recording / reproducing apparatus using a storage element (flash memory or the like) composed of a semiconductor circuit, but it is necessary to form a complicated semiconductor circuit on a Si substrate. The element becomes expensive, and is unsuitable as an element for storing information such as a moving image for a long time. On the other hand, the nonvolatile memory element and the nonvolatile memory circuit of the present invention have an end portion of the first conductor and the second conductor at the intersection of the first conductor and the second conductor, which are wiring patterns. Provided is a low-cost and large-capacity nonvolatile memory element and a nonvolatile memory circuit capable of recording / reproducing information with a very simple configuration of having a third conductor for connecting to the end of the memory. It is possible. Further, by stacking the nonvolatile memory element and the nonvolatile memory circuit, it is possible to provide a nonvolatile memory element having a larger capacity. Therefore, in the recording / reproducing apparatus using the nonvolatile memory element, the nonvolatile memory circuit, or the nonvolatile memory card according to the present invention, a large amount of information such as a moving image is inexpensively stored. It also has the additional effect of being able to memorize.
[Brief description of the drawings]
FIG. 1 is an explanatory diagram showing a planar configuration example of a nonvolatile memory element of the present invention.
2 is an explanatory diagram showing a cross-sectional configuration of the nonvolatile memory element shown in FIG. 1 along the line A-A ′ of FIG. 1;
FIGS. 3A to 3C are process explanatory views showing a method for forming a nonvolatile memory element according to the present invention. FIGS.
4A to 4C are process explanatory views showing processes subsequent to the processes of FIGS. 3A to 3C. FIG.
FIG. 5 is an equivalent circuit diagram of the nonvolatile memory element of the present invention.
FIG. 6 is a circuit diagram of a semiconductor circuit used for recording / reproduction of the nonvolatile memory element of the present invention.
FIG. 7 is a circuit diagram showing a recording state of the semiconductor circuit.
FIG. 8 is a schematic block diagram showing a configuration of a nonvolatile memory circuit of the present invention.
FIG. 9 is an explanatory diagram showing another planar configuration example of the nonvolatile memory element of the present invention.
10 is an explanatory diagram showing a cross-sectional configuration of the nonvolatile memory element shown in FIG. 9 along the line A-A ′ of FIG. 9;
FIG. 11 is a schematic perspective view illustrating a configuration of a substrate surface in the nonvolatile memory circuit of the present invention.
FIG. 12 is a schematic perspective view showing an entire configuration of a nonvolatile memory circuit of the present invention.
FIG. 13 is a schematic perspective view illustrating another configuration of the substrate surface in the nonvolatile memory circuit of the present invention.
FIG. 14 is a schematic perspective view showing another overall configuration of the nonvolatile memory circuit of the present invention.
FIG. 15 is a schematic perspective view illustrating still another configuration of the substrate surface in the nonvolatile memory circuit of the present invention.
FIG. 16 is a schematic perspective view showing still another overall configuration of the nonvolatile memory circuit of the present invention.
FIG. 17 is a schematic perspective view showing a configuration example of a nonvolatile memory card according to the present invention.
FIG. 18 is a schematic perspective view showing another configuration example of the nonvolatile memory card of the present invention.
FIG. 19 is a schematic perspective view showing a part of still another configuration example of the nonvolatile memory card of the present invention.
FIG. 20 is a schematic perspective view showing still another overall configuration of the nonvolatile memory card of the present invention.
FIG. 21 is a schematic block diagram showing a configuration of a nonvolatile memory circuit mounted on the lowermost layer of the nonvolatile memory card shown in FIG. 20;
22 is a schematic block diagram showing a configuration of a nonvolatile memory circuit mounted on the second and higher layers from the bottom of the nonvolatile memory card shown in FIG.
FIG. 23 is an explanatory diagram showing a planar configuration of a conventional nonvolatile memory element.
[Explanation of symbols]
1 Substrate
3 First conductor
4 Insulating film
5 Second conductor
6 Third conductor
7, 8 Insulator
9 Photoresist pattern
10, 29 Nonvolatile memory element
11, 37, 39 Nonvolatile memory circuit
26 Si substrate (semiconductor layer)
27, 31 Circuit input / output terminal
28, 33, 34 Recording / reproduction control circuit
30 substrates
32 Amorphous Si thin film (semiconductor layer)
36 Card-like board
38 Memory circuit selection circuit
41 External input / output terminals

Claims (16)

A plurality of first conductors and a plurality of second conductors insulated with an insulating film interposed therebetween, and a third conductor fused by a potential difference applied between the first conductor and the second conductor. Have
The first conductor, the insulating film, and the second conductor are laminated in this order,
The first conductor and the second conductor are arranged so as to intersect with each other in a matrix shape, and the insulating film is at least at each intersection position of the first conductor and the second conductor. Is formed so as to extend in the same direction as the stretching direction of
Each of the first conductor and the second conductor at each crossing position of the first conductor and the second conductor in a three-layer structure including the first conductor, the insulating film, and the second conductor. At least a part of the outer surface is electrically connected by the third conductor,
The third conductor includes at least a part of one side and an upper surface of the side surface, which is an outer surface of the second conductor extending in the extending direction of the second conductor, and the first conductor at each crossing position. A non-volatile memory element, wherein the outer surface on the side where the insulating film is laminated is connected.   The nonvolatile memory element according to claim 1, wherein information is recorded by cutting the third conductor at at least one of the intersecting positions.   The nonvolatile memory element according to claim 1, wherein a width of the third conductor is narrower than a width of the first conductor and a width of the second conductor.   2. The nonvolatile memory element according to claim 1, wherein the film thickness of the third conductor is smaller than the film thickness of the first conductor and the film thickness of the second conductor.   2. The nonvolatile memory element according to claim 1, wherein a melting point of the third conductor is lower than a melting point of the first conductor and a melting point of the second conductor. The first conductors are linear strips arranged in parallel with each other,
The non-volatile memory element according to claim 1, wherein the second conductor is also formed in a straight strip shape and arranged in parallel with each other.   2. The nonvolatile memory element according to claim 1, wherein there are at least two locations where the outer surfaces of the first conductor and the second conductor are connected by the third conductor at each intersection position. . The nonvolatile memory element according to claim 1 is provided on a semiconductor layer having a recording / reproducing control circuit,
The plurality of first conductors and the plurality of second conductors are each connected to the recording / reproducing control circuit, and the recording / reproducing control circuit is connected to a circuit input / output terminal. A nonvolatile memory circuit.   9. The nonvolatile memory circuit according to claim 8, wherein a plurality of the nonvolatile memory elements are provided on the semiconductor layer, and a recording / reproducing control circuit is provided for each nonvolatile memory element.   The semiconductor layer for forming the recording / reproducing control circuit is an amorphous Si layer provided on the substrate, a polycrystalline Si layer provided on the substrate, or an amorphous Si layer provided on the substrate. The nonvolatile memory circuit according to claim 8, wherein the nonvolatile memory circuit is any one of a polycrystalline Si layer produced by locally raising the temperature of the semiconductor layer. The nonvolatile memory element according to claim 1 is provided on a recording / reproducing control circuit provided on the semiconductor layer via an insulating film,
The plurality of first conductors and the plurality of second conductors are each connected to the recording / reproducing control circuit, and the recording / reproducing control circuit is connected to a circuit input / output terminal. A nonvolatile memory circuit.   A non-volatile memory circuit, wherein a plurality of the non-volatile memory circuits according to claim 8 are stacked.   13. The nonvolatile memory circuit according to claim 12, wherein circuit input / output terminals of the plurality of nonvolatile memory circuits are provided so as not to overlap in the stacking direction.   A memory circuit selection circuit connected to an external input / output terminal, and the circuit input / output terminals of the plurality of nonvolatile memory circuits are connected to the memory circuit selection circuit, and the memory circuit selection circuit performs recording / reproduction A first selection signal for selecting a nonvolatile memory circuit to perform, a second selection signal for selecting a first conductor and a second conductor to be activated in the selected nonvolatile memory circuit, and information to be recorded / reproduced The nonvolatile memory circuit according to claim 12, wherein the signal is input through an external input / output terminal.   15. A nonvolatile memory card, wherein the nonvolatile memory circuit according to claim 8 is provided on a card-like substrate.   The nonvolatile memory element according to any one of claims 1 to 7, or the nonvolatile memory circuit according to any one of claims 8 to 14, or according to claim 15. A recording / reproducing apparatus for recording / reproducing information on / from a nonvolatile storage card.

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