JP4451095B2 - Semiconductor memory device - Google Patents

Description

  The present invention relates to a semiconductor memory device using an SOI substrate.

  As a conventional DRAM cell, a cell composed of a capacitor for storing information and a transistor for reading information is mainly used. The memory operation functions by distinguishing “1” when the electric charge is accumulated in the capacitor and “0” when the electric charge is not accumulated in the capacitor.

  In such a DRAM cell, it is necessary to miniaturize transistors and capacitors in order to miniaturize and increase the density of memory cells. However, if the transistors and capacitors are simply miniaturized, the amount of stored charge decreases, and the amount of charge required for DRAM operation cannot be secured. For this reason, it is required to miniaturize the capacitor without reducing the amount of charge that can be accumulated. Under these circumstances, the use of a three-dimensional structure and a high dielectric constant film has made it possible to miniaturize capacitor dimensions to some extent without reducing the amount of charge that can be stored. There is a problem that the manufacturing cost is increased due to the process.

  Therefore, proposals for realizing a DRAM function with only a transistor without using a capacitor include, for example, Japanese Patent Application Laid-Open No. 2002-260381 (Patent Document 1), Japanese Patent Application Laid-Open No. 2002-343886 (Patent Document 2), and IEEE electron. letters vol.23 NO.2, February 2002 (Non-Patent Document 1). In these proposals, the DRAM function is identified by identifying when a large number of carriers are accumulated and when not accumulated in the body region of a transistor fabricated on an SOI substrate as “1” and “0”, respectively. Realized. Also, impact ionization current is used for carrier accumulation. Further, Patent Documents 1 and 2 also describe that data is written using a GIDL current (Gate Induced Drain Leakage).

FIG. 15 is a cross-sectional view showing the structure of a conventional semiconductor memory device (DRAM). In a conventional DRAM, a buried oxide film 102 is formed on a silicon substrate 101, and a P-type silicon layer 103 is further formed thereon to constitute an SOI substrate 110. For each memory cell, a gate insulating film 105 is formed between the P-type silicon layer 103 and the gate electrode 104 (word line). A sidewall insulating film 106 is formed on the side of the gate electrode 104. Then, the P-type silicon layer 103, for each memory cell, N ⁺ source diffusion layer 107 and N ⁺ drain diffusion layer 108 reaching the buried oxide film 102 is formed, N ⁺ source diffusion under the gate insulating film 105 A region sandwiched between the layer 107 and the N ⁺ drain diffusion layer 108 is a body region 109. The N ⁺ drain diffusion layer 108 is connected to the bit line via a contact plug (not shown) or the like, and the N ⁺ source diffusion layer 107 has a ground potential via the contact plug (not shown) or the like. Supplied.

  However, when an impact ionization current is used for a write operation, there is a problem that a large drain current needs to flow using a high voltage at the time of writing, resulting in an increase in power consumption.

JP 2002-260381 A JP 2002-343886 A IEEE electron letters, February 2002, Volume 30, Issue 2

  An object of the present invention is to provide a semiconductor memory device capable of writing data using a GIDL current with high efficiency.

  As a result of intensive studies to solve the above problems, the present inventor has come up with various aspects of the invention described below.

A first semiconductor memory device according to the present invention is formed on an insulating film, a first conductivity type silicon layer formed on the insulating film, and the silicon layer sandwiched between them. The present invention is directed to a semiconductor memory device having a second conductivity type source diffusion layer and drain diffusion layer, a gate insulating film formed on the silicon layer, and a gate electrode formed on the gate insulating film. The drain diffusion layer overlaps with the gate electrode in plan view, and is formed under the first impurity diffusion layer having an impurity concentration of 1 × 10 ¹⁹ cm ⁻³ or more and the first impurity diffusion layer, A second impurity diffusion layer in contact with the silicon layer and having an impurity concentration lower than that of the first impurity diffusion layer. Further, the thickness of the silicon layer is a thickness at which the silicon layer is partially depleted when a voltage for writing data is applied to the gate electrode. The drain diffusion layer further includes a third impurity diffusion layer formed under the first impurity diffusion layer and sandwiching the second impurity diffusion layer with the silicon layer, The impurity concentration of the third impurity diffusion layer is higher than that of the second impurity diffusion layer.

In the second semiconductor memory device according to the present invention, an insulating film having a recess, a first conductivity type silicon layer formed on the recess, and formed outside the recess on the insulating film. A source diffusion layer and a drain diffusion layer of a second conductivity type sandwiching the silicon layer between them, a gate insulating film formed on the silicon layer, a gate electrode formed on the gate insulating film, Is provided. The drain diffusion layer overlaps the gate electrode in plan view, the impurity concentration of the drain diffusion layer is 1 × 10 ¹⁹ cm ⁻³ or more, and the thickness of the silicon layer is for writing data Therefore, the silicon layer is partially depleted when a voltage is applied to the gate electrode.

  In the first semiconductor memory device, since the drain diffusion layer is composed of the first and second impurity diffusion layers and the impurity concentration of the first impurity diffusion layer is appropriately defined, a sufficient GIDL current flows, High speed writing becomes possible. Further, since the electric field applied to the pn junction with the silicon layer is relaxed due to the presence of the second impurity diffusion layer, an increase in junction leakage current can be avoided.

Further, when the conductivity type between the drain diffusion layer and the gate electrode are different it can be effectively and a score flow the GIDL current. Such an effect is also obtained when the gate electrode is formed from a metal such as Mo, Ni, Al, or Co, or when the gate electrode is formed from a silicide such as CoSi or NiSi into which boron is introduced. It is done.

  Hereinafter, embodiments of the present invention will be specifically described with reference to the accompanying drawings.

(First embodiment)
First, a first embodiment of the present invention will be described. In the first embodiment, an N-type semiconductor is used as the gate electrode of an N-channel MOS transistor using an SOI substrate. FIG. 1 is a layout diagram showing a structure of a semiconductor memory device (DRAM) according to a first embodiment of the present invention, and FIG. 2 is a cross-sectional view taken along line II in FIG.

In the first embodiment, for example, a plurality of word lines WL and a plurality of bit lines BL are arranged orthogonal to each other. A memory cell (DRAM cell) is formed around each intersection of the word line WL and the bit line BL. The word line WL is composed of an N ⁺ polysilicon layer and functions as the gate electrode 4 in each memory cell. Note that the bit line BL is omitted in FIG. 2 for simplicity.

Also, the buried oxide film 2 is formed on the silicon substrate 1, and the P-type silicon layer 3 is further formed thereon to constitute the SOI substrate 10. A gate insulating film 5 is formed between the P-type silicon layer 3 and the gate electrode 4 (word line WL) for each memory cell. A sidewall insulating film 6 is formed on the side of the gate electrode 4 (word line WL). In the P-type silicon layer 3, an N-type source diffusion layer 7 and a drain diffusion layer 8 reaching the buried oxide film 2 are formed for each memory cell, and the source diffusion layer 7 and the drain diffusion layer 8 are formed under the gate insulating film 5. A region sandwiched between the drain diffusion layers 8 is a body region 9. The source diffusion layer 7 is composed of, for example, an N-type low-concentration impurity diffusion layer 7a formed on the buried oxide film 2 and an N-type high-concentration impurity diffusion layer 7b formed thereon, and is a drain diffusion layer. 8 includes, for example, an N-type low-concentration impurity diffusion layer 8a formed on the buried oxide film 2 and an N-type high-concentration impurity diffusion layer 8b formed thereon. Of these diffusion layers, in the present embodiment, only the high-concentration impurity diffusion layers 7b and 8b overlap the gate electrode 4 in plan view. The impurity concentration of the high concentration impurity diffusion layer 8b is 1.00 × 10 ¹⁹ cm ⁻³ or more, and preferably 1.00 × 10 ²⁰ cm ⁻³ or more.

Further, the thickness of the P-type silicon layer 3 is such that it will be partially depleted without being completely depleted by an operation described later. For example, the thickness of the buried oxide film 2 is about 150 nm, and the thickness of the P-type silicon layer 3 is about 70 nm. For example, the gate length is about 0.2 μm, and the thickness of the gate insulating film 5 is about 5.8 nm. The N ⁺ drain diffusion layer 8 is connected to the bit line BL via a contact plug (not shown) or the like, and the N ⁺ source diffusion layer 7 has a constant potential via a contact plug (not shown) or the like. For example, a ground potential is supplied.

  In the first embodiment configured as described above, when data “1” is written, the gate electrode 4 is negatively biased and the drain diffusion layer 8 is positively biased with respect to the memory cell to be written. . For example, −2.4 V is applied to the gate electrode 4 (word line WL), and 0.2 V is applied from the bit line BL to the drain diffusion layer 8. As a result, the bending of the energy band increases in the overlapping region between the gate electrode 4 and the drain diffusion layer 8 (the region where the gate electrode 4 and the high-concentration impurity diffusion layer 8b overlap in plan view), and the electrons in the valence band are A GIDL current is generated by tunneling to the conduction band. With the generation of the GIDL current, surplus holes (holes) are generated, and the surplus holes accumulate in the neutral region 11 of the body region 9 and the threshold voltage decreases.

  On the other hand, when data “0” is written, the drain diffusion layer 8 is negatively biased with respect to the memory cell to be written, and the pn junction between the drain diffusion layer 8 and the body region 9 is forward biased. As a result, the accumulated holes are discharged to the drain diffusion layer 8. For example, 0.8 V is applied to the gate electrode 4 (word line WL), and −1.5 V is applied from the bit line BL to the drain diffusion layer 8. As a result, holes in the neutral region 11 disappear and the threshold voltage rises.

  When reading the written data, for example, 0.8 V is applied to the gate electrode 4 (word line WL) to the memory cell to be written, and 0.V is applied from the bit line BL to the drain diffusion layer 8. Apply 2V. As a result, a drain current corresponding to the threshold voltage of the N-channel MOS transistor flows, and the data stored in the memory cell can be determined.

In the present embodiment, the high-concentration impurity diffusion layer 8b constituting the drain diffusion layer 8 not only overlaps the gate electrode 4 in plan view, but also the impurity concentration of the high-concentration impurity diffusion layer 8b is 1.00 × 10. ^{Since it is 19} cm ⁻³ or more, preferably 1.00 × 10 ²⁰ cm ⁻³ or more, a GIDL current flows effectively.

  When a strong electric field is applied to the drain-body pn junction, the junction leakage current increases and the data retention time (retention time) is shortened. However, in the present embodiment, the low concentration impurity diffusion layer 7b exists between the high concentration impurity diffusion layer 8b and the buried oxide film 2 so as to be in contact with the P-type silicon layer 3. It can be avoided that a strong electric field is applied to the pn junction. Accordingly, it is possible to avoid a reduction in data retention time due to such an increase in leakage current.

In addition, power consumption can be reduced as compared with the case of using impact ionization current. As shown in FIG. 3, the hole current generated by impact ionization is considerably smaller than the current flowing through the N ⁺ drain diffusion layer 8. On the other hand, the GIDL current is almost equal to the current flowing through the N ⁺ drain diffusion layer 8. That is, in writing using an impact ionization current, it is necessary to pass an extra drain current, whereas in writing using a GIDL current, it is almost unnecessary to pass such an extra drain current. As a result, in comparison with the case where the impact ionization current is used, in the present embodiment in which the GIDL current is used for writing, the writing operation can be performed with low power consumption.

  This is due to the following reason. In the case of writing using an impact ionization current, a large drain current is passed to cause impact ionization and generate holes. Therefore, it is necessary to flow a useless drain current that is many orders of magnitude larger than the amount of holes generated. On the other hand, in writing using a GIDL current, holes necessary for writing are generated by band-to-band tunneling, and therefore, electrons substantially equivalent to the generated holes only flow to the drain. Therefore, there is almost no wasteful power consumption.

  Further, as described above, in order to generate the GIDL current, a negative bias is applied to the gate electrode 4 and a positive bias is applied to the drain diffusion layer 8. Since the amount of GIDL current is determined by the potential difference between the gate and the drain, increasing the negative bias of the gate increases the GIDL current and increases the writing speed. Further, by increasing the negative bias of the gate, the body region 9 is also strongly negatively biased by the gate-body capacitive coupling. As a result, the source-body pn junction barrier is increased, and the amount of holes that can be accumulated in the body region 9 is increased. Further, since a reverse bias is strongly applied between the drain and body and between the source and body, the amount of holes generated from the pn junction depletion layer region increases, and the movement of the holes contributes as a write current. , Writing speed will be faster.

(Second Embodiment)
Next, a second embodiment of the present invention will be described. In the second embodiment, part of the low-concentration impurity diffusion layers 7a and 8a in the first embodiment is replaced with a high-concentration impurity diffusion layer. FIG. 4 is a cross-sectional view showing the structure of the semiconductor memory device according to the second embodiment of the present invention, and corresponds to a cross-sectional view taken along the line II in FIG. 1, similarly to FIG.

  In the present embodiment, as shown in FIG. 4, not only the low concentration impurity diffusion layers 7a and 8a, but also the high concentration impurity diffusion layers are interposed between the high concentration impurity diffusion layers 7b and 8b and the buried oxide film 2, respectively. 7c and 8c are formed. The low-concentration impurity diffusion layers 7a and 8a are formed below and in the vicinity of the sidewall insulating film 6, and the high-concentration impurity diffusion layers 7c and 8c are higher than the low-concentration impurity diffusion layers 7a and 8a, respectively. It is formed in the position away from.

  In the second embodiment configured as described above, since the impurity concentration of the source diffusion layer 7 and the drain diffusion layer 8 is higher than that of the first embodiment, parasitic resistance such as contact resistance is further increased. Reduced.

(Third embodiment)
Next, a third embodiment of the present invention will be described. In the third embodiment, the low-concentration impurity diffusion layers 7a and 8a in the first embodiment are substantially replaced with buried oxide films. FIG. 5 is a cross-sectional view showing the structure of the semiconductor memory device according to the third embodiment of the present invention, and corresponds to a cross-sectional view taken along the line II in FIG. 1, as in FIG.

  In this embodiment, as shown in FIG. 5, the source diffusion layer is composed of a high concentration impurity diffusion layer 7b, and the drain diffusion layer is composed of a high concentration impurity diffusion layer 8b. That is, the low-concentration impurity diffusion layers 7a and 8a are not formed. Further, the thickness of the P-type silicon layer 3 is approximately the same as that of the first and second embodiments. Furthermore, the thickness of the buried oxide film 2 is the same as that of the first embodiment below the P-type silicon layer 3, but the thickness is below the high-concentration impurity diffusion layers 7b and 8b. It is thicker than in the first embodiment, and the buried oxide film 2 is in direct contact with the high concentration impurity diffusion layers 7b and 8b.

  In the third embodiment configured as described above, the junction length of the pn junction is shortened as compared with the first and second embodiments, so that the junction leakage current is reduced and the retention time is increased.

  However, if the high-concentration impurity diffusion layers 7b and 8b are in direct contact with the buried oxide film 2 only by making the P-type silicon layer 3 thin, there is a possibility that a fully depleted transistor is obtained. When it becomes a fully depleted transistor, holes (charges) are not accumulated.

  Here, a method for manufacturing the semiconductor memory device according to the third embodiment will be described. 6A to 6D are cross-sectional views showing a method of manufacturing a semiconductor memory device according to the third embodiment of the present invention in the order of steps.

  In this method, as shown in FIG. 6A, an SOI substrate including a silicon substrate 1, a buried oxide film 2, and a P-type silicon layer 3 is prepared, and a gate insulating film 5 and a gate electrode 4 are formed thereon. Form. At this time, the thickness of the P-type silicon layer 3 is approximately the same as that of the first and second embodiments.

  Next, as shown in FIG. 6B, oxygen ions are implanted near the interface between the buried oxide film 2 and the P-type silicon layer 3 in a self-aligning manner using the gate electrode 4 as a mask.

  Next, annealing is performed to cause an oxidation reaction in the vicinity of the region of the P-type silicon layer 3 where oxygen ions are implanted. As a result, as shown in FIG. 6C, the portion of the buried oxide film 2 removed from the gate electrode 4 in plan view becomes thicker, and the P-type silicon layer 3 becomes thinner by that amount.

  Thereafter, using the gate electrode 4 as a mask, an N-type impurity is implanted into the P-type silicon layer 3 in a self-aligned manner, and this impurity is activated to form high-concentration impurity diffusion layers 7b and 8b.

  Then, an interlayer insulating film, wiring, and the like are formed to complete the semiconductor memory device.

(Fourth embodiment)
Next, a fourth embodiment of the present invention will be described. In the fourth embodiment, a P-type semiconductor is used as the gate electrode of an N-channel MOS transistor using an SOI substrate. FIG. 7 is a cross-sectional view showing the structure of a semiconductor memory device (DRAM) according to the fourth embodiment of the present invention, and corresponds to a cross-sectional view taken along the line II in FIG. 1, as in FIG. To do. Here, differences from the first embodiment will be mainly described.

In the fourth embodiment, as shown in FIG. 7, the word line WL is composed of a P ⁺ polysilicon layer and functions as the gate electrode 14 in each memory cell.

  In general, the larger the potential difference between the gate and the drain, the larger the GIDL current flows. In the fourth embodiment, since the conductivity types of the gate and the drain are different, when a write voltage similar to that of the first embodiment is used, a larger amount of GIDL current is obtained as shown in FIG. Therefore, faster writing is possible. On the other hand, when a writing speed comparable to that of the first embodiment is to be achieved, a lower writing voltage is used, so that power consumption can be reduced.

  Such an effect can also be obtained when the gate electrode 14 is formed from a metal material such as Mo, Ni, Al, or Co so that the potential difference between the gate and the drain is increased. Further, when the gate electrode 14 is formed from a silicide material such as CoSi or NiSi into which boron is introduced, the same effect can be obtained.

  In addition, it is possible to provide a semiconductor memory device in which a capacitor is not required to be formed and a manufacturing process can be simplified by being mixedly formed with a logic circuit or another nonvolatile memory in one semiconductor device.

  Next, the result of the simulation actually performed by the inventor will be described. In this simulation, as shown in FIG. 9, the thickness of the buried oxide film 2 is 0.2 μm, the thickness of the P-type silicon layer 3 is 0.1 μm, the thickness of the gate insulating film 5 is 5.8 nm, and the gate The length was 0.2 μm, and the length of the overlapping region (overlap) was 10 nm.

  Then, the value of the GIDL current was simulated by changing the impurity concentration in the high concentration impurity diffusion layers 7b and 8b. Here, at the time of data writing, −1.5 V is applied to the gate electrode 4 and 1.0 V is applied to the drain diffusion layer.

As a result of this simulation, as shown in FIG. 10, the GIDL current increased as the impurity concentration in the high-concentration impurity diffusion layers 7b and 8b (diffusion layer concentration in the overlap region) increased. In particular, a sufficient GIDL current could be obtained when the impurity concentration was 1.00 × 10 ¹⁹ cm ⁻³ or more. When the GIDL current is 1.0 × 10 ⁻⁷ A / μm or more, high-speed memory writing is possible. Therefore, the impurity concentration may be 1.00 × 10 ¹⁹ cm ⁻³ or more, and the GIDL current is substantially reduced. It is preferably 1.00 × 10 ²⁰ cm ⁻³ or more which is saturated.

  In addition, the retention time was measured (simulated) for the first to third embodiments. FIG. 11 is a timing chart showing changes in voltages when data “0” is written and held.

  In the state where the data “0” is held, the body voltage becomes negative, so that the source-body and drain-body pn junctions are reverse-biased. Then, by this reverse bias, holes are gradually injected into the body region, and data “0” is gradually lost. Therefore, if the change of the body voltage with respect to the elapsed time from the start of the data retention is plotted, the time during which the data “0” can be retained is calculated. In this simulation, the elapsed time until the body voltage reaches −0.2 V is defined as a time during which data can be retained (retention time).

In the structure of the first embodiment, the impurity concentration of the high-concentration impurity diffusion layers 7b and 8b is 1 × 10 ²⁰ cm ⁻³ , and the impurity concentration of the low-concentration impurity diffusion layers 7a and 8a is 6 × 10 ¹⁸ cm ^−3. As shown in FIG. 12, the retention time was 0.42 seconds. On the other hand, in the conventional structure in which the impurity concentration of the drain diffusion layer is 1 × 10 ²⁰ cm ⁻³ , the retention time is 0.15 seconds. That is, according to the first embodiment, the retention time can be extended by about 2.8 times.

In the structure of the second embodiment, when the impurity concentration of the high-concentration impurity diffusion layers 7b and 8b is 1 × 10 ²⁰ cm ⁻³ and the impurity concentration of the low-concentration impurity diffusion layers 7a and 8a is 6 × 10 ¹⁸ cm ^−3. As shown in FIG. 13, the retention time was 0.37 seconds.

In the structure of the third embodiment, when the impurity concentration of the high concentration impurity diffusion layers 7b and 8b is 1 × 10 ²⁰ cm ⁻³ , the retention time is as extremely long as 2.3 seconds as shown in FIG. became.

Hereinafter, various aspects of the present invention will be collectively described as supplementary notes.
(Appendix 1)
An insulating film;
A first conductivity type silicon layer formed on the insulating film;
A source diffusion layer and a drain diffusion layer of a second conductivity type formed on the insulating film and sandwiching the silicon layer therebetween;
A gate insulating film formed on the silicon layer;
A gate electrode formed on the gate insulating film;
Have
The drain diffusion layer is
A first impurity diffusion layer overlapping the gate electrode in plan view and having an impurity concentration of 1 × 10 ¹⁹ cm ⁻³ or more;
A second impurity diffusion layer formed under the first impurity diffusion layer, in contact with the silicon layer and having an impurity concentration lower than that of the first impurity diffusion layer;
A semiconductor memory device comprising:

(Appendix 2)
The drain diffusion layer further includes a third impurity diffusion layer that is formed under the first impurity diffusion layer and sandwiches the second impurity diffusion layer with the silicon layer,
2. The semiconductor memory device according to appendix 1, wherein an impurity concentration of the third impurity diffusion layer is higher than that of the second impurity diffusion layer.

(Appendix 3)
An insulating film in which a recess is formed;
A first conductivity type silicon layer formed on the recess;
A source diffusion layer and a drain diffusion layer of a second conductivity type formed on the insulating film outside the recess and sandwiching the silicon layer therebetween;
A gate insulating film formed on the silicon layer;
A gate electrode formed on the gate insulating film;
Have
The drain diffusion layer overlaps the gate electrode in plan view;
The semiconductor memory device, wherein the drain diffusion layer has an impurity concentration of 1 × 10 ¹⁹ cm ⁻³ or more.

(Appendix 4)
The thickness of the silicon layer is any one of appendices 1 to 3, wherein the silicon layer is partially depleted when a voltage for writing data is applied to the gate electrode. The semiconductor memory device described.

(Appendix 5)
An insulating film;
A P-type silicon layer formed on the insulating film;
An N-type source diffusion layer and drain diffusion layer formed on the insulating film and sandwiching the silicon layer therebetween,
A gate insulating film formed on the silicon layer;
A gate electrode made of a P-type semiconductor formed on the gate insulating film;
Have
The semiconductor memory device, wherein the drain diffusion layer overlaps with the gate electrode in plan view.

(Appendix 6)
An insulating film;
A P-type silicon layer formed on the insulating film;
An N-type source diffusion layer and drain diffusion layer formed on the insulating film and sandwiching the silicon layer therebetween,
A gate insulating film formed on the silicon layer;
A gate electrode formed on the gate insulating film and made of metal;
Have
The semiconductor memory device, wherein the drain diffusion layer overlaps with the gate electrode in plan view.

(Appendix 7)
The semiconductor memory device according to appendix 6, wherein the gate electrode is made of one kind of metal selected from the group consisting of Mo, Ni, Al, and Co.

(Appendix 8)
An insulating film;
A P-type silicon layer formed on the insulating film;
An N-type source diffusion layer and drain diffusion layer formed on the insulating film and sandwiching the silicon layer therebetween,
A gate insulating film formed on the silicon layer;
A gate electrode formed on the gate insulating film and made of silicide into which boron is introduced;
Have
The semiconductor memory device, wherein the drain diffusion layer overlaps with the gate electrode in plan view.

(Appendix 9)
9. The semiconductor memory device according to appendix 8, wherein the silicide is one selected from the group consisting of CoSi and NiSi.

(Appendix 10)
Forming a gate insulating film and a gate electrode on the silicon layer with respect to the SOI substrate including the substrate, the oxide film, and the first conductivity type silicon layer;
Implanting oxygen ions toward the interface between the oxide film and the silicon layer using the gate electrode as a mask;
Oxidizing the silicon layer portion of the silicon layer by heat treatment to thicken the oxide film;
Implanting ions of second conductivity type impurities into the silicon layer using the gate electrode as a mask;
Activating the second conductivity type impurity by heat treatment to form a source diffusion layer and a drain diffusion layer reaching the oxide film;
A method for manufacturing a semiconductor memory device, comprising:

1 is a layout diagram illustrating a structure of a semiconductor memory device according to a first embodiment of the present invention. It is sectional drawing along the II line | wire in FIG. It is a graph which shows the relationship between a gate voltage and an electric current. It is sectional drawing which shows the structure of the semiconductor memory device based on the 2nd Embodiment of this invention. It is sectional drawing which shows the structure of the semiconductor memory device based on the 3rd Embodiment of this invention. It is sectional drawing which shows the method of manufacturing the semiconductor memory device based on the 3rd Embodiment of this invention in process order. It is sectional drawing which shows the structure of the semiconductor memory device based on the 4th Embodiment of this invention. It is a graph which shows the relationship between the conductivity type of a gate, and an electric current. It is a figure which shows the structure made into the object of simulation. It is a graph which shows the relationship between the impurity concentration of a diffused layer, and a GIDL electric current. 6 is a timing chart showing changes in voltages when data “0” is written and held. It is a graph which shows the relationship between the elapsed time and body voltage in 1st Embodiment. It is a graph which shows the relationship between the elapsed time and body voltage in 2nd Embodiment. It is a graph which shows the relationship between the elapsed time and body voltage in 3rd Embodiment. It is sectional drawing which shows the structure of the conventional semiconductor memory device (DRAM).

Explanation of symbols

1: silicon substrate 2: buried oxide film 3: P-type silicon layer 4, 14: gate electrode 5: gate insulating film 6: sidewall insulating film 7: source diffusion layer 7a: low-concentration impurity diffusion layer 7b, 7c: high Concentration impurity diffusion layer 8: Drain diffusion layer 8a: Low concentration impurity diffusion layer 8b, 8c: High concentration impurity diffusion layer 9: Body region 10: SOI substrate 11: Neutral region BL: Bit line WL: Word line

Claims (4)

An insulating film in which a recess is formed;
A first conductivity type silicon layer formed on the recess;
A source diffusion layer and a drain diffusion layer of a second conductivity type formed on the insulating film outside the recess and sandwiching the silicon layer therebetween;
A gate insulating film formed on the silicon layer;
A gate electrode formed on the gate insulating film;
Have
The drain diffusion layer overlaps the gate electrode in plan view;
The impurity concentration of the drain diffusion layer is 1 × 10 ¹⁹ cm ⁻³ or more,
2. The semiconductor memory device according to claim 1, wherein the thickness of the silicon layer is such that the silicon layer is partially depleted when a voltage for writing data is applied to the gate electrode. An insulating film;
A first conductivity type silicon layer formed on the insulating film;
A source diffusion layer and a drain diffusion layer of a second conductivity type formed on the insulating film and sandwiching the silicon layer therebetween;
A gate insulating film formed on the silicon layer;
A gate electrode formed on the gate insulating film;
Have
The drain diffusion layer is
A first impurity diffusion layer overlapping the gate electrode in plan view and having an impurity concentration of 1 × 10 ¹⁹ cm ⁻³ or more;
A second impurity diffusion layer formed under the first impurity diffusion layer, in contact with the silicon layer and having an impurity concentration lower than that of the first impurity diffusion layer;
Have
The thickness of the silicon layer is a thickness at which the silicon layer is partially depleted when a voltage for writing data is applied to the gate electrode.
The drain diffusion layer further includes a third impurity diffusion layer that is formed under the first impurity diffusion layer and sandwiches the second impurity diffusion layer with the silicon layer,
The impurity concentration of the third impurity diffusion layer of a semi-conductor memory device you being higher than that of said second impurity diffusion layer.   The first conductivity type is P-type;
  The second conductivity type is N-type;
  The semiconductor memory device according to claim 1, wherein the gate electrode is made of a P-type semiconductor.   The first conductivity type is P-type;
  The second conductivity type is N-type;
  The semiconductor memory device according to claim 1, wherein the gate electrode is made of a metal.

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