JP4452291B2 - Dynamic RAM - Google Patents

Description

  The present invention relates to a dynamic RAM (random access memory) that employs a so-called VSS precharge method in which a bit line is precharged to a ground voltage with respect to a precharge method of a bit line to which a memory cell is connected.

  Conventionally, as a bit line precharge method in a dynamic RAM, a Vii precharge method in which a bit line is precharged to an internal power supply voltage Vii, or a bit line precharged to a voltage half that of the internal power supply voltage Vii Although the Vii precharge method has been proposed, the 1/2 · Vii precharge method has become the mainstream because low power consumption can be achieved.

  FIG. 5 is a circuit diagram showing an example of a sense amplifier mounted in a dynamic RAM. In FIG. 5, BL and / BL are bit lines that make a pair, PSA and NSA are sense amplifier drive voltages, and 1 and 2 are pull-ups. PMOS transistors 3 and 4 are nMOS transistors forming pull-down elements.

  FIG. 6 is a waveform diagram for explaining the operation of the sense amplifier in the dynamic RAM in which the sense amplifier shown in FIG. 5 is mounted and the 1/2 · Vii precharge method is adopted.

  In such a dynamic RAM, before the data is read from the memory cell, the sense amplifier drive voltages PSA and NSA are set to 1/2 · Vii, and the bit lines BL and / BL are set by a bit line precharge circuit (not shown). Is precharged to 1/2 · Vii.

  For example, when a memory cell connected to the bit line BL is selected and the selected memory cell stores, for example, high data, that is, the selected memory cell accumulates electric charge. In this case, the voltage of the bit line BL becomes 1/2 · Vii + ΔV.

  However, ΔV is a minute voltage generated when the electric charge accumulated in the cell capacitor of the selected memory cell is divided between the cell capacitor and the bit line BL.

  Subsequently, the sense amplifier drive voltage PSA = Vii and the sense amplifier drive voltage NSA = VSS are set, and the voltage of the bit line / BL is pulled down from 1/2 · Vii to the ground voltage VSS by the nMOS transistor 4, and the bit line BL Is pulled up from 1/2 · Vii + ΔV to the internal power supply voltage Vii by the pMOS transistor 1.

  When such a 1/2 · Vii precharge method is employed, the gate-source voltage of the pMOS transistors 1 and 2 and the nMOS transistors 3 and 4 that are cross-coupled as the internal power supply voltage Vii is lowered. Since Vgs becomes small, there is a problem that the time required to amplify the minute voltage ΔV between the bit lines BL and / BL becomes long.

  On the other hand, when the VSS precharge method in which the bit lines BL and / BL are precharged to the ground voltage VSS is adopted, the operation speed of the sense amplifier can be increased.

  FIG. 7 is a waveform diagram for explaining the operation of the sense amplifier in the dynamic RAM in which the sense amplifier shown in FIG. 5 is mounted and the VSS precharge method is adopted.

  In such a dynamic RAM, before reading data from the memory cell, the sense amplifier drive voltage PSA is set to the ground voltage VSS, and the bit lines BL and / BL are connected to the ground voltage VSS by a bit line precharge circuit (not shown). Is precharged.

  For example, when a memory cell connected to the bit line BL is selected and the selected memory cell stores, for example, high data, that is, the selected memory cell accumulates electric charge. In this case, the voltage of the bit line BL becomes ΔV, and the bit line / BL becomes ΔVd (<ΔV) due to a dummy cell (not shown).

  Subsequently, the sense amplifier drive voltage PSA = Vii is set, and the voltages of the bit lines BL and / BL are increased by the pMOS transistors 1 and 2, but thereafter, the sense amplifier drive voltage NSA = VSS, the pMOS transistor 1 = ON, and the pMOS The transistor 2 = OFF, the nMOS transistor 3 = OFF, and the nMOS transistor 4 = ON, and the voltage of the bit line BL = Vii and the voltage of the bit line / BL = VSS.

  When such a VSS precharge method is employed, the gate-source voltage Vgs of the pMOS transistors 1 and 2 can be increased, and the minute voltage ΔV−ΔVd between the bit lines BL and / BL is amplified. The time required can be shortened.

  FIG. 8 is a circuit diagram showing a configuration of a general memory cell included in the dynamic RAM. In FIG. 8, WL is a word line, 5 is a cell transistor for charge transfer control composed of an nMOS transistor, and 6 is a storage medium. It is a cell capacitor.

  The cell transistor 5 has a source connected to the bit line BL and a gate connected to the word line WL. The cell capacitor 6 has one electrode connected to the drain of the cell transistor 5 and the other electrode grounded. Yes.

  Here, in the case of adopting the VSS precharge method, when writing high data (logic 1) to the memory cell, the voltage of the word line WL = SVii, the voltage of the bit line BL = Vii, the voltage of the storage node 7 = Vii, and when writing row data (logic 0), the voltage of the word line WL = SVii, the voltage of the bit line BL = VSS, and the voltage of the storage node 7 = VSS.

  However, SVii is a boosted voltage obtained by boosting the internal power supply voltage Vii by a booster circuit (not shown), and is a voltage equal to or higher than Vii + VTHn (the threshold voltage of the nMOS transistor).

  Here, when the VSS precharge method is employed, when the voltage of the bit line BL is set to the ground voltage VSS when the memory cell shown in FIG. 8 is not selected, the voltage between the gate and the source of the cell transistor 5 is set. Vgs becomes 0 [V].

  As a result, for example, when high data is stored in the storage node 7, the cell transistor 5 shows the gate-source voltage Vgs-drain-source current ids characteristic of the cell transistor 5 as shown in FIG. Leak current i flows between the drain and the source.

  For this reason, the voltage drop of the storage node 7 advances and the refresh time tREF is deteriorated. At the time of data reading, the voltage (ΔV) appearing from the cell to the bit line BL is when Vii is stored in the cell. There is a problem that the voltage becomes lower than that, and the margin of the sense amplifier for high data becomes small.

  In the case of adopting the 1/2 · Vii precharge method, when the potential of the storage node 7 of the memory cell is 0 [V], the gate-drain voltage Vgd is 0 [V]. Therefore, the potential of the storage node 7 rises due to the leakage current of the cell transistor 5.

  However, in this case, the gate-drain voltage Vgd becomes negative and the back bias becomes strong, so that the leakage current of the cell transistor 5 is suppressed.

  In view of the above, the present invention is a dynamic RAM that employs a VSS precharge method as a bit line precharge method, and reduces leakage current of a cell transistor when high data is written in a memory cell. Dynamic RAM that can be used, and the sense amplifier margin for high data output to the bit line and the sense amplifier margin for low data output to the bit line can be made comparable. An object is to provide a RAM.

  In the present invention, when the word line is not selected, the word line is set to a negative voltage, whereby the gate-source voltage Vgs of the transistor of the memory cell can be reduced by a negative value, and the leakage current can be reduced. In addition, since the bit line is precharged to the ground voltage, the high level of the bit line can be lowered. Therefore, when not selected, the word line is set to a negative voltage and the threshold voltage can be reduced. Thus, it is not necessary to use the boosted voltage as a high level voltage for driving the word line.

In the first invention (the dynamic RAM according to claim 1), the paired first and second bit lines and the current input / output electrode are connected to the first bit line, and the control electrode is connected to the word line. When the cell transistor and the first electrode are connected to the second current input / output electrode of the cell transistor and the second electrode is grounded, and the memory cell and the first and second bit lines are precharged, A bit line precharge circuit for precharging first and second bit lines to a ground voltage; a reference voltage generating circuit for generating a reference voltage for the second bit line when reading data from the memory cell; and the memory cell In a dynamic RAM having a sense amplifier that amplifies a difference voltage generated between the first and second bit lines when reading data, the word line is set to a negative voltage when the word line is not selected. It includes a word decoder, the reference voltage generating circuit includes a first electrode connected to the second bit line, is that composed of a capacitor connected to the second electrode to the dummy word line.

According to the first aspect of the invention, since the word decoder having the negative voltage on the word line when the word line is not selected is provided, even when high data is stored in the memory cell, the cell transistor Leakage current can be reduced, and the configuration of the reference voltage generation circuit can be simplified.

  According to a second invention (dynamic RAM according to claim 2), in the first invention, the reference voltage generation circuit uses the first bit line from the memory cell as a reference voltage when there is no leak in the cell transistor and the cell capacitor. When high data is output, a voltage lower than 1/2 of the voltage appearing on the first bit line is generated on the second bit line.

  According to the second invention, the same operation as that of the first invention can be obtained, and the sense amplifier margin for the high data output to the first bit line and the first bit line are output. The margin of the sense amplifier for the row data can be made similar.

  A sixth invention (dynamic RAM according to claim 6) precharges the first electrode of the dummy cell capacitor when precharging the first and second bit lines in the fourth or fifth invention. A dummy cell capacitor precharge circuit is provided.

According to a third invention (dynamic RAM according to claim 3 ), in the first invention, the capacitor is a MOS capacitor.

According to a fourth aspect of the present invention (the dynamic RAM according to the fourth aspect ), in the first or third aspect of the invention, the voltage when the dummy word line is not selected is configured to be a ground voltage. .

According to the fourth invention, it is possible to obtain the same operation as that of the first or third invention, and to reduce the current consumption in the negative voltage generating circuit.

In a fifth invention (dynamic DRAM according to claim 5 ), in the first invention, the word decoder decodes an address signal, and when the decoded address indicates the word line, the boosted voltage is applied. A transistor circuit applied to a word line, wherein the boosted voltage is generated from an internal power supply voltage and is higher than the internal power supply voltage;

According to a sixth invention (dynamic DRAM of claim 6 ), in the fifth invention, when the decoded address does not indicate the word line, the transistor circuit applies a negative voltage to the word line. It is a feature.

According to a seventh invention (dynamic DRAM according to claim 7 ), in the first invention, the word decoder decodes an address signal, and when the decoded address indicates the word line, the internal power supply voltage is set. A transistor circuit applied to the word line is included, and as a result, the word line is selected without using a boosted voltage higher than the internal power supply voltage. In the fifth invention, the boosted voltage is applied to the selected word line. However, in the seventh invention, it is specified that the operation is possible even if the boosted voltage is not applied to the word line. This is because when the word line is not selected, the word line is reset to a negative voltage, so that the threshold voltage of the cell transistor can be reduced, and since the bit line is reset to the ground voltage, the high level voltage of the bit line is lowered. Because it can.

In an eighth invention (dynamic DRAM according to claim 8 ), in the seventh invention, when the decoded address does not indicate the word line, the transistor circuit applies a negative voltage to the word line. It is characterized by this.

According to a ninth invention (dynamic RAM according to claim 9 ), in the first to eighth inventions, the word decoder includes a first word decoder including a first inverter and a second inverter including a second inverter. This includes a third word decoder, a third word decoder, a third inverter, and a fourth inverter.

  The first word decoder operates using the power supply voltage on the high voltage side as the internal power supply voltage and the power supply voltage on the low voltage side as the ground voltage, and decodes the upper bits of the row address for selecting the word line. The NAND circuit operates with a boosted voltage obtained by boosting the internal power supply voltage as the power supply voltage on the high voltage side and a negative power supply voltage on the low voltage side, and the output of the first NAND circuit is set to the boosted voltage. The first level conversion circuit that performs level conversion and converts the low level to a negative voltage, and operates with the power supply voltage on the high voltage side as the boost voltage and the power supply voltage on the low voltage side as the negative voltage. And a first inverter that inverts the output.

  The second word decoder operates using the power supply voltage on the high voltage side as the internal power supply voltage and the power supply voltage on the low voltage side as the ground voltage, and decodes the lower bits of the row address for selecting the word line. The NAND circuit is operated with the power supply voltage on the high voltage side as the boosted voltage, the power supply voltage on the low voltage side as the negative voltage, and the output of the second NAND circuit is level-converted to the boosted voltage, and the low level is the negative voltage. And a second inverter that operates with the high-voltage power supply voltage as the boosted voltage and the low-voltage power supply voltage as the negative voltage and inverts the output of the second level conversion circuit. It consists of

  The third inverter operates with the power supply voltage on the high voltage side as the boosted voltage, the power supply voltage on the low voltage side as the negative voltage, and inverts the output of the second inverter. The fourth inverter The power supply voltage on the side is operated with the boosted voltage, the power supply voltage on the low voltage side is operated with a negative voltage, and the output of the third inverter is inverted.

  The third word decoder has a first p having a current input electrode connected to the output terminal of the first inverter, a current output electrode connected to the word line, and a control electrode connected to the output terminal of the third inverter. A channel insulated gate field effect transistor, a current input electrode connected to the output terminal of the first inverter, a current output electrode connected to the word line, and a control electrode connected to the output terminal of the fourth inverter N-channel insulated gate field effect transistor, a current input electrode connected to the word line, a control electrode connected to the output terminal of the third inverter, and a second voltage applied to the current output electrode by a negative voltage It consists of a channel insulated gate field effect transistor.

A tenth invention (dynamic RAM according to claim 10), in the invention of the first to ninth, the word decoder, a second comprising a first word decoder including a first inverter, a second inverter This includes a third word decoder, a third word decoder, a third inverter, and a fourth inverter.

  The first word decoder operates using the power supply voltage on the high voltage side as the internal power supply voltage and the power supply voltage on the low voltage side as the ground voltage, and decodes the upper bits of the row address for selecting the word line. The NAND circuit operates with a boosted voltage obtained by boosting the internal power supply voltage as the power supply voltage on the high voltage side and a negative power supply voltage on the low voltage side, and the output of the first NAND circuit is set to the boosted voltage. The first level conversion circuit that performs level conversion and converts the low level to a negative voltage, and operates with the power supply voltage on the high voltage side as the boost voltage and the power supply voltage on the low voltage side as the negative voltage. And a first inverter that inverts the output.

  The second word decoder operates using the power supply voltage on the high voltage side as the internal power supply voltage and the power supply voltage on the low voltage side as the ground voltage, and decodes the lower bits of the row address for selecting the word line. The NAND circuit is operated with the power supply voltage on the high voltage side as the boosted voltage, the power supply voltage on the low voltage side as the negative voltage, and the output of the second NAND circuit is level-converted to the boosted voltage, and the low level is the negative voltage. And a second inverter that operates with the high-voltage power supply voltage as the boosted voltage and the low-voltage power supply voltage as the negative voltage and inverts the output of the second level conversion circuit. It consists of

  The third inverter operates with the power supply voltage on the high voltage side as the boost voltage and the power supply voltage on the low voltage side as the negative voltage, and inverts the output of the first inverter. The fourth inverter The power supply voltage on the side is operated as a boosted voltage, the power supply voltage on the low voltage side is operated as a negative voltage, and the output of the second inverter is inverted.

  The third word decoder has a first p having a current input electrode connected to the output terminal of the second inverter, a current output electrode connected to the word line, and a control electrode connected to the output terminal of the third inverter. A channel-insulated gate field effect transistor, a current input electrode connected to the word line, a control electrode connected to the output terminal of the third inverter, and a first n-channel insulation in which a negative voltage is applied to the current output electrode A gate type field effect transistor, a second n-channel insulated gate type in which a current output electrode is connected to the word line, a control electrode is connected to an output terminal of a fourth inverter, and a negative voltage is applied to the current output electrode It consists of a field effect transistor.

  According to the present invention, it is possible to reduce the leakage current of the cell transistor when high data is written in the memory cell, and further, the sense amplifier margin for the high data output to the bit line, The margin of the sense amplifier for the row data output to the bit line can be made comparable.

The first and second embodiments of the present invention will be described below with reference to FIGS.
First Embodiment FIG. 1 and FIG.
FIG. 1 is a circuit diagram showing a part of one column section provided in the first embodiment of the present invention. In FIG. 1, 8 is a bit line precharge circuit for precharging the bit lines BL and / BL, PE1 is a control signal, and 9 and 10 are nMOS transistors whose ON and OFF are controlled by the control signal PE1. .

  The nMOS transistor 9 is configured such that the drain is connected to the bit line BL, the source is grounded, and the control signal PE1 is applied to the gate. The nMOS transistor 10 has the drain connected to the bit line / BL. The source is grounded, and the control signal PE1 is applied to the gate.

  Here, at the time of the bit line precharge, the control signal PE1 = Vii, the nMOS transistor 9 = ON, and the nMOS transistor 10 = ON, the bit line BL voltage = VSS, and the bit line / BL voltage = VSS. In cases other than charging, the voltage of the control signal PE1 = VSS, the nMOS transistor 9 = OFF, and the nMOS transistor 10 = OFF.

  Further, 11 is a memory cell, 12 is a cell transistor for charge transfer control composed of an nMOS transistor, and 13 is a cell capacitor constituting a storage medium.

  The cell transistor 12 has a gate connected to the word line WL and a source connected to the bit line BL. The cell capacitor 13 has one electrode connected to the drain of the cell transistor 12 and the other electrode grounded. Yes.

  Here, when high data is written to the memory cell 11, the voltage of the word line WL = SVii, the voltage of the bit line BL = Vii, the voltage of the storage node 14 = Vii, and when writing low data. The voltage of the word line WL = SVii, the voltage of the bit line BL = VSS, and the voltage of the storage node 14 = VSS.

  Reference numeral 15 denotes a dummy cell constituting a reference voltage generating circuit, 16 is a dummy cell transistor for charge transfer control composed of an nMOS transistor, and 17 is a dummy cell capacitor.

  The dummy cell transistor 16 has a gate connected to the dummy word line DWL and a source connected to the bit line / BL, and the dummy cell capacitor 17 has one electrode connected to the drain of the dummy cell transistor 16. The other electrode is grounded.

  Note that the capacitance value of the dummy cell capacitor 17 is ½ or less of the capacitance of the cell capacitor 13, and the cell transistor 12 and the cell capacitor 13 are within a range in which a sense amplifier 22 described later can perform an accurate amplification operation. When there is no leak in the memory cell 11, a high voltage is output from the memory cell 11 to the bit line BL, and a voltage lower than ½ of the voltage appearing on the bit line BL can be generated on the bit line / BL. Is done.

  Further, the voltage of the dummy word line DWL is set to the boosted voltage SVii when selected, and to the negative voltage VBB (for example, −0.4 [V]) when not selected.

  Reference numeral 18 denotes a dummy cell capacitor precharge circuit, PE2 is a control signal, and 19 is an nMOS transistor whose ON and OFF are controlled by the control signal PE2.

  The nMOS transistor 19 is configured such that the drain is connected to the Vii power supply line 20 that supplies the internal power supply voltage Vii, the source is connected to the storage node 21 of the dummy cell 15, and the control signal PE2 is applied to the gate. Yes.

  Here, when the bit line is precharged, the control signal PE2 = Vii + VTHn + α, the nMOS transistor 19 = ON, and the voltage of the storage node 21 = Vii. When the bit line is not precharged, the control signal PE2 = VSS (or negative). Voltage VBB) and nMOS transistor 19 = OFF.

  Reference numeral 22 denotes a sense amplifier composed of a flip-flop circuit, reference numerals 23 and 24 denote pMOS transistors that form pull-up elements, and reference numerals 25 and 26 denote nMOS transistors that form pull-down elements.

  The pMOS transistor 23 is configured such that the drain is connected to the bit line BL, the gate is connected to the bit line / BL, and the sense amplifier drive voltage PSA is applied to the source. The pMOS transistor 24 has the drain connected to the bit line / BL. It is connected to the line / BL, the gate is connected to the bit line BL, and the sense amplifier drive voltage PSA is applied to the source.

  The nMOS transistor 25 is configured such that the drain is connected to the bit line BL, the gate is connected to the bit line / BL, and the sense amplifier drive voltage NSA is applied to the source. Are connected to the bit line / BL, the gate is connected to the bit line BL, and the sense amplifier drive voltage NSA is applied to the source.

  FIG. 2 is a circuit diagram showing a part of a word decoder provided in the first embodiment of the present invention. In FIG. 2, 29 is a main word decoder constituting a first word decoder, and 30 is a NAND circuit for decoding an internal row address signal ADD1 for selecting a word line WL.

  Reference numeral 31 denotes a level conversion circuit for converting the output of the NAND circuit 30 into a boosted voltage SVii at a high level and converting the output into a negative voltage VBB at a low level. In the level conversion circuit 31, 32 is an output of the NAND circuit 30. The nMOS transistor is controlled to be turned on and off by the gate, the source is grounded, and the gate is connected to the output terminal of the NAND circuit 30.

  Reference numeral 33 denotes a pMOS flip-flop circuit, and reference numerals 34 and 35 denote pMOS transistors forming pull-up elements.

  The pMOS transistor 34 has a source connected to the SVii power supply line 36, a gate connected to the drain of the pMOS transistor 35, and a drain connected to the drain of the nMOS transistor 32. The pMOS transistor 35 has a source connected to the SVii power supply line 36. And the gate thereof is connected to the drain of the pMOS transistor 34.

  Reference numeral 37 denotes a pMOS transistor whose ON and OFF are controlled by the output of the NAND circuit 30. The source is connected to the Vii power line 38 and the gate is connected to the output terminal of the NAND circuit 30.

  Reference numeral 39 denotes an nMOS flip-flop circuit, and reference numerals 40 and 41 denote nMOS transistors serving as pull-down elements.

  The nMOS transistor 40 has a source connected to the VBB power supply line 42 that supplies the negative voltage VBB, a gate connected to the drain of the nMOS transistor 41, and a drain connected to the drain of the pMOS transistor 37.

  The nMOS transistor 41 has a source connected to the VBB power supply line 42, a gate connected to the drain of the nMOS transistor 40, and a drain connected to the drain of the pMOS transistor 35.

  43 is a CMOS inverter, 44 is a pMOS transistor, and 45 is an nMOS transistor.

  The pMOS transistor 44 has a source connected to the SVii power supply line 36 and a gate connected to a node 46 that is a connection point between the drain of the pMOS transistor 35 and the drain of the nMOS transistor 41.

  The nMOS transistor 45 has a drain connected to the drain of the pMOS transistor 44, a gate connected to the node 46, and a source connected to the VBB power supply line 42.

  Reference numeral 47 denotes a quarter word decoder which forms a second word decoder. Reference numeral 48 denotes a NAND circuit which decodes the internal row address signal ADD2 for selecting the word line WL.

  Reference numeral 49 denotes a level conversion circuit for converting the output of the NAND circuit 48 into a boosted voltage SVii and converting the low level into a negative voltage VBB. In the level conversion circuit 49, 50 denotes an output of the NAND circuit 48. The nMOS transistor is controlled to be turned on and off by the gate, the source is grounded, and the gate is connected to the output terminal of the NAND circuit 48.

  Reference numeral 51 denotes a pMOS flip-flop circuit, and reference numerals 52 and 53 denote pMOS transistors that form pull-up elements.

  The pMOS transistor 52 has a source connected to the SVii power supply line 36, a gate connected to the drain of the pMOS transistor 53, and a drain connected to the drain of the nMOS transistor 50. The pMOS transistor 53 has a source connected to the SVii power supply line 36. And the gate thereof is connected to the drain of the pMOS transistor 52.

  Reference numeral 54 denotes a pMOS transistor whose ON / OFF is controlled by the output of the NAND circuit 48, and the source is connected to the Vii power line 38 and the gate is connected to the output terminal of the NAND circuit 48.

  Reference numeral 55 denotes an nMOS flip-flop circuit, and reference numerals 56 and 57 denote nMOS transistors forming pull-down elements.

  The nMOS transistor 56 has a source connected to the VBB power supply line 42, a gate connected to the drain of the nMOS transistor 57, and a drain connected to the drain of the pMOS transistor 54.

  The nMOS transistor 57 has a source connected to the VBB power supply line 42, a gate connected to the drain of the nMOS transistor 56, and a drain connected to the drain of the pMOS transistor 53.

  58 is a CMOS inverter, 59 is a pMOS transistor, and 60 is an nMOS transistor.

  The pMOS transistor 59 has a source connected to the SVii power supply line 36 and a gate connected to a node 61 that is a connection point between the drain of the pMOS transistor 53 and the drain of the nMOS transistor 57.

  The nMOS transistor 60 has a drain connected to the drain of the pMOS transistor 59, a gate connected to the node 61, and a source connected to the VBB power supply line 42.

  62 is a CMOS inverter, 63 is a pMOS transistor, and 64 is an nMOS transistor.

  The pMOS transistor 63 has a source connected to the SVii power supply line 36, a gate connected to the output terminal of the CMOS inverter 58, an nMOS transistor 64 has a drain connected to the drain of the pMOS transistor 63, and a gate connected to the CMOS inverter 58. The source is connected to the VBB power line 42.

  65 is a CMOS inverter, 66 is a pMOS transistor, and 67 is an nMOS transistor.

  The pMOS transistor 66 has a source connected to the SVii power supply line 36, a gate connected to the output terminal of the CMOS inverter 62, an nMOS transistor 67 has a drain connected to the drain of the pMOS transistor 66, and a gate connected to the CMOS inverter 62. The source is connected to the VBB power line 42.

  Reference numeral 68 denotes a sub-word decoder constituting a third word decoder, 69 is a pMOS transistor, and 70 and 71 are nMOS transistors.

  The pMOS transistor 69 has a source connected to the output terminal of the CMOS inverter 43, a gate connected to the output terminal of the CMOS inverter 62, and a drain connected to the word line WL.

  The nMOS transistor 70 has a drain connected to the output terminal of the CMOS inverter 43, a gate connected to the output terminal of the CMOS inverter 65, and a source connected to the word line WL.

  The nMOS transistor 71 has a drain connected to the word line WL, a gate connected to the output terminal of the CMOS inverter 62, and a source connected to the VBB power supply line.

  In the first embodiment of the present invention configured as described above, when the word line WL is not selected, the main word decoder 29 is not selected and the quarter word decoder 47 is not selected. When the decoder 29 is selected and the quarter word decoder 47 is not selected, the main word decoder 29 is not selected and the quarter word decoder 47 is selected.

  If the main word decoder 29 is not selected and the quarter word decoder 47 is not selected, the output of the NAND circuit 30 becomes Vii in the main word decoder 29, the nMOS transistor 32 is ON, and the pMOS transistor 37 is ON. = OFF.

  As a result, the pMOS transistor 35 = ON, the pMOS transistor 34 = OFF, the nMOS transistor 40 = ON, the nMOS transistor 41 = OFF, and the voltage at the node 46 = SVii. In the CMOS inverter 43, the pMOS transistor 44 = OFF and the nMOS transistor 45 = ON, and the output of the CMOS inverter 43 = VBB.

  In the quarter word decoder 47, the output of the NAND circuit 48 is Vii, the nMOS transistor 50 is ON, and the pMOS transistor 54 is OFF.

  As a result, the pMOS transistor 53 = ON, the pMOS transistor 52 = OFF, the nMOS transistor 56 = ON, the nMOS transistor 57 = OFF, and the voltage at the node 61 = SVii. In the CMOS inverter 58, the pMOS transistor 59 = OFF and the nMOS transistor 60 = ON, and the output of the CMOS inverter 58 = VBB.

  As a result, in the CMOS inverter 62, the pMOS transistor 63 = ON and the nMOS transistor 64 = OFF, and the output of the CMOS inverter 62 = SVii. In the CMOS inverter 65, the pMOS transistor 66 = OFF and the nMOS transistor 67 = ON. The output of the CMOS inverter 65 = VBB.

  Therefore, in the sub word decoder 68, the pMOS transistor 69 = OFF, the nMOS transistor 70 = OFF, the nMOS transistor 71 = ON, and the voltage of the word line WL = VBB.

  When the main word decoder 29 is selected and the quarter word decoder 47 is not selected, in the main word decoder 29, the output of the NAND circuit 30 is VSS, the nMOS transistor 32 is OFF, and the pMOS transistor 37 is ON. Become.

  As a result, the nMOS transistor 41 = ON, the nMOS transistor 40 = OFF, the pMOS transistor 34 = ON, the pMOS transistor 35 = OFF, and the voltage at the node 46 = VBB. In the CMOS inverter 43, the pMOS transistor 44 = ON and the nMOS transistor 45 = OFF, and the output of the CMOS inverter 43 = SVii.

  On the other hand, in the quarter word decoder 47, the output of the NAND circuit 48 = Vii, the nMOS transistor 50 = ON, and the pMOS transistor 54 = OFF.

  As a result, the pMOS transistor 53 = ON, the pMOS transistor 52 = OFF, the nMOS transistor 56 = ON, the nMOS transistor 57 = OFF, and the voltage at the node 61 = SVii. In the CMOS inverter 58, the pMOS transistor 59 = OFF and the nMOS transistor 60 = ON, and the output of the CMOS inverter 58 = VBB.

  As a result, in the CMOS inverter 62, the pMOS transistor 63 = ON and the nMOS transistor 64 = OFF, and the output of the CMOS inverter 62 = SVii. In the CMOS inverter 65, the pMOS transistor 66 = OFF and the nMOS transistor 67 = ON. The output of the CMOS inverter 65 = VBB.

  Therefore, in the sub word decoder 68, the pMOS transistor 69 = OFF, the nMOS transistor 70 = OFF, the nMOS transistor 71 = ON, and the voltage of the word line WL = VBB.

  When the main word decoder 29 is not selected and the quarter word decoder 47 is selected, in the main word decoder 29, the output of the NAND circuit 30 becomes Vii, the nMOS transistor 32 is ON, and the pMOS transistor 37 is OFF. It becomes.

  As a result, the pMOS transistor 35 = ON, the pMOS transistor 34 = OFF, the nMOS transistor 40 = ON, the nMOS transistor 41 = OFF, and the voltage at the node 46 = SVii. In the CMOS inverter 43, the pMOS transistor 44 = OFF and the nMOS transistor 45 = ON, and the output of the CMOS inverter 43 = VBB.

  On the other hand, in the quarter word decoder 47, the output of the NAND circuit 48 = VSS, the nMOS transistor 50 = OFF, and the pMOS transistor 54 = ON.

  As a result, the nMOS transistor 57 = ON, the nMOS transistor 56 = OFF, the pMOS transistor 52 = ON, the pMOS transistor 53 = OFF, and the voltage at the node 61 = VBB. In the CMOS inverter 58, the pMOS transistor 59 = ON and the nMOS transistor 60 = OFF, and the output of the CMOS inverter 58 = SVii.

  As a result, in the CMOS inverter 62, the pMOS transistor 63 = OFF and the nMOS transistor 64 = ON, and the output of the CMOS inverter 62 = VBB. In the CMOS inverter 65, the pMOS transistor 66 = ON and the nMOS transistor 67 = OFF. The output of the CMOS inverter 65 = SVii.

  Therefore, in the sub word decoder 68, the pMOS transistor 69 = ON, the nMOS transistor 70 = ON, the nMOS transistor 71 = OFF, and the voltage of the word line WL = VBB.

  When the word line WL is selected, in the main word decoder 29, the output of the NAND circuit 30 = VSS, the nMOS transistor 32 = OFF, and the pMOS transistor 37 = ON.

  As a result, the nMOS transistor 41 = ON, the nMOS transistor 40 = OFF, the pMOS transistor 34 = ON, the pMOS transistor 35 = OFF, and the voltage at the node 46 = VBB. In the CMOS inverter 43, the pMOS transistor 44 = ON and the nMOS transistor 45 = OFF, and the output of the CMOS inverter 43 = SVii.

  In the quarter word decoder 47, the output of the NAND circuit 48 = VSS, the nMOS transistor 50 = OFF, and the pMOS transistor 54 = ON.

  As a result, the nMOS transistor 57 = ON, the nMOS transistor 56 = OFF, the pMOS transistor 52 = ON, the pMOS transistor 53 = OFF, and the voltage at the node 61 = VBB. In the CMOS inverter 58, the pMOS transistor 59 = ON and the nMOS transistor 60 = OFF, and the output of the CMOS inverter 58 = SVii.

  As a result, in the CMOS inverter 62, the pMOS transistor 63 = OFF and the nMOS transistor 64 = ON, and the output of the CMOS inverter 62 = VBB. In the CMOS inverter 65, the pMOS transistor 66 = ON and the nMOS transistor 67 = OFF. The output of the CMOS inverter 65 = SVii.

  Therefore, in the sub word decoder 68, the pMOS transistor 69 = ON, the nMOS transistor 70 = ON, the nMOS transistor 71 = OFF, and the voltage of the word line WL = SVii.

  Thus, according to the first embodiment of the present invention, when the word line WL is not selected, the voltage of the word line WL can be set to the negative voltage VBB. Even when the voltage of V i is Vii, the leakage current of the cell transistor 12 can be reduced.

  Further, according to the first embodiment of the present invention, the capacitance value of the dummy cell capacitor 17 does not leak in the cell transistor 12 and the cell capacitor 13 as long as the sense amplifier 22 can perform an accurate amplification operation. In this case, when high data is output from the memory cell 11 to the bit line BL, the voltage is set to a value that can cause the bit line / BL to generate a voltage lower than ½ of the voltage appearing on the bit line BL. In consideration of the actual minute leak, the margin of the sense amplifier 22 for the high data output to the bit line BL and the margin of the sense amplifier 22 for the low data output to the bit line BL can be made comparable.

In the first embodiment of the present invention, the voltage when the dummy word line DWL is not selected is set to the negative voltage VBB. Instead, the dummy word line DWL is anticipated in anticipation of a leak in the dummy cell 15. The voltage at the time of non-selection is the ground voltage VSS, so that the power consumption in the negative voltage generation circuit (not shown) can be reduced and the power consumption can be reduced.
Second Embodiment FIG. 3 and FIG. 4
FIG. 3 is a circuit diagram showing a part of one column portion provided in the second embodiment of the present invention. In the second embodiment of the present invention, the dummy cell 15 and the dummy cell 15 provided in the first embodiment of the present invention and A MOS capacitor 73 is provided in place of the dummy cell capacitor precharge circuit 18, and the others are configured in the same manner as in the first embodiment of the present invention.

  The MOS capacitor 73 has a gate connected to the dummy word line DWL, a source and drain connected, and a connection point connected to the bit line / BL. The voltage of the dummy word line DWL is selected. The boost voltage SVii is sometimes set to the ground voltage VSS when not selected.

  The capacitance value of the MOS capacitor 73 is within a range in which the sense amplifier 22 can perform an accurate amplification operation, and high data is transferred from the memory cell 11 to the bit line BL when there is no leak in the cell transistor 12 and the cell capacitor 13. A voltage lower than ½ of the voltage appearing on the bit line BL when output is set to a value generated on the bit line / BL.

  FIG. 4 is a circuit diagram showing a part of a word decoder provided in the second embodiment of the present invention. In the second embodiment of the present invention, the CMOS inverter 62 provided in the first embodiment of the present invention is not provided. A CMOS inverter 75 is provided, and a subword decoder 76 having a circuit configuration different from that of the subword decoder 68 provided in the first embodiment of the present invention is provided, and the others are configured in the same manner as in the first embodiment of the present invention. It is.

  In the CMOS inverter 75, 77 is a pMOS transistor and 78 is an nMOS transistor.

  The pMOS transistor 77 has a source connected to the SVii power supply line 36 and a gate connected to the output terminal of the CMOS inverter 43. The nMOS transistor 78 has a drain connected to the drain of the pMOS transistor 77 and a gate connected to the CMOS inverter 43. The source is connected to the VBB power line 42.

  In the sub word decoder 76, 79 is a pMOS transistor, and 80 and 81 are nMOS transistors.

  The pMOS transistor 79 has a source connected to the output terminal of the CMOS inverter 58, a gate connected to the output terminal of the CMOS inverter 75, and a drain connected to the word line WL.

  The nMOS transistor 80 has a drain connected to the word line WL, a gate connected to the output terminal of the CMOS inverter 75, and a source connected to the VBB power line 42.

  The nMOS transistor 81 has a drain connected to the word line WL, a gate connected to the output terminal of the CMOS inverter 65, and a source connected to the VBB power line 42.

  In the second embodiment of the present invention configured as described above, when the word line WL is not selected, the main word decoder 29 is not selected and the quarter word decoder 47 is not selected. When the decoder 29 is selected and the quarter word decoder 47 is not selected, the main word decoder 29 is not selected and the quarter word decoder 47 is selected.

  Here, when the main word decoder 29 is not selected and the quarter word decoder 47 is not selected, in the main word decoder 29, the output of the NAND circuit 30 becomes Vii, the nMOS transistor 32 is ON, and the pMOS transistor 37 is OFF. It becomes.

  As a result, the pMOS transistor 35 = ON, the pMOS transistor 34 = OFF, the nMOS transistor 40 = ON, the nMOS transistor 41 = OFF, and the voltage at the node 46 = SVii. In the CMOS inverter 43, the pMOS transistor 44 = OFF and the nMOS transistor 45 = ON, and the output of the CMOS inverter 43 = VBB.

  As a result, in the CMOS inverter 75, the pMOS transistor 77 = ON, the nMOS transistor 78 = OFF, and the output of the CMOS inverter 75 = SVii.

  In the quarter word decoder 47, the output of the NAND circuit 48 = Vii, the nMOS transistor 50 = ON, and the pMOS transistor 54 = OFF.

  As a result, the pMOS transistor 53 = ON, the pMOS transistor 52 = OFF, the nMOS transistor 56 = ON, the nMOS transistor 57 = OFF, and the voltage of the node 61 = SVii. In the CMOS inverter 58, the pMOS transistor 59 = OFF and the nMOS transistor 60 = ON, and the output of the CMOS inverter 58 = VBB.

  As a result, in the CMOS inverter 65, the pMOS transistor 66 = ON and the nMOS transistor 67 = OFF, and the output of the CMOS inverter 65 = SVii.

  Therefore, in the sub word decoder 76, the pMOS transistor 79 = OFF, the nMOS transistor 80 = ON, the nMOS transistor 81 = ON, and the voltage of the word line WL = VBB.

  When the main word decoder 29 is selected and the quarter word decoder 47 is not selected, in the main word decoder 29, the output of the NAND circuit 30 is VSS, the nMOS transistor 32 is OFF, and the pMOS transistor 37 is ON. Become.

  As a result, the nMOS transistor 41 = ON, the nMOS transistor 40 = OFF, the pMOS transistor 34 = ON, the pMOS transistor 35 = OFF, and the voltage at the node 46 = VBB. In the CMOS inverter 43, the pMOS transistor 44 = ON and the nMOS transistor 45 = OFF, and the output of the CMOS inverter 43 = SVii.

  As a result, in the CMOS inverter 75, the pMOS transistor 77 = OFF, the nMOS transistor 78 = ON, and the output of the CMOS inverter 75 = VBB.

  In the quarter word decoder 47, the output of the NAND circuit 48 is Vii, the nMOS transistor 50 is ON, and the pMOS transistor 54 is OFF.

  As a result, the pMOS transistor 53 = ON, the pMOS transistor 52 = OFF, the nMOS transistor 56 = ON, the nMOS transistor 57 = OFF, and the voltage at the node 61 = SVii. In the CMOS inverter 58, the pMOS transistor 59 = OFF and the nMOS transistor 60 = ON, and the output of the CMOS inverter 58 = VBB.

  As a result, in the CMOS inverter 65, the pMOS transistor 66 = ON and the nMOS transistor 67 = OFF, and the output of the CMOS inverter 65 = SVii.

  Therefore, in the sub word decoder 76, the pMOS transistor 79 = ON, the nMOS transistor 80 = OFF, the nMOS transistor 81 = ON, and the voltage of the word line WL = VBB.

  When the main word decoder 29 is not selected and the quarter word decoder 47 is selected, in the main word decoder 29, the output of the NAND circuit 30 becomes Vii, the nMOS transistor 32 is ON, and the pMOS transistor 37 is OFF. It becomes.

  As a result, the pMOS transistor 35 = ON, the pMOS transistor 34 = OFF, the nMOS transistor 40 = ON, the nMOS transistor 41 = OFF, and the voltage at the node 46 = SVii. In the CMOS inverter 43, the pMOS transistor 44 = OFF and the nMOS transistor 45 = ON, and the output of the CMOS inverter 43 = VBB.

  As a result, in the CMOS inverter 75, the pMOS transistor 77 = ON, the nMOS transistor 78 = OFF, and the output of the CMOS inverter 75 = SVii.

  On the other hand, in the quarter word decoder 47, the output of the NAND circuit 48 = VSS, the nMOS transistor 50 = OFF, and the pMOS transistor 54 = ON.

  As a result, the nMOS transistor 57 = ON, the nMOS transistor 56 = OFF, the pMOS transistor 52 = ON, the pMOS transistor 53 = OFF, and the voltage at the node 61 = VBB. In the CMOS inverter 58, the pMOS transistor 59 = ON and the nMOS transistor 60 = OFF, and the output of the CMOS inverter 58 = SVii.

  As a result, in the CMOS inverter 65, the pMOS transistor 66 = OFF and the nMOS transistor 67 = ON, and the output of the CMOS inverter 65 = VBB.

  Accordingly, in the sub word decoder 76, the pMOS transistor 79 = OFF, the nMOS transistor 80 = ON, the nMOS transistor 81 = OFF, and the voltage of the word line WL = VBB.

  On the other hand, when the word line WL is selected, in the main word decoder 29, the output of the NAND circuit 30 = VSS, the nMOS transistor 32 = OFF, and the pMOS transistor 37 = ON.

  As a result, the nMOS transistor 41 = ON, the nMOS transistor 40 = OFF, the pMOS transistor 34 = ON, the pMOS transistor 35 = OFF, and the voltage at the node 46 = VBB. In the CMOS inverter 43, the pMOS transistor 44 = ON and the nMOS transistor 45 = OFF, and the output of the CMOS inverter 43 = SVii.

  As a result, in the CMOS inverter 75, the pMOS transistor 77 = OFF, the nMOS transistor 78 = ON, and the output of the CMOS inverter 75 = VBB.

  In the quarter word decoder 47, the output of the NAND circuit 48 = VSS, the nMOS transistor 50 = OFF, and the pMOS transistor 54 = ON.

  As a result, the nMOS transistor 57 = ON, the nMOS transistor 56 = OFF, the pMOS transistor 52 = ON, the pMOS transistor 53 = OFF, and the voltage at the node 61 = VBB. In the CMOS inverter 58, the pMOS transistor 59 = ON and the nMOS transistor 60 = OFF, and the output of the CMOS inverter 58 = SVii.

  As a result, in the CMOS inverter 65, the pMOS transistor 66 = OFF and the nMOS transistor 67 = ON, and the output of the CMOS inverter 65 = VBB.

  Accordingly, in the sub word decoder 76, the pMOS transistor 79 = ON, the nMOS transistor 80 = OFF, the nMOS transistor 81 = OFF, and the voltage of the word line WL = SVii.

  As described above, according to the second embodiment of the present invention, when the word line WL is not selected, the voltage of the word line WL can be set to the negative voltage VBB. Even when the voltage of V i is Vii, the leakage current of the cell transistor 12 can be reduced.

  Further, according to the second embodiment of the present invention, the capacitance value of the MOS capacitor 73 is within a range in which the sense amplifier 22 can perform an accurate amplification operation, and when the cell transistor 12 and the cell capacitor 13 have no leakage. When high data is output from the memory cell 11 to the bit line BL, a voltage lower than 1/2 of the voltage appearing on the bit line BL is set to a value that can be generated on the bit line / BL. The margin of the sense amplifier 22 for the high data output to the line BL and the margin of the sense amplifier 22 for the low data output to the bit line BL can be made comparable.

  Further, according to the second embodiment of the present invention, since the voltage when the dummy word line DWL is not selected is set to the ground voltage VSS, the current consumption in the negative voltage generation circuit (not shown) is reduced and the power consumption is reduced. Electricity can be achieved.

  Further, according to the second embodiment of the present invention, the reference voltage generating circuit is constituted by the MOS capacitor 73, so that the circuit configuration can be made simpler than that of the first embodiment of the present invention.

  Next, third and fourth embodiments of the present invention will be described.

  FIG. 10 is a diagram showing an operation margin of the 1/2 · Vii precharge method and the VSS precharge method. Blocks I and II indicate the potential of the storage node 7 shown in FIG. 8 for the 1/2 · Vii precharge method and the VSS precharge method, respectively. The reference voltage Ref1 is equal to half of the internal power supply voltage 1/2 · Vii. When the voltage of the storage node 7 is between the upper limit potential Vmax1 and the lower limit potential Vmin1, the 1/2 · Vii precharge type sense amplifier can sense high level data accurately. At this time, as described above, the boosted voltage SVii higher than the internal power supply voltage Vii is applied to the gate of the cell transistor 5.

  In the VSS precharge method, even if the charge stored in the memory cell leaks, the potential of the storage node 7 does not change greatly if the memory cell stores low level data. Accordingly, the reference voltage Ref2 of the sense amplifier for the low level data in the VSS precharge method does not require a large margin. Therefore, as shown in FIG. 10, the reference voltage Ref2 for the low level data is set slightly higher than the ground voltage VSS. Thus, the VSS precharge type sense amplifier can sense high level data within a range defined by the upper limit potential Vmax2 and the lower limit potential Vmin2. Upper limit potential Vmax2 can be made lower than internal power supply voltage Vii. In this case, when a memory cell is selected, the potential of the word line WL needs to be higher than the upper limit potential Vmax2 by at least the threshold voltage VTH of the cell transistor 5. For example, the potential of the word line WL is set to a level equal to the internal power supply voltage Vii. Internal power supply voltage Vii can be made higher than the sum of upper limit potential Vmax2 and the threshold voltage of cell transistor 5. When the cell transistor 5 whose threshold voltage has been lowered by the word line negative voltage reset method is driven by applying the internal power supply voltage Vii, the boost voltage VSii is not necessary. In this case, the high level of the bit line can be set equal to a low level, for example, the power supply voltage Viic obtained by further lowering the internal power supply voltage Vii by the VSS bit line precharge method. Usually, each bit line pair connected to the sense amplifier is provided with a transfer transistor. When the high level of the bit line is equal to Viic, it is necessary to apply a voltage equal to Viic + Vth + α to the gate of the transfer transistor. Vth is a threshold voltage of a transfer transistor (gate) provided on the bit line, and α is a voltage margin. In the VSS bit line precharge method, one bit line is at a high level and the other bit line remains at a low level. Therefore, if the gate of the bit line transfer transistor is in a floating state before the sense amplifier starts its operation, the gate voltage is boosted by coupling with the bit line. Therefore, a booster circuit that generates boosted voltage SVii from internal power supply voltage Vii is not necessary. Therefore, power consumption can be reduced.

  Further, when the internal power supply voltage is generated by stepping down the external power supply voltage VCC inside the semiconductor memory device, the external power supply voltage VCC can be used as the high level of the word line. For example, when the bit line voltage changes between VSS (0 V) and Viic (eg, 1.3 V), it is necessary to apply a voltage equal to Viic + Vth + α to the gate of the transfer transistor. Vth is a threshold voltage of the cell transistor, and α is a voltage margin. As described above, the threshold voltage Vth of the cell transistor can be lowered, and the internal power supply voltage can also be lowered. Therefore, the external power supply voltage VCC (for example, 2.5 V) can be used as the high level of the word line. In this case, the booster circuit is no longer necessary.

In the third and fourth embodiments, the boosted voltage SVii is not applied to the word line, but the internal power supply voltage Vii is applied. The third and fourth embodiments correspond to modifications of the first and second embodiments.
FIG. 11 is a circuit diagram of a word decoder used in the third embodiment. In FIG. 11, the same reference numerals are given to the same components as those shown in the above-mentioned drawings. The word decoder shown in FIG. 11 includes a main word decoder 129, a quarter word decoder 147, and a sub word decoder 68. Main word decoder 129 operates in response to internal power supply voltage Vii. Similarly, the quarter word decoder 147 operates in response to the internal power supply voltage Vii. Further, the CMOS inverters 62 and 65 also operate upon receiving the internal power supply voltage Vii.

  The main word decoder 129 does not include the pMOS flip-flop 33 shown in FIG. The pMOS transistors 34 and 35 to which the internal power supply voltage Vii is applied are connected in series to the nMOS transistors 40 and 41, respectively. The gate of the pMOS transistor 34 is connected to the output terminal of the NAND circuit 30. Inverter 91 inverts the output signal of NAND circuit 30 and provides the inverted signal to the gate of pMOS transistor 35. Accordingly, either the pMOS transistor 34 or the pMOS transistor 35 is turned on according to the output signal of the NAND circuit 30. The output signal of nMOS flip-flop 39 is applied to subword decoder 68 through CMOS inverter 43.

  The quarter word decoder 147 does not include the pMOS flip-flop 51 shown in FIG. The pMOS transistors 52 and 53 to which the internal power supply voltage Vii is applied are connected in series to the nMOS transistors 56 and 57, respectively. The gate of the pMOS transistor 52 is connected to the output terminal of the NAND circuit 48. Inverter 92 inverts the output signal of NAND circuit 48 and provides the inverted signal to the gate of pMOS transistor 53. Accordingly, either the pMOS transistor 52 or the pMOS transistor 53 is turned on according to the output signal of the NAND circuit 48. The output signal of the nMOS flip-flop 55 is given to the CMOS inverter 62 via the CMOS inverter 58.

  FIG. 12 is a circuit diagram of a word decoder used in the fourth embodiment of the present invention. In FIG. 12, the same reference numerals are given to the same components as those shown in the above-mentioned drawings. The word decoder shown in FIG. 12 includes a main word decoder 129, a quarter word decoder 147, a sub word decoder 76, and CMOS inverters 65 and 75. The main word decoder 129 and the quarter word decoder 147 operate in response to the internal power supply voltage Vii. Further, the CMOS inverters 65 and 75 operate upon receiving the internal power supply voltage Vii.

  According to the third and fourth embodiments of the present invention, it operates with the internal power supply voltage Vii and does not require a booster circuit. Therefore, power consumed in the semiconductor memory device can be reduced.

It is a circuit diagram which shows one part of one column part with which 1st Embodiment of this invention is provided. It is a circuit diagram which shows a part of word decoder with which 1st Embodiment of this invention is provided. It is a circuit diagram which shows one part of one column part with which 2nd Embodiment of this invention is provided. It is a circuit diagram which shows a part of word decoder with which 2nd Embodiment of this invention is provided. It is a circuit diagram which shows an example of the sense amplifier mounted in dynamic RAM. FIG. 6 is a waveform diagram for explaining the operation of the sense amplifier in the dynamic RAM in which the sense amplifier shown in FIG. 5 is mounted and the 1/2 · Vii precharge method is adopted. FIG. 6 is a waveform diagram for explaining the operation of a sense amplifier in a dynamic RAM in which the sense amplifier shown in FIG. 5 is mounted and the VSS precharge method is adopted. It is a circuit diagram which shows the structure of the general memory cell with which dynamic RAM is provided. It is a figure which shows the gate-source voltage Vgs-drain-source current ids characteristic of a cell transistor. It is a figure which shows the operation margin of a 1/2 * Vii precharge system and a VSS precharge system. It is a circuit diagram of the word decoder used in the 3rd Example of the present invention. It is a circuit diagram of the word decoder used in the 4th example of the present invention.

Explanation of symbols

WL Word line BL, / BL Bit line DWL Dummy word line PSA Sense amplifier drive voltage PE1, PE2 Control signal SVii Boost voltage Vii Internal power supply voltage VSS Ground voltage VBB Negative voltage

Claims (10)

A pair of first and second bit lines;
A cell transistor having a first current input / output electrode connected to the first bit line, a control electrode connected to a word line, and a first electrode connected to a second current input / output electrode of the cell transistor; A memory cell comprising a cell capacitor with two electrodes grounded;
A bit line precharge circuit for precharging the first and second bit lines to a ground voltage when precharging the first and second bit lines;
A reference voltage generating circuit for generating a reference voltage for the second bit line when reading data from the memory cell;
A dynamic RAM comprising a sense amplifier that amplifies a differential voltage generated between the first and second bit lines when reading data from the memory cell;
A word decoder having a negative voltage when the word line is not selected ;
The dynamic RAM characterized in that the reference voltage generation circuit is composed of a capacitor having a first electrode connected to the second bit line and a second electrode connected to a dummy word line. . The reference voltage generation circuit uses the first bit line from the memory cell as the reference voltage when there is no leak in the cell transistor and cell capacitor within a range in which the sense amplifier can perform an accurate amplification operation. 2. A configuration in which a voltage lower than ½ of a voltage appearing on the first bit line when high data is output to the second bit line is generated. The described dynamic RAM. The capacitor dynamic RAM according to claim 1, characterized in that it is a MOS capacitor. Claim 1 or 3 dynamic RAM according to, characterized in that it is configured to non-selected state of the voltage of the dummy word line and the ground voltage. The word decoder includes a transistor circuit that decodes an address signal and applies a boosted voltage to the word line when the decoded address indicates the word line, and the boosted voltage is generated from an internal power supply voltage and 2. The dynamic RAM according to claim 1, wherein the dynamic RAM is higher than an internal power supply voltage. 6. The dynamic RAM according to claim 5 , wherein when the decoded address does not indicate the word line, the transistor circuit applies a negative voltage to the word line. The word decoder includes a transistor circuit that decodes an address signal and applies an internal power supply voltage to the word line when the decoded address indicates the word line, and as a result, boosts higher than the internal power supply voltage. selecting a word line without using a voltage
Dynamic RAM according to claim 1, wherein. 8. The dynamic RAM according to claim 7 , wherein when the decoded address does not indicate the word line, the transistor circuit applies a negative voltage to the word line. The word decoder
A first NAND circuit that operates using a power supply voltage on the high voltage side as an internal power supply voltage and a power supply voltage on the low voltage side as a ground voltage, and decodes upper bits of a row address for selecting the word line; The power supply voltage on the side is boosted by boosting the internal power supply voltage, the power supply voltage on the low voltage side is operated as a negative voltage, and the output of the first NAND circuit is level-converted to the boosted voltage, The low level operates with a first level conversion circuit that converts the level to the negative voltage, a power supply voltage on the high voltage side as the boost voltage, and a power supply voltage on the low voltage side as the negative voltage. A first word decoder comprising a first inverter for inverting the output;
A second NAND circuit that operates using the power supply voltage on the high voltage side as the internal power supply voltage and the power supply voltage on the low voltage side as the ground voltage, and decodes the lower bits of the row address for selecting the word line; The output voltage of the second NAND circuit is level-converted to the boost voltage, and the low level is leveled to the negative voltage. A second level conversion circuit for conversion, and a second voltage conversion circuit that operates using the high-voltage side power supply voltage as the boosted voltage and the low-voltage side power supply voltage as the negative voltage, and inverts the output of the second level conversion circuit A second word decoder comprising an inverter;
A third inverter that operates with the power supply voltage on the high voltage side as the boosted voltage and the power supply voltage on the low voltage side as the negative voltage, and inverts the output of the second inverter;
A fourth inverter that operates with the power supply voltage on the high voltage side as the boost voltage, the power supply voltage on the low voltage side as the negative voltage, and inverts the output of the third inverter;
A first p-channel insulated gate electric field having a current input electrode connected to the output terminal of the first inverter, a current output electrode connected to the word line, and a control electrode connected to the output terminal of the third inverter. A first n-channel having an effect transistor, a current input electrode connected to the output terminal of the first inverter, a current output electrode connected to the word line, and a control electrode connected to the output terminal of the fourth inverter; An insulated gate field effect transistor, a current input electrode connected to the word line, a control electrode connected to the output terminal of the third inverter, and a second n-channel in which the negative voltage is applied to the current output electrode third word dynamic RAM according to any one of claims 1 to 8, characterized in that it is constituted by a decoder comprising the insulated gate voltage effect transistor . The word decoder
A first NAND circuit that operates using a power supply voltage on the high voltage side as an internal power supply voltage and a power supply voltage on the low voltage side as a ground voltage, and decodes upper bits of a row address for selecting the word line; The power supply voltage on the side is boosted by boosting the internal power supply voltage, the power supply voltage on the low voltage side is operated as a negative voltage, and the output of the first NAND circuit is level-converted to the boosted voltage, The low level operates with a first level conversion circuit that converts the level to the negative voltage, a power supply voltage on the high voltage side as the boost voltage, and a power supply voltage on the low voltage side as the negative voltage. A first word decoder comprising a first inverter for inverting the output;
A second NAND circuit that operates using the power supply voltage on the high voltage side as the internal power supply voltage and the power supply voltage on the low voltage side as the ground voltage, and decodes the lower bits of the row address for selecting the word line; The output voltage of the second NAND circuit is level-converted to the boost voltage, and the low level is leveled to the negative voltage. A second level conversion circuit for conversion, and a second voltage conversion circuit that operates using the high-voltage side power supply voltage as the boosted voltage and the low-voltage side power supply voltage as the negative voltage, and inverts the output of the second level conversion circuit A second word decoder comprising an inverter;
A third inverter that operates with the power supply voltage on the high voltage side as the boosted voltage and the power supply voltage on the low voltage side as the negative voltage, and inverts the output of the first inverter;
A fourth inverter that operates with the power supply voltage on the high voltage side as the boost voltage, the power supply voltage on the low voltage side as the negative voltage, and inverts the output of the second inverter;
A first p-channel insulated gate electric field having a current input electrode connected to the output terminal of the second inverter, a current output electrode connected to the word line, and a control electrode connected to the output terminal of the third inverter. A first n-channel insulated gate electric field having an effect transistor, a current input electrode connected to the word line, a control electrode connected to the output terminal of the third inverter, and the negative voltage applied to the current output electrode; A second n-channel insulated gate electric field in which an effect transistor, a current input electrode are connected to the word line, a control electrode is connected to an output terminal of the fourth inverter, and the negative voltage is applied to the current output electrode third of claims 1 to 9 or a dynamic RAM of one claim of, characterized in that it is constituted by a word decoder comprising a effect transistor.

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