JP4453705B2 - Thin film capacitor, method for manufacturing the same, and electronic component - Google Patents

Description

  The present invention relates to a thin film capacitor, a manufacturing method thereof, and an electronic component including the thin film capacitor.

  Various types of electronic components of surface mounting type are mounted on internal circuits of electronic devices such as computers and portable terminals. Recently, there is an urgent need to make various electronic components thinner (thin film) in order to meet the demand for higher performance and miniaturization of electronic devices. Examples of such a thin film type electronic component include a thin film capacitor, a thin film inductor, a thin film LC composite component, a thin film lumped constant device, a thin film distributed constant device, and a thin film laminated composite component. Among these, the low-pass filter (LPF), the high-pass filter (HPF), and only the signal in the predetermined frequency range are allowed to pass through the composite parts having thin film capacitors. There are a band pass filter (BPF) that attenuates a signal in a frequency range other than the above, a trap filter (Trap Filter) that removes a signal in a predetermined frequency range, and the like. Moreover, as an electronic component combining them, there are a diplexer, a duplexer, an antenna switch module, an RF module, and the like.

In general, such a thin film capacitor has a configuration in which a lower electrode, a dielectric layer, and an upper electrode are sequentially laminated on a base material made of an insulator so that the capacitance can be easily controlled and a breakdown voltage between the electrodes ( From the viewpoint of sufficiently ensuring the dielectric breakdown limit value (hereinafter referred to as “V _BD ”), the dielectric layer on the electrode has an opening at a position facing the central portion of the dielectric layer. What provided the resin layer (insulating layer) so that a peripheral part may be covered is conventionally known. For example, in Patent Document 1, a diffusion prevention layer made of metal or nitride is provided between the dielectric layer and the upper electrode so as to have such an opening, and to prevent a decrease in _VBD between the electrodes. Thin film capacitors are described.
Japanese Patent Laid-Open No. 2006-5293

However, according to the knowledge of the present inventor, in a conventional thin film capacitor provided with a resin layer having an opening, even when the diffusion prevention layer is provided as in the conventional case, the _VBD between the electrodes is sufficiently reduced. It has been found that it is difficult to increase the level of variation among individuals to a satisfactory level. In addition, a thin film capacitor having an opening in a resin layer usually has a resin layer on a lower electrode made of a conductor material such as copper (Cu) or on a dielectric layer made of various oxide materials provided thereon. Although it has a laminated structure, when heat is applied in the process after forming them or the inspection process after completing the thin film capacitor, etc., due to the difference in thermal expansion coefficient and thermal contraction rate of each material, In particular, there may be a difference in expansion and contraction in the extending direction (layer direction) to cause delamination, and in particular, delamination tends to occur easily at the interface between the resin layer and the other layer.

  Although it is conceivable to roughen the electrode surface to prevent such peeling, in order to form a capacitor, it is desirable that the electrode surface be as smooth as possible. In addition, although it is conceivable to interpose an adhesion layer or the like between the respective layers, it is not desirable because the number of steps increases and productivity and economy are deteriorated.

The present invention has been made in view of such circumstances, while more increasing the V _BD, it is possible to suppress variations in V _BD between individuals, and, can be suppressed sufficiently delamination Therefore, it is an object of the present invention to provide a thin film capacitor, a manufacturing method thereof, and an electronic component that can improve device characteristics and product reliability, as well as productivity and economy.

  In order to solve the above problems, a thin film capacitor according to the present invention has a dielectric layer and an insulating layer (preferably a resin layer) formed between a first conductor and a second conductor, and an insulating layer. Has an opening in a region overlapping with the dielectric layer, and at least one of the first conductor, the second conductor, and the dielectric layer has a peripheral portion thereof rather than the region in which the opening is formed. At least a portion of (the upper surface of the peripheral edge on the insulating layer side) is raised and lowered, that is, the upper surface peripheral edge of at least one of the first conductor, the second conductor, and the dielectric layer. This is a thin film capacitor having a shape (a shape in which the peripheral edge is pushed out) so that the portion protrudes from the central portion, which is a region where the opening K is formed. Alternatively, at least one of the first conductor, the second conductor, and the dielectric layer has a protrusion (convex shape) protruding toward the insulating layer at least at a part between the peripheral edge and the opening of the insulating layer. In other words, at least one of the first conductor, the second conductor, and the dielectric layer has an area where an opening is provided (an area inside the peripheral edge). In other words, it may have a concave cross section that is recessed or recessed from at least a part of the peripheral edge. For example, it can be said that at least one of the first conductor, the second conductor, and the dielectric layer has a topographic shape such as a basin or a caldera.

  In the thin film capacitor having such a configuration, the first conductor and the second conductor (at least part of either one functions as a so-called lower electrode and at least part of the other functions as the upper electrode). Is provided in a region where the first conductor or the second conductor and the dielectric layer overlap, and the capacitance of the capacitor is appropriately determined depending on the size of the opening. (Controlled).

  And at least a part of at least one peripheral portion of the first conductor, the second conductor, and the dielectric layer is raised from the region where the opening is formed, or the first conductor, Since a protrusion (convex portion) is formed at least at a part between the peripheral edge of at least one of the two conductors and the dielectric layer and the opening of the insulating layer, the peripheral edge is the first conductor. And it arrange | positions by protruding and inserting in the insulating layer side formed between the 2nd conductors, and it functions as an anchor so to speak. Therefore, when the heating process is performed, the movement due to the expansion and contraction (particularly the layer direction) of the insulating layer or the dielectric layer is caused by the peripheral edge of at least one of the first conductor, the second conductor, and the dielectric layer. It is limited by the anchor effect produced by the shape of the part.

In addition, the formation of the first conductor and / or the second conductor usually forms a seed layer made of the material of the first conductor and / or the second conductor, and the first conductor and / or the second conductor are formed on the seed layer. / Or a conductor layer made of the material of the second conductor is formed by, for example, plating (electroplating or chemical plating may be used, but electroplating is preferable for forming a film having a uniform constant thickness or more). Moreover, after patterning the conductive layer into a predetermined shape, the seed layer remaining around the patterned conductor layer, where performed is removed by milling or etching or the like, the present inventors have, V _BD is deteriorated As a result of diligent analysis and examination of the thin film capacitor, the conventional thin film capacitor has a problem that when the seed layer is removed, the conductive metal particles of the removed seed layer are mixed on the conductor. If, it was found that the conductor surface is contaminated with metal particles of the seed layer. A thin film capacitor obtained by laminating the dielectric layer, the resin layer, and the other conductor in such a state has a low V _BD value itself as shown below, and variation among individual V _BDs. Was also confirmed to be large.

Here, Table 1 shows the result of counting the number of particles existing in the vicinity of the interface between the electrode (conductor) and the dielectric layer in three types of samples which are conventional thin film capacitors, and Table 2 shows each result The result of having measured _VBD about the plural (36 pieces) thin film capacitors corresponding to a sample is shown. From these results, Sample 1 with the smallest number of particles has the highest V _BD and the smallest variation, and conversely, Sample 3 with the largest number of particles has the smallest V _BD and the largest variation. Was confirmed.

From the above, _VBD and its variation degree tend to be worse as the number of conductor particles existing between the first conductor and / or the second conductor as an electrode and the dielectric layer is larger. Understood. In order to prevent such conductor particles from being left on the conductor, it is conceivable to clean the surface of the conductor after removing the seed layer described above. In addition, the economic efficiency is deteriorated.

  In contrast, in the thin film capacitor of the present invention, at least a part of the peripheral portion of the first conductor and / or the second conductor is raised (the region where the opening of the insulating layer is formed is at least a part of the peripheral portion. When the seed layer described above is removed by milling or the like, even if the generated seed layer conductor particles try to flow onto the surface of the electrode, the conductor particles remain as the first conductor. And / or shielded (obstructed, blocked) by the peripheral edge of the second conductor. In other words, the bulge of the peripheral portion of the first conductor and / or the second conductor becomes a wall (obstacle) and is difficult to be mixed into the recessed portion inside the peripheral portion. Therefore, even if the conductor surface is not washed after removing the seed layer, the conductor surface can be prevented from being contaminated by the conductor particles, and the conductor surface can be kept clean. In addition, if at least a part of the peripheral portion of the first conductor and / or the second conductor is raised, the dielectric layer formed between them also has a peripheral edge according to the rise of the peripheral portion of the conductor. At least a part of the portion rises (projects) toward the insulating layer.

  In addition, the above-described anchor effect is that the bulge (projection, projection) of the peripheral edge is formed over the entire circumference of at least one of the first conductor, the second conductor, and the dielectric layer. And the shielding effect of the conductive particles of the seed layer is further enhanced, which is preferable.

  Furthermore, if at least one of the first conductor, the second conductor, and the dielectric layer has a wedge shape (longitudinal cross section), a wedge shape (spiral shape, or a mountain shape), go to the insulating layer side. It is more preferable that the anchor effect is further enhanced by further inserting (inserting).

  Still further, it is more preferable that the insulating layer has a taper formed on the inner wall defining the opening. That is, it is preferable that the inner wall of the opening of the resin layer expands toward the bottom, in other words, the opening diameter gradually increases from the bottom of the opening toward the opening end side.

  In the vicinity of the bottom surface of the opening where the capacitor is defined, if the wall surface of the insulating layer suddenly extends at a steep angle with respect to the bottom surface of the opening, for example, at an angle close to the vertical, electric field concentration occurs at the periphery of the bottom wall of the opening. In some cases, this may easily occur. In such a case, there is a concern that dielectric breakdown may occur at that portion. On the other hand, by forming the taper on the inner wall of the insulating layer that defines the opening as described above, the sudden rise of the wall surface is eliminated, and the dielectric breakdown due to the electric field concentration can be reliably prevented.

  In this case, it is more preferable that the taper slope (taper angle) of the inner wall is formed more gently than the taper slope (taper angle) of the inner wall body. In this way, the steep taper angle of the inner wall body portion is prevented while preventing the electric field concentration at the peripheral edge portion of the opening bottom wall of the insulating layer by preventing the sharp extension of the inner wall bottom portion, thereby increasing the electric field (vertical length) at the opening portion. The uniformity of the electric field can be realized, and the occurrence of dielectric breakdown in the body portion of the opening inner wall of the insulating layer can be effectively prevented.

  The method for manufacturing a thin film capacitor according to the present invention is a method for effectively manufacturing the thin film capacitor of the present invention, comprising the steps of forming a first conductor, forming a second conductor, first and second. Forming a dielectric layer between the first and second conductors, and forming an insulating layer between the first and second conductors, wherein the step of forming the insulating layer includes the first conductor or the second conductor. Forming an opening in a region where the conductor and the dielectric layer overlap, and in at least one of the steps of forming the first conductor, the second conductor, and the dielectric layer, As the at least one of the conductor, the second conductor, and the dielectric layer, at least a part, preferably all of the peripheral part of the peripheral part is formed to have a raised undulation from the region where the opening is formed, in other words , First Conductor, at least a portion between the second conductor, and at least one peripheral edge of the dielectric layer and the opening of the insulating layer preferably forms a protrusion over the entire circumference of the periphery thereof.

  More specifically, forming the first conductor and / or the second conductor includes forming a seed layer made of a material of the first conductor and / or the second conductor; Forming a conductive layer made of a material of the first conductor and / or the second conductor and having undulations in which at least a part of the peripheral edge is raised from the region where the opening is formed, in other words, the first Forming a conductor layer having a convex portion at least at a part between the periphery of the conductor and / or the second conductor and the opening of the insulating layer; patterning the conductor layer into a predetermined shape; It is useful to include removing the seed layer remaining around the conductor layer.

According to the present invention, at least one peripheral portion of the first conductor, the second conductor, and the dielectric layer is a region where the opening of the insulating layer is formed (the first conductor, the second conductor, and A region on the inside of at least one peripheral edge of the dielectric layer), that is, at least one of the first conductor, the second conductor, and the dielectric layer is between the opening of the insulating layer. The protrusions (convex parts) formed on at least a part of the first conductor, the second conductor, and the movement in the layer direction, even when the insulating layer expands and contracts in the thermal process, Since it is limited by at least one peripheral edge (projection) of the dielectric layers, delamination of each layer can be sufficiently prevented. Further, when forming the first conductor and / or the second conductor, fine particles of the conductor that may be generated when the seed layer is removed are shielded by the peripheral portion of the first conductor and / or the second conductor. Therefore, it is possible to prevent the decrease and variation in _VBD caused by the conductor particles. As a result, it is possible to improve device characteristics and product reliability, and productivity and economy of a thin film capacitor and an electronic component including the same.

  Hereinafter, embodiments of the present invention will be described in detail. In addition, the same code | symbol is attached | subjected to the same element and the overlapping description is abbreviate | omitted. Further, the positional relationship such as up, down, left and right is based on the positional relationship shown in the drawings unless otherwise specified. Furthermore, the dimensional ratios in the drawings are not limited to the illustrated ratios. Further, the following embodiments are exemplifications for explaining the present invention, and are not intended to limit the present invention only to the embodiments. Furthermore, the present invention can be variously modified without departing from the gist thereof.

[First embodiment of thin film capacitor and electronic component including the same]
1 to 4 are equivalent circuit diagrams showing configuration examples of electronic components including the first embodiment of the thin film capacitor according to the present invention. An electronic component 1 shown in FIG. 1 includes a capacitor 11 (thin film capacitor) as a capacitive element formed by a thin film forming technique and an inductor 13 electrically connected thereto, and the capacitor 11 and the inductor 13 are connected in series. To form a series resonant circuit. In addition, the electronic component 2 shown in FIG. 2 includes a capacitor 11 and an inductor 13 connected in parallel, and constitutes a parallel resonance circuit. Further, the electronic component 3 shown in FIG. 3 includes a capacitor 11 and an inductor 13 that constitute a low-pass filter. Furthermore, the electronic component 4 shown in FIG. 4 includes a capacitor 11 and an inductor 13 that constitute a high-pass filter.

FIG. 5 is a cross-sectional view showing the main part of the capacitor 11 and its periphery in the electronic components 1 to 4. The electronic components 1 to 4 are obtained by forming an inductor 13 (not shown in FIG. 5) having a capacitor 11 and a conductor coil on a smooth substrate 51 having a planarizing layer 52 formed on the surface as a base material. is there. The substrate 51 and the planarization layer 52 are made of alumina (Al ₂ O ₃ ), for example, and the surface of the planarization layer 52 is polished and planarized by, for example, a CMP (Chemical Mechanical Polishing) method. .

  Further, the capacitor 11 has a lower conductor 21 (first conductor), a dielectric film 31 (dielectric layer), a resin layer J (insulating layer), and an upper conductor 25 (first conductor) on the planarization layer 52 of the substrate 51. 2 conductors) are sequentially laminated. The lower conductor 21 is, for example, a base conductor 21a made of titanium (Ti) / copper (Cu) formed on the planarizing layer 52 of the substrate 51, and a conductor made of copper (Cu) formed on the base conductor 21a. 21b. Thus, by forming the lower conductor 21 with a low-resistance conductor material such as Cu, the equivalent series resistance (ESR) of the capacitor 11 can be kept low.

  The lower conductor 21 is opposed to the upper conductor 25 across the dielectric film 31 and functions as an electrode of the capacitor 11, and a coil conductor (not shown) of this electrode portion and the inductor 13 and other internal or external electrodes. It has a lead conductor portion that is drawn out to connect a terminal or an electrode (not shown). The electrode portion occupies a planar circular or rectangular region at a substantially central portion of the lower conductor 21. In addition, the lead conductor portion of the lower conductor 21 extends in an arbitrary shape that connects the electrode portion and the connection target. By forming the lead conductor portion as wide and short as possible, the ESR and the capacitor 11 can be reduced. Equivalent Series Inductance (ESL) can be kept low.

  In addition, the lower conductor 21 is raised on the upper surface in the figure of the conductor 21b, with at least a part of the peripheral portion, preferably the entire periphery thereof, higher than the central portion, that is, the region where an opening K of an insulating layer J described later is formed. In other words, the peripheral edge portion has a protruding shape protruding (protruding) into the resin layer J. Further, the central portion of the conductor 21b is recessed and flatter than the peripheral portion, and the lower conductor 21 is, for example, the upper portion of the conductor 21b is shaped like a basin or a caldera.

  The dielectric film 31 is formed on substantially the entire surface of the substrate 51 except for a via opening H described later, and covers substantially the entire surface of the lower conductor 21 and the coil conductor of the inductor 13 constituting the capacitor 11. It is provided to cover.

Here, the thickness of the dielectric film 31 is not particularly limited, but is set to a uniform thickness on the order of 0.01 to 1 (μm), for example, and is thinner than the lower conductor 21. Examples of the material of the dielectric film 31 include alumina, silicon nitride (Si ₄ N ₃ ), silicon dioxide (SiO ₂ ), tantalum oxide (Ta ₂ O ₅ ), aluminum nitride (AlN), and magnesium oxide (MgO). Etc. can be used as appropriate.

  Here, FIGS. 6A and 6B are a cross-sectional view and a top view showing the main part below the upper conductor 25, respectively. The resin layer J is provided on the dielectric film 31 so as to cover the periphery of the lower conductor 21. In addition, the resin layer J has a circular opening K having an opening diameter r in a region where the lower conductor 21 and the upper conductor 25 and the dielectric film 31 overlap, and a part of the upper surface 31 a of the dielectric film 31. However, it is exposed in the opening K.

  In addition, the inner wall of the resin layer J that defines the opening K is formed with a taper that expands in the drawing, and the taper angle θ1 of the bottom of the inner wall of the opening K (the inner wall of the opening K of the resin layer J and the dielectric film). 31, the inner angle in the figure formed by the wall surface of the resin layer J with respect to the extending surface direction of the upper surface 31 a is the taper angle θ <b> 2 of the inner wall body portion at the opening K (the opening K of the resin layer J). The wall surface of the resin layer J is made smaller than the inner angle (illustrated in the drawing) with respect to the extending direction of the upper surface 31a at the opening end side of the inner wall. That is, the inner wall of the resin layer J that defines the opening K is formed such that the rising angle (that is, the taper angle θ1) of the bottom portion is smaller than the rising angle (that is, the taper angle θ2) of the body portion. It has a gentle slope.

  Here, the material of the resin layer J is not particularly limited. For example, the resin layer J is mainly composed of a non-novolac resin, preferably a negative photosensitive material (negative photoresist), more specifically, a polyimide resin. (Photosensitive polyimide), epoxy resin (photosensitive epoxy), phenol resin other than novolac resin, silicone resin, and the like, and may include inorganic materials such as alumina and ferrite. Alternatively, a positive photosensitive material (positive photoresist), for example, a material made mainly of a novolac resin may be used. Here, the “novolak resin” refers to a phenol resin molded from an oligomer obtained by condensing phenol or a derivative thereof under an acidic catalyst. Further, when a relatively thick layer is provided as the resin layer J, a negative photosensitive material is preferable. Furthermore, the resin layer J may be composed of a plurality of layers. In this case, a positive photosensitive material (positive photoresist) mainly made of a novolac resin is used as the lower layer, and a negative photosensitive material (negative photoresist) mainly made of a non-novolac resin as the upper layer. ) Is easy to control the shape of the lower layer (high resolution), so that variation in the opening diameter of the opening K can be suppressed, and the upper layer is relatively thick and excellent in environmental resistance. It is.

  FIG. 7 is a cross-sectional view showing the main part below the dielectric film 31. Referring to FIG. 7, an example of the dimensional shape of the lower conductor 21 will be described. The bottom width w of the lower conductor 21 is, for example, 10 to 200 (μm), and the main portion height t1 is, for example, 5 to 10 (μm). The height t2 of the raised protrusion-shaped peripheral edge described above is, for example, about 1 to several (μm) or less.

  Here, returning to FIG. 5, the upper conductor 25 is made of, for example, a base conductor 25a made of, for example, Ti / Cu provided so as to cover the opening K of the resin layer J, and Cu, for example, formed on the base conductor 25a. And a conductor 25b. Thus, the ESR of the capacitor 11 can be further reduced by forming the upper conductor 25 with a low-resistance conductor material such as Cu.

  The upper conductor 25 faces the lower conductor 21 across the dielectric film 31 and functions as an electrode of the capacitor 11, that is, a columnar shape that comes into contact with a portion exposed in the opening K 1 in the upper surface 31 a of the dielectric film 31. A lead conductor drawn out to connect a portion (that is, a portion occupying a planar circular or square region at a substantially central portion of the upper conductor 25) and an internal or external terminal or electrode (not shown). Part. In this way, the capacitor 11 is composed of the above-described electrode portion of the lower conductor 21, the electrode portion of the upper conductor 25, and the portion of the dielectric film 31 sandwiched between them, mainly exposed in the opening K, The area of the electrode portion of the upper conductor 25 is determined by the opening K of the resin layer J (depending on the area of the opening K), and the capacitance value of the capacitor 11 is the area of the electrode portion of the upper conductor 25, the upper conductor 25 and It is defined by the film thickness and dielectric constant of the dielectric film 31 sandwiched between the lower conductors 21.

  In addition, the lead conductor portion in the upper conductor 25 extends in an arbitrary shape that connects the electrode portion and the connection target. By forming the lead conductor portion as wide and short as possible, like the lower conductor 21, The ESR and ESL of the capacitor 11 can be further reduced. Further, the thickness of the upper conductor 25 is sufficiently thick as the lower conductor 21, thereby improving the high frequency characteristics such as the Q characteristic and the self-resonant frequency (SRF) of the capacitor 11 and transmission loss. Can be suppressed.

  Further, a protective film 54 made of, for example, alumina is formed on the entire surface of the upper conductor 25 and the resin layer J.

  A procedure for manufacturing the electronic components 1 to 4 configured as described above will be described mainly focusing on the capacitor 11 and its peripheral region. 8 to 17 are process diagrams (cross-sectional views) showing a state in which the electronic components 1 to 4 including the capacitor 11 are manufactured. Although many electronic components 1 to 4 are simultaneously formed on the substrate 51, FIGS. 8 to 17 mainly show the formation region of the capacitor 11 in the element formation region of one electronic component.

  First, the planarization layer 52 is formed by polishing the surface of the substrate 51 made of alumina by a CMP method (FIG. 8). Next, on the planarization layer 52 of the substrate 51, for example, titanium (Ti) having a thickness of about 10 to 50 (nm) and copper (Cu) (for example, having a thickness of about 0.1 to 0.5 (μm)) A seed layer (that functions as a feeding point) is sequentially laminated by, for example, a sputtering method to form a layer of the underlying conductor 21a (FIG. 9). Further, a photosensitive material (photoresist) is patterned thereon by photolithography, and further Cu, for example, having a thickness of about 10 (μm) is formed on the layer of the underlying conductor 21a in the opening by, for example, an electrolytic plating method. Next, the conductor 21b is formed by polishing the surface of the conductor to a desired thickness by CMP (FIG. 10).

Here, an example of the plating conditions in the case where the conductor 21b having a shape in which the peripheral portion is raised and the central portion is flat by the semi-additive method (precipitation method) by the electrolytic plating method will be described. First, ashing and wet cleaning are performed as pretreatment for plating after patterning of a photosensitive material (photoresist). Then, as a plating bath for forming a Cu plating conductor, a copper sulfate concentration of 40 to 200 g / L, a sulfuric acid concentration of 10 to 200 g / L, a chlorine ion concentration of 10 to 100 mg / L, and an appropriate amount of a plating additive for via fill are included. Build a 200 L plating bath. Next, in this plating bath, an electrolytic copper plate is installed as an anode, and the substrate subjected to the above-described plating pretreatment is installed oppositely. As film formation conditions for Cu plating, for example, the rotation speed of a stirring rod for stirring a plating bath is 45 rpm, and the current density is 0.5 to 10.0 A / dm ² . However, the plating conditions are not limited to the above.

  In such electrolytic plating, the via-fill plating additive promotes film formation at the peripheral portion in the opening of the photoresist pattern, and the film is formed such that the film thickness at the peripheral portion is thicker than that at the central portion. Finally, the conductor 21b is formed which is flattened with the peripheral portion raised and the central portion recessed. At this time, by appropriately adjusting the plating conditions such as the composition of the plating bath, the current density, the electrolysis time, the stirring method and the speed, and the type of the plating additive for via fill, the raised shape (projection shape) of the peripheral portion of the conductor 21b Can be controlled as desired. Prior to actual production, the conductor 21b is formed using various plating conditions, and the shape parameters of the conductor 21b are measured to obtain the relationship between the film forming shape of the conductor 21b and the plating conditions in advance. Can do.

  Next, the substrate on which the conductor 21b is formed is washed, the photosensitive material is peeled off, further washed and dried, and then the underlying conductor 21a layer exposed between the conductors 21b is removed by milling or etching. Thus, the lower conductor 21 composed of the base conductor 21a and the conductor 21b is formed (FIG. 11). In addition, the coil conductor of the inductor 13 can be formed simultaneously with the formation of the lower conductor 21 by desired patterning (not shown).

  Here, when the unnecessary layer of the underlying conductor 21a is removed by milling or the like, the layer of the underlying conductor 21a can be finely divided and move upward from the substrate 51. Some of the particles of the base conductor may flow toward the conductor 21b and adhere to the surface of the conductor 21b, as schematically shown by the arrow Y in FIG. However, since the peripheral portion of the conductor 21b of the lower conductor 21 is raised, the particles of the underlying conductor that try to reach the upper surface of the conductor 21b are blocked from reaching the peripheral portion. Therefore, it is possible to effectively prevent the ground conductor particles from adhering to the upper surface (capacitor electrode portion) of the conductor 21b.

  Next, a dielectric film 31 having a thickness of about 0.01 to 1 (μm) is formed on the entire surface of the substrate 51 on which the lower conductor 21 is formed (FIG. 12). The dielectric film 31 has an undulating shape in which a portion on the raised peripheral edge of the lower conductor 21 is raised so as to follow the shape. Next, on the entire surface of the dielectric film 31, for example, a negative photosensitive material mainly composed of a polyimide resin is applied so that the film thickness becomes, for example, about 0.5 to 30 (μm), and then the photosensitive material is applied. Pre-baking is performed on the film of the functional material. Next, the film is exposed and developed to remove the opening K of the resin layer J and the portion that becomes the contact via opening H (FIG. 13). Next, post-baking is performed to form the resin layer J (FIG. 14).

  The resin layer J is cured and contracted by post-baking and has a maximum film thickness of about 0.5 to 30 (μm). From the shape close to the rectangular cross section shown in FIG. Is formed such that a taper is formed on the inner wall that defines In the negative photosensitive material, the exposed portion remains in the development, and the exposure is stronger toward the upper portion of the photosensitive material. Therefore, the opening K formed by the development has an inverted mortar shape (a hem-opening shape, The inner wall of the tapered resin layer J having the taper angles θ1 and θ2 as shown in FIG. 6A is formed by adjusting the exposure conditions and the like.

  Further, a photosensitive material (photoresist) is patterned by photolithography on the substrate 51 shown in FIG. 14 on which the resin layer J is formed, and a portion of the via opening H is opened (FIG. 15). Next, milling is performed using the remaining photosensitive material layer P as a mask, the dielectric film 31 exposed in the via opening H is removed, and the underlying lower conductor 21 is exposed (FIG. 16). The exposed portion C of the lower conductor 21 is connected to, for example, the inductor 13 and can be a part that contacts an upper conductor 25 to be formed later. Then, after removing the photosensitive material layer P (FIG. 17), an upper conductor 25 composed of a base conductor 25a and a conductor 25b is formed thereon as shown in FIG. 5 in the same manner as the lower conductor 21 described above. (Hereafter, illustration is omitted) The capacitor 11 is obtained. Then, as shown in FIG. 5, an alumina protective film 54 having a thickness of about 10 to 20 (μm) is formed on the entire surface.

  Then, the substrate 51 is cut along a predetermined cutting line, and the plurality of electronic components 1 to 4 formed on the substrate 51 are separated into chips for each element formation region. Furthermore, although illustration is omitted, an external electrode electrically connected to the lower conductor 21 and / or the upper conductor 25 exposed on the cut surface is formed on the cut surface, and corners are formed before and after the formation of the external electrode as necessary. Processing such as chamfering of the part is performed to obtain electronic components 1 to 4.

  Here, FIG. 18 shows an example of an electron micrograph of a cross section of the capacitor 11 portion of the electronic component obtained by forming the conductor 21b having a thickness of about 8.5 μm under the Cu plating conditions described above. FIG. 19 is an enlarged photograph corresponding to the part in the circle marked with the reference R in FIG. 18, and FIG. 20 is an enlarged photograph corresponding to the part in the circle marked with the reference L in FIG. From these photographs, it was confirmed that the lower conductor 21 has a shape in which the peripheral edge is raised from the center.

  FIG. 21 is a chart showing the result of scanning measurement of the cross-sectional shape of the lower conductor obtained in the same manner as the electronic component shown in FIG. In this chart, a solid line having two peaks represents an outer cross-sectional shape of the lower conductor, and the height of both peaks indicates the height of the peripheral edge of the lower conductor. From this chart, this lower conductor has a bottom width w of about 75 (μm), a main portion height t1 of about 6.7 (μm), and a peripheral portion height t2 of about 2.7 (μm). Was confirmed. The unit of numerical values in the chart is (μm), and the scales of the horizontal axis and the vertical axis are different. By looking at this scale, the peripheral portion of the lower conductor has a wedge-shaped cross section (spiral shape, mountain shape). Is easily understood.

  Further, FIG. 22 is a plan view (partially cutaway view) showing the electronic component 1 including the capacitor 11. As described above and shown in FIG. 1, the electronic component 1 is a capacitor 11 in which an inductor 13 is connected in series, and functions as a series resonance circuit. The inductor 13 includes a coil conductor 12 and a conductor 61 connected to an end portion on the inner peripheral side of the coil conductor 12. The coil conductor 12 is formed in the same manner and / or at the same time as the lower conductor 21 of the capacitor 11, and is connected to the lower conductor 21. The conductor 61 is formed in the same manner and / or at the same time as the upper conductor 25 of the capacitor 11.

  According to the thus configured capacitor 11 according to the present invention and the electronic components 1 to 4 including the capacitor 11, the peripheral edge portion of the lower conductor 21 is raised more than the region (center portion) where the opening K is formed. Since the peripheral portion protrudes from the dielectric film 31 and further protrudes and fits into the resin layer J through the dielectric film 31, the post-process (the process of forming the resin layer J) is performed by the anchor function of the peripheral portion of the lower conductor 21. For example, even when a heating process in the inspection of the electronic components 1 to 4 or the like is performed, the movement of the resin layer J in particular in the layer direction is limited. Therefore, delamination of each layer of the lower conductor 21, the dielectric film 31, the resin layer J, and the upper conductor 25 can be sufficiently prevented.

In addition, when the base conductor 21a layer is removed by milling or the like in the manufacturing process of the electronic components 1 to 4, the peripheral portion of the conductor 21b of the lower conductor 21 is raised, so that the fine particles that flow to the upper portion of the conductor 21b. Since the particles of the converted underlying conductor 21a are shielded by the peripheral portion thereof, the conductor particles are mixed between the lower conductor 21 and the dielectric film 31 without requiring a step of cleaning such particles. Can be suppressed. Therefore, it is possible to suppress the decrease in _VBD caused by the conductor particles and the variation in _VBD among individuals.

  Therefore, it is possible to improve device characteristics and product reliability, and productivity and economy of the capacitor 11 and the electronic components 1 to 4 including the capacitor 11.

  In addition, as above-mentioned, this invention is not limited to the said embodiment, A various deformation | transformation is possible in the limit which does not change the summary. For example, the structures of the capacitors 11 and 12 can also be applied to the electronic component 1 having a multilayer capacitor in which a conductor and a dielectric film 31 are repeatedly laminated in order. Specifically, the same capacitors 11 and 12 can be repeatedly stacked, or the capacitors 12 can be alternately stacked on the capacitor 11 repeatedly. Further, a part of the peripheral portion of the lower conductor 21 may be raised, and from the viewpoint of enhancing the anchor effect and the shielding effect of the conductor particles, and from the viewpoint of manufacturability, the peripheral portion is raised over the entire circumference. That is, a shape in which an annular protrusion is formed is preferable.

  Further, the upper conductor 25 may be used only as a lead conductor portion, and a conductor layer functioning as a second conductor may be provided below the upper conductor 25. Furthermore, the opening shape of the opening K is not limited to a circular shape, and may be, for example, a square shape. Furthermore, the formation method of the lower conductor 21 and the upper conductor 25 is not limited to the semi-additive method, but a subtractive method (etching method), damascene method, paste method, lift-off method, ink jet printing method or screen printing method using a conductive material. , Etc. may be used. Further, the lower conductor 21 and the upper conductor 25 may be formed of other or further plural conductive materials so that selective etching can be performed, and the lower conductor 21 and the upper conductor 25 having desired shapes may be formed. Furthermore, instead of the resin layer J, an insulating layer made of an inorganic material such as alumina or ferrite may be provided.

Above-described above, according to the thin film capacitor and a manufacturing method thereof and an electronic component provided with the thin film capacitor of the present invention, while more increasing the V _BD, it is possible to suppress variations in V _BD between individuals, and delamination Therefore, it is possible to improve device characteristics, product reliability, productivity, and economic efficiency. Therefore, devices and apparatuses that incorporate thin-film electronic components. It can be used widely and effectively for systems, various devices, and the like that require particularly small size and high performance.

It is an equivalent circuit diagram which shows the structural example of an electronic component provided with 1st Embodiment of the thin film capacitor by this invention. It is an equivalent circuit diagram which shows the structural example of an electronic component provided with 1st Embodiment of the thin film capacitor by this invention. It is an equivalent circuit diagram which shows the structural example of an electronic component provided with 1st Embodiment of the thin film capacitor by this invention. It is an equivalent circuit diagram which shows the structural example of an electronic component provided with 1st Embodiment of the thin film capacitor by this invention. It is sectional drawing which shows the capacitor | condenser 11 in an electronic component, and the principal part of the periphery. (A) And (B) is sectional drawing and the upper side figure which respectively show the principal part under the upper conductor in the capacitor | condenser 11. FIG. It is sectional drawing which shows the principal part under the dielectric film 31 in an electronic component. FIG. 6 is a process diagram illustrating a state in which an electronic component including a capacitor 11 is manufactured. FIG. 6 is a process diagram illustrating a state in which an electronic component including a capacitor 11 is manufactured. FIG. 6 is a process diagram illustrating a state in which an electronic component including a capacitor 11 is manufactured. FIG. 6 is a process diagram illustrating a state in which an electronic component including a capacitor 11 is manufactured. FIG. 6 is a process diagram illustrating a state in which an electronic component including a capacitor 11 is manufactured. FIG. 6 is a process diagram illustrating a state in which an electronic component including a capacitor 11 is manufactured. FIG. 6 is a process diagram illustrating a state in which an electronic component including a capacitor 11 is manufactured. FIG. 6 is a process diagram illustrating a state in which an electronic component including a capacitor 11 is manufactured. FIG. 6 is a process diagram illustrating a state in which an electronic component including a capacitor 11 is manufactured. FIG. 6 is a process diagram illustrating a state in which an electronic component including a capacitor 11 is manufactured. It is an example of the electron micrograph of the cross section in the capacitor | condenser 11 part of an electronic component. It is an enlarged photograph corresponding to the site | part in the circle | round | yen which attached | subjected the symbol R in FIG. FIG. 19 is an enlarged photograph corresponding to a portion in a circle marked with a symbol L in FIG. 18. It is a chart which shows the result of having carried out the scanning measurement of the cross-sectional shape of the lower conductor of an electronic component. 1 is a plan view (partially cutaway view) showing an electronic component 1 including a capacitor 11. FIG.

Explanation of symbols

  DESCRIPTION OF SYMBOLS 1-4 ... Electronic component 11, 12 ... Capacitor (thin film capacitor), 13 ... Inductor, 21 ... Lower conductor (1st conductor) 21a ... Base conductor, 21b ... Conductor, 25 ... Upper conductor (2nd conductor) 25a ... underlying conductor, 25b ... conductor, 31a ... upper surface, 31 ... dielectric film, 51 ... substrate, 52 ... flattening layer, 54 ... protective film, C ... exposed part, H ... via opening, J ... resin layer (Insulating layer), K ... opening, P ... photosensitive material layer, r ... opening diameter of opening K, .theta.1 ... taper angle of bottom of inner wall of resin layer J, .theta.2 ... taper angle of inner wall of opening of resin layer J. .

Claims (9)

A dielectric layer and an insulating layer are formed between the first conductor and the second conductor, and the insulating layer includes the first conductor or the second conductor and the dielectric layer. A thin film capacitor having an opening in an overlapping region,
At least one of the first conductor, the second conductor, and the dielectric layer has an undulating shape in which at least a part of a peripheral edge is raised to the insulating layer side than the region where the opening is formed. Having
Thin film capacitor. At least one of the first conductor, the second conductor, and the dielectric layer is formed such that the peripheral edge rises over the entire circumference of the first conductor and / or the second conductor. Is
The thin film capacitor according to claim 1. At least one of the first conductor, the second conductor, and the dielectric layer has a peripheral wedge-shaped cross section.
The thin film capacitor according to claim 1 or 2. The insulating layer is a taper formed on the inner wall defining the opening.
The thin film capacitor of any one of Claims 1-3. In the insulating layer, the inclination of the taper at the bottom of the inner wall is formed more gently than the inclination of the taper at the trunk of the inner wall.
The thin film capacitor according to claim 4. The insulating layer is mainly made of resin.
The thin film capacitor of any one of Claims 1-5. Forming a first conductor; forming a second conductor; forming a dielectric layer between the first and second conductors; and between the first and second conductors A method of manufacturing a thin film capacitor comprising a step of forming an insulating layer,
The step of forming the insulating layer includes the step of forming an opening in a region where the first conductor or the second conductor and the dielectric layer overlap,
In at least one of the steps of forming the first conductor, the second conductor, and the dielectric layer, at least one of the first conductor, the second conductor, and the dielectric layer. As one, form what has an undulating shape in which at least a part of the peripheral edge is raised to the insulating layer side than the region in which the opening is formed,
Manufacturing method of thin film capacitor. Forming the first conductor and / or the second conductor comprises:
Forming a seed layer made of a material of the first conductor and / or the second conductor;
A conductor layer made of the material of the first conductor and / or the second conductor on the seed layer and having an undulating shape in which at least a part of a peripheral edge is raised from a region where the opening is formed. Forming a step;
Patterning the conductor layer into a predetermined shape;
Removing the seed layer remaining around the patterned conductor layer;
Having
The method for manufacturing a thin film capacitor according to claim 7. A dielectric layer and an insulating layer are formed between the first conductor and the second conductor, and the insulating layer overlaps the first conductor or the second conductor and the dielectric layer. And at least one of the first conductor, the second conductor, and the dielectric layer has at least a part of the peripheral edge of the region where the opening is formed. A thin film capacitor having a undulating shape raised on the insulating layer side,
With electronic components.