JP4454974B2 - Displacement sensor, optimal origin position candidate detection method for displacement sensor, and stability detection method for origin detection of displacement sensor - Google Patents

Description

出力をＡＮＤ回路１０３ｍ３へ入力している。
【００５１】
また、図３の（Ｃ）に示す具体例では、位置信号（ｃ）の立ち下がり時の、ラッチされた原点検出用信号（ｆ）の値を出力する原点検出用信号検出回路を構成するフリップフロップ１０３ｍ１及びＮＯＴ回路１０３ｍ４と、リサージュ円上で時計回りとなる変位を検出する方向判別回路を構成するフリップフロップ１０３ｍ２と、これらの出力の論理積を取るＡＮＤ回路１０３ｍ３とによって、ラッチされた原点検出信号（ｆ）がハイレベルになった後、設定された同期位置にあることを検出する検出回路１０３ｍを構成している。即ち、フリップフロップ１０３ｍ１のデータＤへはラッチ回路１０６によってラッチされた原点検出用信号（ｆ）を入力し、クロックＣＬＫへはＮＯＴ回路１０３ｍ４で反転した位置信号（ｃ）を入力し、Ｑ出力をＡＮＤ回路１０３ｍ３へ入力している。また、フリップフロップ１０３ｍ２のデータＤへは位置信号（ｄ）を入力し、クロックＣＬＫへは位置信号（ｃ）を入力し、Ｑ出力をＡＮＤ回路１０３ｍ３へ入力している。
【００５２】
図４の（Ａ）に示す具体例では、図３の（Ｂ）及び（Ｃ）の出力の論理和をＯＲ回路で取っている。即ち、フリップフロップ１０３ｍ１ａのデータＤへはラッチ回路１０６によってラッチされた原点検出用信号（ｆ）を入力し、クロックＣＬＫへは位置信号（ｃ）を入力し、Ｑ出力をＡＮＤ回路１０３ｍ３ａへ入力している。また、フリップフロップ１０３ｍ２ａのデータＤへは位置信号（ｄ）を入力し、クロックＣＬＫへは位置信号（ｃ）を入力し、Ｑバー出力をＡＮＤ回路１０３ｍ３ａへ入力している。さらに、フリップフロップ１０３ｍ１ｂのデータＤへはラッチ回路１０６によってラッチされた原点検出用信号（ｆ）を入力し、クロックＣＬＫへはＮＯＴ回路１０３ｍ４で反転した位置信号（ｃ）を入力し、Ｑ出力をＡＮＤ回路１０３ｍ３ｂへ入力している。また、フリップフロップ１０３ｍ２ｂのデータＤへは位置信号（ｄ）を入力し、クロックＣＬＫへは位置信号（ｃ）を入力し、Ｑ出力をＡＮＤ回路１０３ｍ３ｂへ入力している。そして、ＡＮＤ回路１０３ｍ３ａの出力とＡＮＤ回路１０３ｍ３ｂの出力とをＯＲ回路１０３ｍ５に入力している。なお、方向判別用のフリップフロップを２個（１０３ｍ２ａ，１０３ｍ２ｂ）用いているが、出力の取り方以外は同一なので、１つにまとめて出力を分けることも可能である。
【００５３】
図４の（Ｂ）に示す具体例では、位置信号（ｃ）の立ち下がり時の、ラッチされた原点検出用信号（ｆ）の値を出力する原点検出用信号検出回路を構成するフリップフロップ１０３ｍ１及びＮＯＴ回路１０３ｍ４と、リサージュ円上で反時計回りとなる変位を検出する方向判別回路を構成するフリップフロップ１０３ｍ２と、これらの出力の論理積を取るＡＮＤ回路１０３ｍ３とによって、ラッチされた原点検出信号（ｆ）がハイレベルになった後、設定された同期位置にあることを検出する検出回路１０３ｍを構成している。即ち、フリップフロップ１０３ｍ１のデータＤへはラッチ回路１０６によってラッチされた原点検出用信号（ｆ）を入力し、クロックＣＬＫへはＮＯＴ回路１０３ｍ４で反転した位置信号（ｃ）を入力し、Ｑ出力をＡＮＤ回路１０３ｍ３へ入力している。また、フリップフロップ１０３ｍ２のデータＤへは位置信号（ｄ）を入力し、クロックＣＬＫへは位置信号（ｃ）を入力し、Ｑバー出力をＡＮＤ回路１０３ｍ３へ入力している。
【００５４】
そして、図５に示す具体例では、図３の（Ｂ）の構成と、図３の（Ｂ）の原点信号の幅を規定するための、位置信号（ｃ）がハイレベルで位置信号（ｄ）がローレベルのとき出力がハイレベルとなるＡＮＤ回路１０３ｍ６と、そのＡＮＤ回路１０３ｍ６の出力と図３の（Ｂ）の出力との論理積を取るＡＮＤ回路１０３ｍ７とによって、ラッチされた原点検出信号（ｆ）がハイレベルになった後、設定された同期位置にあることを検出する検出回路１０３ｍを構成している。即ち、ＡＮＤ回路１０３ｍ６には、位置信号（ｃ）とＮＯＴ回路１０３ｍ８で反転した位置信号（ｄ）とを入力し、このＡＮＤ回路１０３ｍ６の出力と図３の（Ｂ）の構成におけるＡＮＤ回路１０３ｍ３の出力とを、ＡＮＤ回路１０３ｍ７に入力している。
【００５５】
また、判定回路１０７については、図６乃至図８に示すような３例の構成とする。ここで、図６乃至図８は図２の（Ａ）乃至（Ｃ）にそれぞれ対応している。
【００５６】
図６に示す具体例では、判定回路１０７は、位置信号（ｄ）とその位置信号（ｄ）をＮＯＴ回路１０７Ｄで反転した信号とを原点検出用信号（ｆ）の立ち上がりでラッチするラッチ回路１０７ｍを含む。このラッチ回路１０７ｍから出力される判定Ｏ１の信号は、位置信号（ｄ）がハイレベルの時にハイレベルとなり、また、判定Ｏ２の信号は、位置信号（ｄ）がローレベルの時にハイレベルとなる。さらに、この判定回路１０７は、位置信号（ｃ）とそれをＮＯＴ回路１０７Ｅで反転した信号、位置信号（ｄ）とそれをＮＯＴ回路１０７Ｄで反転した信号を図示されたように入力する４つのＡＮＤ回路１０７Ｆ，１０７Ｇ，１０７Ｈ，１０７Ｉと、それらＡＮＤ回路１０７Ｆ〜１０７Ｉからの４つの出力を原点検出用信号（ｆ）の立ち上がりでラッチする上記ラッチ回路１０７ｍからの出力と現原点位置の指定状況とを入力する安定度判定部１０７Ｊとを含む。即ち、上記ラッチ回路１０７ｍから出力される判定Ｓ１の信号は、位置信号（ｃ）と位置信号（ｄ）が共にハイレベルの時にハイレベルとなる。判定Ｓ２の信号は、位置信号（ｃ）がハイレベルで位置信号（ｄ）がローレベルの時にハイレベルとなる。判定Ｓ３の信号は、位置信号（ｃ）がローレベルで位置信号（ｄ）がハイレベルの時にハイレベルとなる。判定Ｓ４の信号は、位置信号（ｃ）と位置信号（ｄ）が共にローレベルの時にハイレベルとなる。
【００５７】
また、図９に示す具体例では、判定回路１０７は、位置信号（ｃ）とそれをＮＯＴ回路１０７Ｅで反転した信号、位置信号（ｄ）とそれをＮＯＴ回路１０７Ｄで反転した信号を図示されたように入力する４つのＡＮＤ回路１０７Ｆ，１０７Ｇ，１０７Ｈ，１０７Ｉと、それらＡＮＤ回路１０７Ｆ〜１０７Ｉからの４つの出力を原点検出用信号（ｆ）の立ち上がりでラッチするラッチ回路１０７ｍと、該ラッチ回路１０７ｍからの出力と現原点位置の指定状況とを入力する安定度判定部１０７Ｊとからなる。ラッチ回路１０７ｍから出力される判定１の信号は、位置信号（ｃ）と位置信号（ｄ）が共にハイレベルの時にハイレベルとなる。判定２の信号は、位置信号（ｃ）がハイレベルで位置信号（ｄ）がローレベルの時にハイレベルとなる。判定３の信号は、位置信号（ｃ）がローレベルで位置信号（ｄ）がハイレベルの時にハイレベルとなる。判定４の信号は、位置信号（ｃ）と位置信号（ｄ）が共にローレベルの時にハイレベルとなる。
【００５８】
そして、図８に示す具体例では、位置信号（ａ）と位置信号（ｂ）の値を比較するコンパレータ１０７ｈと、位置信号（ｂ）を基準信号（ｊ）を基準に線対称とした信号
【数２】

を生成するための抵抗値の等しい２つの抵抗とオペアンプとでなる反転回路１０７ｇと、信号（ｂ）バーと位置信号（ａ）の値を比較するコンパレータ１０７ｉと、コンパレータ１０７ｈとコンパレータ１０７ｉの出力、及びＮＯＴ回路１０７ｐ，１０７ｒでそれらを反転した信号を図示したように入力する４つのＡＮＤ回路１０７ｎ，１０７ｏ，１０７ｑ，１０７ｓ、それら４つのＡＮＤ回路の出力信号（ｐ）〜（ｓ）と位置信号（ｃ）とそれをＮＯＴ回路１０７Ａで反転した信号と位置信号（ｄ）とそれをＮＯＴ回路１０７ｙで反転した信号とを図示されたように入力する８つのＡＮＤ回路１０７ｔ，１０７ｕ，１０７ｖ，１０７ｗ，１０７ｘ，１０７ｚ，１０７Ｂ，１０７Ｃと、上記信号（ｐ）〜（ｓ）とされら８つのＡＮＤ回路からの８つの出力を原点検出用信号（ｆ）の立ち上がりでラッチするラッチ回路１０７ｍと、該ラッチ回路１０７ｍからの出力で、信号（ｐ）〜（ｓ）に対応する判定（Ｏ１）〜（Ｏ４）と８つのＡＮＤ回路からの８つの出力に対応する信号（Ｓ１）〜（Ｓ８）のうち、信号（Ｓ１）〜（Ｓ８）と現原点位置の指定状況を入力し、現原点位置の安定度判定結果を出力する安定度判定部１０７Ｊとからなる。
【００５９】
現在の原点位置の指定状況や判定結果は、信号処理回路部６内にあり図示されていない記憶器や、スイッチ１０４あるいは当該判定回路１０７内に設けた図示されない記憶器、もしくは、該信号処理回路部６外部に接続された外部記憶器のどれか、または、これらの内の複数に格納される。こうした記憶器は、記憶媒体を中心に、必要に応じて判定結果の加工や入出力のためのロジックアレイやＣＰＵなどから構成される。記憶器では判定回路１０７からの判定結果を記憶しておくと共に、外部へ判定結果を出力したり、その判定結果を同期タイミング切り替えスイッチ１０４へ送り、最適と判断した同期位置に切り替えるよう構成される。記憶器は電源をオフしても情報が維持されるＳＲＡＭやＦＬＡＳＨ ＲＯＭなどの不揮発性の記憶媒体が望ましい。
【００６０】
［作用］
本実施の形態における信号処理回路部６によって、図２４に示したような光検出器５からの入力を処理する際の説明を、図９及び図１０に示すタイムチャートを参照して行う。なお、図９はリサージュ円上で反時計回りとなる方向に変位した際を示しており、図１０はリサージュ円上で時計回りとなる方向に変位した際を示している。
【００６１】
変位（スケール４の相対移動）に伴い周期的に変化するエンコーダのアナログ位置検出信号（ａ）及び（ｂ）を２値化回路１０１でデジタル化することでデジタル位置検出信号（ｃ）及び（ｄ）が得られる。また、２値化回路１０２において、原点検出用信号（ｅ）を所定のスライスレベルで２値化することによって、デジタル原点検出用信号（ｆ）が得られ、ラッチ回路１０６にて、該デジタル原点検出用信号（ｆ）の立ち上がりを検出してラッチ信号（ｉ）をハイレベルとする。
【００６２】
そして、このラッチ信号（ｉ）がハイレベルの領域において、次の２つの検出方法から１つを選択することで、原点信号が得られる。なお、原点検出の方向は、図２の（Ａ）乃至（Ｃ）のリサージュ円周上を（Ｖａ、Ｖｂ）によって決まる点が反時計回りの時、即ち、原点検出方向と矢印で示された方向に動く時のみ検出するものとする。
【００６３】
１つ目の方法は、ラッチ信号（ｉ）発生後に位置信号（ａ）または（ｃ）の最初の立ち上がりに同期させてハイレベルとし、位置信号（ｂ）または（ｄ）のレベル変化に同期させてローレベルとすることで、原点信号（ｇ）を得るというものである。ここで、アナログ信号である位置信号（ａ）及び（ｂ）のレベル変化とは、基準信号（ｊ）のレベルの下から上、または、上から下へのレベル変化を指す。２つ目の方法は、ラッチ信号（ｉ）発生後に位置信号（ａ）または（ｃ）の最初の立ち下がりに同期させてハイレベルとし、位置信号（ｂ）または（ｄ）のレベル変化に同期させてローレベルとすることで、原点信号（ｈ）を得るというものである。これら２つのうちの１つを選択して原点信号（ｇ）または（ｈ）として出力するが、この選択はスイッチ１０４により行う。
【００６４】
ここで、１つ目の原点信号（ｇ）の立ち上がり部分の生成について図３の（Ａ）及び（Ｂ）に基づき詳細に説明する。
【００６５】
図３の（Ａ）に示す検出回路１０３ｍは、位置信号（ｃ）及び（ｄ）とラッチ信号（ｉ）とを入力として、ラッチされた原点検出用信号（ｆ）がハイレベルになった後に、設定された同期位置で原点信号を発生する回路である。なお、本実施の形態は、必ずしもこれに限定したものではない。例えば、方向判別の機能は、入力信号を元に実現できるが、必ずしも、方向判別機能が含まれるとは限らない。
【００６６】
図３の（Ｂ）は、リサージュ円上で反時計回りとなる方向に変位した際に原点検出するものである。方向判別について、まず説明する。フリップフロップ１０３ｍ２のデータＤへは位置信号（ｄ）を、クロックＣＬＫへは位置信号（ｃ）を入力する。この結果、フリップフロップ１０３ｍ２のＱバー出力から出力される信号は、位置信号（ｃ）の立ち上がりの度に位置信号（ｄ）の反転信号として更新される。そのため、位置信号（ｃ）の立ち上がり時に位置信号（ｄ）がローレベルの時のみフリップフロップ１０３ｍ２のＱバー出力がハイレベルとなるため、方向判別が可能となる。また、原点検出用信号の検出については、フリップフロップ１０３ｍ１のデータＤへはラッチ信号（ｉ）を、クロックＣＬＫへは位置信号（ｃ）を入力する。この結果、フリップフロップ１０３ｍ１のＱ出力から出力される信号は、位置信号（ｃ）の立ち上がりの度にラッチ信号（ｉ）として更新される。その結果、原点検出用信号が検出されてから位置信号（ｃ）の立ち上がりのタイミングで同期された原点検出用信号を出力することが可能となる。そして、これら方向判別信号と同期された原点検出用信号との論理積をＡＮＤ回路１０３ｍ３で取ることで、所定の検出方向とタイミングとで図９に示す原点信号（ｇ）を発生させることが可能となる。
【００６７】
一方、逆方向に変位した場合には、図１０の信号（ｇ）に示すように、原点信号（ｇ）は検出されない。
【００６８】
２つ目の原点信号（ｈ）の立ち上がり部分の生成については、図４の（Ｂ）を用いて説明する。図３の（Ｂ）に対して、原点検出用信号の検出について、フリップフロップ１０３ｍ１により、ＮＯＴ回路１０３ｍ４で位置信号（ｃ）を反転した信号の立ち上がりを検出するようにしている。同一の移動方向での検出を行うため、図２の（Ｂ）及び（Ｃ）における同期位置２で、図９に示す原点検出信号（ｈ）を発生させることが可能となる。
【００６９】
一方、逆方向に変位した場合には、図１０に示すように、原点信号（ｈ）は検出されない。
【００７０】
なお、原点検出時の移動方向を変えた場合や、両方向の検出を行う場合について、図３の（Ｃ）及び図４の（Ａ）を用いて説明する。
【００７１】
３の（Ｃ）は、図３の（Ｂ）とは逆にリサージュ円上で時計回りとなる方向に変位したの際に原点検出するものである。方向判別について、図３の（Ｂ）の具体例と同一のフリップフロップ１０３ｍ２を使用しているが、出力としてＱ出力をとることで、逆方向の検出が可能となる。原点検出用信号の検出については、図２の（Ｂ）及び（Ｃ）における同期位置１での位置信号（ｃ）は逆方向の変位になることで立ち下がりとなる。このため、位置信号（ｃ）をＮＯＴ回路１０３ｍ４で反転した信号の立ち上がりを検出するようにしている。これらを組み合わせることで、図３の（Ｂ）と同じ同期位置１で図１０の原点信号（ｇ’）に示すように、逆方向の原点を検出することが可能となる。なお、リサージュ円上で反時計回りとなる方向に変位した場合には、方向検出の結果から図９の原点信号（ｇ’）に示すように、原点は検出されない。
【００７２】
図４の（Ａ）の具体例は、図３の（Ｂ）の具体例の出力と図３の（Ｃ）の具体例の出力との論理和をＯＲ回路１０３ｍ５で取るようにしたものであり、正逆両方向で原点検出をする場合に有効である。結果として、図９の（ｇ）と図１０の（ｇ’）に示す原点信号を検出可能である。
【００７３】
さらに、所定の信号幅を持った原点信号を出すための条件を追加する。本実施の形態では、位置信号（ｃ）の立ち上がりから位置信号（ｄ）の立ち上がりまでを検出するが、位置信号（ｃ）の立ち上がりエッジが重要な点である。一方、検出幅については所定の時間で指定したり、測定対象物の変位量で指定してもよく、幅そのものも任意に指定して構わない。例えば、エンコーダの最小検出幅にしてもよい。本具体例では、方向が指定された上で、位置信号（ｃ）の立ち上がりから位置信号（ｄ）の立ち上がりまでという変位量に応じた条件を設けている。このことは、位置信号（ｃ）がハイレベルで位置信号（ｄ）がローレベルであることと等価であり、この条件を付加する。
【００７４】
図５の具体例では、所定幅の原点信号を得るために、位置信号（ｃ）がハイレベルであり、かつ、位置信号（ｄ）がローレベルである時にハイレベルとなる信号と、図３の（Ｂ）の原点信号との論理積をＡＮＤ回路１０３ｍ７で取るようにしている。これにより、１／４周期の間だけ原点信号（ｇ）を発生させることができる。さらに、図５の回路構成では、原点信号が複数発生される可能性があるため、原点信号検出後は、回路に図示しないリセット信号で、原点検出信号（ｆ）の立ち上がりエッジのラッチ回路と位置信号（ｃ）への同期検出回路として機能しているフリップフロップ１０３ｍ１をリセットするなどして、その出力Ｑをローレベルに戻す必要がある。
【００７５】
なお、図３の（Ｂ）乃至図５においては、移動体が所定の原点検出方向に移動中だったものが反転すると、方向判別回路によってこれが検知されて原点信号の出力がなされなくなる。但し、図４の（Ａ）の例においては、双方向の検出が可能なため、反対方向での原点検出が可能である。
【００７６】
原点検出用信号が発生して、この信号がラッチされた後に方向の反転がなされた場合には、原点検出において誤検出がなされる可能性がある。所定の方向に移動体が移動していない場合には、ラッチされた原点検出用信号をリセットすることで、こうした誤検出を防ぐことが可能である。
【００７７】
具体例を図３の（Ｂ）を用いて説明する。原点検出の方向と異なる方向に移動体が動く時、方向判別用のフリップフロップ１０３ｍ２のＱバー信号はローレベルとなり、Ｑ信号はハイレベルとなる。方向判別用のフリップフロップ１０３ｍ２のＱ信号またはＱバー信号を、必要に応じて反転させるなどして、原点検出用信号検出のフリップフロップ１０３ｍ１の図示されていないリセット端子に接続する。これにより、原点検出の方向と異なる方向に移動体が動く時、原点検出用信号検出のフリップフロップ１０３ｍ１のＱ信号がリセットされて、原点検出のシーケンスは一旦停止される。他の例においても同様の対応が可能である。
【００７８】
上述した図３の（Ａ）乃至図５に示す同期回路１０３を適切に設計することにより、正方向・逆方向の両方向の変位において所望の同期位置において所定の検出幅を持った原点検出が可能となる。
【００７９】
なお、位置信号（ａ）及び（ｃ）と位置信号（ｂ）及び（ｄ）とは、９０°の位相差を持つ。また、アナログ信号である位置検出信号（ａ）及び（ｂ）と原点検出用信号（ｅ）とは、デジタル信号である位置検出信号（ｃ）及び（ｄ）と原点検出用信号（ｆ）とを作り出せれば、どのようなタイプの信号でも構わない。また、検出系からの入力がデジタル信号のみで、アナログ信号を含まなくても構わない。また、位置検出信号をデジタル化する際にはさらに位相分割により分解能を向上させたものとしても構わない。
【００８０】
そして、位置検出は、デジタル位置検出信号（ｃ）及び（ｄ）をカウンタに入力することで行う。この場合、原点信号（ｇ）または（ｈ）が発生したときに、カウンタをリセットする、または、適切なプリセット値をセットするなどすることで、位置検出の原点出しが可能となる。
【００８１】
以上のように、本実施の形態においては、原点検出用信号を検知してから最初の同期位置に合わせて原点信号を出力する。そのため、全ての同期位置は、周期信号の１周期以内に配置されることになる。
【００８２】
また、原点検出の方法によっては、原点近傍での位置検出用の周期信号と原点検出用信号を記憶して、原点検出用信号発生位置に最も近い同期位置を原点と判別することも可能である。この場合、その判別された位置を基準とした変位量をコントローラやカウンタへプリセット値として送ることで原点位置を正確に求めることができる。このような例において、複数の原点検出位置候補を配置する場合には、原点検出用信号発生時点の前後１周期に全ての検出位置候補が配置されることになる。
【００８３】
次に、図２の（Ａ）乃至（Ｃ）を用いて、同期位置の候補と最適同期位置の検知の概要について説明する。原点検出用信号（ｆ）の検出となる立ち上がり時点において位置信号（ａ）及び（ｂ）により決まる点がどの区分にあるかによって最適な同期位置候補の判定を行う。基本的には、複数の区分と複数の同期位置候補について、各区分ごとに全ての同期位置候補との位相余裕度を段階的に判定して、最も位相余裕のある同期位置候補を最適と見なして出力する。本実施の形態においては、区分の数は２、同期位置候補の数は２、位相余裕度は位相差を０°から１８０°で表した時に、位相差が最も大きい時を最適としている。位相余裕度については、リアルタイム処理ではない場合などに見られるように、位相差を０°から１８０°で表現した時に、逆に０°に近い候補を最適と見なしてもよい。
【００８４】
図２の（Ａ）の場合について説明する。同期位置候補は、１８０°位相の離れた同期位置１と同期位置２とがある。位置信号（ａ）及び（ｂ）により決まる点が原点検出用信号（ｆ）の立ち上がり時に含まれる区分が（Ｏ１）である場合、同期位置１に対しては９０°以上の位相差があるが、同期位置２に対しては９０°以内の位相差しかない。従って、同期位置２よりも同期位置１に対して位相差が大きいので、同期位置１を最適同期位置として検知し、判定結果とする。同様に、位置信号（ａ）及び（ｂ）により決まる点が原点検出用信号（ｆ）の立ち上がり時に含まれる区分が（Ｏ２）である場合には、同期位置１よりも同期位置２に対して位相差が大きいので、同期位置１を最適同期位置として検知し、判定結果とする。
【００８５】
次に、図２の（Ｂ）の場合について説明する。同期位置候補は、１８０°位相の離れた同期位置１と同期位置２とがある。位置信号（ａ）及び（ｂ）により決まる点が原点検出用信号（ｆ）の立ち上がり時に含まれる区分が（１）または（２）である場合、同期位置１に対しては９０°以上の位相差があるが、同期位置２に対しては９０°以内の位相差しかない。従って、同期位置２よりも同期位置１に対して位相差が大きいので、同期位置１を最適同期位置として検知し、判定結果とする。同様に、位置信号（ａ）及び（ｂ）により決まる点が原点検出用信号（ｆ）の立ち上がり時に含まれる区分が（３）または（４）である場合には、同期位置１よりも同期位置２に対して位相差が大きいので、同期位置１を最適同期位置として検知し、判定結果とする。
【００８６】
さらに、図２の（Ｃ）の場合について説明する。同期位置候補は、９０°位相置きに、同期位置１乃至同期位置４までの４つがある。同期位置１と同期位置２は１８０°位相が離れて縦軸上に、同期位置３と同期位置４は１８０°位相が離れて横軸上にある。位置信号（ａ）及び（ｂ）により決まる点が原点検出用信号（ｆ）の立ち上がり時に含まれる区分が（Ｏ１）である場合、同期位置３に対しては１３５°以上１８０°以下の位相差があるが、同期位置１と同期位置２に対しては４５°以上１３５°以下の位相差しかなく、同期位置４に対しては０°以上４５°以下の位相差しかない。従って、同期位置１、同期位置２、同期位置４よりも同期位置３に対して位相差が最も大きいので、同期位置３を最適同期位置として検知し、判定結果とする。同様に、位置信号（ａ）及び（ｂ）により決まる点が原点検出用信号（ｆ）の立ち上がり時に含まれる区分が、（Ｏ２）である場合には同期位置１を、（Ｏ３）である場合には同期位置４を、（Ｏ４）である場合には同期位置２を、それぞれを最適同期位置として検知し、判定結果とする。
【００８７】
次に、最適同期位置候補の判定に際して用いる区分に関して、原点検出用信号（ｆ）の検出時に位置信号（ａ）及び（ｂ）により決まる点が含まれる区分の検出については、図６乃至図８を用いて説明する。
【００８８】
図９に示す具体例においては、区分分けは以下の２つの判定により行う。
【００８９】
Ｖａ＞Ｖｒｅｆ …（式３）
Ｖｂ＞Ｖｒｅｆ …（式４）
ここで、式３と式４について共に真の場合に区分（１）、式３が偽で式４が真の場合に区分（２）、共に偽の場合に区分（３）、式３が真で式４が偽の場合に区分（４）、の４通りの分け方をする。図９に示す実際の回路例では、２値化された位置信号（ｃ）及び（ｄ）と２個のＮＯＴ回路１０７Ｄ，１０７Ｅと４個のＡＮＤ回路１０７Ｆ〜１０７Ｉとを用いて生成した４つの区分判定信号を、原点検出用信号検出のタイミングでラッチ回路１０７ｍにてラッチし、４信号の内でハイレベルになる信号によって位置信号（ａ）及び（ｂ）の存在する区分を判断する。従って、判定１は区分（１）に、判定２は区分（４）、判定３は区分（２）、判定４は区分（３）に対応する。
【００９０】
また、図６に示す具体例においては、区分分けは（式４）の判定により行う。式４について真の場合に区分（Ｏ１）、式４が偽の場合に区分（Ｏ２）、の２通りの分け方をする。図６に示す実際の回路例では、２値化された位置信号（ｄ）とそのＮＯＴ回路１０７Ｄとを用いて生成した２つの区分判定信号を、原点検出用信号検出のタイミングでラッチ回路１０７ｍにてラッチし、２信号の内でハイレベルになる信号によって位置信号（ａ）及び（ｂ）の存在する区分を判断する。従って、判定Ｏ１は区分（Ｏ１）に、判定Ｏ２は区分（Ｏ２）に対応する。
【００９１】
図８に示す具体例においては、区分分けは以下の２つの判定により行う。
【００９２】
Ｖａ＞Ｖｂ …（式５）
Ｖａ＋Ｖｂ＞２Ｖｒｅｆ …（式６）
ここで、式５と式６について共に真の場合に区分（Ｏ１）、式５が偽で式６が真の場合に区分（Ｏ２）、共に偽の場合に区分（Ｏ３）、式５が真で式６が偽の場合に区分（Ｏ４）、の４通りの分け方をする。図８に示す実際の回路では、アナログの位置信号（ａ）及び（ｂ）と１個のオペアンプと２個のコンパレータ１０７ｈ，１０７ｉと２個の抵抗と２個のＮＯＴ回路１０７ｐ，１０７ｒと４個のＡＮＤ回路１０７ｎ，１０７ｏ，１０７ｑ，１０７ｓを用いて生成した４つの区分判別信号（ｐ）〜（ｑ）を、原点検出用信号検出のタイミングでラッチ回路１０７ｍにてラッチし、４信号（ｐ）〜（ｓ）の内でハイレベルになる信号によって位置信号（ａ）及び（ｂ）の存在する区分を判断する。従って、判定Ｏ１は区分（Ｏ１）に、判定Ｏ２は区分（Ｏ２）、判定Ｏ３は区分（Ｏ３）、判定Ｏ４は区分（Ｏ４）に対応する。
【００９３】
なお、本実施の形態においてはＶａとＶｂとが共通の振幅中心と振幅を持っているものを扱っているが、実際の信号において差がある場合には、共通の振幅中心と振幅を持つように信号を正規化してから適用したり、ＶａとＶｂで振幅中心値のみが異なる場合には、同一の参照信号Ｖｒｅｆを用いる代わりにＶａとＶｂに対して個別に中心値を設定して、図２の（Ｂ）または図２の（Ｃ）の区分けに当てはまるよう式３、式４、式５、及び式６に適用するものとする。
【００９４】
次に、図６乃至図８を用いて、最適同期位置候補の検知における、その判定論理と具体的な回路の詳細とを説明する。
【００９５】
図６と図９の具体例では、同期位置１はＶｂの２値化信号である位置信号（ｄ）がローレベルとなる領域の中心位相に、同期位置２は位置信号（ｄ）がハイレベルとなる領域の中心位相に、それぞれ設定される。原点検出用信号（ｆ）の検出時に位置信号（ａ）及び（ｂ）が存在する点との位相差が最も大きくなる同期位置を最適と判断するため、原点検出用信号（ｆ）の検出時に位置信号（ｄ）のレベルとは異なるレベルの領域に含まれる同期位置が最適である。
【００９６】
図６の具体例では、位置信号（ｄ）がローレベルとなる領域には区分（Ｏ２）が含まれ、位置信号（ｄ）がハイレベルとなる領域には区分（Ｏ１）が含まれる。従って、判定Ｏ１の結果が得られた場合には、同期位置１が最適同期位置である。さらに、判定Ｏ１では、原点信号検出時の位置から同期位置１まで時計回り方向と反時計回り方向とに共に９０°以上の位相余裕があることが分かる。同様にして、判定Ｏ２の結果が得られた場合には、同期位置２が最適同期位置である。判定Ｏ２では、原点信号検出時の位置から同期位置２まで時計回り方向と反時計回り方向とに共に９０°以上の位相余裕があることが分かる。以上の処理が図６の回路で実現されている。
【００９７】
図９の具体例では、同期位置１はＶｂの２値化信号である位置信号（ｄ）がローレベルとなる領域の中心位相に、同期位置２は位置信号（ｄ）がハイレベルとなる領域の中心位相に、それぞれ設定される。原点検出用信号（ｆ）の検出時に位置信号（ａ）及び（ｂ）が存在する点との位相差が最も大きくなる同期位置を最適と判断するため、原点検出用信号（ｆ）の検出時に位置信号（ｄ）のレベルとは異なるレベルの領域に含まれる同期位置が最適である。
【００９８】
位置信号（ｄ）がローレベルとなる領域には区分（３）と区分（４）が含まれ、位置信号（ｄ）がハイレベルとなる領域には区分（１）と区分（２）が含まれる。従って、実際には４つの区分に分かれているが、最適同期位置の判断には、区分（１）及び（２）を１つにまとめ、かつ区分（３）及び（４）を１つにまとめることで、２つの区分として判定すれば効率的である。さらに細かい区分によって移動方向ごとの位相余裕が確認できる。
【００９９】
従って、判定１または判定３の結果が得られた場合には、同期位置１が最適同期位置である。さらに、判定１では、原点信号検出時の位置から同期位置１まで時計回り方向に９０°以上の位相余裕、反時計回りに１８０°以上の位相余裕があり、判定３では、時計回り方向に１８０°以上の位相余裕、反時計回りに９０°以上の位相余裕があることが分かる。同様にして、判定２または判定４の結果が得られた場合には、同期位置２が最適同期位置である。さらに、判定２では、原点信号検出時の位置から同期位置２まで時計回り方向に１８０°以上の位相余裕、反時計回りに９０°以上の位相余裕があり、判定４では、時計回り方向に９０°以上の位相余裕、反時計回りに１８０°以上の位相余裕があることが分かる。
【０１００】
以上の処理が図９の回路で実現されている。
【０１０１】
図８の具体例では、同期位置１は式５が真で式６が偽の領域である区分Ｏ４の中心位相に、同期位置２は式５が偽で式６が真の領域である区分Ｏ２の中心位相に、同期位置３は式５と式６が共に偽の領域である区分Ｏ３の中心位相に、同期位置４は式５と式６が共に真の領域である区分Ｏ１の中心位相に、それぞれ設定される。原点検出用信号（ｆ）の検出時に位置信号（ａ）及び（ｂ）が存在する点との位相差が最も大きくなる同期位置を最適と判断するため、原点検出用信号（ｆ）の検出時の区分から最も位相の離れた、即ち、反対側の区分に含まれる同期位置が最適である。
【０１０２】
従って、判定Ｏ１の結果が得られた場合には、同期位置３が最適同期位置であり、原点信号検出時の位置から同期位置３まで時計回り方向も反時計回り方向にも９０°以上の位相余裕がある。判定Ｏ２の結果が得られた場合には、同期位置１が最適同期位置であり、原点信号検出時の位置から同期位置１まで時計回り方向も反時計回り方向にも９０°以上の位相余裕がある。判定Ｏ３の結果が得られた場合には、同期位置４が最適同期位置であり、原点信号検出時の位置から同期位置４まで時計回り方向も反時計回り方向にも９０°以上の位相余裕がある。判定Ｏ４の結果が得られた場合には、同期位置２が最適同期位置であり、原点信号検出時の位置から同期位置２まで時計回り方向も反時計回り方向にも９０°以上の位相余裕がある。
【０１０３】
以上の処理が図８の回路で実現されている。
【０１０４】
なお、上記最適同期位置候補の判定結果に関して、出力が判定１から判定４、判定Ｏ１から判定Ｏ４といった信号が、本実施の形態においてはパラレルに出力されているが、エンコードした判定結果を出力しても良い。
【０１０５】
次に、図２の（Ａ）乃至（Ｃ）を用いて、現在設定されている同期位置の安定度の判断方法の概要について説明する。
【０１０６】
即ち、本実施の形態においては、原点検出用信号（ｆ）の検出となる立ち上がり時点において、位置信号（ａ）及び（ｂ）により決まる点がどの区分にあるかによって、同期位置安定度の判断を行う。この判定の仕方としては、上述した最適同期位置の検知と同様に、原点検出用信号（ｆ）の立ち上がり時に含まれる区分と同期位置の位相差が大きいほど安定度が高く、位相差が小さいほど安定度が低いものとする。
【０１０７】
まず、図２の（Ａ）の場合について説明する。同期位置の設定が同期位置１である場合についてであるが、位置信号（ａ）及び（ｂ）により決まる点が原点検出用信号（ｆ）の立ち上がり時に含まれる区分が（Ｓ１）の場合、時計回りに９０°、反時計回りに１８０°の位相余裕がある。区分が（Ｓ２）の場合、時計回りに１８０°、反時計回りに９０°の位相余裕がある。区分が（Ｓ３）の場合、時計回りに２７０°の位相余裕度、反時計回りには位相余裕がない。区分が（Ｓ４）の場合、時計回りには位相余裕がなく、反時計回りには２７０°の位相余裕度がある。以上のことから、安定度には２つのレベルがあり、同期位置１に対して、区分（Ｓ１）と（Ｓ２）は安定度が高く、区分（Ｓ３）と（Ｓ４）は安定度が低い。同様に、同期位置２に対して、区分（Ｓ３）と（Ｓ４）は安定度が高く、区分（Ｓ１）と（Ｓ２）は安定度が低い。
【０１０８】
ただし、あくまで位相差の絶対値が大きいことが安定であるという判断基準を用いており、位相差の変化が片方向に起こる場合など固有の条件があるときには、それらの条件に応じた位相余裕安定度の判定基準を用いる必要がある。
【０１０９】
また、図２の（Ｂ）の場合については、上記図２の（Ａ）の説明について、区分（Ｓ１）〜（Ｓ４）を区分（１）〜（４）に置き換えればよい。
【０１１０】
次に、図２の（Ｃ）の場合について説明する。同期位置の設定が同期位置１である場合についてであるが、位置信号（ａ）及び（ｂ）により決まる点が原点検出用信号（ｆ）の立ち上がり時に含まれる区分が（Ｓ１）の場合、時計回りに９０°、反時計回りに２２５°の位相余裕がある。区分が（Ｓ２）の場合、時計回りに１８０°、反時計回りに１３５°の位相余裕がある。区分が（Ｓ３）の場合、時計回りに１８０°、反時計回りに１３５°の位相余裕がある。区分が（Ｓ４）の場合、時計回りに２２５°、反時計回りに９０°の位相余裕がある。区分が（Ｓ５）の場合、時計回りに２７０°、反時計回りに４５°の位相余裕がある。区分が（Ｓ６）の場合、時計回りには３１５°の位相余裕度があり、反時計回りには位相余裕がない。区分が（Ｓ７）の場合、時計回りには位相余裕がなく、反時計回りには３１５°の位相余裕度がある。区分が（Ｓ８）の場合、時計回りに４５°、反時計回りに２７０°の位相余裕がある。以上のことから、安定度には４つのレベルがあり、同期位置１に対して、区分（Ｓ２）と（Ｓ３）は安定度が一番高く、区分（Ｓ１）と（Ｓ４）は安定度が２番目に高く、区分（Ｓ５）と（Ｓ８）は安定度が３番目に高く、区分（Ｓ６）と（Ｓ７）は安定度が一番低い。
【０１１１】
同様に、同期位置２に対して、区分（Ｓ６）と（Ｓ７）は安定度が一番高く、区分（Ｓ５）と（Ｓ８）は安定度が２番目に高く、区分（Ｓ１）と（Ｓ４）は安定度が３番目に高く、区分（Ｓ２）と（Ｓ３）は安定度が一番低い。同期位置３に対しては、区分（Ｓ１）と（Ｓ８）は安定度が一番高く、区分（Ｓ２）と（Ｓ７）は安定度が２番目に高く、区分（Ｓ３）と（Ｓ６）は安定度が３番目に高く、区分（Ｓ４）と（Ｓ５）は安定度が一番低い。そして、同期位置４に対しては、区分（Ｓ４）と（Ｓ５）は安定度が一番高く、区分（Ｓ３）と（Ｓ６）は安定度が２番目に高く、区分（Ｓ２）と（Ｓ７）は安定度が３番目に高く、区分（Ｓ１）と（Ｓ８）は安定度が一番低い。
【０１１２】
なお、目的によっては１番目と２番目の安定度レベルの組合せや２番目と３番目の安定度レベルの組合せを１つの安定度のグループに分けて、全体として３つの安定度のレベルを設けることも可能である。
【０１１３】
次に、安定度の判断に際して用いる区分に関して、原点検出用信号（ｆ）の検出時に位置信号（ａ）及び（ｂ）により決まる点が含まれる区分の検出について説明する。これは、基本的には、上記最適同期位置の検知の際のそれと同じ手順である。本実施の形態においては、図６乃至図８を用いて説明する。
【０１１４】
図６及び図９の具体例においては、区分分けは図２の（Ｂ）に挙げる構成での最適同期位置の検知の際と同一の方法により行う。即ち、式３と式４について共に真の場合に区分（Ｓ１）または区分（１）、式３が偽で式４が真の場合に区分（Ｓ２）または区分（２）、共に偽の場合に区分（Ｓ３）または区分（３）、式３が真で式４が偽の場合に区分（Ｓ４）または区分（４）、の４通りの分け方をする。実際の回路例では、図６及び図９に示すように、２値化された位置信号（ｃ）及び（ｄ）と２個のＮＯＴ回路１０７Ｄ，１０７Ｅと４個のＡＮＤ回路１０７Ｆ〜１０７Ｉとを用いて区分検知信号を生成し、ラッチ回路１０７ｍへ入力する４信号の内、原点検出用信号検出のタイミングでのハイレベルになる信号によって位置信号（ａ）及び（ｂ）の存在する区分を判断する。
【０１１５】
また、図８の例においては、区分分けは式３、式４、式５、式６の４つの判定により行う。即ち、式３と式４と式５と式６の全てが真の場合に区分（Ｓ１）、式３が真で式４が真で式５が偽で式６が真の場合に区分（Ｓ２）、式３が偽で式４が真で式５が偽で式６が真の場合に区分（Ｓ３）、式３が偽で式４が真で式５が偽で式６が偽の場合に区分（Ｓ４）、式３と式４と式５と式６の全てが偽の場合に区分（Ｓ５）、式３が偽で式４が偽で式５が真で式６が偽の場合に区分（Ｓ６）、式３が真で式４が偽で式５が真で式６が偽の場合に区分（Ｓ７）、式３が真で式４が偽で式５が真で式６が真の場合に区分（Ｓ８）、の８通りの分け方をする。実際の回路では、図８に示すように、最適同期位置の区分けの際に生成した４つの信号（ｐ）〜（ｑ）と、さらに、２値化された位置信号（ｃ）及び（ｄ）と２個のＮＯＴ回路１０７ｙ，１０７Ａと８個のＡＮＤ回路１０７ｔ〜１０７ｘ，１０７ｚ，１０７Ｂ，１０７Ｃを用いて８つの区分検知信号を生成し、原点検出用信号検出のタイミングでラッチ回路１０７ｍにてラッチし、８信号の内でハイレベルになる信号によって位置信号（ａ）及び（ｂ）の存在する区分を検知する。
【０１１６】
次に、図６乃至図８を用いて現状同期位相の安定度判断についてその判定論理と具体的な回路の詳細とを説明する。
【０１１７】
図６及び図９の具体例で、同期位置１はＶｂの２値化信号である位置信号（ｄ）がローレベルとなる領域の中心位相に、同期位置２は位置信号（ｄ）がハイレベルとなる領域の中心位相に設定される。原点検出用信号（ｆ）の検出時に位置信号（ａ）及び（ｂ）が存在する点と現状の同期位置との位相差が大きいほど安定と判断するため、原点検出用信号（ｆ）の検出時に位置信号（ｄ）のレベルとは異なるレベルの領域に同期位置が含まれれば安定であり、同じ領域に含まれれば不安定である。位置信号（ｄ）がローレベルとなる領域には区分（Ｓ３）または（３）と区分（Ｓ４）または（４）が含まれ、位置信号（ｄ）がハイレベルとなる領域には区分（Ｓ１）または（１）と区分（Ｓ２）または（２）が含まれる。従って、実際には４つの区分に分かれているが、安定度の判断には、区分（Ｓ１）及び（Ｓ２）または（１）及び（２）を１つにまとめ、区分（Ｓ３）及び（Ｓ４）または（３）及び（４）を１つにまとめることで、２つの区分として判定すれば効率的である。さらに細かい区分によって移動方向ごとの位相余裕が確認できる。
【０１１８】
まず、同期位置１が現状の同期位置である場合について説明する。判定Ｓ１もしくは判定Ｓ３の結果が得られた場合、または、判定１もしくは判定３の結果が得られた場合には、安定である。判定Ｓ1または判定１では、原点信号検出時の位置から同期位置１まで時計回り方向に９０°以上の位相余裕、反時計回りに１８０°以上の位相余裕があり、判定Ｓ３または判定３では、時計回り方向に１８０°以上の位相余裕、反時計回りに９０°以上の位相余裕があることが分かる。判定Ｓ２もしくは判定Ｓ４の結果が得られた場合、または、判定２もしくは判定４の結果が得られた場合には、不安定である。判定Ｓ２または判定２では、原点信号検出時の位置から同期位置１まで時計回り方向に９０°以下の位相余裕、反時計回りに２７０°以上の位相余裕があり、判定Ｓ４または判定４では、時計回り方向に２７０°以上の位相余裕、反時計回りに９０°以下の位相余裕があることが分かる。
【０１１９】
次に、同期位置２が現状の同期位置である場合について説明する。判定Ｓ１もしくは判定Ｓ３の結果が得られた場合、または、判定１もしくは判定３の結果が得られた場合には、不安定である。判定Ｓ1または判定１では、原点信号検出時の位置から同期位置１まで時計回り方向に２７０°以上の位相余裕、反時計回りに９０°以下の位相余裕があり、判定Ｓ３または判定３では、時計回り方向に９０°以下の位相余裕、反時計回りに２７０°以上の位相余裕があることが分かる。判定Ｓ２もしくは判定Ｓ４の結果が得られた場合、または、判定２もしくは判定４の結果が得られた場合には、安定である。判定Ｓ２または判定２では、原点信号検出時の位置から同期位置１まで時計回り方向に１８０°以上の位相余裕、反時計回りに９０°以上の位相余裕があり、判定Ｓ４または判定４では、時計回り方向に９０°以上の位相余裕、反時計回りに１８０°以上の位相余裕があることが分かる。
【０１２０】
以上の処理が図６及び図９に示す構成の判定回路１０７で処理されて出力される。
【０１２１】
図８の具体例では、同期位置１は式５が真で式６が偽の領域である区分Ｏ４の中心位相に、同期位置２は式５が偽で式６が真の領域である区分Ｏ２の中心位相に、同期位置３は式５と式６が共に偽の領域である区分Ｏ３の中心位相に、同期位置４は式５と式６が共に真の領域である区分Ｏ１の中心位相に、それぞれ設定される。原点検出用信号（ｆ）の検出時に位置信号（ａ）及び（ｂ）が存在する点との位相差が最も大きくなる同期位置を最適と判断するため、原点検出用信号（ｆ）の検出時の区分から最も位相の離れた、即ち、反対側の区分に含まれる同期位置が最適である。図８から分かるように、区分Ｏ１には区分Ｓ１とＳ８、区分Ｏ２には区分Ｓ２とＳ３、区分Ｏ３には区分Ｓ４とＳ５、区分Ｏ４には区分Ｓ６とＳ７がそれぞれ含まれている。
【０１２２】
本具体例の安定度のレベル区分については、特定の同期位置に対して最大４つのレベルに分けることができる。なぜなら、区分の数が８つあり、特定の同期位置から見て、時計回りと反時計回りに対称に４つずつ区分があり、対称の位置にある区分同士を１つにまとめることで４つのグループに分かれるためである。従って、同期位置からの位相余裕度が、レベル１）１３５°から１８０°、レベル２）９０°から１３５°、レベル３）４５°から９０°、レベル４）０°から４５°、の４つの分けられる。さらに、これらのレベルを、隣り合ったレベル同士をまとめることで２レベル、または、３レベルにまとめることができる。以下の説明では、このように４つのレベルに分けた場合について説明するが、実際の適用においては、２、または、３のレベル分けを用いても良い。
【０１２３】
まず、同期位置１が現状の同期位置である場合について説明する。判定Ｓ２または判定Ｓ３の結果が得られた場合にレベル１、判定Ｓ１または判定Ｓ４の結果が得られた場合にレベル２、判定Ｓ５または判定Ｓ８の結果が得られた場合にレベル３、判定Ｓ６または判定Ｓ７の結果が得られた場合にレベル４となる。また、同期位置２が現状の同期位置であるときには、判定Ｓ６または判定Ｓ７の結果が得られた場合にレベル１、判定Ｓ５または判定Ｓ８の結果が得られた場合にレベル２、判定Ｓ１または判定Ｓ４の結果が得られた場合にレベル３、判定Ｓ２または判定Ｓ３の結果が得られた場合にレベル４となる。同期位置３が現状の同期位置であるときには、判定Ｓ１または判定Ｓ８の結果が得られた場合にレベル１、判定Ｓ２または判定Ｓ７の結果が得られた場合にレベル２、判定Ｓ３または判定Ｓ６の結果が得られた場合にレベル３、判定Ｓ４または判定Ｓ５の結果が得られた場合にレベル４となる。そして、同期位置４が現状の同期位置であるときには、判定Ｓ４または判定Ｓ５の結果が得られた場合にレベル１、判定Ｓ３または判定Ｓ６の結果が得られた場合にレベル２、判定Ｓ２または判定Ｓ７の結果が得られた場合にレベル３、判定Ｓ１または判定Ｓ８の結果が得られた場合にレベル４となる。
【０１２４】
さらに、各同期位相での判定により、時計回りと反時計回りの位相余裕度の情報も得ることが可能である。
【０１２５】
以上の処理が、図８に示す構成の判定回路１０７で行われ、安定度の判定結果が出力される。この安定度の判定の出力に関しては、レベル１からレベル４といったレベル判定結果のみを出力しても良い。また、判定１から判定４、判定Ｓ１から判定Ｓ８の信号を、現状の同期位置がどれであるかの情報と共に出力してもよい。この場合、現状の同期位置の情報は、必ずしも判定回路１０７から出力されなくとも、スイッチ１０４から出力したり、外部が設定情報を持っている場合には出力しなくともよい。
【０１２６】
なお、原点検出用信号を２値化した信号の検出位置は基本的には検出方向毎に異なる。そのため、移動体の移動方向が原点検出方向と一致していない場合には、最適同期位置や現状の原点検出位置の安定度についての判定結果は無意味である可能性が高く、場合によっては誤った情報となって混乱のもとになり得る。そのため、移動体の移動方向が原点検出方向と一致していない場合の判定結果は出力しないことが望ましい場合がある。
【０１２７】
また、移動体が所定の原点検出方向に移動中だったものが反転すると、判定結果が誤ったものになる可能性がある。
【０１２８】
上記２つの問題に対応するために、移動体の移動方向が原点検出方向と一致していない場合や途中で反転した場合に判定結果を出力しない方法について図６乃至図８の例を用いて説明する。
【０１２９】
本実施の形態の構成においては、原点検出に図３の（Ｂ）乃至図５に挙げた回路を用いている。これらの回路において、所定の原点検出方向でないことや、途中で反転したことは、方向判別回路を構成するフリップフロップ１０３ｍ２の出力レベル、または、そのレベル変化によって確認できる。所定の原点検出方向でない時や、途中で反転した時には、方向判別用のフリップフロップ１０３ｍ２の出力信号によって判定回路１０７に入力される原点検出用信号（ｆ）をマスクしたり、方向判別用のフリップフロップ１０３ｍ２の出力信号を判定回路１０７に入力して、判定結果の出力をマスクして抑制する。
【０１３０】
このような方法により、最適同期位置の検知、及び、現状の原点位置の安定度判断シーケンスは一旦停止されるか、または、出力が停止される。なお、ここに説明した方法以外にも上記目的を達成可能ならば、他の方法を用いても構わない。
【０１３１】
次に、上記のような最適同期位置や現状の原点検出位置の安定度についての判定結果を、どのように利用するかについて説明する。
【０１３２】
判定結果は、判定回路１０７内で記憶装置（図示せず）に記憶するか、外部へ出力される。外部出力先としては、表示器１０８、スイッチ１０４、インタフェースを通した外部などが挙げられる。また、本実施の形態では、最適同期位置の検知と現状の原点検出位置の安定度判断を行う判定回路が共通化されているが、判定回路が別個に配置されていて、かつ、設定を切り替える場合には、判定回路間での設定情報の交換もあり得る。
【０１３３】
判定結果の出力先としての表示器１０８は、結果が示せるものであればどのようなタイプの物でも良い。例えば、複数のＬＥＤを有しており、最適な同期位置に対応したＬＥＤと現状の同期位置の安定度を示すＬＥＤとを原点検出時に点灯・点滅・消灯するものや、安定度のみならず位相関係までに対応したＬＥＤを点灯・点滅・点灯させるものとすることができる。この表示器１０８の表示出力のタイミングは、判定時や、外部からリクエストがある時点や、原点検出用信号の検出を受けて判定を出す直前であっても、原点検出処理や判定処理に影響を与えない範囲で設定して構わない。
【０１３４】
さらに、スイッチ１０４が同期位置候補の切替をするタイミングも、同様に、原点位置切替設定を受け取った後、直後から、判定時や、外部からリクエストがある時点や、原点検出用信号の検出を受けて判定を出す直前であっても、原点検出処理や判定処理に影響を与えない範囲で設定して構わない。
【０１３５】
同期タイミングの切り替えは、スイッチ１０４によって行われるが、該スイッチ１０４は、手動によって切り替えても構わないし、外部からの設定指令で切り替えても、該スイッチ１０４が情報収集して切り替えるようにしてもよい。スイッチ１０４が情報収集する場合には、必要に応じて設定情報のリクエスト信号を判定回路１０７や記憶器や外部へ出してもよい。また、切り替えについては、現状の同期位置設定と最適な同期位置とが異なっていたり、現状の同期位置の安定度が低い場合に、必ず切り替えるものである必要はない。同期位置の切り替えが原点位置の変動につながるため、必要に応じて、切り替えを有効にするかどうかを設定しておくことも可能である。また、切り替えた設定については、原点信号検出中の切り替えの場合、今回の検出に適用するか、次回の検出から適用するかの設定をする必要があり、必要に応じて切替手段を設けることも可能である。
【０１３６】
判定結果の出力において、結果に応じて異常信号や警告信号を発生させることも可能である。例えば、最適同期位置判定結果と現在の同期位置が異なっていたり、現状の同期位置の安定度が一定レベル以下であったり、記録されている安定度の変化が特定の条件を満たした場合には、異常信号や警告信号によってメンテナンスの必要性等を伝えることが可能である。
【０１３７】
次に、最適同期位置の検知フローを、図１１の（Ａ）及び（Ｂ）を用いて説明する。
【０１３８】
図１１の（Ａ）の例では、まず、原点検出用信号が発生したか否かを検知する（ステップＳ１１）。そして、原点検出用信号の発生が検知されたならば、判定回路１０７により、最適な同期位置候補を検知し（ステップＳ１２）、その判定結果を出力する（ステップＳ１３）。その後、判定結果を反映させる設定であるか否かを判断し（ステップＳ１４）、反映させない場合には、この最適同期位置の検知フローを終了する。これに対して、判定結果を反映させる場合には、同期位置の設定を切り替えてから（ステップＳ１５）、該最適同期位置の検知フローを終了する。
【０１３９】
また、図１１の（Ｂ）の例では、まず、原点検出用信号が発生したか否かを検知する（ステップＳ１１）。そして、原点検出用信号の発生が検知されたならば、判定回路１０７により、最適な同期位置候補を検知し（ステップＳ１２）、その判定結果を出力する（ステップＳ１３）。その後、この判定結果を反映させるために、同期位置の設定を切り替えて（ステップＳ１５）、該最適同期位置の検知フローを終了する。勿論、判定結果の反映については、反映内容と現状の設定が同一の場合に再設定をしないことも可能である。
【０１４０】
なお、図１１の（Ａ）及び（Ｂ）に示したフローは最適同期位置検知についてのフローであるが、同期位置を原点検出位置と置き換えて、最適原点位置検知のフローとしても構わない。
【０１４１】
現状の同期位置の安定度判断フローを、図１２の（Ａ）及び（Ｂ）を用いて説明する。
【０１４２】
図１２の（Ａ）の例では、まず、原点検出用信号が発生したか否かを検知する（ステップＳ２１）。そして、原点検出用信号の発生が検知されたならば、判定回路１０７により現在の同期位置の安定度を判断し（ステップＳ２２）、その判定結果を出力する（ステップＳ２３）。その後、判定結果を反映させる設定であるか否かを判断し（ステップＳ２４）、反映させない場合には、この現状の同期位置の安定度判断フローを終了する。これに対して、判定結果を反映させる場合には、同期位置の設定を切り替えてから（ステップＳ２５）、該現状の同期位置の安定度判断フローを終了する。なお、判定結果の反映については、反映内容と現状の設定が同一の場合に再設定をしないことも可能である。
【０１４３】
また、図１２の（Ｂ）の例では、まず、原点検出用信号が発生したか否かを検知する（ステップＳ２１）。そして、原点検出用信号の発生が検知されたならば、判定回路１０７により現在の同期位置の安定度を判断し（ステップＳ２２）、その判定結果を出力して（ステップＳ２３）、この現状の同期位置の安定度判断フローを終了する。
【０１４４】
図１２の（Ａ）の例では、ステップＳ２４にて同期位置の設定を切り替えており、図１２の（Ｂ）の例では、ステップＳ２３で終わっているが、選択手段が無いような構成に適用した場合も含めて、原点検出用信号発生のタイミングや原点検出位置の調整のステップに置き換えたり、このステップを追加することも可能である。
【０１４５】
なお、図１２の（Ａ）及び（Ｂ）に示したフローは、現状の同期位相の安定度判断についてのフローであるが、同期位置を原点検出位置と置き換えて、現状原点位置の安定度判断のフローとしても構わない。
【０１４６】
［効果］
本実施の形態によれば、原点信号を位置検出信号に同期させる際に、原点検出用信号の検出時の位置検出信号の位置（位相）に応じて、同期位置を選択することが可能である。従って、信号ノイズやふらつき、さらには、光学式のエンコーダでは光源の安定性、発光・受光素子の温度特性とそのばらつき、個々のエンコーダの設計とのずれなどの不安定要素によって生じうる原点検出位置のずれの発生を極力抑える同期位置を選択することが可能である。
【０１４７】
原点信号の位置検出信号への同期をとるに当たり、複数の同期位置の内、どれが最良かを判断する判定回路を有しており、実際にエンコーダを装置に取り付けた状態で最良の同期位置を選ぶことが出来る。本実施の形態においては、位相余裕の大きい方の同期位置を選択することにより、変動などに対する安定性を向上させることが可能となっている。このことにより、位置信号に同期させた原点検出の安定性が増すと共に、エンコーダの取付け時のヘッドとスケールの取付け角度やギャップ等といった相対位置や姿勢のばらつきの影響を事前に考慮したり、調整を行う作業が省ける。即ち、位置検出信号と原点信号の位相差を厳密に設計や製作において設定して加工する必要がないため、製作コストや組立調整の時間短縮につながると共に、設計や製作上の制約が減ることによって機能上の自由度が上がりうる利点がある。
【０１４８】
複数の同期位置候補の設定については、９０°位相差の２つの周期信号のリサージュ波形を、振幅中心を通る任意の直線で２つの区分に分割した際に、どちらの区分にも、原点信号発生位置候補の位相が１つ以上含まれるように設定されている。このような設定においては、任意の原点検出用信号発生時の位置から±９０°以上位相余裕のある同期位置候補が必ずあり、この条件を満たす同期位置候補を選択することで、同期位置と原点検出用信号発生時の位相の間に±９０°以上の位相余裕を取ることができ、安定な原点検出が可能となる。
【０１４９】
また、原点信号発生位置候補が周期信号の１周期以内に配置されることで、各原点信号発生位置候補間の位置の差を最小に抑えることができる。このことは、原点位置の切り替えを行った際の原点位置の変動を最小に抑える効果がある。同様に、作用の説明で例に挙げた、原点近傍での位置検出用の周期信号と原点検出用信号を記憶して、原点検出用信号発生位置に最も近い同期位置を原点と判別する原点検出の方法においては、原点検出用信号発生時点の前後１周期の合計２周期以内に検出位置候補が配置されることになり、本実施の形態に準じて原点位置の切り替えを行った際の原点位置の変動を抑える効果がある。
【０１５０】
本実施の形態において、最適同期位置の検知は、原点検出用信号発生時に９０°位相差の２つの位置検出用信号が存在するリサージュ波形上の区分と同期位置候補との位相差が最も大きくなる候補を選択することによって行われる。同様に、現状の同期位置の安定度の判断は、原点検出用信号発生時に９０°位相差の２つの位置検出用信号が存在するリサージュ波形上の区分と現状の同期位置との位相差の大きさをもとにレベル分けすることで行われる。
【０１５１】
区分の概念を導入することで、位相余裕度を求めるに当たって位置検出用信号が存在するリサージュ波形上の点の位置を直接求めたり、それを用いて演算する必要がなくなり、処理が簡易化されている。区分の数については２、４、８など２以上の数を設定できる。区分の数を増やすことできめ細かい判定が可能となるが、処理能力や回路サイズ・コストなどの面で負担になりうる。システムに見合った適切な区分を設定することで、位置検出信号に同期した原点検出機能が高い安定性でコンパクトで安価なエンコーダを実現できる。
【０１５２】
さらに、図２の（Ｂ）の４つの区分の例のように、各区分の位相余裕度が移動方向によって異なる場合には、原点検出用信号検出時の位相のバラツキが経時変化でドリフトするなど、特に片方向の位相余裕度に注目して判定すべき場合には有効である。また、図２の（Ｃ）のように、最適同期位置の判定よりも現状の同期位置の安定度の判定で区分の数を増やしている場合、位相余裕度の変化の詳細を確認したり、さらには、経時変化の記録を取るのに向いている。
【０１５３】
区分の導入により処理の簡易化が図られると述べたが、このことは、判定の単純化につながり、さらに具体的な回路構成や演算処理が簡便になり、実現も容易となる。例えば、１８０°位相の離れた２つの同期位置と１８０°の半円からなる２つの区分とを設ける際に、各区分がどちらかの同期位置候補に対して９０°以上の位相差ができるように配置したとする。このとき、原点検出用信号検出時点での位置信号（ａ）及び（ｂ）により決まる点が含まれる区分がいずれであっても、適切な同期位置候補を選択することによって９０°以上の位相差が得られる。２つの同期位置を図２の（Ｂ）及び（Ｃ）において縦軸上、または、横軸上に配置することで、原点検出用信号（ｆ）の検出時と同期位置での２値化位置信号のレベルが異なる同期位置を選ぶという、２つの区分と２つの同期位置と簡潔な判定基準のみで容易に最適同期位置が検知でき、高精度で安定な原点検出が可能となる。さらに、この判定基準は、フリップフロップを用いた回路、または、同等の処理が可能なＦＰＧＡやＣＰＵなどへの応用が容易にできる。
【０１５４】
本実施の形態では、図２の（Ｂ）に挙げるように、上記１８０°の半円からなる２つの区分をさらに細分化するように分けた場合にも、２つの区分しかないと見なして処理することで同様の判定処理が可能である。また、細かく分割していることで移動方向ごとに位相余裕が細かく確認可能である。区分の数が４の場合も、ＡＮＤ回路、ＮＯＴ回路で区分の判断が容易にでき、区分数が８の場合にも、コンパレータやオペアンプや抵抗を１〜２個ずつ程度用いることで容易に区分の判断が可能である。従って、簡単な回路の割に細かい区分を用いて詳細な判定結果を得ることが可能である。
【０１５５】
さらに、判定結果の表示部も数個のＬＥＤや数桁の７セグメントの数字表示器などで実現可能であり、追加することによる負担も軽い割に位置信号に同期させた原点検出の安定性の確保と安定性の判断が容易に実現できる。
【０１５６】
また、この実施の形態では、信号処理回路部を除いて原点検出のための補助信号発生用部材などを設けていない。従って、安定した原点検出ができ、かつ、小型で安価なエンコーダを供給することが可能である。
【０１５７】
本実施の形態においては、また、一定方向に変位がなされているときのみ原点検出が可能なことが挙げられる。これにより、可動部のバックラッシュの影響を受けにくくしたり、原点検出時に２重に原点検出をせずに済ませることにつながるなどの利点が生まれ、高精度で使い勝手のよい原点検出が可能となる。
【０１５８】
さらに、記憶器に経時的に逐次保存される判定結果よりシステムとしての挙動が確認できる。例えば、図２の（Ａ）の区分において、ある区分結果から１つ隣の区分結果へ移ることは可動体の構成や検出系の若干の変動により生じる可能性があり、また、許容できるとしても、一定以上変動したり、測定の度に異なる結果が得られる場合には問題があると判断できる。また、原点位置も原点出し後の変動さえなければ良い場合には、例えばシステムの立ち上げ時に原点出しを行い、その際に最適な同期位置を毎回選び直すことも可能となり、経時的な緩やかな変動に対して自己調整が可能となる。
【０１５９】
（第２の実施の形態）
［構成］
次に、本発明の第２の実施の形態を説明する。本実施の形態によるエンコーダの主要構成は、前述の第１の実施の形態と同様に、信号処理回路部６を除き、位置検出信号と原点検出用信号が得られれば特に限定されない。例えば、前述した第１の実施の形態の主要部の構成として図２４に示したような光学式の構成など一般的なものでよい。また、図２４の例では光学式のエンコーダを挙げているが、変位量に応じた位置信号と原点信号を有するものであれば、磁気式・静電式など他のタイプのエンコーダや変位センサでもよい。
【０１６０】
また、本第２の実施の形態における信号処理回路部６の構成については、図１３に示すようになっている。即ち、この第２の実施の形態による信号処理回路部６は、９０°位相差のアナログ位置信号（ａ）及び（ｂ）を元に位相差を分割してＮ個の正弦波信号（ｋ１）〜（ｋＮ）を出力する位相分割回路１１０、これらＮ個の正弦波信号（ｋ１）〜（ｋＮ）と基準信号（ｊ）とからＮ個のデジタル信号（ｐ１）〜（ｐＮ）を生成する２値化回路１０１、これらＮ個のデジタル信号（ｐ１）〜（ｐＮ）を元に、移動体の変位量に応じたパルス信号（ｄａ）及び（ｄｂ）を生成するパルス発生回路１１１、原点検出用信号（ｅ）を所定のスライスレベルで２値化してデジタル原点検出用信号（ｆ）に変換する２値化回路１０２、そのデジタル原点検出用信号（ｆ）をラッチするラッチ回路１０６、そのラッチされたデジタル原点検出用信号（ｆ）を位置信号であるＮ個のデジタル信号（ｐ１）〜（ｐＮ）の１つに同期させて原点信号（ｇ）を発生させる同期回路１０３、同期のタイミングを切り替えるスイッチ１０４、最適同期位置の検知と現在の同期位置の安定度を判断する判定回路１０７、及び、その判定結果を表示する表示器１０８からなる。
【０１６１】
ここで、Ｎ個の正弦波信号（ｋ１）〜（ｋＮ）は、正弦波信号（ｋ１）が位置信号（ｂ）に等しく、位置信号（ｂ）即ち正弦波信号（ｋ１）をｓｉｎθとしたときに、正弦波信号（ｋｉ）、但し、ｉ＝１〜Ｎ、は、以下のように表す。
【０１６２】
（ｋｉ）＝ｓｉｎ［θ−３６０°／Ｎ・（ｉ−１）］ …（式７）
このＮ個の正弦波信号（ｋ１）〜（ｋＮ）は、本実施の形態においては位相分割回路１１０にて生成されているが、（式７）を満足する信号が得られれば、その構成や方法はどんなものであっても構わない。例えば、２つの９０°位相差信号からそれらの反転信号を反転アンプで得たり、これら信号の加減算によって３〜８相程度の多相信号の生成を行ってもよい。また、元々１２０°位相差間隔の３相信号のような信号を直接入力としても良い。
【０１６３】
また、基準信号（ｊ）は、位置信号（ａ）及び位置信号（ｂ）の振幅中心レベルとなる参照信号であり、位相分割回路１１０、２値化回路１０１で用いられる。
【０１６４】
原点信号発生位置候補とアナログ位置信号（ａ）及び（ｂ）のリサージュ図形の区分について、図１４を用いて説明する。リサージュ円上に原点信号発生位置候補のＮ個の位置（位相）が、同期位置１を横軸上の＋側として、位置信号（ａ）及び（ｂ）の周期に対して（３６０°／Ｎ）の位相差置きに並んでいる。また、最適同期位置の検知と現状の同期位置の安定度判断用に上記Ｎ個の原点信号発生位置候補の位相で区切られた、Ｎ個の区分を有し、図１４に示すように、横軸＋側から反時計回りに（１）〜（Ｎ）の番号が振られている。
【０１６５】
信号処理回路部６における２値化回路１０１については、図１５の構成のものとする。即ち、位置信号（ｋ１）〜（ｋＮ）を基準信号（ｊ）とコンパレータ１０１ａ１〜１０１ａＮで比較して、２値化信号（ｄ１）〜（ｄＮ）を生成する。さらに、ＸＯＲ回路１０１ｂ１〜１０１ｂＮにより、隣り合った２値化信号（ｄｉ）と（ｄｉ＋１）、（ただし、ｉ＝１〜Ｎ）、との排他的論理和（ＸＯＲ）を取る。ここで、ｉ＝Ｎの時は、２値化信号（ｄＮ）と（ｄ１）との排他的論理和を取るものとする。そして、ＡＮＤ回路１０１ｃ１〜１０１ｃＮで、それら排他的論理和の結果と２値化信号（ｄｉ）との論理積（ＡＮＤ）を取った結果を信号（ｐｉ）（ただし、ｉ＝１〜Ｎ）とする。
【０１６６】
信号処理回路部６における同期回路１０３については、図１６の（Ａ）及び（Ｂ）の構成のものとする。ここで、図１６の（Ｂ）は図１６の（Ａ）に示した、位置信号に同期をとった原点信号を発生させるための、検出回路１０３ｎの具体例を示す図である。この具体例における原点検出用信号検出回路と方向判別回路の２つの回路は、Ｄ−ＣトリガタイプのＬＳ４２３などのフリップフロップを使用する。
【０１６７】
図１６の（Ｂ）に示す具体例では、位置信号（ｐｉ）（ただし、ｉ＝１〜Ｎ）の立ち上がり時の、ラッチされた原点検出用信号（ｆ）の値を出力する原点検出用信号検出回路を構成するフリップフロップ１０３ｎ１と、リサージュ円上で反時計回りとなる変位を検出する方向判別回路を構成するフリップフロップ１０３ｎ２と、これらの出力の論理積を取るＡＮＤ回路１０３ｎ３とによって、ラッチされた原点検出信号（ｆ）がハイレベルで、設定された同期位置にあることを検出する検出回路１０３ｎを構成している。即ち、フリップフロップ１０３ｎ１のデータＤへはラッチ回路１０６によってラッチされた原点検出用信号（ｆ）を入力し、クロックＣＬＫへは位置信号（ｐｉ）を入力し、Ｑ出力をＡＮＤ回路１０３ｎ３へ入力している。また、フリップフロップ１０３ｎ２のデータＤへは位置信号（ｐ２）を入力し、クロックＣＬＫへは位置信号（ｐ１）を入力し、Ｑバー出力をＡＮＤ回路１０３ｎ３へ入力している。
【０１６８】
また、判定回路１０７については、図１７の構成のものとする。即ち、図１７では、位置信号（ｐ１）〜（ｐＮ）と、ラッチされた原点検出用信号（ｆ）と、現状の原点位置指定とを入力信号とするもので、ラッチ回路１０７ｍと安定度判定部１０７Ｊとから構成されている。ここで、ラッチ回路１０７ｍは、位置信号（ｐ１）〜（ｐＮ）を、ラッチされた原点検出用信号（ｆ）の立ち上がりでラッチする。このラッチ回路１０７ｍの出力を最適同期位置の検知結果（１）〜（Ｎ）とする。安定度判定部１０７Ｊは、これら判定結果（１）〜（Ｎ）と、現状の原点位置指定の情報とを入力として、現状の同期位置の安定度判定結果を出力する。
【０１６９】
これらの現在の原点位置の指定状況や判定結果は、信号処理回路部６内にあり図示されていない記憶器や、スイッチ１０４あるいは当該判定回路１０７内に設けた図示されない記憶器、もしくは、該信号処理回路部６外部に接続された外部記憶器のどれか、または、これらの内の複数に格納される。こうした記憶器は、記憶媒体を中心に、必要に応じて判定結果の加工や入出力のためのロジックアレイやＣＰＵなどから構成される。記憶器では判定回路１０７からの判定結果を記憶しておくと共に、外部へ判定結果を出力したり、その判定結果をスイッチ１０４へ送り、最適と判断した同期位置に切り替えるよう構成される。記憶器は電源をオフしても情報が維持されるＳＲＡＭやＦＬＡＳＨ ＲＯＭなどの不揮発性の記憶媒体が望ましい。
【０１７０】
［作用］
本実施の形態における信号処理回路部６によって、図２４に示したような光検出器５からの入力を処理する際の説明を図９及び図１０に示すタイムチャートの一部を参照して行う。図９はリサージュ円上で反時計回りとなる方向に変位した際を示し、図１０はリサージュ円上で時計回りとなる方向に変位した際を示している。
【０１７１】
即ち、変位（スケール４の相対移動）に伴い周期的に変化するエンコーダの、９０°位相差を持つ２つのアナログ位置信号（ａ）及び（ｂ）を、位相分割回路１１０によって位相分割することで、Ｎ個の位置信号（ｋ１）〜（ｋＮ）が得られる。これら位置信号（ｋ１）〜（ｋＮ）を２値化回路１０１でデジタル化することで、デジタル信号（ｐ１）〜（ｐＮ）が得られる。また、２値化回路１０２で原点検出用信号（ｅ）を所定のスライスレベルで２値化することで、デジタル原点検出用信号（ｆ）が得られる。ラッチ回路１０６にて、このデジタル原点検出用信号（ｆ）の立ち上がりを検出してラッチ信号（ｉ）をハイレベルとする。
【０１７２】
このラッチ信号（ｉ）がハイレベルの領域において、同期回路１０３は、以下のようにして原点信号を生成する。即ち、ラッチ信号（ｉ）発生後に位置信号（ｐｉ）（ただし、ｉ＝１〜Ｎ）の最初の立ち上がりに同期させてハイレベルとし、位置信号（ｐｉ）の立ち下がりに同期させてローレベルとする原点信号（ｇ）を生成する。上記ｉの値を１からＮまで切り替えることでＮ個の検出位置の内から１つを選択することにより、所望の原点信号（ｇ）が得られる。
【０１７３】
図１６の（Ａ）の例は、位置信号（ｐ１）〜（ｐＮ）と、ラッチされた原点検出用信号（ｆ）即ちラッチ信号（ｉ）とを入力として、原点検出用信号（ｆ）がハイレベルになった後に設定された同期位置で原点信号を発生する回路である。なお、同期回路１０３は、本実施の形態の構成に必ずしも限定したものではない。例えば、方向判別の機能は、入力信号を元に実現できるが、必ずしも、方向判別機能が含まれるとは限らない。
【０１７４】
図１６の（Ｂ）は、リサージュ円上で反時計回りとなる方向に変位した際に原点検出する回路構成を示している。
【０１７５】
方向判別について、まず説明する。フリップフロップ１０３ｎ２のデータＤへは位置信号（ｐ２）を、クロックＣＬＫへは位置信号（ｐ１）を入力する。この結果、該フリップフロップ１０３ｎ２のＱバー出力から出力される信号は、位置信号（ｐ１）の立ち上がりの度に位置信号（ｐ２）の反転信号として更新される。そのため、位置信号（ｐ１）の立ち上がり時に位置信号（ｐ２）がローレベルの時のみフリップフロップ１０３ｎ２のＱバー出力がハイレベルとなるため、方向判別が可能となる。
【０１７６】
原点検出用信号を検出する回路については、フリップフロップ１０３ｎ１のデータＤへはラッチ信号（ｉ）を、クロックＣＬＫへは位置信号（ｐｉ）を入力する。この結果、フリップフロップ１０３ｎ１のＱ出力から出力される信号は、位置信号（ｐｉ）の立ち上がりの度にラッチ信号（ｉ）として更新される。その結果、原点検出用信号が検出されてから位置信号（ｐｉ）の立ち上がりのタイミングで同期された原点検出用信号を出力することが可能となる。
【０１７７】
そして、これら方向判別信号と同期された原点検出用信号との論理積をＡＮＤ回路１０３ｎ３で取ることで、所定の検出方向とタイミングとで図９に示す原点信号（ｇ）を発生させることが可能となる。一方、逆方向に変位した場合には、図１０の信号（ｇ）に示すように原点信号は検出されない。
【０１７８】
また、位置検出は、パルス発生回路１１１で生成したパルス信号（ｄａ）及び（ｄｂ）を図示しないカウンタに入力することで行う。このカウンタを、原点信号（ｇ）が発生した時にリセットする、または、適切なプリセット値をセットするなどすることで、位置検出の原点出しが可能となる。
【０１７９】
次に、図１７を用いて、同期位置の候補と最適同期位置の検知について説明する。原点検出用信号（ｆ）の検出となる立ち上がり時点において位置信号（ａ）及び（ｂ）により決まる点がどの区分にあるかによって最適な同期位置の検知を行う。
【０１８０】
基本的には、複数の区分と複数の同期位置候補について、各区分ごとに全ての同期位置候補との位相余裕度を段階的に判定して、最も位相余裕のある同期位置候補を最適と見なして出力する。本実施の形態においては、区分の数は２、同期位置候補の数は２、位相余裕度は位相差を０°から１８０°で表した時に、位相差が最も大きい時を最適としている。位相余裕度については、リアルタイム処理ではない場合などに見られるように、位相差を０°から１８０°で表現した時に、逆に０°に近い候補を最適と見なしてもよい。
【０１８１】
図１７において、同期位置候補は、（３６０°／Ｎ）位相置きに、同期位置１〜同期位置ＮまでのＮ個がある。位置信号（ａ）及び（ｂ）により決まる点が原点検出用信号（ｆ）の立ち上がり時に含まれる区分が（ｉ）である場合について、Ｎが偶数と奇数の場合に分けて説明する。
【０１８２】
Ｎが偶数の場合、ｊ＝［（ｉ＋Ｎ／２） ｍｏｄ Ｎ］として、同期位置ｊと同期位置（ｊ＋１）に対して位相差が（１８０°−３６０°／Ｎ）と最も大きくなるので、同期位置ｊ、または、同期位置（ｊ＋１）を最適同期位置と判定する。ただし、（Ｍ ｍｏｄ Ｎ）は、ＭをＮで割った余りを示し、０から（Ｎ−１）までの数となる。
【０１８３】
Ｎが奇数の場合には、ｊ＝［｛ｉ＋（Ｎ＋１）／２｝ ｍｏｄ Ｎ］として、同期位置ｊに対して位相差が（１８０°−１８０°／Ｎ）と最も大きくなるので、同期位置ｊを最適同期位置と判定する。
【０１８４】
次に、最適同期位相候補の検知に際して用いる区分に関して、原点検出用信号（ｆ）の検出時に位置信号（ａ）及び（ｂ）により決まる点が含まれる区分の検出について、図１５及び図１７を用いて説明する。
【０１８５】
図１５において、各位置信号（ｄｉ）は位置信号（ｋｉ）を２値化したものであり、半周期ごとにハイレベルとローレベルを繰り返す。位置信号（ｄ１）〜（ｄＮ）は、（３６０°／Ｎ）位相差ごとの信号であり、添え字の数が増えるほど位相が遅れている。そのため、ＸＯＲ回路１０１ｂ１〜１０１ｂＮで位置信号（ｄｉ）と位置信号（ｄｉ＋１）との排他的論理和を取り、かつ、それらの結果と位置信号（ｄｉ）との論理積をＡＮＤ回路１０１ｃ１〜１０１ｃＮで取ることで、（式７）に当てはめると、θが３６０°・（ｉ−１）／Ｎから３６０°・ｉ／Ｎの間でのみ、位置信号（ｐｉ）がハイレベルとなる。従って、位置信号（ａ）及び（ｂ）により決まる点が含まれる区分が（ｉ）の時、（式７）より、信号（ｐｉ）のみがハイレベルとなる。
【０１８６】
以上のことから、図１７に示すように、原点検出用信号（ｆ）の検出時に位置信号（ｐ１）〜（ｐＮ）をラッチして、ハイレベルの位置信号が（ｐｉ）であったとき、原点検出用信号（ｆ）の検出時に位置信号（ａ）及び（ｂ）により決まる点が含まれる区分は区分（ｉ）であることが判別出来る。
【０１８７】
以上のことから、原点検出用信号（ｆ）の検出時に位置信号（ｐ１）〜（ｐＮ）をラッチして、ハイレベルの位置信号が（ｐｉ）であった時、即ち、図１７において、判定ｉがハイレベルであった時の最適同期位置の判定の論理を、Ｎが偶数、奇数の場合に分けて説明する。Ｎが偶数の場合、ｊ＝［（ｉ＋Ｎ／２） ｍｏｄ Ｎ］として、同期位置ｊと同期位置（ｊ＋１）に対して位相差が（１８０°−３６０°／Ｎ）と最も大きくなるので、同期位置ｊ、または、同期位置（ｊ＋１）を最適同期位置と判定する。Ｎが奇数の場合は、ｊ＝［｛ｉ＋（Ｎ＋１）／２｝ ｍｏｄ Ｎ］として、同期位置ｊに対して位相差が（１８０°−１８０°／Ｎ）と最も大きくなるので、同期位置ｊを最適同期位置と判定する。
【０１８８】
次に、同期位置の設定が（ｉ）で原点検出用信号（ｆ）の検出時に位置信号（ａ）及び（ｂ）により決まる点が含まれる区分が（ｊ）であった場合の、同期位置安定度の判断方法について説明する。判定の仕方としては、最適同期位置の判定と同様に、原点検出用信号（ｆ）の立ち上がり時に含まれる区分と同期位置との位相差が大きいほど安定度が高く、位相差が小さいほど安定度が低いものとする。
【０１８９】
図１４より、反時計回り方向と時計回り方向とに、同期位置ｉから区分（ｊ）までの位相差の最小値を求める。反時計回り方向の値をθ＋、時計回り方向の値をθ−とすると、
θ＋ ＝［（ｊ−ｉ）ｍｏｄ Ｎ］・３６０°／Ｎ …（式８）
θ− ＝［（ｉ−ｊ−１）ｍｏｄ Ｎ］・３６０°／Ｎ …（式９）
θ＋とθ−の内、小さい方をθｍｉｎとすると、θｍｉｎが位相余裕度となる。θｍｉｎの値によって余裕度の判定を行うことができる。
【０１９０】
位相差θｍｉｎは段階的な値を取り、Ｎが偶数の場合、（Ｎ／２）段階となる。また、Ｎが奇数の場合には、［（Ｎ＋１）／２］段階となる。これらの段階数については、判定レベル分けの仕様に基づき、必要に応じて、隣り合う段階同士をまとめることで段階数を減らすことができる。
【０１９１】
なお、本実施の形態においては、安定度の判断に際して用いる区分は、最適同期位置の検知に用いる区分と同一である。従って、ここでの説明は省略する。
【０１９２】
以上のことから、原点検出用信号（ｆ）の検出時に位置信号（ｐ１）〜（ｐＮ）をラッチして、ハイレベルの位置信号が（ｐｊ）であった時、即ち、図１７において、判定ｉがハイレベルであった時の、現状の同期位置ｉについての安定度判断の論理について、以下に説明する。
【０１９３】
（式８）及び（式９）で表されるθ＋とθ−の内、小さい方をθｍｉｎとして、θｍｉｎの値に応じた位相余裕度の判定を事前に行っておく。この時、θｍｉｎの値は離散的な値を取り、Ｎが偶数の場合、（Ｎ／２）段階、Ｎが奇数の場合には、［（Ｎ＋１）／２］段階となる。ｉとｊの値に基づくレベル判定を安定度判定部１０７Ｊで行い、外部へ出力する。なお、安定度判定部１０７Ｊからはｉとｊの値のみを出力して外部で安定度の判断が可能なようにしても構わない。
【０１９４】
最適同期位置や現状の原点検出位置の安定度についての判定結果を、どのように利用するかについては、上記第１の実施の形態と同様なので、詳細は省略する。
【０１９５】
［効果］
本実施の形態では、概ね上記第１の実施の形態の効果と同等の効果を得ることができる。
【０１９６】
本実施の形態特有の効果としては、ゲイン・オフセットの調整や９０°位相差信号の位相補正のために、９０°位相差信号およびその反転信号の加減算による３〜８相程度の多相信号の生成を行ったり、抵抗分割による位相分割を行う回路においては、判定のための回路がある程度共有できるということが挙げられる。
【０１９７】
前者の加減算による多相信号の生成も広い意味で位相分割の一部と捕らえることも出来、本実施の形態に適用することが可能である。特に、抵抗分割による位相分割を行う回路では、ＡＢ相信号やこれらの反転信号などを重み付けしながら加減算することでＡＢ相の１周期３６０°をＮ分割して、（３６０°／Ｎ）位相差間隔のＮ個の信号の生成を行っている、または、容易に機能追加できる。また、そのＮ個のアナログ位相差信号と基準信号との交差を検出するコンパレータ回路を既に持っている物が大半である。これらのことから、原点信号の位相同期機能や特定のタイミングにおける位相位置の検知は比較的容易である。さらに、原点信号の位相同期機能や特定のタイミングにおける位相位置の検知において、全ての同期位置候補に対して同一の検出方法を適用し、同様に、全ての区分検出に対して同一の検出方法を適用しているため、多数の同期位置候補と区分の割に回路が簡易化できる。
【０１９８】
また、位相分割では、通常、数十から数千程度の分割を行うため、多数の同期位置候補と区分を持つことで、きめ細かい最適同期位置の検知と現状の同期位置の安定度判断が行える。
【０１９９】
以上のことから、本実施の形態の内容は、抵抗分割による位相分割機能を持つ、変位センサの原点検出に容易に適用でき、抵抗分割による位相分割のメリットである、ＩＣ化による小型化と低コスト化のメリットを享受できる。
【０２００】
（第３の実施の形態）
［構成］
図１８は、本発明の変位センサの第３の実施の形態によるエンコーダの主要部の構成を示す図である。但し、信号処理回路部を除き、位置信号と原点検出用信号とが得られるものであれば、この構成に限定されないことは勿論である。
【０２０１】
図１８に示すように、この第３の実施の形態による光学式のエンコーダは、ＬＥＤ等の発光部１と該発光部１からのビーム光を平行光にするための光学素子２とを組み合わせた光源部１０と、該光源部１０からの平行光が順次に照射されるインデックススケール３及びスケール４と、該スケール４から見て光源部１０の反対側に配置された光検出器５と、該光検出器５からの信号を処理してエンコーダ信号として出力する信号処理回路部６からなる。
【０２０２】
このような構成において、インデックススケール３、スケール４、光検出器５のうち、位置検出用に用いられるのは、インデックススケール３に形成されているスリット３ａと、スケール４に形成されているスリット４ａと、光検出器５に形成されている光検出部５ａとの組合せである。また、原点検出用に用いられるのはインデックススケール３に形成されているスリット３ｂと、スケール４に形成されているスリット４ｂと、光検出器５に形成されている光検出部５ｂとの組合せである。
【０２０３】
ステージやモータなどの位置検出を行う対象物において、上記光源部１０とインデックススケール３と光検出器５との組合せは、可動部と固定部のどちらか一方に取り付けられる。また、スケール４は、可動部と固定部のどちらか他方に取り付けられる。
【０２０４】
そして、本実施の形態では、スケール４と光検出器５とにおいて、原点検出用のスリット４ｂと光検出部５ｂとが、それぞれ、３個ずつ設けられている。これら３個の光検出部５ｂでの各検出信号は、３つとも同様の波形パターンを有し、位相差は、以下の式を満足する。
【０２０５】
位相差α＝［位置信号の１周期］×（ｉ＋１／Ｎ） …（式１０）
ただし、ｉは整数の定数であり、Ｎは原点検出用信号の数を表す。本実施の形態においては、Ｎ＝３となる。
【０２０６】
なお、本実施の形態では光学式のエンコーダを挙げているが、磁気式など他のタイプを含めて、式１０を満足する位相差の複数の原点検出用信号が得られれば、どのような構成であっても良い。
【０２０７】
図１９は、本実施の形態によるエンコーダの信号処理回路部６の構成を示すブロック図である。即ち、この信号処理回路部６は、アナログ位置信号（ａ）及び（ｂ）をデジタル位置信号（ｃ）及び（ｄ）に変換するための２値化回路１０１と、原点検出用信号（ｅ１），（ｅ２），及び（ｅ３）を所定のスライスレベルで２値化してデジタル原点検出用信号（ｆ１），（ｆ２），及び（ｆ３）に変換する２値化回路１０２と、この２値化回路１０２からのデジタル原点検出用信号（ｆ１），（ｆ２），及び（ｆ３）の内の１つを選択して原点信号（ｇ）として発生させる選択回路１０５と、この選択回路１０５における選択候補を切り替えるスイッチ１０４と、最適同期位置を検知する判定回路１０７と、この判定回路１０７による最適同期位置判定結果を表示する表示器１０８とからなる。
【０２０８】
式１０では、原点信号と位置検出信号との同期の位相タイミングを複数用意するために１／Ｎずつ位相がずれているが、同期の位相タイミングを合わせたい場合には、位相差が以下のようになるよう、原点検出用のスリット４ｂの位置を設定すれば良い。
【０２０９】
位相差α＝［位置信号の１周期］×ｉ …（式１１）
ただし、ｉは整数の定数である。
【０２１０】
さらに、位相差ではなく、間隔や特定の原点位置を設けたい場合には、以下のように原点検出用のスリット４ｂと光検出部５ｂの間隔ａ、または、間隔ａｊ（ｊ＝１，…，Ｎ、本実施の形態ではＮ＝３）を設定すれば良い。
【０２１１】
間隔ａ＝Ｌ …（式１２）
間隔ａｊ＝Ｌｊ …（式１３）
ただし、Ｌ及びＬｊは定数である。
【０２１２】
式１０や式１１の場合には、原点検出用信号の検出位置での位置検出用信号の位相が正確に決められるよう構成されており、式１２や式１３の場合には、原点信号発生位置が位置検出信号に正確に同期している必要は必ずしも無く、間隔のみが指定されることになる。
【０２１３】
［作用］
図２０乃至図２２は、図１９の信号処理回路部６によって、図１８に示したような光検出器５からの入力が処理されている様子を示すタイムチャートである。特に、図２０は式１０に、図２１は式１１に、図２２は式１２に、それぞれ対応するものである。なお、式１３固有のタイムチャートは図示していないが、図２２は式１３の特殊な場合と見なすことができる。なお、図２０乃至図２３において、横軸は時間を表し、一定速度の変位が生じているときの各信号の変化を示している。
【０２１４】
即ち、２値化回路１０１において、変位（スケール４の相対移動）に伴い周期的に変化するエンコーダのアナログ位置信号（ａ）及び（ｂ）を２値化することによって、デジタル位置信号（ｃ）及び（ｄ）が得られる。また、２値化回路１０２において、原点検出用信号（ｅ１），（ｅ２），及び（ｅ３）を所定のスライスレベルで２値化することによって、デジタル原点検出用信号（ｆ１），（ｆ２），及び（ｆ３）が得られる。そして、選択回路１０５において、このデジタル原点検出用信号（ｆ１），（ｆ２），及び（ｆ３）の内の１つをスイッチ１０４に応じて選択する。図２０乃至図２２において、デジタル原点検出用信号（ｆ１），（ｆ２），及び（ｆ３）に対応する原点信号（ｇ）の検出状態部分はパルス状の部分の内、ぞれぞれ、実線の部分、細い点線の部分、点線の部分である。
【０２１５】
なお、本実施の形態では、デジタル原点検出用信号（ｆ）をそのまま原点信号としているが、デジタル原点検出用信号（ｆ）を加工して中間点でシャープな原点信号を出したり、さらには、式１０乃至式１３の条件を満たす範囲において、各原点検出用信号（ｅ）からデジタル原点検出用信号（ｆ）を作り出す方法を個別に設定しても良い。
【０２１６】
ここで、位置信号（ａ）及び（ｃ）と位置信号（ｂ）及び（ｄ）とは９０°の位相差を持つ。なお、アナログ信号である位置信号（ａ）及び（ｂ）と原点検出用信号（ｅ１），（ｅ２），及び（ｅ３）は、デジタル信号である位置信号（ｃ）及び（ｄ）と原点検出用信号（ｆ１），（ｆ２），及び（ｆ３）を作り出せれば、どのようなタイプの信号でも構わない。また、検出系からの入力がデジタル信号のみで、アナログ信号を含まなくても構わない。また、位置信号をデジタル化する際にはさらに位相分割により分解能を向上させたものとしても構わない。
【０２１７】
位置検出は、デジタル位置信号（ｃ）及び（ｄ）を図示しないカウンタに入力することで行う。そして、原点信号（ｇ）が発生したときに、カウンタをリセットすることによって、位置検出の原点出しが可能となる。
【０２１８】
次に、図２３の（Ａ）及び（Ｂ）に示すように、位置信号（ａ）と（ｂ）の描くリサージュ円と縦軸＋側との交点を原点検出の目標位相とし、図において右回りを原点検出方向としたときの判定回路１０７の処理内容を説明する。図において、右回りを原点検出方向とし、図示された目標位相を検出するには、位置信号（ｄ）がハイレベルとなる位置信号（ｃ）の立ち上がりを検出すれば良い。
【０２１９】
判定回路１０７では、原点検出用信号（ｆ１），（ｆ２），または（ｆ３）を検知した時点での位置検出信号の位相と目標位相との位相差が最も小さい原点検出用信号を最適と見なして出力する。さらに、現状の原点位置の設定について、目標位相と実際の検出位相との差より、現状の安定度を判断して出力する。これらの最適同期位置と現状の原点検出の安定度の判定結果は、表示器１０８へ、または、電気信号として外部へ出力される。なお、表示器１０８は、結果が示せるものであれば、どのようなタイプの物でも良いが、例えば、各原点検出用信号を表す３つＬＥＤの内、最適なものを原点検出時に点灯するものや、現状の原点検出の安定度を２色点灯可能なＬＥＤの表示色で表示することなどができる。
【０２２０】
ここで、具体的な判定方法を図２０と図２３の（Ａ）及び（Ｂ）を参照して説明する。図２３の（Ａ）及び（Ｂ）は式１０に対応し、図中の（ｆ１），（ｆ２），及び（ｆ３）の３点は、原点検出用信号（ｆ１），（ｆ２），及び（ｆ３）が検出された瞬間の位置信号（ａ）及び（ｂ）の位置を示している。
【０２２１】
図２０の位置信号（ａ），（ｂ），（ｃ），及び（ｄ）においては、位置信号（ｂ）及び（ｄ）の方が位置信号（ａ）及び（ｃ）に対して位相が９０°進んでいる。これらを、図２３の（Ａ）及び（Ｂ）を用いて説明する。図２０の位置信号（ａ）及び（ｂ）の信号レベルの組合せを２次元のグラフに表すと図２３の（Ａ）及び（Ｂ）の円周上を右回りに動くことになる。ここで、位置信号（ａ）のレベルがマイナスからプラスになる、即ち、位置信号（ｃ）の立ち上がりは、図２３の（Ａ）及び（Ｂ）中矢印で示した縦軸と円の交点の内、位置信号（ｂ）がプラス側である上方の点となる。この点から最も近い原点検出用信号検出時の位置が、系の変動に対して最も安定であり、最適な候補と言える。また、現状の原点の設定において、原点検出用信号検出時の位置が目標位相に近ければ原点検出が安定と見なせる。
【０２２２】
原点検出用信号が検出された際の位置信号（ｄ）のレベルがハイレベル、即ち、原点検出用信号検出時の位置が円周上で上半分に存在すれば、少なくとも位相差が９０°以内であり、安定である。各原点検出用信号の位相差は、既知であり、ほぼ１２０°である。従って、原点検出用信号が検出された際の位置信号（ｄ）のレベルがハイレベルになる原点検出用信号は１つ、または、２つである。
【０２２３】
図２３の（Ａ）の例のように、条件を満たす原点検出用信号が１つならば、それを最適な検出信号と判定すれば良い。
【０２２４】
これに対して、図２３の（Ｂ）の例のように、条件を満たす原点検出用信号が２つならば、両方を安定と見なしても良い。ここで、２つの中からさらに１つに絞るのであれば、以下のようにする。即ち、図２３の（Ｂ）の例では、位置信号（ｄ）のレベルがローレベルになる原点検出用信号が（ｆ２）唯１つとなる。各原点検出用信号の位相差は既知でほぼ１２０°であるから、対応する点（ｆ２）での位置信号（ａ）（即ち位置信号（ｃ））のレベル（ハイレベル）と同じレベルを持つ点（ｆ３）に対応する原点検出用信号（ｆ３）が最も安定な原点検出用信号として判定できる。
【０２２５】
判定について式１０を例に説明したが、他の式に対応する原点検出信号を持つ原点検出系について説明する。
【０２２６】
式１１の場合においては、図２３の（Ａ）及び（Ｂ）において（ｆ１），（ｆ２），及び（ｆ３）の３点がほぼ同一点に重なることになる。この場合、どれが最適という判断を行うことはできない。安定性については、目標位置から外れているかの安定性については式１０と同様に判断できる。
【０２２７】
式１２及び式１３についても、原点検出位置での位置信号の位相についての指定があれば、式１０のような最適位置や安定度の判定が行える。また、原点検出時での位置信号の位相の指定がない場合でも、それぞれの検出位置に応じたシステムの目的が想定されるので、その目的に応じた最適位置や安定度の判定を行うことは可能である。
【０２２８】
例えば、限定された可動範囲での使用に用いられ、しかもその可動範囲が使用目的や時間によって変化する場合には、その可動範囲内にある原点検出信号のみ原点検出に用いることが可能となる。また、複数の原点検出信号がその可動範囲内で検出可能な場合にも、原点位置が可動範囲の座標系のマイナス側の端にあるべきとか、中央にあるべきといったシステムの使用条件などに応じて最適な原点検出位置が存在する。同様に、現状の原点位置の安定度も判定すべき状況が存在する。このような場合、可動範囲などシステム使用条件などの情報、または、その情報に対応するコードを判定回路にスイッチや外部入力信号として与えることで判定が可能となる。
【０２２９】
［効果］
本実施の形態によれば、複数の原点検出用信号の中から１つを選択することで、位置信号との位相差を３つの候補の中から選択することも可能である。従って、位置信号の所望の位相に同期して原点信号を出力することが可能である。しかも、原点信号の位置信号への同期をとるに当たり、複数の原点検出用信号の内、どれが最良かを判断する判定回路１０７を有しており、実際にエンコーダを装置に取り付けた状態で最良の同期位置を選ぶことができる。これにより、変動などに対する安定性を向上させることが可能となっている。このことにより、位置信号に同期させた原点検出の安定性が増すと共に、エンコーダの取付け時のヘッドとスケールの取付け角度やギャップ等といった相対位置や姿勢のばらつきの影響を事前に考慮する必要が無くなる。即ち、位置信号と原点信号の位相差を厳密に設計や製作において設定して加工する必要がないため、製作コストや組立調整の時間短縮につながると共に、設計や製作上の制約が減ることによって機能上の自由度が上がり得る利点がある。
【０２３０】
さらに、本実施の形態によれば、複数の原点検出用信号の中から１つを選択することで原点位置の選択が可能である。さらに、式１０と式１１に挙げる原点検出部の配置によっては、位置信号との同期位相をも指定することが可能である。さらに、本実施の形態の式１０においては、１２０°間隔の位相差を設けているが、原点検出用信号発生部の数Ｎを適切に選ぶことで、原点検出用信号の位相差（３６０°／Ｎ）を所望の値にすることが可能である。
【０２３１】
本実施の形態では、複数の原点信号発生位置候補があり、各原点信号発生位置候補には、物理的に、少なくとも一部が、独立した検出系が構成され、原点信号発生位置候補の間隔を変化させることが設計上可能である。このため、使用条件などに応じて原点位置を変え、離れた別の場所に動かしたいというニーズには有効である。
【０２３２】
以上、実施の形態に基づいて本発明を説明したが、本発明は上述した実施の形態に限定されるものではなく、本発明の要旨の範囲内で種々の変形や応用が可能なことは勿論である。
【０２３３】
【発明の効果】
以上説明したように、本発明によれば、信号ノイズやふらつき、さらに光源の安定性、発光素子及び受光素子の温度特性などの不安定要素が発生しても、安定して原点位置の検出が可能となるので、変位センサ、その中でも特に、変位検出に用いられるエンコーダにおいて、ＡＢ相に同期した原点検出が安定して行える安価な変位センサ、並びに、そのような変位センサの、最適な原点位置候補の検知方法、及び、原点検出の安定度判断方法を提供することができる。
【０２３４】
また特に、本発明によれば、現状の原点位置候補の安定度判定回路が実装されているため、その判定結果に基づき原点位置の切り替えや原点検出機構の取り付け調整の必要性が判断でき、その結果として常に安定した原点検出が可能となる。
【図面の簡単な説明】
【図１】 本発明の第１の実施の形態によるエンコーダの信号処理回路部の構成を示すブロック図である。
【図２】 （Ａ）は原点信号発生位置候補とアナログ位置信号（ａ）及び（ｂ）のリサージュ図形の区分とを示す図、（Ｂ）は原点信号発生位置候補とアナログ位置信号（ａ）及び（ｂ）のリサージュ図形の別の区分とを示す図であり、（Ｃ）は原点信号発生位置候補とアナログ位置信号（ａ）及び（ｂ）のリサージュ図形のさらに別の区分とを示す図である。
【図３】 （Ａ）は第１の実施の形態によるエンコーダの信号処理回路部における同期回路の構成を示す図、（Ｂ）は（Ａ）の回路の具体的な構成を示す図であり、（Ｃ）は（Ａ）の回路の具体的な別の構成を示す図である。
【図４】 （Ａ）は図３の（Ａ）の回路の具体的なさらに別の構成を示す図であり、（Ｂ）は図３の（Ａ）の回路の具体的な他の構成を示す図である。
【図５】 図３の（Ａ）の回路の具体的なさらに他の構成を示す図である。
【図６】 第１の実施の形態によるエンコーダの信号処理回路部における判定回路の具体的な構成を示す図である。
【図７】 第１の実施の形態によるエンコーダの信号処理回路部における判定回路の具体的な別の構成を示す図である。
【図８】 第１の実施の形態によるエンコーダの信号処理回路部における判定回路の具体的なさらに別の構成を示す図である。
【図９】 図１の信号処理回路によって、リサージュ円上で反時計回りとなる方向に変位した際の光検出器からの入力が処理されている様子を示すタイムチャートである。
【図１０】 図１の信号処理回路によって、リサージュ円上で時計回りとなる方向に変位した際の光検出器からの入力が処理されている様子を示すタイムチャートである。
【図１１】 （Ａ）は最適同期位置の検知フローを示す図であり、（Ｂ）は最適同期位置の検知フローの別の例を示す図である。
【図１２】 （Ａ）は現状の同期位置の安定度判断フローを示す図であり、（Ｂ）は現状の同期位置の安定度判断フローの別の例を示す図である。
【図１３】 本発明の第２の実施の形態によるエンコーダの信号処理回路部の構成を示すブロック図である。
【図１４】 原点信号発生位置候補とアナログ位置信号（ａ）及び（ｂ）のリサージュ図形の区分とを示す図である。
【図１５】 第２の実施の形態によるエンコーダの信号処理回路部における位置信号の２値化回路の構成を示す図である。
【図１６】 （Ａ）は第２の実施の形態によるエンコーダの信号処理回路部における同期回路の構成を示す図であり、（Ｂ）は（Ａ）の回路の具体的な構成を示す図である。
【図１７】 第２の実施の形態によるエンコーダの信号処理回路部における判定回路の構成を示す図である。
【図１８】 本発明の第３の実施の形態によるエンコーダの主要部の構成を示す図である。
【図１９】 第３の実施の形態によるエンコーダの信号処理回路部の構成を示すブロック図である。
【図２０】 第３の実施の形態によるエンコーダの信号処理回路部によって光検出器からの入力が処理されている様子を示すタイムチャートである。
【図２１】 第３の実施の形態によるエンコーダの信号処理回路部によって光検出器からの入力が処理されている様子を示すタイムチャートである。
【図２２】 第３の実施の形態によるエンコーダの信号処理回路部によって光検出器からの入力が処理されている様子を示すタイムチャートである。
【図２３】 （Ａ）及び（Ｂ）はそれぞれ位置信号（ａ），（ｂ）と原点検出用信号（ｆ１），（ｆ２），（ｆ３）との関係を説明するため、位置信号（ａ），（ｂ）の信号レベルの組合せを２次元のグラフに表した図である。
【図２４】 従来の技術による光学式のエンコーダの主要部の構成を示す図である。
【図２５】 特開平８−２６１７９５号公報に示されている従来のエンコーダの構成を示す図である。
【符号の説明】
１…発光部、 ２…光学素子、 ３…インデックススケール、 ３ａ，３ｂ，４ａ４ｂ…スリット、 ４…スケール、 ５…光検出器、 ５ａ，５ｂ…光検出部、 ６…信号処理回路部、 １０…光源部、 １０１，１０２…２値化回路、 １０１ａ１〜１０１ａＮ，１０７ｈ，１０７ｉ…コンパレータ、 １０１ｂ１〜１０１ｂＮ…ＸＯＲ回路、 １０１ｃ１〜１０１ｃＮ，１０３ｍ３，１０３ｍ３ａ，１０３ｍ３ｂ，１０３ｍ６，１０３ｍ７，１０３ｎ３，１０７ｎ，１０７ｏ，１０７ｑ，１０７ｓ，１０７ｔ〜１０７ｘ，１０７ｚ，１０７Ｂ，１０７Ｃ，１０７Ｆ〜１０７Ｉ…ＡＮＤ回路、 １０３…同期回路、 １０３ｍ…ラッチされた原点検出信号（ｆ）がハイレベルになった後、設定された同期位置にあることを検出する検出回路、 １０３ｍ１，１０３ｍ１ａ，１０３ｍ１ｂ，１０３ｍ２，１０３ｍ２ａ，１０３ｍ２ｂ，１０３ｎ１，１０３ｎ２…フリップフロップ、 １０３ｍ４，１０３ｍ８，１０７ｐ，１０７ｒ，１０７ｙ，１０７Ａ，１０７Ｄ，１０７Ｅ…ＮＯＴ回路、 １０３ｍ５…ＯＲ回路、 １０３ｎ…ラッチされた原点検出信号（ｆ）がハイレベルで、設定された同期位置にあることを検出する検出回路、 １０４…スイッチ、 １０５…選択回路、 １０６，１０７ｍ…ラッチ回路、 １０７…判定回路、 １０７ｇ…反転回路、 １０７Ｊ…安定度判定部、 １０８…表示器、 １１０…位相分割回路、 １１１…パルス発生回路。[0001]
BACKGROUND OF THE INVENTION
The present invention relates to a displacement sensor used for displacement detection, and more particularly to an encoder having an origin detection function.
[0002]
The present invention also relates to an optimal origin position candidate detection method and origin detection stability determination method for such a displacement sensor.
[0003]
[Prior art]
As a general example of a conventional encoder, an optical encoder is known.
[0004]
That is, as shown in FIG. 24, the optical encoder includes a light source unit 10 that combines a light emitting unit 1 such as an LED and an optical element 2 for making the light beam from the light emitting unit 1 parallel light, From the index scale 3 and the scale 4 to which the parallel light from the light source unit 10 is sequentially irradiated, the photodetector 5 disposed on the opposite side of the light source unit 10 when viewed from the scale 4, and the photodetector 5 And a signal processing circuit section 6 for processing the above signals and outputting them as encoder signals.
[0005]
In such a configuration, among the index scale 3, the scale 4, and the photodetector 5, the slits 3 a formed in the index scale 3 and the slits 4 a formed in the scale 4 are used for position detection. And a combination with a light detection unit 5 a formed in the light detector 5. Also, a combination of a slit 3b formed in the index scale 3, a slit 4b formed in the scale 4, and a light detection unit 5b formed in the photodetector 5 is used for origin detection. It is.
[0006]
In an object for position detection such as a stage and a motor, the combination of the light source unit 10, the index scale 3, and the photodetector 5 is attached to one of the movable unit and the fixed unit. The scale 4 is attached to either the movable part or the fixed part.
[0007]
Also, the general encoder output signal includes a sine wave signal having a phase difference of 90 ° or a pulse (rectangular wave) signal that is output in accordance with displacement of a movable part such as a device, and a B phase signal. Signal, and a Z-phase signal (origin signal) output when the reference position of the movable part is detected.
[0008]
If the absolute position of the movable part is unknown when the apparatus is turned on or the position information is cleared, accurate position information can be obtained by detecting the origin. Of the encoders, linear encoders that perform linear position detection often place an origin detection pattern near one end of a linear scale. In a rotary encoder that detects rotational motion, an origin detection pattern is usually arranged at one place on a disk-like scale. Then, the movable portion is moved to detect the origin detection pattern of the scale, and the origin signal is output in synchronization with the AB phase signal as necessary.
[0009]
For example, in Patent Document 1, as shown in FIG. 25, the scale / index scale / light receiving unit is provided with a mechanism for generating and detecting a signal having a longer period than the position detection signal. Thus, the origin signal is used as an index when synchronizing with the position detection signal.
[0010]
That is, in FIG. 25, a collimator lens 32 that converts light from the light source 31 into parallel light and a main scale 33 are provided. The main scale 33 is provided with a pattern 34 for generating a displacement signal, a slit pattern 35 for generating a reference position signal, and a slit pattern 39 for generating a reference position auxiliary signal.
[0011]
In addition, the index scale 36 fixed to a moving body or a fixed body that moves relative to the main scale 33 and arranged to face the main scale 33 has 4 in order to generate displacement signals having phases different by 90 °. Slit patterns 71 to 74 provided at positions, a slit pattern 38 for generating a reference position signal, and slit patterns 75 and 76 for generating a reference position auxiliary signal are formed.
[0012]
Further, on the opposite side to the light source side of the index scale 36, on the opposite side, the light receiving elements 51 to 54 for displacement signals, the light receiving elements 55 for reference signals, and the light receiving elements 61 and 62 for reference position auxiliary signals. And are provided. Thus, a reference position auxiliary signal is generated in addition to the displacement signal and the reference position signal, and is used as an index for synchronizing the origin signal with the position detection signal.
[0013]
In the encoder disclosed in Patent Document 2, the reference position is detected by detecting a specific edge of a Z-phase signal that is a rectangular pulse. Therefore, the rising or falling edge of the Z phase signal is selected and detected according to the moving direction.
[0014]
On the other hand, Patent Document 3 discloses a technique for setting the counter value to be zero at a predetermined angle by adjusting the offset value of the counter when the origin of the rotary encoder is detected.
[0015]
Furthermore, Patent Document 4 discloses an encoder having an optimum candidate determination unit for selecting one of a plurality of phases for synchronizing with the AB phase.
[0016]
[Patent Document 1]
Japanese Patent Laid-Open No. 8-261895
[0017]
[Patent Document 2]
JP 7-4991 A
[0018]
[Patent Document 3]
JP-A-7-203661
[0019]
[Patent Document 4]
Japanese Patent Laid-Open No. 2003-83771
[0020]
[Problems to be solved by the invention]
In recent years, as the resolution and accuracy of encoders have increased, there has been an increasing demand for the accuracy of the origin signal, and the same resolution and accuracy as the AB phase signal has been demanded. It has been raised as a request to output in synchronization with the AB phase signal. That is, an origin signal with high detection accuracy and good reproducibility is required. Accordingly, encoders are required to suppress deterioration in origin detection accuracy and detection timing shift due to unstable elements as a system.
[0021]
Instability factors include signal noise and fluctuations, and with optical encoders, the stability of the light source, the temperature characteristics and variations of the light emitting and receiving elements, the backlash of the stage, changes in the gap and mounting angle over time, etc. There are head and scale arrangements and posture fluctuations when detecting the origin of the stage to be incorporated.
[0022]
In particular, when the origin detection is synchronized with the AB phase while the AB phase signal and the Z phase signal are detected by separate optical systems, the detection is performed unless the phases of the A phase or B phase signal and the Z phase signal are accurately synchronized. There is a possibility that the origin is a position shifted by one cycle or more of the AB phase signal due to the timing shift.
[0023]
In the encoder disclosed in Patent Document 1, an auxiliary signal generating member for detecting the origin is provided. Thereby, it is possible to suppress the deviation of AB phase signals by several cycles. However, it has not yet been suppressed to a shift of one period of the AB phase signal due to the synchronization timing. Also, adding components / special optical systems or adding a scale pattern may increase the head size or scale width, which may lead to an increase in cost, which is contrary to the trend toward miniaturization and cost reduction. It is easy to become.
[0024]
In addition, the encoder disclosed in Patent Document 2 has specific-side edge selection means for the rectangular wave Z-phase signal, but performs selection according to the moving direction, and eventually detects the same position. It is a selection means and does not have a plurality of origin position candidates for selecting a stable origin position.
[0025]
In the encoder disclosed in Patent Document 3, the origin position is switched as the position control system. However, the origin position itself of the encoder is not changed, and therefore the origin detection stability is not improved.
[0026]
The encoder disclosed in Patent Document 4 has a plurality of origin position candidates for improving the stability of origin detection, and further has an optimum candidate determination unit for selection. However, the current origin detection stability is not judged, and the necessity of setting change is not indicated.
[0027]
The present invention has been made in view of the above circumstances, and in a displacement sensor, in particular, in an encoder used for displacement detection, an inexpensive displacement sensor capable of stably performing origin detection synchronized with the AB phase, and its It is an object of the present invention to provide an optimal origin position candidate detection method and origin detection stability determination method for such a displacement sensor.
[0028]
[Means for Solving the Problems]
  In order to achieve the above object, a displacement sensor according to the present invention comprises:
  A displacement sensor that detects a displacement amount based on a periodic signal generated according to a displacement of a position or an angle of a moving body, and generates an origin signal when the moving body is in a predetermined range.
  There are a plurality of origin signal generation position candidates that generate the origin signal,
  A selection unit that selects and switches one generation position candidate from among the plurality of origin signal generation position candidates as an origin signal generation positionWhen,
  Among the plurality of origin signal generation position candidates, a determination unit that detects an optimal candidate;
  A stability determination unit that determines the stability of the current origin signal generation position;
  Comprising
  The selection unit can select the origin signal generation position based on the determination result from the determination unit,
  The stability determination unit determines the stability of the current origin signal generation position when the optimum origin signal generation position candidate is detected.It is characterized by that.
  In order to achieve the above object, the displacement sensor according to the present invention is
  A displacement sensor that detects a displacement amount based on a periodic signal generated according to a displacement of a position or an angle of a moving body, and generates an origin signal when the moving body is in a predetermined range.
  There are a plurality of origin signal generation position candidates that generate the origin signal,
  A selection unit that selects and switches one generation position candidate from among the plurality of origin signal generation position candidates as an origin signal generation position;
  The plurality of origin signal generation position candidates correspond to a plurality of phases of the periodic signal,
  The selection unit can switch one of the plurality of phases as the origin signal generation position,
  The periodic signal is two periodic signals having a phase difference of approximately 90 ° with each other in the same period,
  Taking one output of the two periodic signals in the horizontal axis direction of the two-dimensional orthogonal coordinate system and the other output in the vertical axis direction, the value of each coordinate force at the intersection of the horizontal axis and the vertical axis is A waveform that takes a coordinate system so as to coincide with the amplitude center value of each output of the two periodic signals, and a point determined by the output of each of the two periodic signals on the coordinate system is drawn as the displacement of the moving body Is a Lissajous waveform of the above two periodic signals,
  When the moving body is in a predetermined range, an origin detection signal that is not necessarily synchronized with the periodic signal is generated,
  Among the plurality of sections that can be divided from the Lissajous waveforms of the two periodic signals, a section including a point determined by the two periodic signals can be determined at least when the origin detection signal is generated,
  Judgment for detecting an optimum origin signal generation position candidate from among the plurality of origin signal generation position candidates based on the section on the Lissajous waveform where there is a point determined by the two periodic signals when the origin detection signal is generated Further comprising
  The selection unit can select the origin signal generation position based on the determination result from the determination unit,
  The determination unit determines a phase difference between a phase on the Lissajous waveform where a point determined by the two periodic signals exists when the origin detection signal is generated and each phase of the periodic signal at the origin signal generation position candidate. Is represented by 0 ° to 180 °, the combination of the above-mentioned section and each origin signal generation position candidate is defined as the phase difference between the section and each origin signal generation position candidate. It is characterized in that the origin signal generation position candidate with the largest is determined to be optimal.
[0029]
  In order to achieve the above object, the displacement according to the present inventionSensor is,
  Generated according to the displacement of the position or angle of the moving bodyCycleDisplacement that generates an origin signal when the amount of displacement is detected based on the signal and the moving object is within the specified rangeSensor,
  There are a plurality of origin signal generation position candidates that generate the origin signal,
  One generation position candidate is selected as the origin signal generation position from the plurality of origin signal generation position candidates.To switchSelect partComprising
  The plurality of origin signal generation position candidates correspond to a plurality of phases of the periodic signal,
  The selection unit can switch one of the plurality of phases as the origin signal generation position,
  The periodic signal is a plurality of displacement detection periodic signals detected for detecting the displacement amount of the moving body, or a plurality of phase division periodic signals generated when phase-dividing the plurality of displacement detecting periodic signals. A plurality of displacement amount detection signals of three or more consisting of any of the following:
  There are the same number of origin signal generation position candidates as the number of displacement amount detection signals,
  There is a one-to-one correspondence between the plurality of origin signal generation position candidates and the periodic signal.
  The selection unit uses the corresponding displacement amount detection signal for phase detection of the plurality of origin signal generation position candidates.It is characterized by that.
[0030]
Further, in order to achieve the above object, an optimal origin position candidate detection method of the displacement sensor according to the present invention is:
The amount of displacement is detected based on a periodic signal generated according to the displacement of the position or angle of the moving body, and when the moving body is within a predetermined range, the optimal origin position candidate of the displacement sensor that generates the origin signal Detection method,
The displacement sensor is
When the moving body is in a predetermined range, an origin detection signal is generated,
There are multiple origin signal generation position candidates at the origin signal generation position where the origin signal is generated,
A selection unit that selects one generation position candidate from among the plurality of generation position candidates as an origin signal generation position, and an optimal generation position candidate among the plurality of origin signal generation position candidates is selected when an origin detection signal is generated. A determination unit for detecting,
In the method of detecting an optimal origin position candidate of the displacement sensor, the selection unit is capable of selecting an origin signal generation position based on the determination result of the determination unit.
Detecting the origin detection signal generation;
Detecting an optimum origin position candidate by the determination unit;
Outputting a determination result; and
A step of determining whether the setting reflects the determination result;
Only when it is determined to reflect the setting, the step of switching the setting of the origin position,
It is characterized by having.
[0031]
In order to achieve the above object, the displacement sensor according to the present invention is
A displacement sensor that detects an amount of displacement based on a periodic signal generated according to a displacement of a position or an angle of a moving body, and generates an origin signal when the moving body is in a predetermined range,
An origin detection signal generator for generating an origin detection signal that is not necessarily synchronized with the periodic signal when the moving body is in a predetermined range;
A stability determination unit that determines the stability of the current origin signal generation position based on the phase margin between the generation of the origin detection signal and the periodic signal at the origin signal generation position;
It is characterized by comprising.
[0032]
In order to achieve the above object, the stability determination method for detecting the origin of the displacement sensor according to the present invention includes:
Displacement that generates an origin signal when the amount of displacement is detected based on a periodic signal that is generated according to the displacement of the position or angle of the moving body, and the moving body is at the origin signal generation position at a predetermined position or angle It is a method for judging the stability of sensor origin detection,
The displacement sensor is
When the moving body is in a predetermined range, an origin detection signal is generated,
It has a stability determination unit that determines the stability of the current origin signal generation position based on the phase margin between the generation of the origin detection signal and the periodic signal at the origin signal generation position. In the method for determining the stability of the origin detection of the displacement sensor,
Detecting the origin detection signal generation;
Determining the stability of the current origin position by the stability determination unit;
Outputting the determination result;
It is characterized by having.
[0033]
DETAILED DESCRIPTION OF THE INVENTION
Embodiments of the present invention will be described below with reference to the drawings. In each of the following embodiments, a linear encoder that performs linear position detection will be described as an example of the displacement sensor. However, the present invention is not limited to such a linear encoder, and rotational movement is performed. Needless to say, the present invention can be applied to a displacement sensor for detecting various mechanical displacements such as a rotary encoder for detection.
[0034]
(First embodiment)
[Constitution]
The configuration of the main part of the encoder according to the first embodiment of the displacement sensor of the present invention is not particularly limited as long as a position signal (position detection signal) and an origin detection signal can be obtained except for the signal processing circuit section. , Not limited.
[0035]
For example, a general configuration such as a configuration using an optical encoder as shown in FIG. 24 can be applied. In the example of FIG. 24, an optical encoder is used, but other types of encoders and displacement sensors such as a magnetic type and an electrostatic type may be used as long as they have a position signal and an origin signal corresponding to the amount of displacement. Good.
[0036]
That is, as shown in FIG. 24, this optical encoder includes a light source unit 10 that combines a light emitting unit 1 such as an LED and an optical element 2 for making the beam light from the light emitting unit 1 parallel light, From the index scale 3 and the scale 4 to which the parallel light from the light source unit 10 is sequentially irradiated, the photodetector 5 disposed on the opposite side of the light source unit 10 when viewed from the scale 4, and the photodetector 5 And a signal processing circuit section 6 for processing the above signals and outputting them as encoder signals.
[0037]
In such a configuration, among the index scale 3, the scale 4, and the photodetector 5, the slits 3 a formed in the index scale 3 and the slits 4 a formed in the scale 4 are used for position detection. And a combination with a light detection unit 5 a formed in the light detector 5. Also, a combination of a slit 3b formed in the index scale 3, a slit 4b formed in the scale 4, and a light detection unit 5b formed in the photodetector 5 is used for origin detection. It is.
[0038]
In an object for position detection such as a stage and a motor, the combination of the light source unit 10, the index scale 3, and the photodetector 5 is attached to one of the movable unit and the fixed unit. The scale 4 is attached to either the movable part or the fixed part.
[0039]
Here, signals (A (+), A (−), B (+), B (−)) whose phases are different from each other by 90 ° corresponding to the movement of the scale 4 are received from the light receiving element of the light detection unit 5a. In order to simplify the description, the A (+) signal is used as the position signal (a), the B (+) signal is used as the position signal (b), or [A (+) − A. The (−)] signal is displayed as the position signal (a), the [B (+) − B (−)] signal is displayed as the position signal (b), and the other signals are not displayed. The light receiving element of the light detection unit 5b outputs an origin detection signal (e) as a Z-phase signal that is output when the reference position of the movable unit is detected. The origin detection signal (e) is an origin detection original signal that is not necessarily synchronized with the position signals (a) and (b) that are periodic signals.
[0040]
FIG. 1 is a block diagram showing a configuration of the signal processing circuit unit 6 in the encoder of FIG. 24 according to the first embodiment of the present invention. This signal processing circuit section 6 has a binarization circuit 101 for converting analog position signals (a) and (b) into digital position signals (c) and (d), and an origin detection signal (e). A binarization circuit 102 that binarizes and converts the digital origin detection signal (f) into a digital origin detection signal (f); a latch circuit 106 that latches the digital origin detection signal (f) from the binarization circuit 102; The origin signal (g) or (h) is generated by synchronizing the digital origin detection signal (f) latched by the latch circuit 106 with the digital position signals (c) and (d) from the binarization circuit 101. A synchronization circuit 103, a switch 104 as a selection unit that switches the synchronization timing in the synchronization circuit 103, a determination circuit 107 that detects the optimum synchronization position and determines the stability of the current synchronization position, And a display unit 108. displaying the determination circuit 107 optimal synchronous position determination result by the output. In FIG. 1, the origin signal (g) or (h) is obtained in synchronization with the digital position signals (c) and (d), but in synchronization with the analog position signal (a) or (b). Obtaining the origin signal (g) or (h) can also be realized by a similar function.
[0041]
In the present embodiment, a reference signal (j) is further given. The reference signal (j) is a reference signal that is the amplitude center level of the position signal (a) and the position signal (b), and is used in the binarization circuit 101 and the determination circuit 107. For example, when the position signals (a) and (b) are designed to change in the range of −5V to 5V, the reference signal (j) is 0V, and the position signals (a) and (b) Is designed to vary in the range 0V to 5V, it will be 2.5V.
[0042]
In the determination circuit 107, the reference signal (j) is not always necessary depending on the processing content. Further, the binarization circuit 101 is not necessarily a binarized signal, and may be a digitized multi-bit signal. In the case of a multi-bit signal, the same processing can be performed thereafter by extracting only the most significant code bit in order to extract binary data.
[0043]
Here, classification of the Lissajous figure of the origin signal generation position candidate and the analog position signals (a) and (b) will be described with reference to (A) to (C) of FIG. 2A to 2C show different configurations, both can correspond to the circuit configuration shown in FIG. 1 and are shown in parallel.
[0044]
In FIG. 2A, the origin signal generation position candidate has two phases, ie, two intersections of the vertical axis and the Lissajous circle, and is 180 ° relative to the period of the position signals (a) and (b). There is a phase difference. Here, the vertical axis − side is the synchronization position 1, and the vertical axis + side is the synchronization position 2. Further, for determining the optimum synchronization position, the Lissajous circle is divided by the horizontal axis, and the vertical axis + side is the section (O1), and the vertical axis-side is the section (O2). Further, for determining the phase stability of the currently designated origin detection position candidate, there are four sections divided by the vertical axis and the horizontal axis, and from the first quadrant counterclockwise (S1) to (S4). Is numbered.
[0045]
In FIG. 2B, the phase of the origin signal generation position candidate is two points of intersection of the vertical axis and the Lissajous circle, and 180 when viewed with reference to the position signals (a) and (b). There is a phase difference of °. Here, the vertical axis − side is the synchronization position 1, and the vertical axis + side is the synchronization position 2. Moreover, it has four divisions divided by the vertical axis and the horizontal axis, and numbers (1) to (4) are assigned counterclockwise from the first quadrant as shown in FIG. .
[0046]
In FIG. 2C, the phase of the origin signal generation position candidate is four of the four intersections of the two axes of the vertical and horizontal axes and the Lissajous circle, and the position signals (a) and (b) As a reference, they are lined up with a phase difference of 90 °. Here, the vertical axis − side is the synchronization position 1, the vertical axis + side is the synchronization position 2, the horizontal axis − side is the synchronization position 3, and the horizontal axis + side is the synchronization position 4. In addition, for optimum synchronization position determination, the Lissajous circle is divided by two straight lines represented by the following two formulas, and as shown in FIG. The numbers (O1) to (O4) are assigned counterclockwise. In the following two expressions, Va represents the output of the position signal (a), Vb represents the output of the position signal (b), and Vref represents the value of the reference signal (j).
[0047]
Va = Vb (Formula 1)
Va + Vb = 2Vref (Formula 2)
Further, for the phase stability determination of the currently designated origin detection position candidate, the Lissajous circle is divided by a total of four straight lines including the two straight lines represented by the above formulas 1 and 2 and the vertical and horizontal axes. As shown in FIG. 2C, the numbers (S1) to (S8) are assigned from the section close to the horizontal axis + side of the first quadrant.
[0048]
Regarding the setting of a plurality of synchronization position candidates in the examples of FIGS. 2A to 2C, the Lissajous waveform of two periodic signals having a phase difference of 90 ° is divided into two sections by an arbitrary straight line passing through the amplitude center. When divided into two, each section is set to include one or more phases of origin signal generation position candidates. In such a setting, there is always a synchronization position candidate having a phase margin of ± 90 ° or more from the position when an arbitrary origin detection signal is generated.
[0049]
Further, the synchronization circuit 103 in the signal processing circuit unit 6 is assumed to have the configuration shown in FIGS. Here, FIG. 3B to FIG. 5 show five specific examples of the detection circuit 103m for generating the origin signal synchronized with the position signal shown in FIG. ing. The two circuits of the origin detection signal detection circuit and the direction determination circuit in these specific examples use a flip-flop such as a DC trigger type LS423.
[0050]
In the specific example shown in FIG. 3B, the flip-flop 103m1 constituting the origin detection signal detection circuit that outputs the value of the latched origin detection signal (f) at the rise of the position signal (c), The latched origin detection signal (f) is high by the flip-flop 103m2 constituting the direction discrimination circuit that detects the counterclockwise displacement on the Lissajous circle and the AND circuit 103m3 that takes the logical product of these outputs. After reaching the level, the detection circuit 103m is configured to detect that it is at the set synchronization position. That is, the origin detection signal (f) latched by the latch circuit 106 is input to the data D of the flip-flop 103m1, the position signal (c) is input to the clock CLK, and the Q output is input to the AND circuit 103m3. ing. Further, the position signal (d) is input to the data D of the flip-flop 103m2, and the position signal (c) is input to the clock CLK.
[Expression 1]

The output is input to the AND circuit 103m3.
[0051]
In the specific example shown in FIG. 3C, a flip-flop constituting an origin detection signal detection circuit that outputs the value of the latched origin detection signal (f) when the position signal (c) falls. 103m1 and NOT circuit 103m4, a flip-flop 103m2 that forms a direction discriminating circuit that detects a clockwise displacement on the Lissajous circle, and an AND circuit 103m3 that takes the logical product of these outputs, and latched origin detection After the signal (f) becomes high level, the detection circuit 103m is configured to detect that it is at the set synchronization position. That is, the origin detection signal (f) latched by the latch circuit 106 is input to the data D of the flip-flop 103m1, the position signal (c) inverted by the NOT circuit 103m4 is input to the clock CLK, and the Q output is output. This is input to the AND circuit 103m3. The position signal (d) is input to the data D of the flip-flop 103m2, the position signal (c) is input to the clock CLK, and the Q output is input to the AND circuit 103m3.
[0052]
In the specific example shown in FIG. 4A, the logical sum of the outputs of FIGS. 3B and 3C is taken by an OR circuit. That is, the origin detection signal (f) latched by the latch circuit 106 is input to the data D of the flip-flop 103m1a, the position signal (c) is input to the clock CLK, and the Q output is input to the AND circuit 103m3a. ing. The position signal (d) is input to the data D of the flip-flop 103m2a, the position signal (c) is input to the clock CLK, and the Q-bar output is input to the AND circuit 103m3a. Further, the origin detection signal (f) latched by the latch circuit 106 is input to the data D of the flip-flop 103m1b, the position signal (c) inverted by the NOT circuit 103m4 is input to the clock CLK, and the Q output is output. This is input to the AND circuit 103m3b. The position signal (d) is input to the data D of the flip-flop 103m2b, the position signal (c) is input to the clock CLK, and the Q output is input to the AND circuit 103m3b. The output of the AND circuit 103m3a and the output of the AND circuit 103m3b are input to the OR circuit 103m5. Two flip-flops for direction discrimination (103m2a, 103m2b) are used. However, since the outputs are the same except for the way of output, it is possible to divide the outputs into one.
[0053]
In the specific example shown in FIG. 4B, the flip-flop 103m1 constituting the origin detection signal detection circuit that outputs the value of the latched origin detection signal (f) when the position signal (c) falls. And a NOT circuit 103m4, a flip-flop 103m2 constituting a direction discriminating circuit that detects a counterclockwise displacement on the Lissajous circle, and an AND circuit 103m3 that takes the logical product of these outputs, and latched origin detection signal After (f) becomes a high level, the detection circuit 103m is configured to detect that it is at the set synchronization position. That is, the origin detection signal (f) latched by the latch circuit 106 is input to the data D of the flip-flop 103m1, the position signal (c) inverted by the NOT circuit 103m4 is input to the clock CLK, and the Q output is output. This is input to the AND circuit 103m3. The position signal (d) is input to the data D of the flip-flop 103m2, the position signal (c) is input to the clock CLK, and the Q-bar output is input to the AND circuit 103m3.
[0054]
In the specific example shown in FIG. 5, the position signal (c) for defining the configuration of FIG. 3B and the width of the origin signal of FIG. ) Is at the low level, the output is high, and the origin detection signal latched by the AND circuit 103m7 that takes the logical product of the output of the AND circuit 103m6 and the output of FIG. After (f) becomes a high level, the detection circuit 103m is configured to detect that it is at the set synchronization position. That is, the AND circuit 103m6 receives the position signal (c) and the position signal (d) inverted by the NOT circuit 103m8, and outputs the AND circuit 103m6 and the AND circuit 103m3 in the configuration of FIG. The output is input to the AND circuit 103m7.
[0055]
The determination circuit 107 has three examples as shown in FIGS. Here, FIGS. 6 to 8 correspond to (A) to (C) of FIG. 2, respectively.
[0056]
In the specific example shown in FIG. 6, the determination circuit 107 latches the position signal (d) and a signal obtained by inverting the position signal (d) by the NOT circuit 107D at the rising edge of the origin detection signal (f). including. The determination O1 signal output from the latch circuit 107m is high when the position signal (d) is high, and the determination O2 signal is high when the position signal (d) is low. . Further, the determination circuit 107 receives four position signals (c), a signal obtained by inverting the position signal (c) by the NOT circuit 107E, and a position signal (d) and a signal obtained by inverting the position signal (d) by the NOT circuit 107D as illustrated. Circuits 107F, 107G, 107H, and 107I, and outputs from the latch circuit 107m that latches the four outputs from the AND circuits 107F to 107I at the rising edge of the origin detection signal (f) and the current origin position designation status. And an input stability determination unit 107J. That is, the signal of determination S1 output from the latch circuit 107m is at a high level when both the position signal (c) and the position signal (d) are at a high level. The signal of determination S2 is high when the position signal (c) is high and the position signal (d) is low. The signal of determination S3 becomes high level when the position signal (c) is low level and the position signal (d) is high level. The signal of the determination S4 becomes a high level when both the position signal (c) and the position signal (d) are at a low level.
[0057]
In the specific example shown in FIG. 9, the determination circuit 107 shows the position signal (c) and a signal obtained by inverting it with the NOT circuit 107E, and the position signal (d) and a signal obtained by inverting it with the NOT circuit 107D. The four AND circuits 107F, 107G, 107H, and 107I that are input in this way, the latch circuit 107m that latches the four outputs from the AND circuits 107F to 107I at the rising edge of the origin detection signal (f), and the latch circuit 107m And a stability determination unit 107J for inputting the current origin position designation status. The determination 1 signal output from the latch circuit 107m is at a high level when both the position signal (c) and the position signal (d) are at a high level. The signal of decision 2 is high when the position signal (c) is high and the position signal (d) is low. The signal of decision 3 is high when the position signal (c) is low and the position signal (d) is high. The determination 4 signal is at a high level when both the position signal (c) and the position signal (d) are at a low level.
[0058]
In the specific example shown in FIG. 8, a comparator 107h that compares the values of the position signal (a) and the position signal (b), and a signal in which the position signal (b) is line-symmetric with respect to the reference signal (j).
[Expression 2]

Inverting circuit 107g composed of two resistors and operational amplifiers having the same resistance value for generating signal, comparator 107i for comparing values of signal (b) bar and position signal (a), outputs of comparator 107h and comparator 107i, In addition, four AND circuits 107n, 107o, 107q, and 107s that receive signals obtained by inverting them in the NOT circuits 107p and 107r as shown in the figure, output signals (p) to (s) of these four AND circuits, and position signals ( c) and eight AND circuits 107t, 107u, 107v, 107w, 107x for inputting the signal obtained by inverting the signal by the NOT circuit 107A and the position signal (d) and the signal obtained by inverting the signal by the NOT circuit 107y as illustrated. , 107z, 107B, and 107C and the above signals (p) to (s) from eight AND circuits. A latch circuit 107m that latches eight outputs at the rising edge of the origin detection signal (f), and determinations (O1) to (O4) corresponding to the signals (p) to (s) based on the outputs from the latch circuit 107m. Of the signals (S1) to (S8) corresponding to the eight outputs from the eight AND circuits, the signals (S1) to (S8) and the current origin position designation status are input, and the current origin position stability determination result And a stability determination unit 107J.
[0059]
The current origin position designation status and determination result are stored in the signal processing circuit unit 6 and are not shown in the figure, a storage unit not shown in the switch 104 or the judgment circuit 107, or the signal processing circuit. The unit 6 is stored in one of the external storage devices connected to the outside or a plurality of them. Such a storage device is composed of a logic array, a CPU, and the like for processing of determination results and input / output as necessary, with a storage medium as a center. The storage unit stores the determination result from the determination circuit 107, outputs the determination result to the outside, and sends the determination result to the synchronization timing changeover switch 104 to switch to the synchronization position determined to be optimal. . The storage device is preferably a non-volatile storage medium such as SRAM or FLASH ROM that maintains information even when the power is turned off.
[0060]
[Action]
The processing when the signal processing circuit unit 6 in the present embodiment processes the input from the photodetector 5 as shown in FIG. 24 will be described with reference to the time charts shown in FIGS. Note that FIG. 9 shows a case of displacement in the counterclockwise direction on the Lissajous circle, and FIG. 10 shows a case of displacement in the clockwise direction on the Lissajous circle.
[0061]
Digital position detection signals (c) and (d) are obtained by digitizing the analog position detection signals (a) and (b) of the encoder that periodically change with displacement (relative movement of the scale 4) by the binarization circuit 101. ) Is obtained. Further, the binarization circuit 102 binarizes the origin detection signal (e) at a predetermined slice level to obtain a digital origin detection signal (f). The rising edge of the detection signal (f) is detected and the latch signal (i) is set to the high level.
[0062]
Then, in the region where the latch signal (i) is at a high level, the origin signal can be obtained by selecting one of the following two detection methods. Note that the origin detection direction is indicated by the arrows when the point determined by (Va, Vb) on the Lissajous circle in FIGS. 2A to 2C is counterclockwise, that is, the origin detection direction and the arrow. Detect only when moving in the direction.
[0063]
In the first method, after the latch signal (i) is generated, the high level is set in synchronization with the first rise of the position signal (a) or (c), and the level signal (b) or (d) is synchronized with the level change. The origin signal (g) is obtained by setting the signal to the low level. Here, the level change of the position signals (a) and (b), which are analog signals, refers to a level change from the bottom to the top or the top to the bottom of the level of the reference signal (j). In the second method, after the latch signal (i) is generated, the high level is set in synchronization with the first fall of the position signal (a) or (c), and the level signal (b) or (d) is synchronized with the level change. The origin signal (h) is obtained by setting the signal to a low level. One of these two is selected and output as the origin signal (g) or (h). This selection is performed by the switch 104.
[0064]
Here, the generation of the rising portion of the first origin signal (g) will be described in detail with reference to (A) and (B) of FIG.
[0065]
The detection circuit 103m shown in FIG. 3A receives the position signals (c) and (d) and the latch signal (i) and inputs the latched origin detection signal (f) to the high level. This is a circuit for generating an origin signal at a set synchronization position. Note that the present embodiment is not necessarily limited to this. For example, the direction discrimination function can be realized based on an input signal, but the direction discrimination function is not always included.
[0066]
FIG. 3B is for detecting the origin when displaced in the counterclockwise direction on the Lissajous circle. First, the direction determination will be described. The position signal (d) is input to the data D of the flip-flop 103m2, and the position signal (c) is input to the clock CLK. As a result, the signal output from the Q-bar output of the flip-flop 103m2 is updated as an inverted signal of the position signal (d) every time the position signal (c) rises. Therefore, only when the position signal (d) is at the low level when the position signal (c) rises, the Q-bar output of the flip-flop 103m2 is at the high level, so that the direction can be determined. For detection of the origin detection signal, the latch signal (i) is input to the data D of the flip-flop 103m1, and the position signal (c) is input to the clock CLK. As a result, the signal output from the Q output of the flip-flop 103m1 is updated as the latch signal (i) every time the position signal (c) rises. As a result, it is possible to output the origin detection signal synchronized with the rising timing of the position signal (c) after the origin detection signal is detected. Then, an AND circuit 103m3 obtains the logical product of these direction determination signals and the origin detection signal synchronized with each other, so that the origin signal (g) shown in FIG. 9 can be generated with a predetermined detection direction and timing. It becomes.
[0067]
On the other hand, in the case of displacement in the reverse direction, the origin signal (g) is not detected as shown by the signal (g) in FIG.
[0068]
The generation of the rising portion of the second origin signal (h) will be described with reference to FIG. 3B, with respect to the detection of the origin detection signal, the rising edge of the signal obtained by inverting the position signal (c) by the NOT circuit 103m4 is detected by the flip-flop 103m1. Since detection is performed in the same movement direction, the origin detection signal (h) shown in FIG. 9 can be generated at the synchronization position 2 in FIGS. 2B and 2C.
[0069]
On the other hand, when displaced in the opposite direction, the origin signal (h) is not detected as shown in FIG.
[0070]
In addition, the case where the moving direction at the time of origin detection is changed and the case where the detection is performed in both directions will be described with reference to FIG. 3C and FIG.
[0071]
In (C) of FIG. 3, the origin is detected when it is displaced in the clockwise direction on the Lissajous circle, contrary to (B) of FIG. For the direction discrimination, the same flip-flop 103m2 as that in the specific example of FIG. 3B is used. However, by taking the Q output as an output, the reverse direction can be detected. Regarding the detection of the origin detection signal, the position signal (c) at the synchronous position 1 in FIGS. 2B and 2C falls as it is displaced in the opposite direction. For this reason, the rising of the signal obtained by inverting the position signal (c) by the NOT circuit 103m4 is detected. By combining these, it is possible to detect the origin in the reverse direction as indicated by the origin signal (g ′) in FIG. 10 at the same synchronization position 1 as in FIG. In the case of displacement in the counterclockwise direction on the Lissajous circle, the origin is not detected as indicated by the origin signal (g ′) in FIG. 9 from the direction detection result.
[0072]
In the specific example of FIG. 4A, an OR circuit 103m5 takes the logical sum of the output of the specific example of FIG. 3B and the output of the specific example of FIG. This is effective when detecting the origin in both forward and reverse directions. As a result, the origin signal shown in (g) of FIG. 9 and (g ′) of FIG. 10 can be detected.
[0073]
Further, a condition for outputting an origin signal having a predetermined signal width is added. In this embodiment, the rise from the rise of the position signal (c) to the rise of the position signal (d) is detected. The rising edge of the position signal (c) is an important point. On the other hand, the detection width may be specified at a predetermined time, may be specified by the amount of displacement of the measurement object, or the width itself may be arbitrarily specified. For example, the minimum detection width of the encoder may be used. In this specific example, after the direction is specified, a condition corresponding to the amount of displacement from the rising edge of the position signal (c) to the rising edge of the position signal (d) is provided. This is equivalent to the position signal (c) being at a high level and the position signal (d) being at a low level, and this condition is added.
[0074]
In the specific example of FIG. 5, in order to obtain an origin signal having a predetermined width, a signal that becomes high when the position signal (c) is at a high level and the position signal (d) is at a low level; The AND circuit 103m7 takes a logical product with the origin signal of (B). As a result, the origin signal (g) can be generated only during a quarter period. Further, in the circuit configuration of FIG. 5, since a plurality of origin signals may be generated, after the origin signal is detected, the reset signal (not shown) in the circuit and the position of the latch circuit and position of the rising edge of the origin detection signal (f) It is necessary to reset the output Q to a low level by resetting the flip-flop 103m1 functioning as a synchronization detection circuit for the signal (c).
[0075]
In FIGS. 3B to 5, when the moving body is moving in a predetermined origin detection direction, this is detected by the direction discrimination circuit and the origin signal is not output. However, in the example of FIG. 4A, since bidirectional detection is possible, the origin detection in the opposite direction is possible.
[0076]
If an origin detection signal is generated and the direction is reversed after the signal is latched, there is a possibility that erroneous detection is performed in the origin detection. When the moving body does not move in a predetermined direction, it is possible to prevent such erroneous detection by resetting the latched origin detection signal.
[0077]
A specific example will be described with reference to FIG. When the moving body moves in a direction different from the direction of origin detection, the Q bar signal of the direction determining flip-flop 103m2 becomes low level, and the Q signal becomes high level. The Q signal or Q bar signal of the direction determination flip-flop 103m2 is inverted as necessary, and connected to a reset terminal (not shown) of the origin detection signal detection flip-flop 103m1. Thereby, when the moving body moves in a direction different from the direction of origin detection, the Q signal of the flip-flop 103m1 for signal detection for origin detection is reset, and the sequence of origin detection is temporarily stopped. The same measures can be taken in other examples.
[0078]
By appropriately designing the synchronization circuit 103 shown in FIGS. 3A to 5 described above, it is possible to detect the origin having a predetermined detection width at a desired synchronization position in both forward and reverse displacements. It becomes.
[0079]
The position signals (a) and (c) and the position signals (b) and (d) have a phase difference of 90 °. Further, the position detection signals (a) and (b) which are analog signals and the origin detection signal (e) are the position detection signals (c) and (d) which are digital signals and the origin detection signal (f). Any type of signal can be used as long as the signal can be created. Further, the input from the detection system may be only a digital signal and may not include an analog signal. Further, when the position detection signal is digitized, the resolution may be further improved by phase division.
[0080]
Position detection is performed by inputting digital position detection signals (c) and (d) to a counter. In this case, when the origin signal (g) or (h) is generated, the origin of position detection can be obtained by resetting the counter or setting an appropriate preset value.
[0081]
As described above, in the present embodiment, the origin signal is output in accordance with the first synchronization position after the origin detection signal is detected. Therefore, all the synchronization positions are arranged within one cycle of the periodic signal.
[0082]
Also, depending on the origin detection method, it is possible to store a periodic signal for position detection near the origin and a signal for origin detection, and determine the synchronization position closest to the origin detection signal generation position as the origin. . In this case, the origin position can be accurately obtained by sending the displacement amount based on the determined position as a preset value to the controller or counter. In such an example, when a plurality of origin detection position candidates are arranged, all the detection position candidates are arranged in one cycle before and after the origin detection signal is generated.
[0083]
Next, an outline of detection of the synchronization position candidate and the optimum synchronization position will be described with reference to FIGS. The optimum synchronization position candidate is determined depending on which section has the point determined by the position signals (a) and (b) at the time of rising when the origin detection signal (f) is detected. Basically, for a plurality of divisions and a plurality of synchronization position candidates, the phase margins of all the synchronization position candidates are determined step by step for each division, and the synchronization position candidate having the most phase margin is regarded as the optimum. Output. In the present embodiment, the number of sections is 2, the number of synchronization position candidates is 2, and the phase margin is optimal when the phase difference is the largest when the phase difference is expressed from 0 ° to 180 °. As for the phase margin, when the phase difference is expressed from 0 ° to 180 °, a candidate close to 0 ° may be regarded as the optimum, as seen in cases other than real-time processing.
[0084]
The case of FIG. 2A will be described. The synchronization position candidates include a synchronization position 1 and a synchronization position 2 that are 180 degrees out of phase. If the point determined by the position signals (a) and (b) is (O1) that is included when the origin detection signal (f) rises, there is a phase difference of 90 ° or more with respect to the synchronization position 1. The phase is within 90 ° with respect to the synchronization position 2. Therefore, since the phase difference with respect to the synchronization position 1 is larger than that of the synchronization position 2, the synchronization position 1 is detected as the optimum synchronization position and used as a determination result. Similarly, when the point determined by the position signals (a) and (b) includes (O2) when the origin detection signal (f) rises, the synchronization position 2 is more than the synchronization position 1. Since the phase difference is large, the synchronization position 1 is detected as the optimum synchronization position and used as the determination result.
[0085]
Next, the case of FIG. 2B will be described. The synchronization position candidates include a synchronization position 1 and a synchronization position 2 that are 180 degrees out of phase. When the point determined by the position signals (a) and (b) includes (1) or (2) when the origin detection signal (f) rises, the position of 90 ° or more with respect to the synchronization position 1 Although there is a phase difference, the phase is within 90 ° with respect to the synchronization position 2. Therefore, since the phase difference with respect to the synchronization position 1 is larger than that of the synchronization position 2, the synchronization position 1 is detected as the optimum synchronization position and used as a determination result. Similarly, when the point that is determined by the position signals (a) and (b) includes (3) or (4) when the origin detection signal (f) rises, the synchronization position is greater than the synchronization position 1. Since the phase difference is larger than 2, the synchronization position 1 is detected as the optimum synchronization position and used as the determination result.
[0086]
Further, the case of FIG. 2C will be described. There are four synchronization position candidates from synchronization position 1 to synchronization position 4 every 90 ° phase. The synchronization position 1 and the synchronization position 2 are 180 degrees apart from each other on the vertical axis, and the synchronization position 3 and the synchronization position 4 are 180 degrees apart from each other on the horizontal axis. When the point determined by the position signals (a) and (b) is (O1) that is included when the origin detection signal (f) rises, the phase difference of 135 ° or more and 180 ° or less with respect to the synchronization position 3 However, there is no phase difference of 45 ° to 135 ° with respect to the synchronization position 1 and the synchronization position 2, and there is only a phase difference of 0 ° to 45 ° with respect to the synchronization position 4. Accordingly, since the phase difference is the largest with respect to the synchronization position 3 than the synchronization position 1, the synchronization position 2, and the synchronization position 4, the synchronization position 3 is detected as the optimum synchronization position, and the determination result is obtained. Similarly, when the segment included at the rising edge of the origin detection signal (f) is a point determined by the position signals (a) and (b) is (O2), the synchronization position 1 is (O3). In the case of (O4), the synchronization position 4 is detected as the optimum synchronization position, and the result is determined.
[0087]
Next, regarding the classification used for determining the optimum synchronization position candidate, the detection of the classification including points determined by the position signals (a) and (b) when the origin detection signal (f) is detected will be described with reference to FIGS. Will be described.
[0088]
In the specific example shown in FIG. 9, the division is performed by the following two determinations.
[0089]
Va> Vref (Formula 3)
Vb> Vref (Formula 4)
Here, when both Expression 3 and Expression 4 are true, the classification (1), when Expression 3 is false and Expression 4 is true, the classification (2), when both are false, the classification (3), and Expression 3 are true. Then, when the expression 4 is false, the division (4) is performed in four ways. In the actual circuit example shown in FIG. 9, the four position signals (c) and (d) binarized, the two NOT circuits 107D and 107E, and the four AND circuits 107F to 107I are used. The division determination signal is latched by the latch circuit 107m at the timing of detecting the origin detection signal, and the division in which the position signals (a) and (b) exist is determined by a signal that becomes a high level among the four signals. Therefore, the decision 1 corresponds to the category (1), the decision 2 corresponds to the category (4), the decision 3 corresponds to the category (2), and the decision 4 corresponds to the category (3).
[0090]
Further, in the specific example shown in FIG. 6, the division is performed by the determination of (Equation 4). When the expression 4 is true, the division (O1) is performed, and when the expression 4 is false, the classification (O2) is performed. In the actual circuit example shown in FIG. 6, two classification determination signals generated using the binarized position signal (d) and the NOT circuit 107D are sent to the latch circuit 107m at the timing of detecting the origin detection signal. The position signals (a) and (b) are determined based on the signal that becomes high level among the two signals. Accordingly, the determination O1 corresponds to the section (O1), and the determination O2 corresponds to the section (O2).
[0091]
In the specific example shown in FIG. 8, the division is performed by the following two determinations.
[0092]
Va> Vb (Formula 5)
Va + Vb> 2Vref (Formula 6)
Here, when both Expression 5 and Expression 6 are true, the classification (O1), when Expression 5 is false and Expression 6 is true, the classification (O2), when both are false, the classification (O3), and Expression 5 is true. When the expression 6 is false, the division (O4) is performed in four ways. In the actual circuit shown in FIG. 8, analog position signals (a) and (b), one operational amplifier, two comparators 107h and 107i, two resistors, and two NOT circuits 107p and 107r are provided. The four classification determination signals (p) to (q) generated using the AND circuits 107n, 107o, 107q, and 107s are latched by the latch circuit 107m at the timing of detecting the origin detection signal, and four signals (p) The section where the position signals (a) and (b) exist is determined based on the signal which becomes high level in .about. (S). Accordingly, the determination O1 corresponds to the section (O1), the determination O2 corresponds to the section (O2), the determination O3 corresponds to the section (O3), and the determination O4 corresponds to the section (O4).
[0093]
In the present embodiment, Va and Vb are handled with a common amplitude center and amplitude. However, when there is a difference in actual signals, the common amplitude center and amplitude are assumed to be common. When the signal is normalized and applied, or when only the amplitude center value is different between Va and Vb, instead of using the same reference signal Vref, the center value is individually set for Va and Vb. It shall be applied to Formula 3, Formula 4, Formula 5, and Formula 6 so that it may apply to the classification of (B) of 2 or (C) of FIG.
[0094]
Next, the determination logic and specific circuit details in the detection of the optimum synchronization position candidate will be described with reference to FIGS.
[0095]
In the specific examples of FIGS. 6 and 9, the synchronization position 1 is at the center phase of the region where the position signal (d), which is a binary signal of Vb, is at a low level, and the position signal (d) is at a high level at the synchronization position 2. Is set to the center phase of each region. When the origin detection signal (f) is detected, the synchronization position where the phase difference with the point where the position signals (a) and (b) exist is the optimum when the origin detection signal (f) is detected. A synchronization position included in a region having a level different from the level of the position signal (d) is optimal.
[0096]
In the specific example of FIG. 6, the region where the position signal (d) is at the low level includes the section (O2), and the region where the position signal (d) is at the high level includes the section (O1). Therefore, when the result of determination O1 is obtained, the synchronization position 1 is the optimum synchronization position. Further, in the determination O1, it can be seen that there is a phase margin of 90 ° or more in both the clockwise direction and the counterclockwise direction from the position at the time of detecting the origin signal to the synchronization position 1. Similarly, when the result of determination O2 is obtained, the synchronization position 2 is the optimum synchronization position. In the determination O2, it can be seen that there is a phase margin of 90 ° or more in both the clockwise direction and the counterclockwise direction from the position at the time of detecting the origin signal to the synchronization position 2. The above processing is realized by the circuit of FIG.
[0097]
In the specific example of FIG. 9, the synchronization position 1 is an area where the position signal (d), which is a binary signal of Vb, is in the center phase of the area where the level signal is low, and the synchronization position 2 is an area where the position signal (d) is the high level. Is set to the center phase of each. When the origin detection signal (f) is detected, the synchronization position where the phase difference with the point where the position signals (a) and (b) exist is the optimum when the origin detection signal (f) is detected. A synchronization position included in a region having a level different from the level of the position signal (d) is optimal.
[0098]
The region where the position signal (d) is at the low level includes divisions (3) and (4), and the region where the position signal (d) is at the high level includes divisions (1) and (2). It is. Therefore, although it is actually divided into four sections, the sections (1) and (2) are combined into one and the sections (3) and (4) are combined into one for determining the optimum synchronization position. Thus, it is efficient if it is determined as two sections. Further, the phase margin for each moving direction can be confirmed by a finer section.
[0099]
Therefore, when the result of determination 1 or determination 3 is obtained, the synchronization position 1 is the optimum synchronization position. Further, in the determination 1, there is a phase margin of 90 ° or more in the clockwise direction from the position at the time of detecting the origin signal to the synchronization position 1, and a phase margin of 180 ° or more in the counterclockwise direction, and in the determination 3, the phase margin is 180 in the clockwise direction. It can be seen that there is a phase margin of more than 90 ° and a phase margin of more than 90 ° counterclockwise. Similarly, when the result of determination 2 or determination 4 is obtained, the synchronization position 2 is the optimum synchronization position. Further, in the determination 2, there is a phase margin of 180 ° or more in the clockwise direction from the position at the time of detecting the origin signal to the synchronization position 2, and a phase margin of 90 ° or more in the counterclockwise direction. It can be seen that there is a phase margin of more than ° and a phase margin of 180 ° or more counterclockwise.
[0100]
The above processing is realized by the circuit of FIG.
[0101]
In the specific example of FIG. 8, the synchronization position 1 is the central phase of the section O4 where the expression 5 is true and the expression 6 is false, and the synchronization position 2 is the section O2 where the expression 5 is false and the expression 6 is the true area. The synchronization position 3 is at the center phase of the section O3 where both Expression 5 and Expression 6 are false areas, and the synchronization position 4 is at the center phase of the section O1 where both Expression 5 and Expression 6 are true areas. , Respectively. When detecting the origin detection signal (f), the synchronization position where the phase difference from the point where the position signals (a) and (b) exist is the optimum when the origin detection signal (f) is detected. The synchronization position that is farthest from the section, that is, included in the opposite section is optimal.
[0102]
Therefore, when the result of the determination O1 is obtained, the synchronization position 3 is the optimum synchronization position, and the phase is 90 ° or more in the clockwise direction and the counterclockwise direction from the position at the time of detecting the origin signal to the synchronization position 3. Afford. When the result of determination O2 is obtained, the synchronization position 1 is the optimum synchronization position, and there is a phase margin of 90 ° or more in the clockwise and counterclockwise directions from the position at the time of detecting the origin signal to the synchronization position 1. is there. When the result of determination O3 is obtained, the synchronization position 4 is the optimum synchronization position, and there is a phase margin of 90 ° or more in the clockwise and counterclockwise directions from the position at the time of detecting the origin signal to the synchronization position 4. is there. When the result of determination O4 is obtained, the synchronization position 2 is the optimum synchronization position, and there is a phase margin of 90 ° or more in the clockwise and counterclockwise directions from the position when the origin signal is detected to the synchronization position 2. is there.
[0103]
The above processing is realized by the circuit of FIG.
[0104]
Regarding the determination result of the optimum synchronization position candidate, signals such as output from determination 1 to determination 4 and determination O1 to determination O4 are output in parallel in this embodiment, but the encoded determination result is output. May be.
[0105]
Next, an outline of a method for determining the stability of the currently set synchronization position will be described with reference to FIGS.
[0106]
That is, in the present embodiment, the determination of the synchronization position stability is made depending on which section has the point determined by the position signals (a) and (b) at the rising point when the origin detection signal (f) is detected. I do. As a method of this determination, as in the above-described detection of the optimum synchronization position, the stability is higher as the phase difference between the section included in the origin detection signal (f) and the synchronization position is larger, and the phase difference is smaller. The stability is low.
[0107]
First, the case of FIG. 2A will be described. As for the case where the setting of the synchronization position is the synchronization position 1, the point determined by the position signals (a) and (b) when the classification included in the rising edge of the origin detection signal (f) is (S1). There is a phase margin of 90 ° around and 180 ° counterclockwise. When the segment is (S2), there is a phase margin of 180 ° clockwise and 90 ° counterclockwise. When the category is (S3), there is no phase margin of 270 ° clockwise and no phase margin counterclockwise. When the category is (S4), there is no phase margin clockwise and there is a phase margin of 270 ° counterclockwise. From the above, there are two levels of stability. With respect to the synchronization position 1, the sections (S1) and (S2) have high stability, and the sections (S3) and (S4) have low stability. Similarly, with respect to the synchronization position 2, the sections (S3) and (S4) have high stability, and the sections (S1) and (S2) have low stability.
[0108]
However, if the criteria for determining that the absolute value of the phase difference is large is stable, and there are unique conditions such as when the change in phase difference occurs in one direction, the phase margin is stable according to those conditions. A degree criterion should be used.
[0109]
Further, in the case of FIG. 2B, the sections (S1) to (S4) may be replaced with the sections (1) to (4) in the description of FIG.
[0110]
Next, the case of FIG. 2C will be described. As for the case where the setting of the synchronization position is the synchronization position 1, the point determined by the position signals (a) and (b) when the classification included in the rising edge of the origin detection signal (f) is (S1). There is a phase margin of 90 ° around and 225 ° counterclockwise. When the segment is (S2), there is a phase margin of 180 ° clockwise and 135 ° counterclockwise. When the section is (S3), there is a phase margin of 180 ° clockwise and 135 ° counterclockwise. When the division is (S4), there is a phase margin of 225 ° clockwise and 90 ° counterclockwise. When the segment is (S5), there is a phase margin of 270 ° clockwise and 45 ° counterclockwise. When the classification is (S6), there is a phase margin of 315 ° clockwise, and there is no phase margin counterclockwise. When the category is (S7), there is no phase margin clockwise and there is a phase margin of 315 ° counterclockwise. When the division is (S8), there is a phase margin of 45 ° clockwise and 270 ° counterclockwise. From the above, there are four levels of stability. With respect to the synchronization position 1, the sections (S2) and (S3) have the highest stability, and the sections (S1) and (S4) have the stability. The second highest, sections (S5) and (S8) have the third highest stability, and sections (S6) and (S7) have the lowest stability.
[0111]
Similarly, with respect to the synchronization position 2, the sections (S6) and (S7) have the highest stability, the sections (S5) and (S8) have the second highest stability, and the sections (S1) and (S4). ) Has the third highest degree of stability, and sections (S2) and (S3) have the lowest degree of stability. For synchronization position 3, sections (S1) and (S8) have the highest stability, sections (S2) and (S7) have the second highest stability, and sections (S3) and (S6) Stability is the third highest, and sections (S4) and (S5) have the lowest stability. For the synchronization position 4, the sections (S4) and (S5) have the highest stability, the sections (S3) and (S6) have the second highest stability, and the sections (S2) and (S7). ) Has the third highest degree of stability, and sections (S1) and (S8) have the lowest degree of stability.
[0112]
Depending on the purpose, the combination of the first and second stability levels or the combination of the second and third stability levels may be divided into one stability group to provide three stability levels as a whole. Is also possible.
[0113]
Next, regarding the classification used for determining the stability, detection of a classification including a point determined by the position signals (a) and (b) when the origin detection signal (f) is detected will be described. This is basically the same procedure as that in the detection of the optimum synchronization position. This embodiment will be described with reference to FIGS.
[0114]
In the specific examples of FIGS. 6 and 9, the division is performed by the same method as that for detecting the optimum synchronization position in the configuration shown in FIG. That is, if both formula 3 and formula 4 are true, the section (S1) or section (1), if formula 3 is false and the formula 4 is true, section (S2) or section (2), both are false When the section (S3) or the section (3) is true and the expression 3 is true and the expression 4 is false, the section (S4) or the section (4) is divided into four ways. In an actual circuit example, as shown in FIGS. 6 and 9, binarized position signals (c) and (d), two NOT circuits 107D and 107E, and four AND circuits 107F to 107I are provided. Use this to generate the segment detection signal, and determine the segment where the position signals (a) and (b) exist based on the high level signal at the timing of detecting the origin detection signal among the four signals input to the latch circuit 107m. To do.
[0115]
Further, in the example of FIG. 8, the division is performed by four determinations of Expression 3, Expression 4, Expression 5, and Expression 6. That is, the classification (S1) is performed when all of the expressions 3, 4, 5, and 6 are true, and the classification is performed when the expression 3 is true, the expression 4 is true, the expression 5 is false, and the expression 6 is true (S2 ), When the expression 3 is false, the expression 4 is true, the expression 5 is false, and the expression 6 is true (S3), the expression 3 is false, the expression 4 is true, the expression 5 is false, and the expression 6 is false (S4), when all of Formula 3, Formula 4, Formula 5, and Formula 6 are false. When the formula 3 is false, Formula 4 is false, Formula 5 is true, and Formula 6 is false. (S6), if the expression 3 is true, the expression 4 is false, the expression 5 is true, and the expression 6 is false (S7), the expression 3 is true, the expression 4 is false, the expression 5 is true, and the expression 6 If is true, the division (S8) is performed in eight ways. In an actual circuit, as shown in FIG. 8, four signals (p) to (q) generated when the optimum synchronization position is divided, and further binarized position signals (c) and (d). And two NOT circuits 107y and 107A and eight AND circuits 107t to 107x, 107z, 107B, and 107C are used to generate eight division detection signals, which are latched by the latch circuit 107m at the timing of detecting the origin detection signal. Then, the section where the position signals (a) and (b) exist is detected by a signal that becomes a high level among the eight signals.
[0116]
Next, with reference to FIG. 6 to FIG. 8, the determination logic and specific circuit details for the current synchronization phase stability determination will be described.
[0117]
In the specific examples of FIGS. 6 and 9, the synchronization position 1 is at the center phase of the region where the position signal (d), which is a binary signal of Vb, is at a low level, and the position signal (d) is at a high level at the synchronization position 2. Is set to the center phase of the region. The detection of the origin detection signal (f) is performed because it is determined that the larger the phase difference between the position where the position signals (a) and (b) exist and the current synchronization position is larger when the origin detection signal (f) is detected. Sometimes it is stable if the synchronization position is included in a region of a level different from the level of the position signal (d), and unstable if it is included in the same region. The region where the position signal (d) is low level includes the division (S3) or (3) and the division (S4) or (4), and the region where the position signal (d) is high level is the division (S1 ) Or (1) and section (S2) or (2). Therefore, although it is actually divided into four categories, for the determination of stability, the categories (S1) and (S2) or (1) and (2) are combined into one, and the categories (S3) and (S4 ) Or (3) and (4) are combined into one, and it is efficient if they are determined as two sections. Further, the phase margin for each moving direction can be confirmed by a finer section.
[0118]
First, a case where the synchronization position 1 is the current synchronization position will be described. When the result of determination S1 or determination S3 is obtained, or when the result of determination 1 or determination 3 is obtained, it is stable. In judgment S1 or judgment 1, there is a phase margin of 90 ° or more in the clockwise direction from the position at the time of detecting the origin signal to the synchronization position 1, and a phase margin of 180 ° or more in the counterclockwise direction. It can be seen that there is a phase margin of 180 ° or more in the rotation direction and a phase margin of 90 ° or more in the counterclockwise direction. When the result of determination S2 or determination S4 is obtained, or when the result of determination 2 or determination 4 is obtained, it is unstable. In judgment S2 or judgment 2, there is a phase margin of 90 ° or less in the clockwise direction and a phase margin of 270 ° or more in the counterclockwise direction from the position at the time of detecting the origin signal to the synchronization position 1, and in judgment S4 or judgment 4, It can be seen that there is a phase margin of 270 ° or more in the rotation direction and a phase margin of 90 ° or less in the counterclockwise direction.
[0119]
Next, the case where the synchronization position 2 is the current synchronization position will be described. When the result of determination S1 or determination S3 is obtained, or when the result of determination 1 or determination 3 is obtained, it is unstable. In judgment S1 or judgment 1, there is a phase margin of 270 ° or more in the clockwise direction and a phase margin of 90 ° or less in the counterclockwise direction from the position at the time of detecting the origin signal to the synchronization position 1, and in judgment S3 or judgment 3, It can be seen that there is a phase margin of 90 ° or less in the rotation direction and a phase margin of 270 ° or more in the counterclockwise direction. When the result of determination S2 or determination S4 is obtained, or when the result of determination 2 or determination 4 is obtained, it is stable. In judgment S2 or judgment 2, there is a phase margin of 180 ° or more in the clockwise direction and a phase margin of 90 ° or more in the counterclockwise direction from the position at the time of detecting the origin signal to the synchronization position 1, and in judgment S4 or judgment 4, It can be seen that there is a phase margin of 90 ° or more in the rotation direction and a phase margin of 180 ° or more in the counterclockwise direction.
[0120]
The above processing is processed and output by the determination circuit 107 having the configuration shown in FIGS.
[0121]
In the specific example of FIG. 8, the synchronization position 1 is the central phase of the section O4 where the expression 5 is true and the expression 6 is false, and the synchronization position 2 is the section O2 where the expression 5 is false and the expression 6 is the true area. The synchronization position 3 is at the center phase of the section O3 where both Expression 5 and Expression 6 are false areas, and the synchronization position 4 is at the center phase of the section O1 where both Expression 5 and Expression 6 are true areas. , Respectively. When detecting the origin detection signal (f), the synchronization position where the phase difference from the point where the position signals (a) and (b) exist is the optimum when the origin detection signal (f) is detected. The synchronization position that is farthest from the section, that is, included in the opposite section is optimal. As can be seen from FIG. 8, the section O1 includes sections S1 and S8, the section O2 includes sections S2 and S3, the section O3 includes sections S4 and S5, and the section O4 includes sections S6 and S7.
[0122]
The stability level classification in this example can be divided into a maximum of four levels for a specific synchronization position. Because there are 8 sections, there are 4 sections in the clockwise and counterclockwise directions as viewed from a specific synchronization position, and 4 sections can be obtained by combining the sections in the symmetric positions into one. This is because it is divided into groups. Accordingly, there are four phase margins from the synchronization position: Level 1) 135 ° to 180 °, Level 2) 90 ° to 135 °, Level 3) 45 ° to 90 °, Level 4) 0 ° to 45 °. Divided. Furthermore, these levels can be combined into two or three levels by combining adjacent levels. In the following description, the case where the level is divided into four levels will be described. However, in actual application, two or three levels may be used.
[0123]
First, a case where the synchronization position 1 is the current synchronization position will be described. Level 1 when the result of determination S2 or determination S3 is obtained, level 2 when the result of determination S1 or determination S4 is obtained, level 3 when the result of determination S5 or determination S8 is obtained, level 3, determination S6 Alternatively, the level is 4 when the result of determination S7 is obtained. When the synchronization position 2 is the current synchronization position, the level 1 is obtained when the result of the determination S6 or the determination S7 is obtained, and the level 2, the determination S1 or the determination is obtained when the result of the determination S5 or the determination S8 is obtained. Level 3 when the result of S4 is obtained, and level 4 when the result of judgment S2 or judgment S3 is obtained. When the synchronization position 3 is the current synchronization position, the level 1 is obtained when the result of the determination S1 or the determination S8 is obtained, and the level 2, the determination S3 or the determination S6 is obtained when the result of the determination S2 or the determination S7 is obtained. Level 3 when the result is obtained, and level 4 when the result of judgment S4 or judgment S5 is obtained. When the synchronization position 4 is the current synchronization position, the level 1 is obtained when the result of the determination S4 or the determination S5 is obtained, and the level 2, the determination S2 or the determination is obtained when the result of the determination S3 or the determination S6 is obtained. Level 3 is obtained when the result of S7 is obtained, and level 4 is obtained when the result of judgment S1 or judgment S8 is obtained.
[0124]
Furthermore, it is possible to obtain information on the phase margin in the clockwise direction and the counterclockwise direction by the determination at each synchronization phase.
[0125]
The above processing is performed by the determination circuit 107 having the configuration shown in FIG. 8, and a stability determination result is output. Regarding the output of the stability determination, only the level determination result such as level 1 to level 4 may be output. Further, the signals from the determination 1 to the determination 4 and the determination S1 to the determination S8 may be output together with the information indicating the current synchronization position. In this case, the information on the current synchronization position is not necessarily output from the determination circuit 107 but may be output from the switch 104 or may not be output when the outside has setting information.
[0126]
Note that the detection position of the signal obtained by binarizing the origin detection signal is basically different for each detection direction. For this reason, if the moving direction of the moving object does not match the origin detection direction, the judgment result regarding the optimal synchronization position and the stability of the current origin detection position is likely to be meaningless. Can become a source of confusion. Therefore, it may be desirable not to output a determination result when the moving direction of the moving body does not match the origin detection direction.
[0127]
Further, if the moving object is moving in the predetermined origin detection direction, the determination result may be incorrect.
[0128]
In order to deal with the above two problems, a method of not outputting a determination result when the moving direction of the moving body does not coincide with the origin detection direction or when it is reversed halfway will be described with reference to the examples of FIGS. To do.
[0129]
In the configuration of this embodiment, the circuits shown in FIGS. 3B to 5 are used for origin detection. In these circuits, it can be confirmed from the output level of the flip-flop 103m2 constituting the direction determination circuit or the level change that the direction is not a predetermined origin detection direction or inversion in the middle. When the direction is not the predetermined origin detection direction or when it is inverted halfway, the origin detection signal (f) input to the determination circuit 107 is masked by the output signal of the direction determination flip-flop 103m2, or the direction determination flip-flop The output signal of the block 103m2 is input to the determination circuit 107, and the output of the determination result is masked and suppressed.
[0130]
By such a method, the detection of the optimum synchronization position and the current stability determination sequence of the origin position are temporarily stopped or the output is stopped. In addition to the method described here, other methods may be used as long as the above object can be achieved.
[0131]
Next, how to use the determination result about the stability of the optimum synchronization position and the current origin detection position as described above will be described.
[0132]
The determination result is stored in a storage device (not shown) in the determination circuit 107 or output to the outside. Examples of the external output destination include the display 108, the switch 104, and the outside through an interface. In the present embodiment, the determination circuit that detects the optimum synchronization position and the stability determination of the current origin detection position is shared, but the determination circuit is separately arranged and the setting is switched. In some cases, setting information may be exchanged between the determination circuits.
[0133]
The display 108 as the output destination of the determination result may be any type of display as long as the result can be displayed. For example, it has a plurality of LEDs, and the LED corresponding to the optimum synchronization position and the LED indicating the stability of the current synchronization position are turned on / flashing / turned off when the origin is detected, and not only the stability but also the phase The LED corresponding to the relationship can be lit, blinked, or lit. The display output timing of the display unit 108 affects the origin detection process and the determination process even at the time of determination, at the time when there is a request from the outside, or just before the determination is made upon detection of the signal for detecting the origin. It does not matter if it is set within the range not given.
[0134]
In addition, the timing at which the switch 104 switches the synchronization position candidate is similarly received immediately after receiving the origin position switching setting, at the time of determination, when there is a request from the outside, or detection of the origin detection signal. Even before the determination is made, it may be set within a range that does not affect the origin detection process or the determination process.
[0135]
Switching of the synchronization timing is performed by the switch 104. However, the switch 104 may be switched manually, or may be switched by collecting information by the switch 104 even when switched by an external setting command. . When the switch 104 collects information, a request signal for setting information may be output to the determination circuit 107, the storage device, or the outside as necessary. Further, the switching is not necessarily performed when the current synchronization position setting is different from the optimum synchronization position or when the stability of the current synchronization position is low. Since the switching of the synchronization position leads to the change of the origin position, it is possible to set whether to enable the switching as necessary. As for the switched setting, in the case of switching during origin signal detection, it is necessary to set whether to apply to the current detection or to apply from the next detection, and switching means may be provided if necessary. Is possible.
[0136]
In outputting the determination result, an abnormal signal or a warning signal can be generated according to the result. For example, when the optimal synchronization position determination result is different from the current synchronization position, the stability of the current synchronization position is below a certain level, or the recorded stability change satisfies a specific condition The necessity of maintenance can be communicated by an abnormal signal or warning signal.
[0137]
Next, the detection flow of the optimum synchronization position will be described using (A) and (B) of FIG.
[0138]
In the example of FIG. 11A, first, it is detected whether or not an origin detection signal has been generated (step S11). If the generation of the origin detection signal is detected, the determination circuit 107 detects the optimum synchronization position candidate (step S12) and outputs the determination result (step S13). Thereafter, it is determined whether or not the setting is to reflect the determination result (step S14). If not, the optimal synchronization position detection flow is terminated. On the other hand, when reflecting the determination result, the setting of the synchronization position is switched (step S15), and the detection flow of the optimum synchronization position is ended.
[0139]
In the example of FIG. 11B, first, it is detected whether or not an origin detection signal has been generated (step S11). If the generation of the origin detection signal is detected, the determination circuit 107 detects the optimum synchronization position candidate (step S12) and outputs the determination result (step S13). Thereafter, in order to reflect this determination result, the setting of the synchronization position is switched (step S15), and the detection flow of the optimum synchronization position is ended. Of course, the reflection of the determination result may not be reset when the reflection content and the current setting are the same.
[0140]
The flow shown in FIGS. 11A and 11B is a flow for detecting the optimum synchronization position. However, the synchronization position may be replaced with the origin detection position to obtain the optimum origin position detection flow.
[0141]
The current synchronization position stability determination flow will be described with reference to FIGS.
[0142]
In the example of FIG. 12A, first, it is detected whether or not an origin detection signal has been generated (step S21). If the generation of the origin detection signal is detected, the determination circuit 107 determines the stability of the current synchronization position (step S22) and outputs the determination result (step S23). Thereafter, it is determined whether or not the setting is to reflect the determination result (step S24), and if it is not to be reflected, the current synchronization position stability determination flow is terminated. On the other hand, when reflecting the determination result, the setting of the synchronization position is switched (step S25), and then the current synchronization position stability determination flow is terminated. In addition, about the reflection of a determination result, when the reflection content and the present setting are the same, it is also possible not to reset.
[0143]
In the example of FIG. 12B, first, it is detected whether or not an origin detection signal has been generated (step S21). If the generation of the origin detection signal is detected, the determination circuit 107 determines the stability of the current synchronization position (step S22), and outputs the determination result (step S23). The position stability determination flow ends.
[0144]
In the example of FIG. 12A, the setting of the synchronization position is switched in step S24. In the example of FIG. 12B, the process ends in step S23, but this is applied to a configuration in which there is no selection means. Including this case, it is possible to replace this step with the step of adjusting the origin detection signal generation timing or the origin detection position, or to add this step.
[0145]
The flow shown in FIGS. 12A and 12B is a flow for determining the stability of the current synchronization phase, but replacing the synchronization position with the origin detection position to determine the stability of the current origin position. It does not matter as the flow.
[0146]
[effect]
According to this embodiment, when synchronizing the origin signal with the position detection signal, it is possible to select the synchronization position according to the position (phase) of the position detection signal when the origin detection signal is detected. . Therefore, the origin detection position that can be caused by unstable factors such as signal noise and wobbling, and the stability of the light source in the optical encoder, temperature characteristics and variations of the light emitting / receiving elements, and deviations from the design of the individual encoder It is possible to select a synchronization position that minimizes the occurrence of deviation.
[0147]
In order to synchronize the origin signal with the position detection signal, it has a determination circuit that determines which of the multiple synchronization positions is the best, and the best synchronization position is determined with the encoder actually attached to the device. You can choose. In the present embodiment, it is possible to improve the stability against fluctuation and the like by selecting the synchronization position with the larger phase margin. This increases the stability of origin detection synchronized with the position signal, and takes into account the effects of variations in relative position and orientation, such as the mounting angle and gap between the head and scale when mounting the encoder, and adjustments. The work of performing can be omitted. In other words, it is not necessary to set and process the phase difference between the position detection signal and the origin signal strictly in design and production, leading to reduction in production cost and assembly adjustment time, and reduction in design and production constraints. There is an advantage that the degree of freedom in function can be increased.
[0148]
For setting multiple synchronization position candidates, when a Lissajous waveform of two periodic signals with a phase difference of 90 ° is divided into two sections along an arbitrary straight line passing through the amplitude center, origin signals are generated in both sections. It is set to include one or more phase candidates. In such a setting, there is always a synchronization position candidate having a phase margin of ± 90 ° or more from the position at the time of generation of an arbitrary origin detection signal. By selecting a synchronization position candidate that satisfies this condition, the synchronization position and the origin are selected. A phase margin of ± 90 ° or more can be provided between the phases when the detection signal is generated, and stable origin detection is possible.
[0149]
Further, since the origin signal generation position candidates are arranged within one cycle of the periodic signal, the position difference between the origin signal generation position candidates can be minimized. This has the effect of minimizing fluctuations in the origin position when the origin position is switched. Similarly, as described in the explanation of the operation, the periodic signal for position detection near the origin and the signal for origin detection are memorized, and the synchronization position closest to the origin detection signal generation position is determined as the origin. In this method, the detection position candidates are arranged within a total of two periods before and after the origin detection signal is generated, and the origin position when the origin position is switched according to the present embodiment. It has the effect of suppressing fluctuations.
[0150]
In the present embodiment, the optimum synchronization position is detected with the largest phase difference between the segment on the Lissajous waveform where two position detection signals having a phase difference of 90 ° exist and the synchronization position candidate when the origin detection signal is generated. This is done by selecting a candidate. Similarly, the determination of the stability of the current synchronization position is based on the magnitude of the phase difference between the segment on the Lissajous waveform where two position detection signals having a phase difference of 90 ° exist when the origin detection signal is generated and the current synchronization position. This is done by dividing the level based on this.
[0151]
By introducing the concept of division, it is no longer necessary to directly calculate the position of the point on the Lissajous waveform where the signal for position detection exists in calculating the phase margin, and the processing is simplified. Yes. As for the number of divisions, two or more numbers such as 2, 4, 8 can be set. Although detailed determination is possible by increasing the number of classifications, it can be a burden in terms of processing capacity, circuit size, and cost. By setting an appropriate section suitable for the system, the origin detection function synchronized with the position detection signal can realize a highly stable, compact and inexpensive encoder.
[0152]
Further, as in the example of the four sections in FIG. 2B, when the phase margin of each section varies depending on the moving direction, the phase variation at the time of detecting the origin detection signal drifts with time. In particular, this is effective when the determination should be made paying attention to the phase margin in one direction. In addition, as shown in FIG. 2C, when the number of sections is increased in the determination of the stability of the current synchronization position rather than the determination of the optimal synchronization position, the details of the change in the phase margin can be confirmed, Furthermore, it is suitable for recording changes over time.
[0153]
Although it has been described that the processing can be simplified by the introduction of the classification, this leads to simplification of the determination, further simplifies the specific circuit configuration and arithmetic processing, and facilitates the implementation. For example, when providing two synchronization positions that are 180 degrees apart and two sections consisting of a 180-degree semicircle, each section may have a phase difference of 90 degrees or more with respect to either synchronization position candidate. Suppose that At this time, a phase difference of 90 ° or more can be obtained by selecting an appropriate synchronization position candidate regardless of the section including the point determined by the position signals (a) and (b) at the time of detecting the origin detection signal. Is obtained. By arranging the two synchronization positions on the vertical axis or the horizontal axis in FIGS. 2B and 2C, the binarization position at the time of detection of the origin detection signal (f) and the synchronization position The optimum synchronization position can be easily detected only by using two sections, two synchronization positions, and a simple determination criterion of selecting synchronization positions having different signal levels, and highly accurate and stable origin detection is possible. Furthermore, this determination criterion can be easily applied to a circuit using a flip-flop, or an FPGA or CPU capable of performing equivalent processing.
[0154]
In the present embodiment, as shown in FIG. 2B, even when the two sections of the 180 ° semicircle are divided so as to be further subdivided, it is assumed that there are only two sections. By doing so, the same determination process is possible. In addition, the phase margin can be finely confirmed for each moving direction by finely dividing. Even when the number of divisions is 4, the determination of the division can be made easily by using an AND circuit and a NOT circuit, and even when the number of divisions is 8, the division can be easily made by using about one or two comparators, operational amplifiers and resistors. Is possible. Therefore, it is possible to obtain a detailed determination result using a fine division for a simple circuit.
[0155]
Furthermore, the judgment result display section can be realized with several LEDs or a 7-digit number display with several digits, and the stability of the origin detection synchronized with the position signal is reduced although the burden of adding it is light. Securement and stability judgment can be easily realized.
[0156]
In this embodiment, an auxiliary signal generating member for detecting the origin is not provided except for the signal processing circuit unit. Therefore, it is possible to supply a small and inexpensive encoder that can stably detect the origin.
[0157]
In the present embodiment, the origin can be detected only when the displacement is made in a certain direction. As a result, there are advantages such as being less susceptible to the backlash of the movable part and leading to the need to avoid double origin detection at the time of origin detection, making it possible to perform origin detection with high accuracy and ease of use. .
[0158]
Furthermore, the behavior of the system can be confirmed from the determination results that are sequentially stored in the memory over time. For example, in the classification shown in FIG. 2A, the transition from one classification result to the next classification result may occur due to slight fluctuations in the configuration of the movable body or the detection system, and even if it is acceptable. It can be determined that there is a problem if the result fluctuates more than a certain value or a different result is obtained for each measurement. In addition, if the origin position does not need to fluctuate after the origin is found, it is possible to search for the origin at the start-up of the system, for example, and to select the optimum synchronization position every time. Self-adjustment is possible for fluctuations.
[0159]
(Second Embodiment)
[Constitution]
Next, a second embodiment of the present invention will be described. The main configuration of the encoder according to the present embodiment is not particularly limited as long as the position detection signal and the origin detection signal can be obtained except for the signal processing circuit unit 6 as in the first embodiment. For example, a general configuration such as the optical configuration shown in FIG. 24 may be used as the configuration of the main part of the first embodiment described above. In the example of FIG. 24, an optical encoder is used, but other types of encoders and displacement sensors such as a magnetic type and an electrostatic type may be used as long as they have a position signal and an origin signal corresponding to the amount of displacement. Good.
[0160]
The configuration of the signal processing circuit unit 6 in the second embodiment is as shown in FIG. That is, the signal processing circuit unit 6 according to the second embodiment divides the phase difference based on the analog position signals (a) and (b) having a phase difference of 90 ° to obtain N sine wave signals (k1). ˜ (kN) to output the phase dividing circuit 110, and N digital signals (p1) to (pN) are generated from these N sine wave signals (k1) to (kN) and the reference signal (j) 2 Based on these N digital signals (p1) to (pN), a value generation circuit 101, a pulse generation circuit 111 that generates pulse signals (da) and (db) corresponding to the displacement of the moving body, and origin detection A binarization circuit 102 that binarizes the signal (e) at a predetermined slice level and converts it to a digital origin detection signal (f), a latch circuit 106 that latches the digital origin detection signal (f), and is latched Position the digital origin detection signal (f) The synchronizing circuit 103 that generates the origin signal (g) in synchronization with one of the N digital signals (p1) to (pN), the switch 104 that switches the timing of synchronization, the detection of the optimum synchronization position and the current It comprises a determination circuit 107 that determines the stability of the synchronization position, and a display 108 that displays the determination result.
[0161]
Here, the N sine wave signals (k1) to (kN) are obtained when the sine wave signal (k1) is equal to the position signal (b) and the position signal (b), that is, the sine wave signal (k1) is sin θ. The sine wave signal (ki), where i = 1 to N, is expressed as follows.
[0162]
(Ki) = sin [θ-360 ° / N · (i−1)] (Expression 7)
The N sine wave signals (k1) to (kN) are generated by the phase division circuit 110 in the present embodiment. If a signal satisfying (Equation 7) is obtained, its configuration and Any method can be used. For example, an inverted signal of two 90 ° phase difference signals may be obtained by an inverting amplifier, or a multiphase signal of about 3 to 8 phases may be generated by adding and subtracting these signals. In addition, a signal such as a three-phase signal having an original 120 ° phase difference interval may be directly input.
[0163]
The reference signal (j) is a reference signal that is the amplitude center level of the position signal (a) and the position signal (b), and is used in the phase division circuit 110 and the binarization circuit 101.
[0164]
The division of the Lissajous figure of the origin signal generation position candidate and the analog position signals (a) and (b) will be described with reference to FIG. N positions (phases) of origin signal generation position candidates on the Lissajous circle are (360 ° / N) with respect to the period of the position signals (a) and (b), with the synchronization position 1 as the + side on the horizontal axis. ) Are arranged in phase difference. In addition, there are N sections divided by the phases of the N origin signal generation position candidates for detection of the optimum synchronization position and determination of the stability of the current synchronization position, as shown in FIG. Numbers (1) to (N) are assigned counterclockwise from the axis + side.
[0165]
The binarization circuit 101 in the signal processing circuit unit 6 has the configuration shown in FIG. That is, the position signals (k1) to (kN) are compared with the reference signal (j) by the comparators 101a1 to 101aN to generate binarized signals (d1) to (dN). Further, the XOR circuits 101b1 to 101bN take the exclusive OR (XOR) of the adjacent binarized signals (di) and (di + 1) (where i = 1 to N). Here, when i = N, the exclusive OR of the binarized signals (dN) and (d1) is assumed. The AND circuit 101c1 to 101cN obtains the logical product (AND) of the exclusive OR result and the binarized signal (di) as a signal (pi) (where i = 1 to N). To do.
[0166]
The synchronization circuit 103 in the signal processing circuit unit 6 has the configuration shown in FIGS. Here, FIG. 16B is a diagram showing a specific example of the detection circuit 103n shown in FIG. 16A for generating the origin signal synchronized with the position signal. The two circuits of the origin detection signal detection circuit and the direction determination circuit in this specific example use a flip-flop such as a DC trigger type LS423.
[0167]
In the specific example shown in FIG. 16B, the origin detection signal that outputs the value of the latched origin detection signal (f) at the rise of the position signal (pi) (where i = 1 to N). Latched by the flip-flop 103n1 constituting the detection circuit, the flip-flop 103n2 constituting the direction discrimination circuit for detecting the counterclockwise displacement on the Lissajous circle, and the AND circuit 103n3 taking the logical product of these outputs A detection circuit 103n for detecting that the origin detection signal (f) is at the high level and is at the set synchronization position is configured. That is, the origin detection signal (f) latched by the latch circuit 106 is input to the data D of the flip-flop 103n1, the position signal (pi) is input to the clock CLK, and the Q output is input to the AND circuit 103n3. ing. The position signal (p2) is input to the data D of the flip-flop 103n2, the position signal (p1) is input to the clock CLK, and the Q-bar output is input to the AND circuit 103n3.
[0168]
The determination circuit 107 has the configuration shown in FIG. That is, in FIG. 17, the position signals (p1) to (pN), the latched origin detection signal (f), and the current origin position designation are used as input signals. Part 107J. Here, the latch circuit 107m latches the position signals (p1) to (pN) at the rising edge of the latched origin detection signal (f). The outputs of the latch circuit 107m are detected as the optimum synchronization position detection results (1) to (N). The stability determination unit 107J receives the determination results (1) to (N) and the current origin position designation information, and outputs the current synchronization position stability determination result.
[0169]
These current origin position designation states and determination results are stored in the signal processing circuit unit 6 and not shown in the memory, the switch 104 or the memory not shown in the judgment circuit 107, or the signal The data is stored in one of the external storage devices connected to the outside of the processing circuit unit 6 or in a plurality of them. Such a storage device is composed of a logic array, a CPU, and the like for processing of determination results and input / output as necessary, with a storage medium as a center. The storage unit stores the determination result from the determination circuit 107 and outputs the determination result to the outside or sends the determination result to the switch 104 to switch to the synchronization position determined to be optimal. The storage device is preferably a non-volatile storage medium such as SRAM or FLASH ROM that maintains information even when the power is turned off.
[0170]
[Action]
The signal processing circuit unit 6 in the present embodiment will explain the processing when the input from the photodetector 5 as shown in FIG. 24 is processed with reference to part of the time charts shown in FIGS. . FIG. 9 shows a state of displacement in the counterclockwise direction on the Lissajous circle, and FIG. 10 shows a state of displacement in the clockwise direction on the Lissajous circle.
[0171]
That is, the phase dividing circuit 110 divides the two analog position signals (a) and (b) having a 90 ° phase difference of the encoder that periodically changes with displacement (relative movement of the scale 4). , N position signals (k1) to (kN) are obtained. These position signals (k1) to (kN) are digitized by the binarization circuit 101 to obtain digital signals (p1) to (pN). Further, the binarization circuit 102 binarizes the origin detection signal (e) at a predetermined slice level, thereby obtaining a digital origin detection signal (f). The latch circuit 106 detects the rising edge of the digital origin detection signal (f) and sets the latch signal (i) to the high level.
[0172]
In a region where the latch signal (i) is at a high level, the synchronization circuit 103 generates an origin signal as follows. That is, after the latch signal (i) is generated, the position signal (pi) (where i = 1 to N) is set to the high level in synchronization with the first rising edge, and the position signal (pi) is set to the low level in synchronization with the falling edge. The origin signal (g) to be generated is generated. A desired origin signal (g) is obtained by selecting one of N detection positions by switching the value of i from 1 to N.
[0173]
In the example of FIG. 16A, the position signals (p1) to (pN) and the latched origin detection signal (f), that is, the latch signal (i) are input, and the origin detection signal (f) This is a circuit for generating an origin signal at a synchronization position set after the high level. Note that the synchronization circuit 103 is not necessarily limited to the configuration of this embodiment. For example, the direction discrimination function can be realized based on an input signal, but the direction discrimination function is not always included.
[0174]
FIG. 16B shows a circuit configuration for detecting the origin when the Lissajous circle is displaced in the counterclockwise direction.
[0175]
First, the direction determination will be described. The position signal (p2) is input to the data D of the flip-flop 103n2, and the position signal (p1) is input to the clock CLK. As a result, the signal output from the Q-bar output of the flip-flop 103n2 is updated as an inverted signal of the position signal (p2) every time the position signal (p1) rises. Therefore, since the Q bar output of the flip-flop 103n2 becomes high level only when the position signal (p2) is low level when the position signal (p1) rises, the direction can be determined.
[0176]
As for the circuit for detecting the origin detection signal, the latch signal (i) is input to the data D of the flip-flop 103n1, and the position signal (pi) is input to the clock CLK. As a result, the signal output from the Q output of the flip-flop 103n1 is updated as the latch signal (i) every time the position signal (pi) rises. As a result, it is possible to output the origin detection signal synchronized with the rising timing of the position signal (pi) after the origin detection signal is detected.
[0177]
Then, the AND circuit 103n3 takes the logical product of these direction determination signals and the origin detection signal synchronized to generate the origin signal (g) shown in FIG. 9 with a predetermined detection direction and timing. It becomes. On the other hand, in the case of displacement in the reverse direction, the origin signal is not detected as shown by the signal (g) in FIG.
[0178]
Position detection is performed by inputting pulse signals (da) and (db) generated by the pulse generation circuit 111 to a counter (not shown). By resetting this counter when the origin signal (g) is generated or by setting an appropriate preset value, the origin of position detection can be obtained.
[0179]
Next, the detection of the synchronization position candidate and the optimum synchronization position will be described with reference to FIG. The optimum synchronization position is detected depending on which section has the point determined by the position signals (a) and (b) at the time of rising when the origin detection signal (f) is detected.
[0180]
Basically, for a plurality of divisions and a plurality of synchronization position candidates, the phase margins of all the synchronization position candidates are determined step by step for each division, and the synchronization position candidate having the most phase margin is regarded as the optimum. Output. In the present embodiment, the number of sections is 2, the number of synchronization position candidates is 2, and the phase margin is optimal when the phase difference is the largest when the phase difference is expressed from 0 ° to 180 °. As for the phase margin, when the phase difference is expressed from 0 ° to 180 °, a candidate close to 0 ° may be regarded as the optimum, as seen in cases other than real-time processing.
[0181]
In FIG. 17, there are N synchronization position candidates from synchronization position 1 to synchronization position N every (360 ° / N) phase. The case where the point determined by the position signals (a) and (b) is included in the rising edge of the origin detection signal (f) is (i) will be described separately when N is an even number and an odd number.
[0182]
When N is an even number, j = [(i + N / 2) mod N], and the phase difference between the synchronization position j and the synchronization position (j + 1) is the largest (180 ° -360 ° / N). The position j or the synchronization position (j + 1) is determined as the optimum synchronization position. However, (M mod N) indicates a remainder obtained by dividing M by N, and is a number from 0 to (N−1).
[0183]
When N is an odd number, j = [{i + (N + 1) / 2} mod N], and the phase difference is the largest (180 ° −180 ° / N) with respect to the synchronization position j. j is determined as the optimum synchronization position.
[0184]
Next, with regard to the classification used when detecting the optimum synchronization phase candidate, FIG. 15 and FIG. 17 are used for the detection of the classification including points determined by the position signals (a) and (b) when the origin detection signal (f) is detected. It explains using.
[0185]
In FIG. 15, each position signal (di) is obtained by binarizing the position signal (ki), and repeats a high level and a low level every half cycle. The position signals (d1) to (dN) are signals for each (360 ° / N) phase difference, and the phase is delayed as the number of subscripts increases. Therefore, the XOR circuits 101b1 to 101bN take the exclusive OR of the position signal (di) and the position signal (di + 1), and the AND of the result and the position signal (di) is AND circuits 101c1 to 101cN. Thus, when applied to (Equation 7), the position signal (pi) is at a high level only when θ is between 360 ° · (i−1) / N and 360 ° · i / N. Therefore, when the section including the points determined by the position signals (a) and (b) is (i), only the signal (pi) is at the high level from (Equation 7).
[0186]
From the above, as shown in FIG. 17, when the position signals (p1) to (pN) are latched when the origin detection signal (f) is detected and the high level position signal is (pi), It can be determined that the section including the point determined by the position signals (a) and (b) when the origin detection signal (f) is detected is the section (i).
[0187]
From the above, the position signals (p1) to (pN) are latched when the origin detection signal (f) is detected, and the determination is made when the high level position signal is (pi), that is, in FIG. The logic for determining the optimum synchronization position when i is at the high level will be described separately for N being an even number and an odd number. When N is an even number, j = [(i + N / 2) mod N], and the phase difference between the synchronization position j and the synchronization position (j + 1) is the largest (180 ° -360 ° / N). The position j or the synchronization position (j + 1) is determined as the optimum synchronization position. When N is an odd number, j = [{i + (N + 1) / 2} mod N], and the phase difference is the largest (180 ° −180 ° / N) with respect to the synchronization position j. Is determined as the optimum synchronization position.
[0188]
Next, the synchronization position when the setting of the synchronization position is (i) and the section including the point determined by the position signals (a) and (b) is (j) when the origin detection signal (f) is detected. A method for determining the stability will be described. As the determination method, as in the determination of the optimum synchronization position, the stability is higher as the phase difference between the section included at the rising edge of the origin detection signal (f) and the synchronization position is larger, and the stability is smaller as the phase difference is smaller. Is assumed to be low.
[0189]
From FIG. 14, the minimum value of the phase difference from the synchronization position i to the section (j) is obtained in the counterclockwise direction and the clockwise direction. If the counterclockwise value is θ + and the clockwise value is θ−,
θ + = [(j−i) mod N] · 360 ° / N (Expression 8)
θ − = [(i−j−1) mod N] · 360 ° / N (Equation 9)
If the smaller one of θ + and θ− is θmin, θmin is the phase margin. The margin can be determined by the value of θmin.
[0190]
The phase difference θmin takes a stepwise value. When N is an even number, the phase difference θmin is (N / 2). When N is an odd number, there are [(N + 1) / 2] stages. Regarding the number of stages, it is possible to reduce the number of stages by grouping adjacent stages as necessary based on the specification of the determination level division.
[0191]
In the present embodiment, the classification used for determining the stability is the same as the classification used for detecting the optimum synchronization position. Therefore, the description here is omitted.
[0192]
From the above, the position signals (p1) to (pN) are latched when the origin detection signal (f) is detected, and when the high level position signal is (pj), that is, in FIG. The logic of the stability determination for the current synchronization position i when i is high will be described below.
[0193]
Of θ + and θ− represented by (Expression 8) and (Expression 9), the smaller one is set as θmin, and the phase margin according to the value of θmin is determined in advance. At this time, the value of θmin takes a discrete value, and when N is an even number, it has (N / 2) stages, and when N is an odd number, it has [(N + 1) / 2] stages. Level determination based on the values of i and j is performed by the stability determination unit 107J and output to the outside. Note that the stability determination unit 107J may output only the values of i and j so that the stability can be determined externally.
[0194]
Since how to use the determination result about the stability of the optimum synchronization position and the current origin detection position is the same as in the first embodiment, the details are omitted.
[0195]
[effect]
In the present embodiment, it is possible to obtain substantially the same effect as that of the first embodiment.
[0196]
As an effect peculiar to the present embodiment, in order to adjust the gain / offset and to correct the phase of the 90 ° phase difference signal, a multiphase signal of about 3 to 8 phases by adding / subtracting the 90 ° phase difference signal and its inverted signal is used. In a circuit that performs generation or phase division by resistance division, a circuit for determination can be shared to some extent.
[0197]
The former generation of multiphase signals by addition and subtraction can also be regarded as a part of phase division in a broad sense, and can be applied to this embodiment. In particular, in a circuit that performs phase division by resistance division, an AB phase signal, an inverted signal thereof, and the like are added and subtracted while weighting to divide one cycle 360 ° of the AB phase into N portions to obtain a (360 ° / N) phase difference. Generation of N signals at intervals is performed, or functions can be easily added. Most of them already have a comparator circuit for detecting the intersection of the N analog phase difference signals and the reference signal. For these reasons, the phase synchronization function of the origin signal and the detection of the phase position at a specific timing are relatively easy. Furthermore, in the phase synchronization function of the origin signal and the detection of the phase position at a specific timing, the same detection method is applied to all the synchronization position candidates, and similarly, the same detection method is applied to all the division detections. Since it is applied, the circuit can be simplified for a large number of synchronization position candidates and divisions.
[0198]
Further, in the phase division, normally, about several tens to several thousand divisions are performed, and by having a large number of synchronization position candidates and sections, it is possible to finely detect the optimum synchronization position and judge the stability of the current synchronization position.
[0199]
From the above, the contents of the present embodiment can be easily applied to the origin detection of a displacement sensor having a phase division function by resistance division, and the advantages of phase division by resistance division are the downsizing and low-cost by the IC. We can enjoy merit of cost reduction.
[0200]
(Third embodiment)
[Constitution]
FIG. 18 is a diagram showing the configuration of the main part of the encoder according to the third embodiment of the displacement sensor of the present invention. However, it is needless to say that the present invention is not limited to this configuration as long as the position signal and the origin detection signal can be obtained except for the signal processing circuit unit.
[0201]
As shown in FIG. 18, the optical encoder according to the third embodiment is a combination of a light emitting unit 1 such as an LED and an optical element 2 for making the light beam from the light emitting unit 1 parallel light. A light source unit 10, an index scale 3 and a scale 4 to which parallel light from the light source unit 10 is sequentially irradiated, a photodetector 5 disposed on the opposite side of the light source unit 10 when viewed from the scale 4, and the It comprises a signal processing circuit unit 6 that processes a signal from the photodetector 5 and outputs it as an encoder signal.
[0202]
In such a configuration, among the index scale 3, the scale 4, and the photodetector 5, the slits 3 a formed in the index scale 3 and the slits 4 a formed in the scale 4 are used for position detection. And a combination with a light detection unit 5 a formed in the light detector 5. Further, the combination of the slit 3b formed in the index scale 3, the slit 4b formed in the scale 4 and the light detection unit 5b formed in the photodetector 5 is used for detecting the origin. is there.
[0203]
In an object for position detection such as a stage and a motor, the combination of the light source unit 10, the index scale 3, and the photodetector 5 is attached to either the movable unit or the fixed unit. The scale 4 is attached to either the movable part or the fixed part.
[0204]
In the present embodiment, the scale 4 and the photodetector 5 are each provided with three slits 4b for detecting the origin and three photodetectors 5b. Each of the three detection signals in the three light detection units 5b has the same waveform pattern, and the phase difference satisfies the following expression.
[0205]
Phase difference α = [one cycle of position signal] × (i + 1 / N) (Equation 10)
Here, i is an integer constant, and N represents the number of origin detection signals. In the present embodiment, N = 3.
[0206]
In this embodiment, an optical encoder is used. However, any configuration can be used as long as a plurality of origin detection signals having a phase difference satisfying Expression 10 can be obtained including other types such as a magnetic type. It may be.
[0207]
FIG. 19 is a block diagram showing a configuration of the signal processing circuit unit 6 of the encoder according to the present embodiment. That is, the signal processing circuit unit 6 includes a binarization circuit 101 for converting the analog position signals (a) and (b) into digital position signals (c) and (d), and an origin detection signal (e1). , (E2), and (e3) are binarized at a predetermined slice level and converted to digital origin detection signals (f1), (f2), and (f3), and this binarization A selection circuit 105 that selects one of the digital origin detection signals (f1), (f2), and (f3) from the circuit 102 and generates it as an origin signal (g), and a selection candidate in the selection circuit 105 A switch 104 for switching between them, a determination circuit 107 for detecting the optimum synchronization position, and a display 108 for displaying the optimum synchronization position determination result by the decision circuit 107.
[0208]
In Equation 10, the phases are shifted by 1 / N in order to prepare a plurality of synchronization phase timings of the origin signal and the position detection signal. However, when the synchronization phase timings are to be matched, the phase difference is as follows: The position of the slit 4b for detecting the origin may be set so that
[0209]
Phase difference α = [one cycle of position signal] × i (Expression 11)
However, i is an integer constant.
[0210]
Further, when it is desired to provide an interval or a specific origin position instead of the phase difference, the interval a between the origin detection slit 4b and the light detection unit 5b or the interval aj (j = 1,... N, in this embodiment, N = 3) may be set.
[0211]
Interval a = L (Expression 12)
Interval aj = Lj (Expression 13)
However, L and Lj are constants.
[0212]
In the case of Expression 10 and Expression 11, the phase of the position detection signal is accurately determined at the detection position of the origin detection signal. In the case of Expression 12 and Expression 13, the origin signal generation position is determined. Are not necessarily synchronized accurately with the position detection signal, and only the interval is specified.
[0213]
[Action]
20 to 22 are time charts showing how the input from the photodetector 5 as shown in FIG. 18 is processed by the signal processing circuit unit 6 of FIG. In particular, FIG. 20 corresponds to Expression 10, FIG. 21 corresponds to Expression 11, and FIG. 22 corresponds to Expression 12. Although the time chart specific to Equation 13 is not shown, FIG. 22 can be regarded as a special case of Equation 13. 20 to 23, the horizontal axis represents time, and shows changes in each signal when a constant speed displacement occurs.
[0214]
That is, in the binarization circuit 101, the digital position signal (c) is obtained by binarizing the analog position signals (a) and (b) of the encoder that periodically change with displacement (relative movement of the scale 4). And (d) are obtained. Further, the binarization circuit 102 binarizes the origin detection signals (e1), (e2), and (e3) at a predetermined slice level, thereby providing digital origin detection signals (f1) and (f2). , And (f3) are obtained. Then, the selection circuit 105 selects one of the digital origin detection signals (f1), (f2), and (f3) according to the switch 104. In FIGS. 20 to 22, the origin state signal (g) corresponding to the digital origin detection signals (f1), (f2), and (f3) is a solid line in the pulse-like portion. Part, thin dotted line part, dotted line part.
[0215]
In the present embodiment, the digital origin detection signal (f) is used as the origin signal as it is, but the digital origin detection signal (f) is processed to produce a sharp origin signal at an intermediate point. A method of generating the digital origin detection signal (f) from each origin detection signal (e) within a range satisfying the expressions 10 to 13 may be individually set.
[0216]
Here, the position signals (a) and (c) and the position signals (b) and (d) have a phase difference of 90 °. The position signals (a) and (b), which are analog signals, and the origin detection signals (e1), (e2), and (e3) are the position signals (c) and (d), which are digital signals, and the origin detection. Any type of signal may be used as long as the signals (f1), (f2), and (f3) can be generated. Further, the input from the detection system may be only a digital signal and may not include an analog signal. Further, when the position signal is digitized, the resolution may be further improved by phase division.
[0217]
Position detection is performed by inputting digital position signals (c) and (d) to a counter (not shown). When the origin signal (g) is generated, the origin of position detection can be obtained by resetting the counter.
[0218]
Next, as shown in FIGS. 23A and 23B, the intersection of the Lissajous circle drawn by the position signals (a) and (b) and the vertical axis + side is set as the target phase for origin detection, and the right side in the figure. Processing contents of the determination circuit 107 when the rotation is set as the origin detection direction will be described. In the figure, in order to detect the target phase shown in the clockwise direction as the origin detection direction, it is only necessary to detect the rising edge of the position signal (c) at which the position signal (d) becomes high level.
[0219]
In the determination circuit 107, the origin detection signal having the smallest phase difference between the phase of the position detection signal and the target phase when the origin detection signal (f1), (f2), or (f3) is detected is regarded as the optimum. Output. Furthermore, regarding the setting of the current origin position, the current stability is judged and output from the difference between the target phase and the actual detection phase. The determination result of the optimum synchronization position and the current origin detection stability is output to the display unit 108 or externally as an electrical signal. The display 108 may be of any type as long as the result can be shown. For example, among the three LEDs representing each origin detection signal, the optimum one is turned on when the origin is detected. In addition, the current stability of origin detection can be displayed in the display color of an LED that can be lit in two colors.
[0220]
Here, a specific determination method will be described with reference to FIGS. 20 and 23 (A) and (B). (A) and (B) in FIG. 23 correspond to Expression 10, and three points (f1), (f2), and (f3) in the figure are origin detection signals (f1), (f2), and The position of the position signals (a) and (b) at the moment when (f3) is detected is shown.
[0221]
In the position signals (a), (b), (c), and (d) of FIG. 20, the position signals (b) and (d) are more out of phase with respect to the position signals (a) and (c). It has advanced 90 °. These will be described with reference to (A) and (B) of FIG. When the combination of the signal levels of the position signals (a) and (b) in FIG. 20 is represented in a two-dimensional graph, it moves clockwise on the circumferences of (A) and (B) in FIG. Here, the level of the position signal (a) changes from minus to plus, that is, the rise of the position signal (c) occurs at the intersection of the vertical axis and the circle indicated by the arrows in FIGS. 23 (A) and 23 (B). Among them, the position signal (b) is an upper point on the plus side. The position at the time of detecting the origin detection signal closest to this point is the most stable against the fluctuation of the system and can be said to be the optimum candidate. Further, in the current setting of the origin, if the position at the time of origin detection signal detection is close to the target phase, the origin detection can be regarded as stable.
[0222]
If the level of the position signal (d) when the origin detection signal is detected is high, that is, if the position at the time of origin detection signal detection exists in the upper half on the circumference, at least the phase difference is within 90 ° And stable. The phase difference of each origin detection signal is known and is approximately 120 °. Accordingly, there are one or two origin detection signals at which the level of the position signal (d) when the origin detection signal is detected becomes high.
[0223]
As in the example of FIG. 23A, if there is one origin detection signal that satisfies the condition, it may be determined as the optimum detection signal.
[0224]
On the other hand, as in the example of FIG. 23B, if there are two origin detection signals that satisfy the condition, both may be considered stable. Here, if one of the two is narrowed down, the following is performed. That is, in the example of FIG. 23B, there is only one origin detection signal (f2) at which the level of the position signal (d) becomes low. Since the phase difference of each origin detection signal is known and is approximately 120 °, it has the same level as the level (high level) of the position signal (a) (that is, the position signal (c)) at the corresponding point (f2). The origin detection signal (f3) corresponding to the point (f3) can be determined as the most stable origin detection signal.
[0225]
The determination has been described by using the expression 10 as an example, but an origin detection system having an origin detection signal corresponding to another expression will be described.
[0226]
In the case of Expression 11, the three points (f1), (f2), and (f3) in FIGS. 23A and 23B substantially overlap the same point. In this case, it cannot be determined which is optimal. About stability, it can judge similarly to Formula 10 about the stability of having deviated from a target position.
[0227]
As for Expressions 12 and 13, if the position signal phase at the origin detection position is designated, the optimum position and stability can be determined as in Expression 10. Even if there is no designation of the phase of the position signal at the time of origin detection, the purpose of the system according to each detected position is assumed, so it is possible to determine the optimum position and stability according to the purpose Is possible.
[0228]
For example, when the movable range is used in a limited movable range, and the movable range changes depending on the purpose of use and time, only the origin detection signal within the movable range can be used for origin detection. Also, even when multiple origin detection signals can be detected within the movable range, depending on the usage conditions of the system, such as the origin position should be at the minus end of the coordinate system of the movable range or at the center. The optimum origin detection position exists. Similarly, there is a situation where the stability of the current origin position should be determined. In such a case, it is possible to make a determination by giving information such as a system usage condition such as a movable range or a code corresponding to the information to the determination circuit as a switch or an external input signal.
[0229]
[effect]
According to the present embodiment, it is possible to select a phase difference from the position signal from among three candidates by selecting one from a plurality of origin detection signals. Therefore, the origin signal can be output in synchronization with the desired phase of the position signal. In addition, when synchronizing the origin signal with the position signal, it has a determination circuit 107 that determines which one of the plurality of origin detection signals is the best, and is best when the encoder is actually attached to the apparatus. Can be selected. This makes it possible to improve the stability against fluctuations. This increases the stability of origin detection synchronized with the position signal, and eliminates the need to consider in advance the effects of variations in relative position and orientation, such as the mounting angle and gap between the head and scale when the encoder is mounted. . In other words, it is not necessary to set and process the phase difference between the position signal and the origin signal strictly in design and production, leading to shortening of production cost and assembly adjustment time, and function by reducing design and production restrictions. There is an advantage that the degree of freedom can be increased.
[0230]
Furthermore, according to the present embodiment, the origin position can be selected by selecting one of a plurality of origin detection signals. Furthermore, depending on the arrangement of the origin detection units listed in Equations 10 and 11, it is possible to specify the synchronization phase with the position signal. Furthermore, in Equation 10 of the present embodiment, phase differences of 120 ° intervals are provided, but by appropriately selecting the number N of origin detection signal generators, the phase difference (360 ° of origin detection signals) is selected. / N) can be set to a desired value.
[0231]
In the present embodiment, there are a plurality of origin signal generation position candidates, and each origin signal generation position candidate is physically configured at least partially as an independent detection system, and the interval between the origin signal generation position candidates is set. It is possible to change the design. For this reason, it is effective for the need to change the origin position according to the use conditions and move to another location.
[0232]
The present invention has been described above based on the embodiments. However, the present invention is not limited to the above-described embodiments, and various modifications and applications are possible within the scope of the gist of the present invention. It is.
[0233]
【The invention's effect】
As described above, according to the present invention, even when unstable factors such as signal noise and wobbling, light source stability, temperature characteristics of light emitting elements and light receiving elements occur, the origin position can be detected stably. Therefore, an inexpensive displacement sensor that can stably perform origin detection synchronized with the AB phase in an encoder used for displacement detection, and in particular, an optimum origin position of such a displacement sensor. A candidate detection method and an origin detection stability determination method can be provided.
[0234]
In particular, according to the present invention, since the current origin position candidate stability determination circuit is implemented, it is possible to determine the necessity of switching the origin position and adjusting the attachment of the origin detection mechanism based on the determination result. As a result, stable origin detection is always possible.
[Brief description of the drawings]
FIG. 1 is a block diagram showing a configuration of a signal processing circuit unit of an encoder according to a first embodiment of the present invention.
FIG. 2A is a diagram showing origin signal generation position candidates and analog position signals (a) and (b) of Lissajous figures; FIG. 2B is an origin signal generation position candidate and analog position signal (a); And (b) is a diagram showing another division of the Lissajous figure, and (C) is a diagram showing origin signal generation position candidates and still another division of the Lissajous figure of the analog position signals (a) and (b). It is.
3A is a diagram illustrating a configuration of a synchronization circuit in the signal processing circuit unit of the encoder according to the first embodiment, and FIG. 3B is a diagram illustrating a specific configuration of the circuit of FIG. (C) is a figure which shows another concrete structure of the circuit of (A).
4A is a diagram showing still another specific configuration of the circuit of FIG. 3A, and FIG. 4B is a specific other configuration of the circuit of FIG. FIG.
FIG. 5 is a diagram showing still another specific configuration of the circuit shown in FIG.
FIG. 6 is a diagram showing a specific configuration of a determination circuit in the signal processing circuit unit of the encoder according to the first embodiment.
FIG. 7 is a diagram showing another specific configuration of the determination circuit in the signal processing circuit unit of the encoder according to the first embodiment.
FIG. 8 is a diagram showing still another specific configuration of the determination circuit in the signal processing circuit unit of the encoder according to the first embodiment.
9 is a time chart showing a state in which the input from the photodetector is processed when the signal processing circuit of FIG. 1 is displaced in the counterclockwise direction on the Lissajous circle.
10 is a time chart showing a state in which the input from the photodetector is processed when the signal processing circuit of FIG. 1 is displaced in the clockwise direction on the Lissajous circle.
FIGS. 11A and 11B are diagrams illustrating a detection flow of an optimal synchronization position, and FIG. 11B is a diagram illustrating another example of a detection flow of an optimal synchronization position.
FIG. 12A is a diagram showing a current synchronization position stability determination flow, and FIG. 12B is a diagram showing another example of the current synchronization position stability determination flow;
FIG. 13 is a block diagram showing a configuration of a signal processing circuit unit of an encoder according to a second embodiment of the present invention.
FIG. 14 is a diagram showing origin signal generation position candidates and the division of Lissajous figures of analog position signals (a) and (b).
FIG. 15 is a diagram illustrating a configuration of a position signal binarization circuit in a signal processing circuit unit of an encoder according to a second embodiment;
16A is a diagram illustrating a configuration of a synchronization circuit in a signal processing circuit unit of an encoder according to a second embodiment, and FIG. 16B is a diagram illustrating a specific configuration of the circuit of FIG. is there.
FIG. 17 is a diagram illustrating a configuration of a determination circuit in a signal processing circuit unit of an encoder according to a second embodiment.
FIG. 18 is a diagram illustrating a configuration of a main part of an encoder according to a third embodiment of the present invention.
FIG. 19 is a block diagram showing a configuration of a signal processing circuit unit of an encoder according to a third embodiment.
FIG. 20 is a time chart showing a state in which an input from a photodetector is processed by a signal processing circuit unit of an encoder according to a third embodiment.
FIG. 21 is a time chart showing a state in which an input from a photodetector is processed by a signal processing circuit unit of an encoder according to a third embodiment.
FIG. 22 is a time chart showing how an input from a photodetector is processed by a signal processing circuit unit of an encoder according to a third embodiment;
FIGS. 23A and 23B are diagrams for explaining the relationship between the position signals (a) and (b) and the origin detection signals (f1), (f2), and (f3), respectively. (B) is a diagram representing a combination of signal levels in a two-dimensional graph.
FIG. 24 is a diagram showing a configuration of a main part of a conventional optical encoder.
FIG. 25 is a diagram showing a configuration of a conventional encoder disclosed in Japanese Patent Application Laid-Open No. 8-261695.
[Explanation of symbols]
DESCRIPTION OF SYMBOLS 1 ... Light emission part, 2 ... Optical element, 3 ... Index scale, 3a, 3b, 4a4b ... Slit, 4 ... Scale, 5 ... Photodetector, 5a, 5b ... Photodetection part, 6 ... Signal processing circuit part, 10 ... Light source unit, 101, 102 ... binarization circuit, 101a1 to 101aN, 107h, 107i ... comparator, 101b1 to 101bN ... XOR circuit, 101c1 to 101cN, 103m3, 103m3a, 103m3b, 103m6, 103m7, 103n3, 107n, 107o, 107q , 107s, 107t to 107x, 107z, 107B, 107C, 107F to 107I ... AND circuit, 103 ... synchronization circuit, 103m ... After the latched origin detection signal (f) becomes high level, the synchronization position is set. 10 a detection circuit for detecting the presence m1, 103m1a, 103m1b, 103m2, 103m2a, 103m2b, 103n1, 103n2 ... flip-flop, 103m4, 103m8, 107p, 107r, 107y, 107A, 107D, 107E ... NOT circuit, 103m5 ... OR circuit, 103n ... latched origin detection Detection circuit that detects that the signal (f) is at a high level and is in the set synchronization position, 104... Switch, 105... Selection circuit, 106, 107 m ... latch circuit, 107 ... determination circuit, 107 g. ... Stability determination unit, 108 ... Display, 110 ... Phase division circuit, 111 ... Pulse generation circuit.

Claims (12)

A displacement sensor that detects a displacement amount based on a periodic signal generated according to a displacement of a position or an angle of a moving body, and generates an origin signal when the moving body is in a predetermined range.
There are a plurality of origin signal generation position candidates that generate the origin signal,
A selection unit that selects and switches one generation position candidate from among the plurality of origin signal generation position candidates as an origin signal generation position ;
Among the plurality of origin signal generation position candidates, a determination unit that detects an optimal candidate;
A stability determination unit that determines the stability of the current origin signal generation position;
Comprising
The selection unit can select the origin signal generation position based on the determination result from the determination unit,
The above-described stability determination unit is configured to determine the current stability of the origin signal generation position when an optimum origin signal generation position candidate is detected . A displacement sensor that detects a displacement amount based on a periodic signal generated according to a displacement of a position or an angle of a moving body, and generates an origin signal when the moving body is in a predetermined range.
There are a plurality of origin signal generation position candidates that generate the origin signal,
A selection unit that selects and switches one generation position candidate from among the plurality of origin signal generation position candidates as an origin signal generation position;
The plurality of origin signal generation position candidates correspond to a plurality of phases of the periodic signal,
The selection unit can switch one of the plurality of phases as the origin signal generation position,
The periodic signal is two periodic signals having a phase difference of approximately 90 ° with each other in the same period,
Taking one output of the two periodic signals in the horizontal axis direction of the two-dimensional orthogonal coordinate system and the other output in the vertical axis direction, the value of each coordinate force at the intersection of the horizontal axis and the vertical axis is A waveform that takes a coordinate system so as to coincide with the amplitude center value of each output of the two periodic signals, and a point determined by the output of each of the two periodic signals on the coordinate system is drawn as the displacement of the moving body Is a Lissajous waveform of the above two periodic signals,
When the moving body is in a predetermined range, an origin detection signal that is not necessarily synchronized with the periodic signal is generated,
Among the plurality of sections that can be divided from the Lissajous waveforms of the two periodic signals, a section including a point determined by the two periodic signals can be determined at least when the origin detection signal is generated,
Judgment for detecting an optimum origin signal generation position candidate from among the plurality of origin signal generation position candidates based on the section on the Lissajous waveform where there is a point determined by the two periodic signals when the origin detection signal is generated Further comprising
The selection unit can select the origin signal generation position based on the determination result from the determination unit,
The determination unit determines a phase difference between a phase on the Lissajous waveform where a point determined by the two periodic signals exists when the origin detection signal is generated and each phase of the periodic signal at the origin signal generation position candidate. Is expressed by 0 ° to 180 °, the minimum value of the phase difference in the section is set as the phase difference between the section and each origin signal generation position candidate for the combination of the above section and each origin signal generation position candidate. A displacement sensor characterized in that the origin signal generation position candidate having the largest is determined to be optimal. A displacement sensor that detects a displacement amount based on a periodic signal generated according to a displacement of a position or an angle of a moving body, and generates an origin signal when the moving body is in a predetermined range.
There are a plurality of origin signal generation position candidates that generate the origin signal,
A selection unit that selects and switches one generation position candidate from among the plurality of origin signal generation position candidates as an origin signal generation position;
The plurality of origin signal generation position candidates correspond to a plurality of phases of the periodic signal,
The selection unit can switch one of the plurality of phases as the origin signal generation position,
The periodic signal is a plurality of displacement detection periodic signals detected for detecting the displacement amount of the moving body, or a plurality of phase division periodic signals generated when phase-dividing the plurality of displacement detecting periodic signals. A plurality of displacement amount detection signals of three or more consisting of any of the following:
There are the same number of origin signal generation position candidates as the number of displacement amount detection signals,
There is a one-to-one correspondence between the plurality of origin signal generation position candidates and the periodic signal.
The selection unit, the phase detection of the plurality of reference signal generation position candidate corresponding displacement sensor which comprises using the displacement detection signal. The displacement amount detection signal is a plurality of phase division period signals generated by phase division based on the plurality of displacement detection period signals of any of 2 signals, 3 signals, and 4 signals having a phase difference of 90 °. displacement sensor according to claim 3, characterized in that. The amount of displacement is detected based on a periodic signal generated according to the displacement of the position or angle of the moving body, and when the moving body is within a predetermined range, the optimal origin position candidate of the displacement sensor that generates the origin signal Detection method,
The displacement sensor is
When the moving body is in a predetermined range, an origin detection signal is generated,
There are multiple origin signal generation position candidates at the origin signal generation position where the origin signal is generated,
A selection unit that selects one generation position candidate from among the plurality of generation position candidates as an origin signal generation position, and an optimal generation position candidate among the plurality of origin signal generation position candidates is selected when an origin detection signal is generated. A determination unit for detecting,
In the method of detecting an optimal origin position candidate of the displacement sensor, the selection unit is capable of selecting an origin signal generation position based on the determination result of the determination unit.
Detecting the origin detection signal generation;
Detecting an optimum origin position candidate by the determination unit;
Outputting a determination result; and
A step of determining whether the setting reflects the determination result;
Only when it is determined to reflect the setting, the step of switching the setting of the origin position,
A method for detecting an optimum origin position candidate of a displacement sensor, comprising: A displacement sensor that detects an amount of displacement based on a periodic signal generated according to a displacement of a position or an angle of a moving body, and generates an origin signal when the moving body is in a predetermined range,
An origin detection signal generator for generating an origin detection signal that is not necessarily synchronized with the periodic signal when the moving body is in a predetermined range;
A stability determination unit that determines the stability of the current origin signal generation position based on the phase margin between the generation of the origin detection signal and the periodic signal at the origin signal generation position;
A displacement sensor comprising: The stability determination unit is most stable when the phase difference is 180 ° when the phase difference between the origin detection signal generation and the periodic signal at the origin signal generation position is represented by 0 ° to 180 °. The displacement sensor according to claim 6 , wherein the displacement sensor is determined to be most unstable when the phase difference is 0 °. The origin signal generation position has a plurality of candidates, and one of them can be selected as the origin signal generation position.
The displacement sensor according to claim 6 , wherein the designation of the origin signal generation position can be changed based on the determination result of the stability. The periodic signal is two periodic signals having a phase difference of approximately 90 °,
One output of the two periodic signals is taken in the horizontal axis direction of the two-dimensional orthogonal coordinate system, the other output is taken in the vertical axis direction, and the value of each coordinate at the intersection of the horizontal axis and the vertical axis is A coordinate system is taken so as to coincide with the amplitude center value of each output of the two periodic signals, and a waveform drawn by the point determined by the output of each of the two periodic signals on the coordinate system as the displacement of the moving body is obtained. Lissajous waveform of two periodic signals,
The stability determination unit divides the Lissajous waveform of the two periodic signals into two or more sections, and has a point determined by the two periodic signals when the origin detection signal is generated. The displacement sensor according to claim 6 , wherein the stability is determined based on the classification. The stability determination unit sets the phase difference between the segment on the Lissajous waveform where a point determined by the two periodic signals exists when the origin detection signal is generated and the periodic signal at the origin signal generation position to 0 ° to 180 °. When expressing, the minimum value of the phase difference in the section is defined as the phase difference between the section and the origin signal generation position, and the most stable when the phase difference is 180 ° and the most unstable when the phase difference is 0 °. The displacement sensor according to claim 9 . Displacement that generates an origin signal when the amount of displacement is detected based on a periodic signal that is generated according to the displacement of the position or angle of the moving body, and the moving body is at the origin signal generation position at a predetermined position or angle. It is a method for judging the stability of sensor origin detection,
The displacement sensor is
When the moving body is in a predetermined range, an origin detection signal is generated,
It has a stability determination unit that determines the stability of the current origin signal generation position based on the phase margin between the generation of the origin detection signal and the periodic signal at the origin signal generation position. In the method for determining the stability of the origin detection of the displacement sensor,
Detecting the origin detection signal generation;
Determining the stability of the current origin position by the stability determination unit;
Outputting the determination result;
A stability determination method for detecting the origin of a displacement sensor. There are a plurality of candidates for the origin signal generation position, one of which can be selected as the origin signal generation position, and a step of determining whether to reflect the determination result and a step of switching the setting of the origin position The method for determining the stability of the origin detection of the displacement sensor according to claim 11 , wherein the method is performed automatically.

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