JP4455310B2 - Manufacturing method of semiconductor device - Google Patents

Description

  The present invention relates to an insulated gate field effect type semiconductor device having a high withstand voltage structure, and more particularly to a semiconductor device used for a driver IC for driving a liquid crystal or a thermal paper resistance.

  For example, in a thermal paper type printer, a high voltage MOS transistor having a structure as shown in FIG. 2 is used as an IC for driving a heating resistor. An N + -type source region 4 and a drain region 5 are provided on the surface of the P-type silicon single crystal substrate 1. In order to obtain high breakdown voltage characteristics, a low concentration drain region 21 connected to the drain region 5 is provided under the field insulating film 7. The channel formation region becomes the surface of the substrate 1 between the source region 4 and the drain region 21. The impedance of the channel formation region is controlled by the gate electrode provided through the gate insulating film 6.

In the case of a heating resistor driving IC, the drain withstand voltage is 30 to 50V. Accordingly, the gate insulating film 6 is a silicon oxide film having a thickness of 500 to 1500A. An IC having a thin gate insulating film has been developed by us and has been applied for a patent (see Japanese Patent Application Laid-Open No. 7-226505).
JP 7-226505 A

  However, in a conventional semiconductor device in which a high breakdown voltage MOS transistor and a low breakdown voltage MOS transistor are integrated, a photolithography process for forming a low concentration drain region for the high breakdown voltage MOS transistor is required. In other words, it is necessary to add one more photolithographic process as compared with an integrated circuit using only a normal low voltage MOS transistor.

  Accordingly, an object of the present invention is to obtain a semiconductor device capable of flowing a large current with a small area in a high voltage MOS transistor in which a high voltage of 10 V or more is applied to a drain region. A further object of the present invention is to obtain a semiconductor device that can be manufactured at low cost by a simple manufacturing method.

  In order to solve the above problems, the present invention has the following configuration.

  (1) A second conductivity type source region provided on the surface of the first conductivity type semiconductor region, and a second conductivity type second region provided on the surface of the semiconductor region away from the source region via the channel formation region. 1 drain region, a second drain region of a second conductivity type connected to the first drain region and provided on the surface of the semiconductor region, and a channel forming region and a first drain region, respectively. The gate electrode is provided through a gate insulating film and a field insulating film, and an impurity region containing a first conductivity type impurity element at least in the semiconductor region is provided on the surface of the first drain region. A semiconductor device characterized by the above.

  (2) a second conductivity type low drain withstand voltage insulated gate field effect transistor provided on the surface of the first conductivity type semiconductor region, and the low drain withstand voltage insulated gate field effect transistor separated from the semiconductor region via the isolation region; In a semiconductor device comprising a high drain withstand voltage insulated gate field effect transistor provided on the surface, a field doped region of a first conductivity type whose isolation region is higher in concentration than the semiconductor region provided on the surface of the semiconductor region, and field doping The drain region of the high drain withstand voltage insulated gate field effect transistor is composed of a second conductivity type impurity region having a higher concentration than the field doped region including the field doped region. The semiconductor device is characterized by this.

  (3) A second conductivity type low drain withstand voltage insulated gate field effect transistor provided on the surface of the first conductivity type semiconductor region, and the low drain withstand voltage insulated gate field effect transistor and the isolation region on the surface of the semiconductor region In a method of manufacturing a semiconductor device comprising a provided high drain breakdown voltage insulated gate field effect transistor, a step of forming an oxidation resistant mask film on the surface of the semiconductor, and an isolation region and a low concentration drain region of the high drain breakdown voltage insulated gate field effect transistor A step of selectively removing the oxidation-resistant mask film corresponding to the step, and a step of ion-implanting a first conductivity type impurity into the surface of the semiconductor region corresponding to the isolation region and the low-concentration drain region using the oxidation-resistant mask film as a mask. And a step of forming a resist film on the surface of the semiconductor region, and a resist corresponding to the low concentration drain region. A step of removing the conductive film, a step of ion-implanting impurities of the second conductivity type using the resist film as a mask, a step of forming a field oxide film by selectively oxidizing the surface of the semiconductor region using the oxidation resistant mask film as a mask, Forming a field doped region on the surface of the semiconductor region under the field oxide film in the isolation region and forming a field oxide film on the low concentration drain region and the low concentration drain region in the selective oxidation step; The step of removing the oxidation-resistant mask film and forming a gate insulating film on the surface of the semiconductor region, and patterning the gate electrodes of the low drain withstand voltage insulated gate field effect transistor and the high drain withstand voltage insulated gate field effect transistor on the gate insulating film And doping a second conductivity type impurity on the surface of the semiconductor region using the gate electrode as a mask. And to the method for manufacturing the semiconductor device comprising a step of forming a low-drain breakdown voltage insulated gate field effect transistor and the source-drain region of the high drain breakdown voltage insulated gate field effect transistor.

  (4) A first conductivity type first source and drain region provided on the surface of the second conductivity type semiconductor region, and separated from the first source and drain region via a second conductivity type element isolation region. A second drain and source region of the first conductivity type provided on the surface of the semiconductor region, a field insulating film provided on the element isolation region of the second conductivity type, and a surface of the element isolation region The semiconductor device is characterized in that an impurity region containing at least the first conductivity type impurity element is included in the semiconductor region.

  As described above, according to the present invention, a high drain breakdown voltage MOS transistor to which a high voltage of 10 V or higher is applied to the drain region, a low drain breakdown voltage MOS transistor to which a low voltage of 5 V or lower is applied, and a low breakdown voltage MOS isolation element are provided. In a semiconductor device comprising a high voltage MOS isolation element and its manufacturing method, an apparatus and a manufacturing method that can be easily manufactured can be realized by reducing the photolithography process once. Further, the manufacturing variation of the channel current can be reduced by forming the source region and the drain region symmetrically.

  Embodiments of the present invention will be described below with reference to the drawings.

  FIG. 1 is a cross-sectional view of a high drain withstand voltage insulated gate field effect transistor (hereinafter abbreviated as HVMOSFET) included in a semiconductor device of the present invention.

An N + -type source region 4 is provided on the surface of the P-type silicon substrate 1, and an N ± type drain region 5 A is provided apart from a channel formation region which is the surface of the substrate 1. N ± type drain region 5A has a low concentration and is provided under field oxide film 7. Therefore, an N + type drain region 5 for ohmic contact with the aluminum wiring is provided in connection with the N ± type drain region 5A. The N + -type source region 4 and the N + -type drain region 5 are formed at a high concentration having a surface concentration of 5 × 10 ¹⁹ atoms / cm ³ or more. The N ± type low-concentration drain region 5A is formed at a low surface concentration of about 3 × 10 ^{16 to} 5 × 10 ¹⁸ atoms / cm ^3, preferably about 5 × 10 ^{16 to} 5 × 10 ¹⁷ atoms / cm ^3. 7 × 10 ^{16 to} 3 × 10 ¹⁷ atoms / cm ³ is optimal. Further, N ± type but the low-concentration drain region 5A depth is formed at ^{0.2 × 10 -4 ~5.0 × 10 -4} cm ^{approximately, 0.5 × 10 -4 ~1.5 × 10} - ^{About 4} cm is desirable, and about 0.7 × 10 ^{−4 to} 1.0 × 10 ⁻⁴ cm is optimal. A silicon dioxide film having a thickness of 10 to 30 nm is formed as a gate insulating film 6 on the channel forming region which is the surface of the substrate 1 between the N + type source region 4 and the N ± type drain region 5A. . A gate electrode 8 is provided on the field oxide film 7 on the gate insulating film 6 and the N ± type drain region 5A. The field oxide film 7 has a thickness of 300 to 1500 nm, preferably 600 to 1200 nm, and most preferably 600 to 800 nm.

  The bird's beak region (region connecting the field oxide film 7 and the gate insulating film 6) 7A is formed on the N ± type low concentration drain region 5A, and the end of the bird's beak region 7A on the channel forming region side is N It is formed on a depletion layer in the N ± type low concentration drain region 5A that is generated when a drain voltage is applied to the ± type low concentration drain region 5A.

  A boron element diffusion region 5B, which is a P-type impurity, is provided on the surface of the N ± type drain region 5A and immediately below the field oxide film 7. The N ± type drain region 5A is made N-type by doping with phosphorus element.

FIG. 4 is a view showing the impurity distribution along the depth direction of the substrate 1 from the field oxide film 7. The surface concentration of phosphorus element is about 1.5 to 100 times higher than that of boron element, but it is desirable to form it about 2 to 5 times higher, and about 2 to 3 times is optimum. Further, the N ± type drain region 5A is formed on the N ± type drain region 5A side when a drain voltage is applied between the N ± type drain region 5A and the P-type silicon substrate 1 directly below the boron element diffusion region 5B. It is formed deeper than the depletion layer width. Desirably, it is about 0.3 × 10 ^{−4 to} 2.0 × 10 ⁻⁴ cm deeper than the depletion layer width, and the optimum condition is about 0.3 × 10 ^{−4 to} 0.5 × 10 ⁻⁴ cm from the depletion layer width. Form deeply. Since the drain region is formed with a high breakdown voltage structure including the N ± type drain region 5A and the field oxide film 7 thereon, the drain region is 20-50 V with respect to the source region 4, the P-type silicon substrate 1 and the gate electrode 8. A drain breakdown voltage characteristic is obtained. By applying a positive voltage to the gate electrode 8 with respect to the source region 4, the channel formation region is inverted from P-type to N-type, so that a channel current flows.

FIG. 3 is a cross-sectional view of the semiconductor device manufacturing method according to the present invention in the order of steps.
FIG. 3 shows an embodiment of a method of manufacturing a CMOS type semiconductor device. An N type MOSFET is composed of an HVMOSFET, an LVMOSFET (abbreviation of low drain withstand voltage insulated gate field effect transistor) and an isolation region.

  First, as shown in FIG. 3A, after an insulating film is formed on the surface of the substrate 1, a region in which the PMOSFET is to be formed and a portion of the insulating film in which the HVMOSFET is to be formed are subjected to a normal photolithography technique. Etching is removed by doping, and the etching removal portion is doped with phosphorus element. After doping, the N well 31 is formed by thermal diffusion at about 1150 ° C. and about 10H.

  Next, after removing the insulating film on the surface of the substrate 1, an oxide film 32 of 35 nm and a silicon nitride film 33 of 150 nm are sequentially formed again. The nitride film 33 in the region to be field oxidized is removed by etching. Not only the isolation regions of the PMOSFET and NMOSFET but also the nitride film 33 in the region corresponding to the low concentration drain region of the HVNMOSFET is removed by etching. Next, boron element is ion-implanted into the entire surface of the substrate 1 using the nitride film 33 as a mask.

  FIG. 3B is a cross-sectional view when ions are implanted after the resist film for patterning the nitride film 33 is removed. Ion implantation may be performed before the resist film for patterning of the nitride film 33 is removed. Boron ion implantation is also performed on the surface of the substrate 1 corresponding to the isolation region of the PMOSFET and the low concentration drain region of the HVNMOSFET. Next, in order to ion-implant phosphorus element only on the surface of the substrate 1 that should become the low-concentration drain region of the HVNMOSFET and the isolation region of the PMOSFET, a resist film 34 is formed by a normal photolithography technique as shown in FIG. Pattern. A window of a resist film 34 is formed on the surface of the substrate 1 in the N well region 31 and the portion of the low concentration drain region of the HVNMOSFET. Therefore, the resist film 34 is formed in the NMOSFET region except for the low concentration drain region of the HVMOSFET. Here, phosphorus ion implantation is performed.

  Next, as shown in FIG. 3D, the field oxide film 6 is formed by selective oxidation using the nitride film 33 as a mask. The field oxide film 6 is formed not only in the isolation region but also in the low concentration drain region of the HVNMOSFET. At the time of field oxidation, boron and phosphorus elements doped in FIGS. 3B and 3C diffuse under the field oxide film. As a result, an NMOSFET isolation impurity region 35 and a PMOSFET isolation impurity region 29 are formed. Further, a low concentration drain region 5A of the HVNMOSFET is also formed. Immediately below the field oxide film 6 on the surface of the low concentration drain region 5A, an impurity region 5B having the same boron element distribution as the P ± impurity region 35 is formed. Further, an NMOSFET isolation impurity region 35 is similarly formed on the surface of the isolation impurity region 29 of the PMOSFET.

  The boron and phosphorus element doping conditions in FIGS. 3 (b) and 3 (c) and the field oxidation condition in FIG. 3 (d) are the NMOSFET isolation impurity region 35, the PMOSFET isolation impurity region 29, and the low HVNMOSFET. The formation of the concentration drain region 5A is greatly affected. The implantation energy of boron is set so that the maximum value of the boron concentration profile enters the region of the silicon substrate 1 that will be the field oxide film 6. This is because a segregation phenomenon (suction) of boron into the field oxide film is used in order to obtain a diffusion length difference between phosphorus and boron in a region where phosphorus ions are also implanted. The energy value can be set to about 15 to 60 keV when the field oxide film is 300 to 800 nm, but is preferably about 25 to 45 keV.

  In the case of the field oxide film 800 to 1500 nm, it can be set to about 15 to 200 keV, but is preferably about 25 to 60 keV. Since phosphorus is segregated to the surface of the silicon substrate 1 immediately below the field oxide film 6 during field oxidation, the implantation energy must be set so that the maximum value of the phosphorus concentration profile enters deeper than the region of the silicon substrate 1 that becomes the field oxide film 6. However, a sufficient diffusion length difference between phosphorus and boron can be obtained in a region where boron ions are also implanted.

  The energy value can be set to about 35 to 1500 keV when the field oxide film is 300 to 1500 nm, but is preferably about 60 to 120 keV, and most preferably about 80 to 120 keV.

In the case of a field oxide film of 300 to 800 nm, the dose must be set to at least 1 × 10 ¹³ / cm ² or more of boron in order to obtain the isolation breakdown voltage of the isolation region 35 of the NMOSFET. In order to obtain the isolation breakdown voltage of the region 29 and to obtain the drain breakdown voltage of the low concentration drain region 5A of the HVNMOSFET, it is necessary to set phosphorus to at least 20 to 200% of the boron dose, preferably 30 to 80%. 60% is optimal. In the case of the field oxide film of 800 to 1500 nm, it is necessary to set boron to at least 2 × 10 ¹³ / cm ² or more for the same reason, and phosphorus must be set to at least 20 to 100% of the boron dose. 70% is desirable, but 40-60% is optimal.

  The field oxidation is formed at 950 to 1050 ° C., preferably 975 to 1025 ° C., and most preferably about 1000 ° C. The field oxidation process usually includes a thermal diffusion (annealing) process, but in the thermal diffusion (annealing) process that is performed before the field oxidation process, boron and phosphorus with different depths of segregation phenomenon are different from those during ion implantation. When diffusing up to the substrate 1 region, the ion implantation conditions need to be changed according to the difference in the tendency of the segregation phenomenon. In other words, when boron is diffused deeply into the silicon substrate 1, the amount of boron absorbed into the field oxide film is reduced, and the amount of diffusion into the silicon substrate 1 is increased, so that the boron ion implantation amount is reduced or phosphorus ion implantation is performed. It is necessary to increase the amount.

  Next, after the nitride film 33 and the oxide film 32 are removed, gate oxidation is performed to form the gate oxide film 6. Next, a polysilicon film to be a gate electrode is formed on the substrate surface.

  Next, the polysilicon film is patterned by a normal photolithography technique, and the gate electrodes 36A, 36B, and 36C of the respective transistors are patterned as shown in FIG. Next, as shown in FIG. 3F, an N-type impurity element is doped in a self-aligned manner with respect to the gate electrodes 36A and 36B in the region of the NMOSFET to form source / drain regions.

  A source region 37S and a drain region 37D of the LVNMOSFET, and a source region 4 and a drain region 5 of the HVNMOSFET are formed. In the PMOSFET, a P-type impurity element is doped on the surface of the substrate 1 in a self-aligned manner with respect to the gate electrode 36C to form a source region 39S and a drain region 39D of the PMOSFET. Further, although not shown, after forming the intermediate insulating film, a contact hole for connecting each region and electrode to the wiring is opened in the intermediate insulating film, and then the aluminum film as the wiring is patterned. Further, a passivation film is formed on the surface of the substrate to complete.

  FIG. 5 is a cross-sectional view of another embodiment of an HVMOSFET included in the present invention.

  The source region is composed of a high concentration source region 4 and a low concentration source region 51. By forming the source region and the drain region symmetrically, manufacturing variations in channel current can be reduced.

FIG. 6 is a cross-sectional view of a low breakdown voltage PMOS transistor isolation element included in the semiconductor device of the present invention. An N well region 31 is provided near the surface of the P type silicon substrate 1, a P + type source region 39 S is provided on the surface in the N well region 31, and a drain region 39 D is provided via an N ± type element isolation region 61. Is provided. The P + -type source region 39S and the P + -type drain region 39D are formed to have a surface concentration of 5 × 10 ¹⁹ atoms / cm ³ or higher. The N ± type element isolation region 61 is formed with a low surface concentration of about 3 × 10 ^{16 to} 5 × 10 ¹⁸ atoms / cm ³ , preferably about 5 × 10 ^{16 to} 5 × 10 ¹⁷ atoms / cm ³ , 7 × 10 ^{16 to} 3 × 10 ¹⁷ atoms / cm ³ is optimal. The N ± type element isolation region 61 is formed with a depth of about 0.2 × 10 ^{−4 to} 5.0 × 10 ⁻⁴ cm, but 0.5 × 10 ^{−4 to} 1.5 × 10 ^−4. About cm is desirable, and about 0.7 × 10 ^{−4 to} 1.0 × 10 ⁻⁴ cm is optimal. A field oxide film 7 is provided with a film thickness of 300 to 1500 nm on the N ± type element isolation region 61, a film thickness of 600 to 1200 nm is desirable, and a film thickness of 600 to 800 nm is optimal.

A boron element diffusion region 5B, which is a P-type impurity, is provided on the surface of the N ± type element isolation region 61 and immediately below the field oxide film 7. The N ± type element isolation region 61 is made N-type by doping with phosphorus element. Further, the N ± type element isolation region 61 immediately below the bird's beak region 7A is formed from the boron element diffusion region 5B with a P + type drain region 39D and a P + type source region 39S provided via the N ± type element isolation region 61. It is formed deeper than the depletion layer width on the N ± type element isolation region 61 side that is generated when a power supply voltage is applied between them. Desirably, the depth is 0.1 × 10 ⁻⁴ cm or more deeper than the depletion layer width, and the optimum condition is about 0.1 × 10 ^{−4 to} 0.5 × 10 ⁻⁴ cm deeper than the depletion layer width. The element isolation region is formed with a structure comprising an N ± type element isolation region 61, a boron element diffusion region 5B, and a field oxide film 7 thereon, but is -5 to-with respect to the source region 39S and the N well region 31. A drain breakdown voltage characteristic of 3V is obtained. Even if a poly or aluminum wiring to which a voltage within the power supply voltage range is applied is arranged on the N ± type element isolation region 61, a leak current due to depletion of the N ± type element isolation region 61 does not flow.

It is sectional drawing of the semiconductor device of this invention. It is sectional drawing of the conventional semiconductor device. It is sectional drawing in order of a manufacturing process of the semiconductor device of this invention. It is a figure which shows the impurity distribution of the low concentration drain region of the high voltage | pressure-resistant MOSFET of this invention. It is sectional drawing of another Example of the semiconductor device of this invention. It is sectional drawing of another Example of the semiconductor device of this invention.

Explanation of symbols

1 P-type silicon substrate 4 N + type source region 5 N + type drain region 5A Low concentration drain region 5B Boron element diffusion region 6 Gate oxide film 7 Field oxide film 7A Bird's beak region 8 Gate electrode 29 PMOSFET isolation impurity region 31 N Well region 32 Oxide film 33 Nitride film 34 Resist film 35 (5B) P ± impurity region 36A Gate electrode (LVNMOS)
36B Gate electrode (HVNMOS)
36C Gate electrode (LVPMOS)
37S source region (LVNMOS)
37D Drain region (LVNMOS)
39S source region (LVPMOS)
39D Drain region (LVPMOS)
51 (5A) Low-concentration drain region 52 (5B) Boron element diffusion region 61 (5A) N ± type element isolation region

Claims (1)

An N- type high drain breakdown voltage insulated gate field effect transistor provided on the surface of the P- type semiconductor region, the N- type high drain breakdown voltage insulated gate field effect transistor, and the semiconductor region via the first isolation region An N-type low drain withstand voltage insulated gate field effect transistor provided on the surface, the high drain withstand voltage insulated gate field effect transistor, and an N type well provided on the surface of the semiconductor region via a second isolation region A method of manufacturing a semiconductor device comprising a P-type low drain withstand voltage insulated gate field effect transistor disposed in a region ,
Forming the N- type well region in the vicinity of the surface of the semiconductor region;
Forming an oxidation-resistant mask film on the surface of the semiconductor region;
Selectively etching away the oxidation-resistant mask film corresponding to the first and second isolation regions and the low-concentration drain region of the high drain breakdown voltage insulated gate field effect transistor;
Ion-implanting P-type boron into the surface of the semiconductor region corresponding to the first and second isolation regions and the low-concentration drain region using the oxidation-resistant mask film as a mask;
Forming a resist film on a surface of the semiconductor region,
Removing the resist film corresponding to the second isolation region and the low-concentration drain region;
Ion-implanting N-type phosphorus using the resist film as a mask;
Selectively oxidizing the surface of the semiconductor region using the oxidation-resistant mask film as a mask to form a field oxide film having a thickness of 300 to 1500 nm ;
In the selective oxidation step, a P-type field doped region is formed on the surface of the semiconductor region under the field oxide film in the first isolation region, and under the field oxide film in the second isolation region. An N-type field doped region is formed on the surface of the N-type well region, and an N-type lightly doped drain region is formed on the surface of the semiconductor region under the field oxide film in the lightly doped drain region. And forming an impurity region having the same boron element distribution as the P-type field doped region immediately below the field oxide film on the surface of the N-type field doped region and the low-concentration drain region;
Removing the oxidation-resistant mask film and forming a gate insulating film on the surface of the semiconductor region;
Patterning the N-type and P-type low drain withstand voltage insulated gate field effect transistors and the gate electrodes of the high drain withstand voltage insulated gate field effect transistors on the gate insulating film;
Doping N-type impurities on the surface of the semiconductor region using the gate electrode as a mask to form source and drain regions of the N-type low drain withstand voltage insulated gate field effect transistor and high drain withstand voltage insulated gate field effect transistor , And forming the source and drain regions of the P-type low drain withstand voltage insulated gate field effect transistor by doping a P-type impurity into the N-type well region using the gate electrode as a mask in the order described above. ,
The high drain withstand voltage insulated gate field effect transistor has the drain region which is a high concentration N type provided on the surface of the semiconductor region connected to the low concentration drain region,
The step of ion-implanting boron is a step of ion-implanting so that the implantation energy at the time of boron implantation has a maximum value of a boron concentration profile in the semiconductor region that becomes the field oxide film,
The step of ion-implanting the phosphorus is a step of ion-implanting so that the dose amount is 30 to 80% of the ion implantation dose amount of boron when the film thickness of the field oxide film is 300 to 800 nm, or When the field oxide film has a thickness of 800 to 1500 nm, it is a step of ion implantation so that the dose is 25 to 70% of the boron ion implantation dose.
A method for manufacturing a semiconductor device.

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