JP4457426B2 - Manufacturing method of semiconductor device - Google Patents

Description

[0001]
BACKGROUND OF THE INVENTION
The present invention relates to a method for manufacturing a semiconductor device, and more particularly to a method for manufacturing a semiconductor device having a fine contact junction.
[0002]
[Prior art]
As seen in recent VLSI and the like, as the miniaturization, higher integration and higher performance of semiconductor devices progress, silicon oxide (SiO 2)₂ As for the dry etching of the inter-layer insulating layer made up of, etc.), the technical elements are becoming increasingly strict.
For example, the distance between the gate electrode of a MOS (Metal-Oxide-Semiconductor) transistor and the contact hole to the source / drain diffusion layer is becoming shorter. For this reason, the gate electrode and the contact to the source / drain diffusion layer are short-circuited due to misalignment in the lithography process for forming the contact hole.
[0003]
In order to avoid the above problem, the top and side walls of the gate electrode are covered with a material different from the interlayer insulating film, such as silicon nitride, to prevent the contact with or close to the gate electrode, and to align the contact hole. Self-aligned contact (hereinafter abbreviated as SAC) technology that can eliminate the design margin on the mask has been developed and proposed, and active research on SAC has been conducted to date.
[0004]
Similarly to the above SAC, there is a problem that the contact is disposed on the element isolation region due to misalignment between the contact hole and the source / drain diffusion layer, and the element isolation insulating film is etched when the contact hole is formed. . This will be described with reference to the drawings.
FIG. 14A is a cross-sectional view of the semiconductor device before the step of forming a contact hole.
A gate insulating film 22 made of silicon oxide is formed on an active region separated by an STI (Shallow Trench Isolation) type element isolation insulating film 21 embedded in the element isolation trench T of the silicon semiconductor substrate 10. A gate electrode 32 having a polycide structure including a lower gate electrode 30a made of polysilicon and an upper gate electrode 31a made of tungsten silicide is formed in the upper layer.
A sidewall insulating film 24 a that is made of, for example, silicon nitride and serves as an LDD (Lightly Doped Drain) spacer is formed so as to cover the sidewall of the gate electrode 32, and the semiconductor substrate 10 on both sides of the gate electrode 32 has a low A source / drain diffusion layer having an LDD structure composed of the concentration diffusion layer 11 and the high concentration diffusion layer 12 is formed, and a MOS transistor is formed.
[0005]
An interlayer insulating film 26 made of, for example, silicon oxide is formed on the entire surface so as to cover the transistor, and a resist film R to which an opening pattern of a contact hole is transferred is formed thereon._CHIs formed.
Here, it is assumed that the opening portion of the contact hole opening pattern covers the STI element isolation insulating film 21 due to misalignment or the like in the photolithography process.
[0006]
From the above structure, the resist film R_CHBy using RIE (reactive ion etching) or the like as a mask, a contact hole CH is opened in the interlayer insulating film 26 as shown in FIG. 14B. Since the opening portion of the opening pattern covers the STI element isolation insulating film 21, the element isolation insulating film portion X in the contact hole CH is also etched, and the surface of the silicon semiconductor substrate 10 in the element isolation trench T is exposed. Therefore, when a buried electrode or the like is formed in the contact hole CH, there arises a problem that the junction leakage current increases.
[0007]
In order to prevent even the element isolation insulating film portion in the contact hole from being etched, a method of covering and protecting the source / drain diffusion layer and the element isolation insulating film with an etching stopper film made of, for example, silicon nitride Has been developed.
FIG. 15A is a cross-sectional view of the semiconductor device before the step of forming contact holes.
The above semiconductor device is different from the semiconductor device shown in FIG. 14A in that a transistor is covered and a silicon nitride etching stopper film 25 is formed on the entire surface, and a silicon oxide interlayer insulating film is formed thereon. It is different that it is formed.
[0008]
When a contact hole is opened for the above structure, the resist film R_CHAs a mask, etching is performed with an etching stopper film 25 such as RIE (reactive ion etching) under conditions that slow the etching, and the etching is once stopped on the etching stopper film 25 as shown in FIG. .
[0009]
Next, as shown in FIG. 15C, the etching stopper film 25 in the contact hole CH is etched by changing the etching conditions so as to selectively remove silicon nitride exposed in the contact hole CH. And the source / drain diffusion layer is exposed.
In the subsequent steps, a buried semiconductor electrode is formed in the contact hole CH to form a desired semiconductor device.
[0010]
According to the manufacturing method of the semiconductor device described above, it is possible to prevent even the element isolation insulating film portion in the contact hole from being etched, and the problem that the junction leakage current increases can be avoided.
In recent years, the layout has been gradually reduced in order to further improve the degree of integration, and accordingly, the contact to the diffusion layer is formed in a self-aligned manner with respect to the gate electrode, It is necessary to achieve both prevention of element isolation insulating film etching during contact formation.
[0011]
A method for manufacturing a semiconductor device will be described in which a contact to the diffusion layer is formed in a self-aligned manner with respect to the gate electrode and an element isolation insulating film is prevented from being etched when the contact is formed.
First, as shown in FIG. 16A, silicon nitride is deposited on the silicon semiconductor substrate 10 by, for example, a CVD (Chemical Vapor Deposition) method, and an active region, for example, a region (DRAM) portion and a logic portion are formed. A resist film (not shown) having a pattern opening the element isolation region except for the region 2 to be formed is formed, and silicon nitride in the element isolation region is removed by etching such as RIE (reactive ion etching) to form an element isolation groove. A mask layer 20 is formed.
Here, the gate electrode having a gate line width of 0.13 μm is used for the region 1 so that the interval between the gate electrodes of the plurality of transistors is 0.18 μm in the subsequent steps, while the region 2 is 0.24 μm. Is a region to form.
[0012]
Next, as illustrated in FIG. 16B, etching such as RIE is performed using the mask layer 20 as a mask to form element isolation trenches T in the semiconductor substrate 10.
[0013]
Next, as shown in FIG. 16C, after forming a trench inner wall protective film (not shown) on the inner wall of the element isolation trench T by, for example, thermal oxidation, a trench-shaped element is formed by, for example, high-density plasma CVD. After the silicon oxide is deposited on the entire surface while filling the isolation trench T, the element isolation insulating film 21 is formed by polishing from the upper surface of the silicon oxide film using the mask layer 20 as a stopper by a CMP (Chemical Mechanical Polishing) method.
[0014]
Next, as shown in FIG. 17D, the mask layer 20 is removed by wet etching such as hot phosphoric acid. At this time, the element isolation insulating film 21 has a shape protruding from the surface of the semiconductor substrate 10 by an amount corresponding to the thickness of the mask layer 20 after the CMP process.
[0015]
Next, as shown in FIG. 17E, after forming a well by ion implantation, a silicon oxide layer is formed to a thickness of several nanometers by, for example, a thermal oxidation method to form a gate insulating film 22.
Next, polysilicon is deposited to a thickness of 70 nm on the upper layer of the gate insulating film 22 by, for example, the CVD method to form the lower gate electrode layer 30.
Next, tungsten nitride and tungsten are stacked to a thickness of 5 nm and 60 nm, respectively, by CVD, for example, and the upper gate electrode layer 31 is formed.
Next, an offset insulating film 23 is formed by depositing silicon nitride with a film thickness of 100 nm by, for example, the CVD method.
[0016]
Next, as shown in FIG. 17F, a resist film R is formed on the pattern of the gate electrode by a photolithography process, and etching such as RIE is performed using the resist film R as a mask to form the upper gate electrode layer 31 and the lower layer. The gate electrode layer 30 is patterned in order to comprise a polysilicon lower gate electrode 30a and an upper gate electrode 31a which is a laminate of tungsten nitride and tungsten, and a gate electrode 32 with an offset insulating film 23a of silicon nitride. Form.
Here, as described above, in the region 1, the gate electrode 32 has an interval b between the gate electrodes of a plurality of transistors.₁On the other hand, in the region 2, the gate electrode spacing b is 0.18 μm.₂Are each formed to have a gate line width a of 0.13 μm.
At this time, the thin gate insulating film 22 is also processed into a gate electrode pattern.
[0017]
Next, as shown in FIG. 18 (g), using the gate electrode 32 as a mask, a conductive impurity D 1 such as phosphorus or boron is ion-implanted, and the impurity is reduced in the active region of the semiconductor substrate 10 on both sides of the gate electrode 32. A concentration diffusion layer 11 is formed.
[0018]
Next, as shown in FIG. 18H, the gate electrode 32 is covered by, for example, the CVD method, and silicon nitride is deposited on the entire surface to a thickness of 70 nm to form the sidewall insulating film layer 24.
[0019]
Next, as shown in FIG. 18 (i), etch back is performed by etching such as RIE, for example, and the other portions except for the sidewall insulating film layers 24 on both sides of the gate electrode 32 are removed. A sidewall insulating film 24a having a film thickness of about 70 nm which is substantially the same as the film thickness and serving as an LDD spacer is formed.
Therefore, at this time, the interval of the sidewall insulating film 24a between the gate electrodes 32 in the region 1 is 0.04 μm, and in the region 2, it is 0.10 μm.
[0020]
Next, as shown in FIG. 19 (j), the conductive impurity D 2 is ion-implanted using the sidewall insulating film 24 a as a mask, and the low concentration diffusion layer 11 is formed in the active region of the semiconductor substrate 10 on both sides of the gate electrode 32. A high concentration diffusion layer 12 connected to is formed. Thereby, a source / drain diffusion layer having an LDD structure is formed.
[0021]
Next, as shown in FIG. 19K, the entire surface including the offset insulating film 23a, the sidewall insulating film 24a, the upper layer of the high-concentration diffusion layer 12 and the upper layer of the element isolation insulating film 21 is nitrided by, eg, CVD. Silicon is deposited with a thickness of 20 nm to form an etching stopper film 25.
Here, in the region 1, the space between the sidewall insulating films 24 a between the gate electrodes 32 is filled with the etching stopper film 25.
[0022]
Next, as shown in FIG. 19L, silicon oxide such as BPSG is deposited by, for example, a CVD method, and planarized by reflow, etchback, CMP, or the like, thereby forming an interlayer insulating film 26. Next, as shown in FIG.
[0023]
Next, as shown in FIG. 20M, a resist film (not shown) having an opening pattern of contact holes is formed on the interlayer insulating film 26 by a photolithography process, and an etching stopper such as RIE or plasma etching is formed. Etching is performed on the film 25 so that the etching is slow, and the first contact hole CH1 is opened in the region 1 and the second contact hole CH2 is opened in the region 2. Etching is stopped once at the etching stopper film 25.
[0024]
Next, as shown in FIG. 20 (n), the etching stoppers in the contact holes CH are changed by changing the etching conditions so as to selectively remove the silicon nitride exposed in the contact holes CH1 and CH2. The film 25 is removed to expose the source / drain diffusion layer.
In this way, the etching stopper film 25 covers the upper layer of the source / drain diffusion layer and the element isolation insulating film, and once the etching is stopped and the source / drain diffusion layer region is opened again. Etching of the isolation insulating film can be prevented.
In addition, since the upper and side walls of the gate electrode are covered with a material different from the interlayer insulating film such as silicon nitride, the contact is opened in a self-aligned manner with respect to the diffusion layer, It is possible to prevent the contact from contacting or approaching the gate electrode.
[0025]
In the subsequent steps, for example, the contact hole is filled with tungsten to form a plug connected to the source / drain diffusion layer, and an upper layer wiring such as aluminum is formed on the upper layer to achieve a desired semiconductor device.
[0026]
[Problems to be solved by the invention]
However, in the above method for manufacturing a semiconductor device, in the step of removing the etching stopper film in the contact hole CH by etching under conditions that selectively remove silicon nitride exposed in the contact hole, in the region 2 A portion 25a of the sidewall-like etching stopper film is formed to open a contact hole reaching the high concentration diffusion layer 12, and in the region 1 not in the region between the gate electrodes 32, the high concentration diffusion layer 12 is formed. The reaching contact hole is opened. On the other hand, the portion between the gate insulating film 24a between the gate electrodes 32 in the region 1 is buried in the etching stopper film 25, so that FIG. As shown, the silicon nitride film 25c is left in the contact hole. My, becomes defective opening, contact failure occurs in the contact.
[0027]
In order to avoid the above problem, when the thickness of the side wall insulating film serving as the LDD spacer is reduced and the space between the side wall insulating films between the gate electrodes is widened, there is no problem in opening the contact hole. In this case, the width of the LDD spacer is reduced, that is, another problem arises in that the LDD width is reduced and the short channel effect of the transistor is increased.
In particular, in the salicide process in which a silicide layer is formed in a self-aligned manner in the source / drain diffusion layer, the silicide layer becomes too close to the channel formation region of the transistor, and the transistor due to the diffusion of refractory metal and stress due to the silicide layer. This increases the short channel effect and increases the leakage current in the diffusion layer around the gate electrode.
[0028]
The present invention has been made in view of the above situation, and therefore the present invention can stably open a self-aligned contact hole without deteriorating transistor characteristics such as an increase in the short channel effect of the transistor. An object is to provide a method for manufacturing a semiconductor device.
[0037]
[Means for Solving the Problems]
  In order to achieve the above object, a method of manufacturing a semiconductor device according to the present invention includes a step of forming a conductive layer on the semiconductor substrate in the first region and the second region of the semiconductor substrate, and the first region and the second region. Forming an offset insulating film on the conductive layer in two regions, forming a sidewall insulating film on the sidewalls of the offset insulating film and the conductive layer in the first region and the second region, and A step of covering the offset insulating film, the sidewall insulating film and the semiconductor substrate in the first region and the second region to form an etching stopper film; and in the first region, the sidewall insulating film and Using the etching stopper film as a mask, conductive impurities are introduced while passing through the etching stopper film in the upper layer portion of the semiconductor substrate. Forming a first impurity-containing region containing a first concentration of conductive impurities in the semiconductor substrate; and leaving the etching stopper film at least in a sidewall portion of the sidewall insulating film in the second region. However, the step of removing the etching stopper film at least in a portion covering the semiconductor substrate, and conducting in the second region by using the sidewall insulating film and the etching stopper film on the sidewall portion of the sidewall insulating film as a mask. Forming a second impurity-containing region containing a second concentration of conductive impurities in the semiconductor substrate, and forming an insulating film on the entire surface in the first and second regions. And a selection ratio with respect to the etching stopper film in the first region and the second region. Then, by etching to remove the insulating film in the contact hole opening region, the etching stopper film is exposed in the contact hole opening region in the first region, and in the contact hole opening region in the second region. AboveSecondA step of opening a contact hole exposing the impurity-containing region; and removing the etching stopper film exposed in the contact hole opening region in the first region,FirstAnd a step of opening a contact hole that exposes the impurity-containing region.And carry out the above steps sequentially..
[0038]
In the method for manufacturing a semiconductor device according to the present invention, preferably, after the step of forming the offset insulating film in the first region and the second region, before the step of forming the sidewall insulating film, Conductive impurities are introduced using the offset insulating film as a mask, and a third impurity-containing region containing a third concentration of conductive impurities lower than the first concentration and the second concentration in the semiconductor substrate In the first region, the step of forming the first impurity-containing region is formed by connecting to the third impurity-containing region, and the second region includes the second impurity-containing region. In the step of forming the impurity-containing region, the impurity-containing region is formed in connection with the third impurity-containing region.
[0039]
In the method of manufacturing a semiconductor device according to the present invention, preferably, after the step of forming the second impurity-containing region in the second region, before the step of forming the insulating film in the first region and the second region. And forming a metal silicide layer on a surface layer portion of the second impurity-containing region in the second region, and exposing the second impurity-containing region in the contact hole opening region in the second region. In the step of forming, the metal silicide layer formed in the surface layer portion of the second impurity-containing region is exposed.
[0040]
Preferably, in the semiconductor device manufacturing method of the present invention, at least the first region and the second region of the semiconductor substrate are formed before the step of forming the conductive layer in the first region and the second region. The method further includes a step of forming an element isolation insulating film in an element isolation region that is separated into regions, and in the step of forming the etching stopper film, the element isolation insulating film is further covered. More preferably, in the step of opening the contact hole in the first region, the contact hole opening region includes a part of the element isolation region.
[0041]
In the method of manufacturing a semiconductor device according to the present invention, preferably, after the step of opening the contact hole in the first region, the contact hole is filled with a conductor and connected to the first impurity-containing region. It further has the process of forming an electrode. Preferably, after the step of opening the contact hole in the second region, the method further includes a step of forming a buried electrode connected to the second impurity-containing region by filling the contact hole with a conductor.
[0042]
In the method for manufacturing a semiconductor device according to the present invention, preferably, the etching stopper film is formed of a silicon nitride-containing layer in the first region and the second region, and in the first region and the second region, An insulating film is formed of a silicon oxide containing layer. More preferably, in the first region and the second region, the offset insulating film and the sidewall insulating film are formed of a silicon nitride-containing layer.
[0043]
In the method of manufacturing a semiconductor device according to the present invention, preferably, the step of forming the element isolation insulating film includes a step of forming an element isolation groove in the semiconductor substrate, and the element isolation groove by an insulator. Embedding. More preferably, the element isolation insulating film is formed of a silicon oxide-containing layer.
[0044]
In the semiconductor device manufacturing method of the present invention, an element isolation insulating film is formed in an element isolation region of a semiconductor substrate, and a conductive layer is formed on the semiconductor substrate in the first region and the second region separated by the element isolation insulating film. Forming an offset insulating film over the conductive layer, introducing a conductive impurity using the offset insulating film as a mask, and forming a third impurity-containing region containing the conductive impurity at a third concentration in the semiconductor substrate; Then, sidewall insulating films are formed on the side walls of the offset insulating film and the conductive layer.
Next, in the first region and the second region, an etching stopper film is formed so as to cover the offset insulating film, the sidewall insulating film, the semiconductor substrate (third impurity-containing region), and the element isolation insulating film.
Next, in the first region, conductive impurities are introduced while passing through the etching stopper film in the upper layer portion of the semiconductor substrate (third impurity-containing region) using the sidewall insulating film and the etching stopper film as a mask. A first impurity containing region connected to the third impurity containing region is formed by containing conductive impurities at a first concentration higher than the third concentration.
Next, in the second region, at least the etching stopper film covering the semiconductor substrate (third impurity-containing region) is removed while leaving the etching stopper film at least on the side wall portion of the sidewall insulating film, and the sidewall insulating film is removed. A conductive impurity is introduced using the etching stopper film on the side wall portion of the sidewall insulating film as a mask, and the conductive impurity is contained in the semiconductor substrate at a second concentration higher than the third concentration. A second impurity-containing region connected to the impurity-containing region is formed.
Next, an insulating film is formed on the entire surface in the first region and the second region, and etching is performed to remove the insulating film in the contact hole opening region with a selection ratio with respect to the etching stopper film. An etching stopper film is exposed in the contact hole opening region, and a contact hole is formed in the second region to expose the second impurity-containing region in the contact hole opening region.
Next, in the first region, the etching stopper film exposed in the contact hole opening region is removed to open a contact hole exposing the first impurity-containing region.
[0045]
According to the above-described method for manufacturing a semiconductor device of the present invention, in the first region, the etching stopper film in the upper layer portion of the semiconductor substrate (third impurity-containing region) is transmitted through the sidewall insulating film and the etching stopper film as a mask. While introducing conductive impurities, the first impurity-containing region is formed.
On the other hand, in the second region, the etching stopper film covering the semiconductor substrate (third impurity-containing region) is removed while leaving the etching stopper film on the side wall portion of the sidewall insulating film, and the sidewall insulating film Conductive impurities are introduced using the etching stopper film in the sidewall portion of the sidewall insulating film as a mask to form a second impurity-containing region.
Therefore, in the first region, the sidewall insulating film and the etching stopper film have a function as an LDD spacer. Therefore, even if the thickness of the sidewall insulating film is reduced, transistor characteristics such as an increase in the short channel effect of the transistor can be obtained. The sidewall insulating film between the gate electrodes is buried in the etching stopper film because the thickness of the sidewall insulating film can be reduced. It is possible to prevent the occurrence of defective opening in the step of preventing and removing the etching stopper film in the contact hole, and to stably open the self-aligned contact hole.
On the other hand, in the second region, the sidewall insulating film and the etching stopper film on the sidewall portion of the sidewall insulating film function as an LDD spacer. Therefore, even if the sidewall insulating film is thin, The transistor can be formed without deteriorating transistor characteristics such as an increase in the short channel effect. Further, since the etching stopper film covering the semiconductor substrate (the third impurity-containing region) is removed, a silicide layer can be formed in a self-aligned manner on the source / drain diffusion layer. The silicide stopper is not too close to the channel formation region of the transistor by the etching stopper film on the side wall portion of the film and the side wall insulating film, the short channel effect is suppressed, and the leakage current in the diffusion layer around the gate electrode is suppressed. It can be formed while suppressing the increase.
[0046]
DETAILED DESCRIPTION OF THE INVENTION
Embodiments of the present invention will be described below with reference to the drawings.
[0047]
First embodiment
The semiconductor device according to the present embodiment is a semiconductor device having contact connection by SAC, and FIG. 1 is a sectional view thereof.
An element isolation trench T is formed in the silicon semiconductor substrate 10 in an element isolation region that is divided into an active region, for example, a region 1 that is a DRAM (memory) portion and a region 2 that is a logic portion, and is made of, for example, silicon oxide. An element isolation insulating film 21 is embedded.
[0048]
In the region 1, the upper layer of the semiconductor substrate 10 is composed of a polysilicon lower gate electrode 30a with a gate insulating film 22 interposed therebetween and an upper gate electrode 31a that is a laminate of tungsten nitride and tungsten. A gate electrode 32 with an offset insulating film 23a is formed.
Further, in the semiconductor substrate 10 on both sides of the gate electrode 32, a low concentration diffusion layer 11 containing a low concentration of conductive impurities and a high concentration diffusion layer 12 containing a high concentration are formed, and LDD (Lightly A source / drain diffusion layer having a Doped Drain structure is formed.
A sidewall insulating film 24a made of, for example, silicon nitride is formed on both sides of the gate electrode 32, and an etching stopper film 25 of silicon nitride is formed over the entire region 1 on the upper layer. The LDD width of the source / drain diffusion layer is determined by the thickness of the sidewall insulating film 24a and the etching stopper film 25.
[0049]
A silicon oxide-based interlayer insulating film 26 such as BPSG (silicon oxide containing boron and phosphorus) is formed on the etching stopper film 25.
In the interlayer insulating film 26 and the etching stopper film 25, a first contact hole CH1 reaching the high concentration diffusion layer 12 is opened. In the first contact hole CH1 opened in the region between the gate electrodes, the first contact reaching the high concentration diffusion layer 12 while leaving a part 25b of the etching stopper film on the side of the sidewall insulating film 24a. A hole CH1 is opened.
An adhesion layer 33 that is, for example, a laminate of titanium and titanium nitride is formed so as to cover the inner wall of the first contact hole CH1, and a plug 34a made of, for example, tungsten is formed so as to embed the first contact hole in the upper layer. Further, an upper layer wiring 35 made of, for example, aluminum is formed on the upper layer.
[0050]
Next, a method for manufacturing the semiconductor device will be described.
First, as shown in FIG. 2A, silicon nitride is deposited on the silicon semiconductor substrate 10 by, for example, a CVD (Chemical Vapor Deposition) method, and an active region, for example, a region (DRAM) portion and a logic portion are formed. A resist film (not shown) having a pattern opening the element isolation region except for the region 2 to be formed is formed, and silicon nitride in the element isolation region is removed by etching such as RIE (reactive ion etching) to form an element isolation groove. A mask layer 20 is formed.
Here, the gate electrode having a gate line width of 0.13 μm is used for the region 1 so that the interval between the gate electrodes of the plurality of transistors is 0.18 μm in the subsequent steps, while the region 2 is 0.24 μm. Is a region to form.
[0051]
Next, as shown in FIG. 2B, etching such as RIE is performed using the mask layer 20 as a mask to form element isolation trenches T in the semiconductor substrate 10.
[0052]
Next, as shown in FIG. 2C, after forming a trench inner wall protective film (not shown) on the inner wall of the element isolation trench T by, for example, thermal oxidation, a trench-shaped element is formed by, for example, high-density plasma CVD. After the silicon oxide is deposited on the entire surface while filling the isolation trench T, the element isolation insulating film 21 is formed by polishing from the upper surface of the silicon oxide film using the mask layer 20 as a stopper by a CMP (Chemical Mechanical Polishing) method.
[0053]
Next, as shown in FIG. 3D, the mask layer 20 is removed by wet etching such as hot phosphoric acid. At this time, the element isolation insulating film 21 has a shape protruding from the surface of the semiconductor substrate 10 by an amount corresponding to the thickness of the mask layer 20 after the CMP process.
[0054]
Next, as shown in FIG. 3E, after well formation or channel impurity introduction by ion implantation, a silicon oxide layer is formed to a thickness of several nm (eg, 3 nm) by, eg, thermal oxidation. The gate insulating film 22 is used.
Next, polysilicon is deposited to a thickness of 70 nm on the upper layer of the gate insulating film 22 by, for example, the CVD method to form the lower gate electrode layer 30.
Next, tungsten nitride and tungsten are stacked to a thickness of 5 nm and 60 nm, respectively, by CVD, for example, and the upper gate electrode layer 31 is formed.
Next, an offset insulating film 23 is formed by depositing silicon nitride with a film thickness of 100 nm by, for example, the CVD method.
[0055]
Next, as shown in FIG. 3F, a resist film R is formed on the gate electrode pattern by a photolithography process, and etching such as RIE is performed using the resist film R as a mask to form the upper gate electrode layer 31 and the lower layer. The gate electrode layer 30 is patterned in order to comprise a polysilicon lower gate electrode 30a and an upper gate electrode 31a which is a laminate of tungsten nitride and tungsten, and a gate electrode 32 with an offset insulating film 23a of silicon nitride. Form.
Here, as described above, in the region 1, the gate electrode 32 has an interval b between the gate electrodes of a plurality of transistors.₁On the other hand, in the region 2, the gate electrode spacing b is 0.18 μm.₂Are each formed to have a gate line width a of 0.13 μm.
At this time, the thin gate insulating film 22 is also processed into a gate electrode pattern.
[0056]
Next, as shown in FIG. 4G, using the gate electrode 32 as a mask, a conductive impurity D1 such as phosphorus or boron is ion-implanted, and the active region of the semiconductor substrate 10 on both sides of the gate electrode 32 is implanted. A low concentration diffusion layer 11 is formed.
[0057]
Next, as shown in FIG. 4H, the gate electrode 32 is covered by, eg, CVD, and silicon nitride is deposited on the entire surface to a thickness of 50 nm to form the sidewall insulating film layer 24.
[0058]
Next, as shown in FIG. 4I, etching back is performed by etching such as RIE, for example, and the other portions except for the side wall insulating film layers 24 on both sides of the gate electrode 32 are removed, and the film is deposited. A sidewall insulating film 24a having a film thickness of about 50 nm which is substantially the same as the film thickness is formed.
Accordingly, at this time, the interval of the sidewall insulating film 24a between the gate electrodes 32 in the region 1 is 0.08 μm, and in the region 2, it is 0.14 μm.
[0059]
Next, as shown in FIG. 5J, the entire surface including the offset insulating film 23a, the sidewall insulating film 24a, the upper layer of the low concentration diffusion layer 11 and the upper layer of the element isolation insulating film 21 is nitrided by, eg, CVD. Silicon is deposited with a thickness of 20 nm to form an etching stopper film 25.
Here, in the region 1, the space between the sidewall insulating films 24 a between the gate electrodes 32 is not completely filled with the etching stopper film 25, and has a gap of, for example, 0.04 μm.
[0060]
Next, as shown in FIG. 5 (k), a resist film R2 that protects the region 2 and opens the region 1 is formed, and low concentration diffusion is performed in the region 1 using the sidewall insulating film 24a and the etching stopper film 25 as a mask. Conductive impurities D2 are ion-implanted so as to have a higher concentration than the layer 11, and the high concentration diffusion layer 12 connected to the low concentration diffusion layer 11 is formed in the active region of the semiconductor substrate 10 on both sides of the gate electrode 32. . Thereby, a source / drain diffusion layer having an LDD structure is formed.
[0061]
Next, as shown in FIG. 5L, a resist film R3 that protects the region 1 and opens the region 2 is formed, and the region 2 is etched back by etching such as RIE to form the sidewall insulating film 24a. The other portions of the side wall-like etching stopper film 25a are removed except for the portions 25a.
[0062]
Next, as shown in FIG. 6 (m), the conductive impurity D3 is added in the region 2 so as to have a higher concentration than the low concentration diffusion layer 11 using the sidewall insulating film 24a and the etching stopper film part 25a as a mask. Ions are implanted to form a high concentration diffusion layer 12 connected to the low concentration diffusion layer 11 in the active region of the semiconductor substrate 10 on both sides of the gate electrode 32. As a result, a source / drain diffusion layer having an LDD structure is also formed in the region 2.
Next, for example, a lamp annealing process is performed at 1000 ° C. for 10 seconds in a nitrogen atmosphere to activate and diffuse the conductive impurities in the low concentration diffusion layer 11 and the high concentration diffusion layer 12 in the regions 1 and 2.
[0063]
Next, as shown in FIG. 6 (n), after removing the resist film R3, for example, a metal such as cobalt is deposited on the entire surface at a substrate temperature of 450 ° C. to a thickness of 10 nm, and lamp annealing is performed at 550 ° C. for 30 seconds. Is processed to cause silicidation by reacting a metal such as cobalt with silicon of the substrate, and removing the unreacted metal such as cobalt by sulfuric acid / hydrogen peroxide so that the cobalt in a self-aligned manner with respect to the high concentration diffusion layer in the region 2. A metal silicide layer 13 such as a silicide layer is formed.
[0064]
Next, as shown in FIG. 6 (o), for example, a silicon oxide such as BPSG is deposited with a film thickness of 1200 nm by a CVD method and planarized by an etch back or a CMP method to form an interlayer insulating film with a film thickness of 700 nm. 26 is formed. Further, it can be flattened by reflow or the like.
[0065]
Next, as shown in FIG. 7 (p), a resist film (not shown) having a contact hole opening pattern is formed on the interlayer insulating film 26 by a photolithography process, and an etching stopper such as RIE or plasma etching is formed. In the region 1, etching corresponding to a film thickness of 900 nm of silicon oxide is performed under such a condition that the etching is slow in the film 25 (for example, a condition in which silicon oxide is removed at an etching rate 20 times that of silicon nitride). A first contact hole CH1 exposing the etching stopper film 25 and a second contact hole CH2 exposing the metal silicide layer 13 in the region 2 are opened.
Here, as etching conditions, for example (RF power: 2 kW, gas flow rate: Ar / O₂/ C_FourF₈= 200/10/20 sccm, pressure: 5 Pa).
[0066]
Next, as shown in FIG. 7 (q), by changing the etching conditions, for example, under the condition that silicon nitride is removed at an etching rate 7 times that of silicon oxide, the film thickness corresponds to 30 nm of silicon nitride. By this etching, the silicon nitride (etching stopper film 25) exposed in the first contact hole CH1 is selectively removed, and the high concentration diffusion layer 12 is exposed.
Here, as etching conditions, for example (RF power: 500 W, gas flow rate: Ar / O₂/ CHF_Three= 100/10/20 sccm, pressure: 5 Pa).
In this way, the etching stopper film 25 covers the upper layer of the source / drain diffusion layer and the element isolation insulating film, and once the etching is stopped and the source / drain diffusion layer region is opened again. Etching of the isolation insulating film can be prevented.
In addition, since the upper and side walls of the gate electrode are covered with a material different from the interlayer insulating film such as silicon nitride, the contact is opened in a self-aligned manner with respect to the diffusion layer, It is possible to prevent the contact from contacting or approaching the gate electrode.
[0067]
Next, as shown in FIG. 8 (r), for example, titanium and titanium nitride are deposited to a thickness of 20 nm and 50 nm, respectively, in the contact hole to form an adhesion layer 33, and further, tungsten is deposited to a thickness of 250 nm by CVD. The plug layers 34 are formed by depositing the film thickness to fill the contact holes CH1 and CH2.
[0068]
Next, as shown in FIG. 8S, the plug layer 34 and the adhesion layer 33 deposited outside the contact holes CH1 and 2 are removed by, for example, a CMP method, and the contact holes CH1 and 2 are embedded. The adhesion layer 33 and the plug 34a are formed.
[0069]
In the subsequent steps, the upper layer wiring 35 is formed of a conductive material such as aluminum on the plug 34a, whereby the semiconductor device shown in FIG. 1 can be obtained.
[0070]
According to the manufacturing method of the semiconductor device of the present embodiment, the conductive impurity D2 is ion-implanted in the region 1 using the sidewall insulating film 24a and the etching stopper film 25 as a mask. Therefore, the sidewall insulating film 24a and the etching stopper are used. The film 25 has a function as an LDD spacer, and can be formed without deteriorating the transistor characteristics such as an increase in the short channel effect of the transistor even when the sidewall insulating film is thin.
[0071]
In the region 2, since the conductive impurity D3 is ion-implanted using the sidewall insulating film 24a and a part of the etching stopper film 25a on the side wall of the sidewall insulating film as a mask, the sidewall insulating film 24a and the etching stopper are used. A part of the film 25a functions as an LDD spacer, and can be formed without deteriorating the transistor characteristics such as an increase in the short channel effect of the transistor even when the sidewall insulating film is thin.
Furthermore, in the step of forming the silicide layer in a self-aligned manner with respect to the high concentration diffusion layer, the region 1 is covered with the etching stopper film, so that silicidation is not performed, and the source / drain diffusion layer self-alignment is performed in the region 2. A silicide layer can be formed in a consistent manner. Even in this case, the silicide layer is not too close to the channel formation region of the transistor by the sidewall insulating film and the etching stopper film on the side wall portion of the sidewall insulating film, and the short channel effect is suppressed, and the peripheral portion of the gate electrode is suppressed. It can be formed while suppressing an increase in leakage current in the diffusion layer.
[0072]
According to the semiconductor device manufacturing method described above, it is possible to form contacts in the diffusion layer between the gate electrodes at a narrower gap between the gate electrodes, further reducing the design rule, improving the degree of integration, and operating the semiconductor device. High speed, low power consumption and low cost are possible.
Further, the contact etching stopper film can also function as a silicidation preventing film in the salicide process, and the salicide portion can be formed without increasing the number of steps.
[0073]
Second embodiment
The semiconductor device according to the present embodiment is substantially the same as the semiconductor device according to the first embodiment, and a cross-sectional view thereof is shown in FIG.
The semiconductor device according to the first embodiment is different in that a plug 36a made of, for example, polysilicon is formed in the first contact hole CH1 in the region 1.
[0074]
A method for manufacturing the semiconductor device will be described.
First, the process up to the state shown in FIG. 10A is formed in the same manner as the process shown in FIG. 6O in the first embodiment.
[0075]
Next, as shown in FIG. 10B, the entire region 2 is protected by a photolithography process, and a resist film (not shown) having a contact hole opening pattern only in the region 1 is formed on the interlayer insulating film 26. A pattern is formed, and RIE or plasma etching or other etching stopper film 25 is used so that etching is slow (for example, silicon oxide is removed at an etching rate 20 times that of silicon nitride). Etching corresponding to the film thickness is performed, and a first contact hole CH1 exposing the etching stopper film 25 is opened.
Here, as etching conditions, for example (RF power: 2 kW, gas flow rate: Ar / O₂/ C_FourF₈= 200/10/20 sccm, pressure: 5 Pa).
[0076]
Next, as shown in FIG. 11C, the etching conditions are changed, and for example, silicon nitride is removed at an etching rate 7 times that of silicon oxide. By this etching, the silicon nitride (etching stopper film 25) exposed in the first contact hole CH1 is selectively removed, and the high concentration diffusion layer 12 is exposed.
Here, as etching conditions, for example (RF power: 500 W, gas flow rate: Ar / O₂/ CHF_Three= 100/10/20 sccm, pressure: 5 Pa).
[0077]
Next, as shown in FIG. 11D, the plug contact layer 36 is formed by filling the first contact hole CH1 and depositing polysilicon on the entire surface by, eg, CVD.
[0078]
Next, as shown in FIG. 12E, the polysilicon deposited outside the first contact hole CH1 is removed by etch back or CMP, and the plug 36a embedded in the first contact hole CH1 is removed. Form.
[0079]
Next, as shown in FIG. 12F, the entire region 1 is protected by a photolithography process, and a resist film (not shown) having a contact hole opening pattern only in the region 2 is formed on the interlayer insulating film 26. A pattern is formed, and RIE or plasma etching or other etching stopper film 25 is used so that etching is slow (for example, silicon oxide is removed at an etching rate 20 times that of silicon nitride). Etching corresponding to the film thickness is performed to open a second contact hole CH2 exposing the metal silicide layer 13.
Here, as etching conditions, for example (RF power: 2 kW, gas flow rate: Ar / O₂/ C_FourF₈= 200/10/20 sccm, pressure: 5 Pa).
[0080]
Next, as shown in FIG. 13G, for example, titanium and titanium nitride are deposited to a thickness of 20 nm and 50 nm in the second contact hole CH2 to form an adhesion layer 33, and further, tungsten is formed by CVD. Is deposited to a thickness of 250 nm to fill the second contact hole CH2 to form a plug layer 34.
[0081]
Next, as shown in FIG. 13H, the plug layer 34 and the adhesion layer 33 deposited outside the second contact hole CH2 are removed by, for example, the CMP method, and the second contact hole CH2 is embedded. The adhesion layer 33 and the plug 34a are formed.
[0082]
In the subsequent steps, the upper layer wiring 35 such as aluminum is formed on the upper layers of the plugs 34a and 36a, whereby the semiconductor device shown in FIG. 9 can be obtained.
[0083]
According to the manufacturing method of the semiconductor device of the present embodiment, as in the first embodiment, the short channel effect of the transistor is increased even if the sidewall insulating film is thin in the regions 1 and 2. For example, it can be formed without deteriorating the transistor characteristics.
[0084]
The present invention relates to a semiconductor device in which a contact hole is formed in a region between electrodes having a narrow interval formed on a semiconductor substrate in a semiconductor device of a MOS transistor such as a DRAM, for example, a semiconductor device in which a DRAM and a logic circuit are mixedly mounted. Any device manufacturing method can be applied.
[0085]
The present invention is not limited to the above embodiment.
For example, each of the offset insulating film and the sidewall insulating film may be a single layer or may have a multilayer structure or more. It is also possible to form with an insulating material other than silicon nitride.
The interlayer insulating film formed so as to cover the inner wall of the contact hole may have a single layer structure or a multilayer structure.
Further, the etching stopper film can be composed of other insulating materials, and can be a single layer or a multilayer.
In addition, various changes can be made without departing from the scope of the present invention.
[0086]
【The invention's effect】
According to the present invention, it is possible to provide a method for manufacturing a semiconductor device capable of stably opening a self-aligned contact hole without deteriorating transistor characteristics such as an increase in the short channel effect of the transistor.
[Brief description of the drawings]
FIG. 1 is a cross-sectional view of a semiconductor device according to a first embodiment.
FIG. 2 is a cross-sectional view showing a manufacturing process of the manufacturing method of the semiconductor device according to the first embodiment, wherein (a) shows a process up to a mask layer forming process for forming an element isolation trench; Is up to the element isolation trench forming step, and (c) is up to the element isolation insulating film forming step.
3 is a cross-sectional view showing a continuation process of FIG. 2, in which (d) is up to the mask layer removing process, (e) is up to the offset insulating film forming process, and (f) is the gate electrode. Up to the pattern processing step is shown.
4 is a cross-sectional view showing a continuation process of FIG. 3, in which (g) shows a process up to a low concentration diffusion layer formation process, (h) shows a process up to a formation process of a side wall insulating film layer; ) Shows up to the step of forming the sidewall insulating film.
5 is a cross-sectional view showing a continuation process of FIG. 4, in which (j) is up to the etching stopper film forming process, (k) is up to the high concentration diffusion layer forming process in region 1; ) Shows the process up to the step of removing the etching stopper film on the side of the side wall insulating film in the region 2.
6 is a cross-sectional view showing a continuation process of FIG. 5, in which (m) shows a process for forming a high-concentration diffusion layer in region 2 and (n) shows the formation of a self-aligned silicide layer in region 2; Up to the process, (o) shows up to the process of forming the interlayer insulating film.
7 is a cross-sectional view showing a continuation process of FIG. 6, in which (p) shows up to a contact hole opening process and (q) shows up to an etching stopper film removal process at the bottom of the contact hole.
8 is a cross-sectional view showing a continuation process of FIG. 7, in which (r) shows up to the plug layer forming process and (s) shows up to the plug forming process.
FIG. 9 is a cross-sectional view of a semiconductor device according to a second embodiment.
FIGS. 10A and 10B are cross-sectional views showing the manufacturing process of the semiconductor device manufacturing method according to the second embodiment, wherein FIG. 10A shows the process until the formation of the interlayer insulating film, and FIG. 10B shows the contact hole in the region 1; Up to the opening process.
11 is a cross-sectional view showing a continuation process of FIG. 10, in which (c) is up to the step of removing the etching stopper film at the bottom of the contact hole in region 1 and (d) is up to the process of forming the plug layer. Indicates.
12 is a cross-sectional view showing a continuation process of FIG. 11, in which (e) shows up to a plug formation process in region 1 and (f) shows up to a contact hole opening process in region 2. FIG.
13 is a cross-sectional view showing a continuation process of FIG. 12, in which (g) shows a plug layer forming process and (h) shows a plug forming process in region 2. FIG.
FIGS. 14A and 14B are cross-sectional views showing a manufacturing process of the semiconductor device manufacturing method according to the first conventional example, wherein FIG. 14A is a process up to a resist film forming process of an opening pattern of contact holes, and FIG. Up to the hole opening process.
FIGS. 15A and 15B are cross-sectional views showing a manufacturing process of a semiconductor device manufacturing method according to a second conventional example, wherein FIG. 15A is a process up to a resist film forming process of an opening pattern of a contact hole, and FIG. (C) shows the process up to the step of removing the etching stopper film at the bottom of the contact hole.
FIG. 16 is a cross-sectional view showing a manufacturing process of a semiconductor device manufacturing method according to a third conventional example. FIG. 16 (a) shows a process up to a process of forming a mask layer for element isolation trench formation; Is up to the element isolation trench forming step, and (c) is up to the element isolation insulating film forming step.
17 is a cross-sectional view showing a continuation process of FIG. 16, in which (d) is up to the mask layer removal process, (e) is up to the offset insulating film formation process, and (f) is the gate electrode. Up to the pattern processing step is shown.
FIG. 18 is a cross-sectional view showing a continuation process of FIG. 17, (g) until the formation process of the low concentration diffusion layer, (h) until the formation process of the side wall insulating film layer; ) Shows up to the step of forming the sidewall insulating film.
FIG. 19 is a cross-sectional view showing a continuation process of FIG. 18, in which (j) is up to the high concentration diffusion layer forming process, (k) is up to the etching stopper film forming process, and (l) is the interlayer. The process up to the formation process of the insulating film is shown.
20 is a cross-sectional view showing a process continued from FIG. 19, where (m) shows a process up to a contact hole opening process, and (n) shows a process up to a process of removing an etching stopper film at the bottom of the contact hole.
[Explanation of symbols]
DESCRIPTION OF SYMBOLS 10 ... Semiconductor substrate, 11 ... Low concentration diffusion layer, 12 ... High concentration diffusion layer, 13 ... Metal silicide layer, 20 ... Mask layer, 21 ... Element isolation insulating film, 22 ... Gate insulating film, 23, 23a ... Offset insulating film 24 ... sidewall insulating film layer, 24a ... sidewall insulating film, 25, 25a, 25b, 25c ... etching stopper film, 26 ... interlayer insulating film, 30 ... lower gate electrode layer, 30a ... lower gate electrode, 31 ... upper gate electrode layer, 31a ... upper gate electrode, 32 ... gate electrode, 33 ... adhesion layer, 34, 36 ... plug layer, 34a, 36a ... plug, 35 ... upper wiring, D1, D2, D3 ... conductivity Impurities, R1, R2, R3, R_CH... resist film, CH, CH1, CH2 ... contact hole, T ... element isolation groove.

Claims (11)

Forming a conductive layer on the semiconductor substrate in the first region and the second region of the semiconductor substrate;
Forming an offset insulating film on the conductive layer in the first region and the second region; and
Forming a sidewall insulating film on a sidewall portion of the offset insulating film and the conductive layer in the first region and the second region;
Forming an etching stopper film so as to cover the offset insulating film, the sidewall insulating film, and the semiconductor substrate in the first region and the second region;
In the first region, using the sidewall insulating film and the etching stopper film as a mask, conductive impurities are introduced while passing through the etching stopper film in the upper layer portion of the semiconductor substrate, and the first region is introduced into the semiconductor substrate. Forming a first impurity-containing region containing a concentration of conductive impurities;
Removing the etching stopper film at least in a portion covering the semiconductor substrate while leaving the etching stopper film in at least a sidewall portion of the sidewall insulating film in the second region;
In the second region, a conductive impurity is introduced using the sidewall insulating film and the etching stopper film in a sidewall portion of the sidewall insulating film as a mask, and the semiconductor substrate contains a second concentration of the conductive impurity. Forming a second impurity-containing region that includes:
Forming an insulating film on the entire surface in the first region and the second region;
In the first region and the second region, the insulating film in the contact hole opening region is removed with a selection ratio with respect to the etching stopper film, so that the first region is within the contact hole opening region. Exposing the etching stopper film and opening a contact hole exposing the second impurity-containing region in the contact hole opening region in the second region;
In the first area, it possesses a step of forming a contact hole exposing the contact hole opening region of the first impurity-containing region by removing the exposed etching stopper film in,
A method for manufacturing a semiconductor device, wherein the steps are performed in the order described above . In the first region and the second region, after the step of forming the offset insulating film and before the step of forming the sidewall insulating film, a conductive impurity is introduced using the offset insulating film as a mask, and the semiconductor Forming a third impurity containing region containing a conductive impurity having a third concentration lower than the first concentration and the second concentration in the substrate;
In the first region, the step of forming the first impurity-containing region is formed by connecting to the third impurity-containing region,
In the second region, wherein in the second step of forming an impurity-containing region, the method of manufacturing a semiconductor device according to claim 1, wherein the formation connected to the third impurity concentration region. After the step of forming the second impurity-containing region in the second region and before the step of forming the insulating film in the first region and the second region, the surface layer of the second impurity-containing region in the second region A step of forming a metal silicide layer on the portion;
Wherein in the second step of exposing the second impurity concentration region in the contact hole area in the region, the semiconductor of claim 1, wherein exposing the metal silicide layer formed in a surface portion of said second impurity concentration region Device manufacturing method. In the first region and the second region, before the step of forming the conductive layer, a step of forming an element isolation insulating film in an element isolation region that separates at least the first region and the second region of the semiconductor substrate Further comprising
The etching in the stopper film forming a method of manufacturing a semiconductor device according to claim 1 wherein the forming further cover the device isolation insulating film. The method of manufacturing a semiconductor device according to claim 4 , wherein in the step of opening the contact hole in the first region, the contact hole opening region is formed so as to include a part of the element isolation region. After the step of opening the contact holes in the first region, the semiconductor device according to claim 1, further comprising a step of forming a buried electrode connected to the first impurity-containing region by filling the contact hole with a conductive material Production method. After the step of opening the contact holes in the second region, the semiconductor device according to claim 1, further comprising a step of forming a buried electrode connected to said second impurity concentration region embed the contact hole with a conductive material Production method. In the first region and the second region, the etching stopper film is formed of a silicon nitride-containing layer,
Wherein the first and second regions, the method of manufacturing a semiconductor device according to claim 1, wherein forming the insulating film of silicon oxide-containing layer. The method for manufacturing a semiconductor device according to claim 8 , wherein the offset insulating film and the sidewall insulating film are formed of a silicon nitride-containing layer in the first region and the second region. The method of manufacturing a semiconductor device according to claim 4 , wherein the step of forming the element isolation insulating film includes a step of forming an element isolation groove in the semiconductor substrate and a step of filling the element isolation groove with an insulator. The method of manufacturing a semiconductor device according to claim 10, wherein the element isolation insulating film is formed of a silicon oxide-containing layer.

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