JP4457688B2 - Semiconductor device - Google Patents

Description

The present invention is, for example, relates to a semiconductor equipment that integrates a plurality of field effect transistors.

  In order to achieve high performance, high functionality, and low power consumption, it is increasingly important to improve the performance of transistors having a plurality of threshold voltages (Vth). An example of a conventional process technology having a plurality of Vths (High Speed version, General-purpose version, Low-power version) will be described below (see Non-Patent Document 1).

  In Table II of Non-Patent Document 1, three process technologies (High Speed version, General-purpose version, and Low-power version) are first provided from the viewpoint of power consumption. For example, an HS version is used for a server in which high speed is important, and an LP version is used for a mobile in which low power consumption is important. The HS, G, and LP versions each contain an I / O transistor in the right column. Further, among the HS, G, and LP versions, transistors (Low-Vth, std-Vth, and High-Vth) having different Vth are prepared, and the designer selects them according to the circuit application. In the conventional method, a plurality of Vths are realized by changing the channel implantation concentration and the gate oxide film thickness.

  On the other hand, full silicide gate technology has been proposed for the purpose of gate depletion countermeasures (see Patent Document 1 and Non-Patent Documents 2 to 7).

JP 2000-252462 A C.C.Wu etc., “A 90-nm CMOS Device Technology with High-speed, General-purpose, and Low-leakage Transistors for System on Chip Applications”, IEDM2002 B. Tavel etc, "Totally Silicided (CoSi2) Polysilicon: a novel approach to very low-resistive gate without metal CMP nor etching", IEDM2001 Qi Xiang etc, "Strained Silicon NMOS with Nickel-Silicide Metal Gate", VLSI Symposium 2003 Z. Krivokapic, etc, “Nickel Silicide Metal Gate FDSOI Devices with Improved Gate Oxide Leakage”, IEDM2002 Jakub Kedzierski, etc, “Metal-gate FinFET and fully-depleted SOI devices using total gate silicidation”, IEDM2002 S. Monfray, etc, “SON (Silicon-On-Nothing) P-MOSFETs with totally silicided (CoSi2) Polysilicon on 5nm-thick Si-films: The simplest way to integration of Metal Gates on thin FD channels”, IEDM2002 Jakub Kedzierski, etc, "Issues in NiSi-gated FDSOI device integration", IEDM2003

  In the conventional method, transistors having different Vths are realized by performing channel implantation a plurality of times, and high-concentration impurity implantation is required to set channel implantation conditions for a transistor having a high threshold voltage. Increasing the concentration of the channel region causes a decrease in mobility, an increase in junction leakage, an increase in junction capacitance, and the like, and there is a problem that the speed performance is greatly deteriorated more than a decrease in driving force due to an increase in threshold voltage. From the viewpoint of gate oxide film reliability, the increase in concentration was a cause of increasing crystal defects and causing a decrease in reliability.

  In addition, when all the polysilicon is fully silicided using a fully silicided gate as a gate depletion countermeasure, the resistance required for the analog circuit becomes extremely high if a resistor element is fabricated using the fully silicided polysilicon. There is a problem that the layout becomes smaller to obtain a desired resistance value. In addition, the analog circuit requires a high-precision polysilicon resistance element.

  The present invention has been made in view of the above circumstances, and an object of the present invention is to utilize the material characteristics of a fully silicided gate and a silicided gate that is partially silicided, depending on the application of the field effect transistor. An object of the present invention is to provide a semiconductor device capable of controlling the threshold and improving the reliability by making different electrodes.

  Another object of the present invention is to provide a method of manufacturing a semiconductor device capable of selectively forming a full silicide gate and a partially silicided gate with silicide on the same semiconductor substrate. .

In order to achieve the above object, a semiconductor device of the present invention includes a gate electrode formed on a semiconductor substrate through a gate insulating film, and a source region and a drain region formed on the semiconductor substrate with the gate electrode interposed therebetween. And a plurality of field effect transistors having a channel formed under the gate electrode are integrated, and the gate electrode in a plurality of field effect transistors of the same conductivity type among the plurality of field effect transistors is a full silicide gate. And a gate length of the gate electrode formed by the fully silicided gate is made to be selectively divided into a partially silicided gate with silicide, and the gate length of the gate electrode formed by the gate with silicide is Also long.

In the semiconductor device of the present invention described above, the gate electrode of the field effect transistor is selectively divided into a full silicide gate and a partially silicided gate with silicide.
The full silicide gate and the gate with silicide differ in work function difference and thermal conductivity with respect to the semiconductor substrate. If the thickness of the gate insulating film and the impurity concentration of the channel are the same, the threshold value of the field effect transistor having a fully silicided gate and the field effect transistor having a silicided gate are controlled by different work functions with respect to the semiconductor substrate. The

According to the semiconductor device of the present invention, by utilizing the material characteristics of the fully silicided gate and the partially silicided gate with silicide, the gate electrode is formed according to the use of the field effect transistor, and threshold control is performed. And reliability can be improved.
According to the method for manufacturing a semiconductor device of the present invention, a full silicide gate and a partially silicided gate with silicide can be selectively formed on the same semiconductor substrate.

  Embodiments of the present invention will be described below with reference to the drawings.

  The first embodiment is an invention in which a full silicide gate and a polysilicon gate with silicide are mixed on the same substrate to achieve a plurality of threshold (multi-Vth) technologies. The multi-Vth technology uses low threshold transistors mainly for circuits that require high speed, and uses high threshold transistors for circuits that require low power consumption, and at the same time achieves high speed, low power consumption, and high functionality. It is a technology to be realized. FIG. 1 is a cross-sectional view of the semiconductor device according to the first embodiment. In the first embodiment, an nMOS transistor is used as an example. However, in the case of a pMOS transistor, the following explanation can be applied in the same manner by setting the conductivity type of an impurity added to each part to a reverse polarity.

  As shown in FIG. 1, an element isolation insulating film 2 is formed on a semiconductor substrate 1 made of, for example, p-type silicon. A p-type well 3 is formed in the semiconductor substrate 1, and a region of the p-type well 3 partitioned by the element isolation insulating film 2 becomes an active region. Two types of transistors Tr1 and Tr2 are formed on the semiconductor substrate 1 in the active region.

  The transistor Tr1 has a full silicide gate FG made of a silicide film 6 in which polysilicon is completely silicided on a semiconductor substrate 1 with a gate insulating film 4 interposed therebetween. On the side wall of the full silicide gate FG, an offset spacer 7 made of a silicon oxide film and a side wall insulating film 8 made of a silicon oxide film 8a and a silicon nitride film 8b are formed. A p-type source / drain region 9 is formed in the well 3 with the full silicide gate FG interposed therebetween. Note that since the positions of the source region and the drain region are reversed in accordance with the voltage application direction, the region that becomes the source region or the drain region is collectively referred to as a source / drain region 9. A silicided silicide layer 10 is formed on the surface of the source / drain region 9. A channel is formed between the source / drain regions 9 in the full silicide gate FG.

  The transistor Tr2 has a silicided gate SG partially silicided on the semiconductor substrate 1 with a gate insulating film 4 interposed therebetween. That is, the silicide-attached gate SG includes the polysilicon film 5 and the silicide film 6 in which the upper surface of the polysilicon film 5 is silicided. An offset spacer 7 made of a silicon oxide film and a sidewall insulating film 8 made of a silicon oxide film 8a and a silicon nitride film 8b are formed on the side wall of the gate SG with silicide. A p-type source / drain region 9 is formed in the well 3 with the silicide gate SG interposed therebetween. A channel is formed between the source / drain regions 9 in the gate SG with silicide.

  As shown in FIG. 1, the gate electrodes of two transistors Tr1 and Tr2 formed on the same semiconductor substrate 1 are selectively used as a full silicide gate FG and a partially silicided gate with silicide SG. It is formed separately. In the first embodiment, the conditions such as the impurity concentration of the channel, the thickness of the gate insulating film 4 and the applied voltage are the same.

  Taking an nMOS transistor as an example, the flat band voltage of polysilicon with silicide is about -1.0V, the flat band voltage of full silicide is -0.5V, and the threshold voltage of the transistor Tr1 having the full silicide gate FG is about 0.5V higher. The difference in the flat band voltage is because the work function difference with respect to the semiconductor substrate 1 is different between the full silicide gate FG and the gate SG with silicide. FIG. 2 is a diagram illustrating the gate length (Lg) dependence of the threshold voltage Vth in the transistor Tr1 having the full silicide gate FG and the transistor Tr2 having the silicided gate SG. As can be seen from FIG. 2, the threshold voltage of the transistor Tr1 having the full silicide gate FG is higher than that of the transistor Tr2 having the silicided gate SG.

  Therefore, the transistor Tr1 having the full silicide gate FG can be employed as the high threshold transistor. In the first embodiment, the multi-Vth is realized by using the difference in the flat band voltage, so that a higher Vth can be realized in a state where the channel concentration is lower than in the conventional case. Since the mobility drop is low and gate depletion can be suppressed by the first embodiment, the transistor Tr1 having a high current driving capability can be manufactured. The reduction in impurity concentration can suppress an increase in junction leakage and junction capacitance.

  Further, Example 1 has the following effects. Polysilicon has a higher thermal conductivity than silicide. Therefore, by adopting the gate SG with silicide having polysilicon having relatively high thermal conductivity for the low threshold transistor Tr2 having large current driving capability and power consumption, heat dissipation from the gate electrode is facilitated, and the temperature of the chip rises. Can be suppressed and reliability can be maintained. The effect of heat dissipation is particularly noticeable in analog / RF circuits that are often used in a current mode such as a differential circuit. In addition, when an SOI (Silicon on insulator) substrate is used, since there is an oxide film having a low thermal conductivity under the channel, the effect of efficiently radiating heat from the gate SG with silicide is great. Moreover, the problem of heat generation can be reduced by applying the full silicide gate FG to the high threshold transistor Tr1 with low power consumption.

The thermal conductivity of a typical material constituting the transistor is as follows: SiO ₂ is 0.014, Si is 1.5, n-type Si is 0.75, and p-type Si is 0.50. TiSi is 0.08 and Al is 2.4. The unit is Wcm ⁻¹ K ⁻¹ .

  Example 2 is an example corresponding to claim 3 of the present invention. In the second embodiment, a combination of a gate technology that changes the work function using a full silicide gate FG and a silicide-attached gate SG and a technology that changes the impurity concentration of the channel, the thickness of the gate insulating film 4, or the applied voltage, The multi-Vth is realized.

  For example, when the film thickness of the gate insulating film 4 and the power supply voltage are made constant, the channel impurity concentration is made two types, and a transistor having a full silicide gate FG and a transistor Tr having a silicided gate SG are formed under each channel condition. Thus, a total of four types of transistors Tr having Vth can be integrated, and the semiconductor device can be further multifunctional.

  Example 3 is an example corresponding to claim 4 of the present invention. FIG. 3 is a cross-sectional view of the semiconductor device according to the third embodiment. In addition, also about Example 3 and subsequent Examples, the same code | symbol is attached | subjected to the component equivalent to FIG. 1 referred in Example 1, and duplication description is abbreviate | omitted.

  As shown in FIG. 3, the third embodiment is a CMOS technology in which the gate electrode of the short channel transistor Tr3 having a short gate length Lg is a full silicide gate FG, and the gate electrode of the long channel transistor Tr4 is a silicided gate SG. The gate length of the short channel transistor Tr3 is typically about 0.1 μm or less.

  By using the full silicide gate FG for the short channel transistor Tr3, the threshold drop in the short channel, which has been a problem in the prior art, is suppressed by using the full silicide gate FG for the short channel transistor Tr3 as compared with the conventional example using polysilicon with silicide for the gates of all transistors. can do.

  The short channel effect is a phenomenon in which the threshold voltage Vth decreases as the gate length Lg is shortened, as shown in FIG. The reduction of the threshold voltage in the short channel region increases the off-current, and in the worst case, the on-off ratio cannot be obtained and an important switching operation as a transistor cannot be performed.

  As shown in FIG. 4B, the threshold voltage can be raised by applying a full silicide gate FG to the gate electrode of a transistor having a gate length Lg in a region where the threshold voltage decreases. As described above, in the third embodiment of the present invention, a full silicide gate that can increase the threshold voltage by using the work function of the gate is applied to the short channel transistor Tr3 in which the threshold voltage is physically decreased. The short channel effect can be suppressed.

  Example 4 is an example corresponding to claim 5 of the present invention. FIG. 5 is a cross-sectional view of the semiconductor device according to the fourth embodiment.

  As shown in FIG. 5, the silicided gate SG of the transistor Tr5 is fully silicided at the gate edge, that is, in the vicinity of the source / drain region 9. The transistor Tr5 of the fourth embodiment can be employed as the structure of the long channel transistor Tr4 of the third embodiment (see FIG. 3), for example.

  According to the fourth embodiment, in the silicided gate SG described in the first to third embodiments, the potential decrease due to the drain electric field in the vicinity of the source can be suppressed by performing full silicidation only in the vicinity of the source / drain region 9. . Thereby, short channel effects such as punch-through current can be suppressed. The longer the full silicide length x shown in FIG.

  FIG. 6 shows the gate length dependence of the threshold voltage of the conventional transistor having a gate with silicide (indicated by CV1 in the figure) and the transistor Tr5 having the gate with silicide SG in Example 4 (indicated by CV2 in the figure). FIG.

  As shown in FIG. 6, when x is fixed, when the gate length Lg is long, the threshold can be controlled to the same level as a conventional transistor having a silicided gate. When the gate length Lg is shortened, the ratio of full silicide increases, so that a threshold drop due to punch-through can be prevented in the short channel region. When the gate length Lg is shortened and Lg ≦ 2x, complete full silicide is obtained. Further, in Example 3, as shown in FIG. 4B, the curve of the Vth-Lg characteristic becomes discontinuous at the gate length that becomes the boundary for adopting the gate SG with silicide or the full silicide gate FG. In this structure, the Vth-Lg characteristic curve is continuous.

  As will be described later, normally, in the silicidation process, the silicidation of the edge portion of the polysilicon proceeds relatively faster than the central portion. Therefore, by controlling the polysilicon film thickness and the silicide temperature, only the edge portion can be fully silicided when the gate length is relatively long.

  The fifth embodiment is an embodiment corresponding to claim 6 of the present invention. FIG. 7 is a cross-sectional view of the semiconductor device according to the fifth embodiment.

  In the fifth embodiment, a full silicide gate FG is employed as the gate electrode of the low voltage transistor Tr6, and a gate SG with silicide is employed as the gate electrode of the high voltage transistor Tr7. The film thickness t2 of the gate insulating film 4 of the high-voltage transistor Tr7 is thicker than the film thickness t1 of the gate insulating film 4 of the low-voltage transistor Tr6, and has a high breakdown voltage structure.

  By using a gate SG with a silicide having a polysilicon film 5 having a relatively high thermal conductivity as the gate of the high voltage transistor Tr7 in which a high power supply voltage is used, the temperature rise can be suppressed. High breakdown voltage can be achieved.

  In addition, by using the full silicide gate FG for the gate of the low-voltage transistor Tr6, mobility reduction and depletion can be suppressed, and high speed and high driving power can be achieved. However, as in the first and third embodiments, a part of the low-voltage transistor may employ a transistor with a silicide depending on the application. Further, as in the fourth embodiment, a structure in which the gate SG with silicide of the high-voltage transistor Tr7 is full silicide only at the gate edge may be adopted.

  Example 6 is an example corresponding to claim 7 of the present invention. FIG. 8 is a plan view of a semiconductor device having a CMOS transistor according to the sixth embodiment.

  In an active region partitioned by the element isolation insulating film 2, an nMOS transistor Tr8 and a pMOS transistor Tr9 are formed. In the sixth embodiment, both the nMOS transistor Tr8 and the pMOS transistor Tr9 have the full silicide gate FG. As shown in FIG. 8, transistors Tr8 and Tr9 having a full silicide gate FG and source / drain regions 9 are formed in the active region. Contacts 17 connected to the source / drain regions 9 of the transistors Tr8 and Tr9 are formed.

  A wide gate pad GP is formed on the element isolation insulating film 2 outside the active region. The gate pad GP is connected to the first layer wiring 18 through the contact 17. The full silicide gate FG of the nMOS transistor Tr8, the full silicide gate FG of the pMOS transistor Tr9, and the gate pad GP are integrally formed and electrically connected.

  In the sixth embodiment, as shown in FIG. 8, the gate pad GP connected to the transistors Tr8 and Tr9 having the full silicide gate FG is made of polysilicon with silicide. FIG. 9 is a cross-sectional view taken along line X-X ′ of FIG. 8.

  As shown in FIG. 9, a gate pad GP having a polysilicon film 5 and a silicide film 6 is formed on the element isolation insulating film 2. The gate pad GP is covered with an interlayer insulating film 16 and connected to the first layer wiring 18 through a contact 17.

  In the sixth embodiment, by using polysilicon with silicide having polysilicon whose pinhole generation is lower than that of full silicide for the gate pad GP, element isolation is performed in the etching of the interlayer insulating film 16 for forming the contact 17. Etching damage can be prevented from entering the insulating film 2. Thereby, the leak LC between the gate pad GP and the semiconductor substrate 1 can be prevented.

Further, since the polysilicon film 5 is closer to the thermal expansion coefficient of the element isolation insulating film 2 made of silicon oxide than the silicide, the presence of the polysilicon film 5 in the portion in contact with the element isolation insulating film 2 The gate pad GP can be prevented from peeling off. The thermal expansion coefficients of SiO ₂ , Poly-Si, and CoSi ₂ are 0.55, 3.7, and 8.4 (× 10 ⁻⁶ / ° C.), respectively.

  Further, by using polysilicon with silicide for the gate pad GP, the resistance can be reduced as compared with non-silicide (polysilicon film 5 only). Further, when etching the interlayer insulating film 16 for forming the contact 17, the etching selectivity with respect to the silicon oxide film as the interlayer insulating film 16 is higher in the polysilicon with silicide than in the non-silicide. There is.

  Example 7 is an example corresponding to claim 8 of the present invention. The seventh embodiment is a preferable structural example of the transistor Tr10 having the gate SG with silicide. FIG. 10 is a plan view of the semiconductor device according to the seventh embodiment, and FIG. 11 is a cross-sectional view taken along line Y-Y ′ of FIG. 10.

  As shown in FIG. 10, a transistor Tr10 having a silicided gate SG is formed in the active region partitioned by the element isolation insulating film 2. The gate SG with silicide is formed extending on the active region and the element isolation insulating film 2. In Example 7, only the boundary portion between the active region and the element isolation insulating film 2 has a full silicide structure including only the silicide film 6.

  FIG. 12 is an enlarged view of a main part of FIG. As shown in FIG. 12, when STI is adopted as the element isolation insulating film 2, a dent D called Divot may occur at the boundary with the active region. When the depression D is generated, when the gate width is small, the influence of the sneak electric field E caused by the gate electrode on the element isolation insulating film 2 cannot be ignored, and the problem of the reverse narrow channel effect that the threshold is lowered due to the influence. is there. This phenomenon becomes more prominent as the recess D of the element isolation insulating film is larger. In Example 7, the reverse narrow channel effect can be suppressed by fully siliciding the edge portion in order to increase the threshold voltage. The structure of the seventh embodiment can be adopted in the structure of the transistor having the silicided gate SG of the first to fifth embodiments.

  The eighth embodiment is an embodiment corresponding to claim 9 of the present invention. Example 8 relates to a resistance element using the gate material of the transistors of Examples 1 to 7. FIG. 13 is a cross-sectional view of a principal part of the resistance element according to the eighth embodiment. The resistance element RS shown in FIG. 13 is manufactured on the same semiconductor substrate 1 as the transistors shown in Examples 1 to 7.

  As shown in FIG. 13, the resistance element RS is formed on the element isolation insulating film 2 formed on the semiconductor substrate 1. The resistance element RS is composed of a polysilicon film 5 serving as a gate material and a silicide film 6 in which a part of the polysilicon film 5 is silicided. An interlayer insulating film 16 is formed so as to cover the resistance element RS, and a contact 17 connected to the resistance element RS is embedded in the interlayer insulating film 16.

The sheet resistance of full silicide (eg, CoSi ₂ ) is about 2Ω / □, and the sheet resistance of polysilicon with silicide (poly-Si / CoSi ₂ ) is about 10Ω / □, and non-silicide (eg, n-type poly− The sheet resistance of Si) is about 150 to 200 Ω / □.

For this reason, a non-silicide or polysilicon with a high resistance is mainly applied to the resistance element RS formed on the same semiconductor substrate 1 as the transistors described in the first to seventh embodiments, and a part thereof is silicided to have a resistance value. By adjusting this, the area of the resistance element for obtaining a desired resistance value can be reduced, and the degree of integration can be improved.
Further, by applying mainly non-silicide or polysilicon with silicide higher thermal conductivity than full silicide to the resistance element, the temperature rise of the resistance element can be suppressed, and a highly reliable resistance element can be realized.

  As will be described later, the resistance element RS can be manufactured by adding a process for blocking silicidation and manufacturing non-silicide polysilicon or polysilicon with silicide.

  Example 9 relates to a method of manufacturing the transistors and resistance elements of Examples 1 to 8. As a ninth embodiment for manufacturing the transistors and resistance elements of the first to eighth embodiments, a method of manufacturing a transistor having a full silicide gate FG, a gate SG with silicide, and a non-silicide gate on the same substrate will be described. The following description applies to the production methods of all the examples in the same manner.

  As the semiconductor substrate 1 shown in FIG. 14A, for example, a Si substrate (specific resistance> about 10 mmΩ · cm) is used. Note that a substrate including an SOI (silicon-on-insulator) or SiGe layer may be used. The semiconductor substrate 1 is thermally oxidized to form a pad oxide film 21 having a thickness of about 15 nm, for example. Next, a silicon nitride film 22 having a thickness of about 160 nm is formed on the pad oxide film 21 by LPCVD (Low Pressure CVD). In the drawing, the structure is a silicon nitride film / pad oxide film, but may be a silicon nitride film / polysilicon film or an α-Si / pad oxide film.

Next, as shown in FIG. 14B, lithography is performed to process the silicon nitride film 22 and the pad oxide film 21 with a resist mask. Etching equipment is RIE (Reactive Ion
Etching) apparatus or ECR (Electron Cyclotron Resonance) apparatus is used. After the processing, the resist is removed by an ashing device or the like.

  Next, as shown in FIG. 15A, trench etching is performed using the silicon nitride film 22 as an etching mask. As an etching apparatus, an RIE (Reactive Ion Etching) apparatus or an ECR (Electron Cyclotron Resonance) apparatus is used. The trench depth is about 0.3 μm. Next, the semiconductor substrate 1 is thermally oxidized at about 800 ° C. to 900 ° C. to form a coating oxide film 23 on the trench surface. The covering oxide film 23 may be a silicon oxide film containing nitrogen or a silicon nitride film formed by CVD. The film thickness is about 4 to 10 nm.

  Next, as shown in FIG. 15B, an HDP (High Density Plasma) oxide film is deposited to form the element isolation insulating film 2. This oxide film may be an inorganic or organic oxide film such as SOG (Spin on Glass). Next, CMP (Chemical Mechanical Polishing) is performed. CMP is stopped at the silicon nitride film 22.

  Next, in order to adjust the step of the element isolation insulating film 2 from the surface of the semiconductor substrate, the element isolation insulating film 2 is wet-etched. The etching film thickness is about 40 nm to 100 nm. Next, the silicon nitride film 22 is removed by hot phosphoric acid. As a result, as shown in FIG. 16A, the element isolation insulating film 2 with the step difference from the semiconductor substrate 1 adjusted is obtained.

Next, as shown in FIG. 16B, after performing lithography, p-well implantation and channel implantation are performed to form a p-well 3p. The p well 3p is formed by implanting boron (B) at 200 keV by about 1 × 10 ¹³ cm ⁻² . The channel implantation is performed by implanting B at 10 to 20 keV and about 1 × 10 ¹¹ to 1 × 10 ¹³ cm ⁻² . After removing the resist, lithography is performed, and n-well implantation and channel implantation are performed to form an n-well 3n. The n-well 3n is formed by implanting phosphorus (P) at 200 keV by about 1 × 10 ¹³ cm ⁻² . The channel implantation is performed by implanting arsenic (As) at about 1 × 10 ¹¹ to 1 × 10 ¹³ cm ⁻² at 100 keV. Thereafter, the resist is removed.

Next, the pad oxide film 21 is removed by wet etching. Then, after a silicon oxide film is formed on the semiconductor substrate 1, lithography is performed to remove the silicon oxide film formed in the low voltage transistor region. After removing the resist, a silicon oxide film is formed again. Thereby, as shown in FIG. 17A, a thick gate insulating film 4a for high voltage and a thin gate insulating film 4b for low voltage are formed. The film thickness of the thick gate insulating film 4a is about 7.5 nm for the transistor for power supply voltage 3.3V, and about 5.5 nm for the transistor for 2.5V. The film thickness of the thin gate insulating film 4b is a transistor for 1.0 V and is about 1.2 to 1.8 nm. The material of the gate insulating film may be a thermal oxide film or an oxynitride film using RTO (Rapid Thermal Oxidation). Further, a high dielectric film using an oxide film such as Hf or Zr may be used to further reduce gate leakage.
Hereafter, due to the simplification of the drawings and description, the thick gate insulating film 4a and the thin gate insulating film 4b are simply illustrated and described as the gate insulating film 4 without distinguishing them.

Next, polysilicon is deposited by LPCVD. The deposited film thickness is about 150 to 200 nm at the 90 nm node, although it depends on the technology node. Gate depletion (With the reduction in gate oxide thickness, not only the physical gate oxide thickness but also the influence of the depletion layer thickness in the gate polysilicon cannot be ignored. The effective gate thickness is not reduced, As a countermeasure against the problem that the transistor performance improvement rate decreases, SiGe polycrystal (poly) may be used instead of polysilicon. In addition, SiGe poly tends to have a larger silicide region than polysilicon, and is an effective material for the full silicide gate of the present invention.
Subsequently, lithography is performed, and P or As is implanted into the nMOS region and B or BF ₂ or In is implanted into the pMOS region as a countermeasure against gate depletion. The injection amount is about 1 × 10 ¹⁵ to 1 × 10 ¹⁶ cm ⁻² . In order to prevent impurities from penetrating directly under the gate oxide film, N ₂ implantation may be combined. As a result, as shown in FIG. 17B, an n-type polysilicon film 5n is formed in the nMOS region, and a p-type polysilicon film 5p is formed in the pMOS region.
Next, a mask insulating film 24 to be a mask for gate processing is formed. As the mask material, a silicon oxide film or a silicon nitride film is used. The film thickness is about 10 to 100 nm. Lithography is performed, and the mask insulating film 24 is processed using an RIE apparatus or the like. Remove the resist.

  Next, as shown in FIG. 18A, gate processing is performed by etching using an RIE apparatus or the like using the processed mask insulating film 24 as an etching mask. Next, an offset spacer HTO (High Temperature Oxide) film is deposited. Etch back is performed using an RIE apparatus to form an offset spacer 7. The offset spacer 7 may be a TEOS (Tetraethoxysilane) film or a silicon nitride film. The offset spacer 7 has an effect of increasing the effective channel length and suppressing the short channel effect by being formed on the gate side wall. Further, before forming the offset spacer 7, a gate sidewall re-oxidation process may be added by RTO or the like. This step has an effect of reducing the gate overlap capacitance which is a parasitic capacitance.

Next, as shown in FIG. 18B, using a lithography technique, pocket implantation and extension implantation are performed to form a p-type pocket region 11p and an n-type extension region 12n in the nMOS region. Then, an n-type pocket region 11n and a p-type extension region 12p are formed. In the pocket implantation of the nMOS region, BF ₂ or B or In is used, and the implantation concentration is about 1 × 10 ¹² to 1 × 10 ¹⁴ cm ⁻² . In extension implantation, As is used, and the implantation concentration is about 1 × 10 ¹⁴ to 1 × 10 ¹⁵ cm ⁻² . In the pocket implantation of the pMOS region, As or P is used, and the implantation concentration is about 1 × 10 ¹² to 1 × 10 ¹⁴ cm ⁻² . In extension implantation, BF ₂ or B or In is used, and the implantation concentration is about 1 × 10 ¹⁴ to 1 × 10 ¹⁵ cm ⁻² . Further, pre-amorphization may be performed by implanting Ge or the like as a channeling suppression technique for implantation before pocket implantation of nMOS and pMOS. Further, after the extension region is formed, an RTA (Rapid Thermal Annealing) process at about 800 to 900 ° C. may be added in order to reduce implantation defects that cause TED (Transient Enhanced Diffusion) or the like.
For simplification of illustration, illustration of the n-type pocket region 11n and the p-type pocket region 11p is omitted in the subsequent steps.

Next, as shown in FIG. 19A, for example, a silicon oxide film 8a having a thickness of about 10 nm and a silicon nitride film 8b having a thickness of about 50 nm are deposited by CVD. Subsequently, etch back is performed using an RIE apparatus or the like to form a sidewall insulating film 8 composed of the silicon oxide film 8a and the silicon nitride film 8b. As the structure of the sidewall insulating film 8, instead of a two-layer structure of _{SiO 2 / Si 3 N 4,} SiO 2 / Si 3 N 4 / SiO 2 in or a three-layer structure.

Next, as shown in FIG. 19B, lithography is performed to form an n-type source / drain region 9n in the nMOS region and a p-type source / drain region 9p in the pMOS region. In the formation of the n-type source / drain region 9n in the nMOS region, As or P ions are implanted, and the concentration is 1 × 10 ¹⁵ to 1 × 10 ¹⁶ cm ⁻² . In the formation of the p-type source / drain region 9p in the pMOS region, B or BF ₂ is implanted, and the concentration is 1 × 10 ¹⁵ to 1 × 10 ¹⁶ cm ⁻² . Next, activation annealing is performed at about 800 to 1100 ° C. The apparatus uses RTA, Spike-RTA, or the like.

Next, as shown in FIG. 20A, silicide is performed to form a silicide layer 10 on the surface layer of the n-type source / drain region 9n and the p-type source / drain region 9p. CoSi ₂ , NiSi, TiSi ₂ , PtSi, WSi ₂ or the like is formed as the silicide layer 10. As a manufacturing method, an example of forming a silicide layer 10 made of NiSi will be described. First, about 10 nm of Ni is deposited using a sputtering apparatus. After annealing at about 300 to 400 ° C., Ni is wet etched. When wet etching is performed, only the silicon or polysilicon surface other than the insulating film is silicided in a self-aligning manner. Then, it anneals at about 500-600 degreeC. This annealing may be omitted because there is a silicide process again in a later process. Next, a stopper film 13 is formed by depositing a silicon nitride film using LPCVD or the like. The film thickness of the stopper film 13 is about 5 nm to 50 nm. This stopper film 13 serves as a stopper film for CMP in the next process. In addition, it acts as a stopper for the first etching of the 2Step etching technique for the contact, and realizes a highly accurate contact depth. This is because the edge of the STI at the time of the borderless contact (a part of the contact is not only the active layer and the gate electrode but also the element isolation insulating film 2. The integration degree can be improved by this technique). This has the effect of suppressing an increase in junction leakage.
Subsequently, a flattened film 14 is formed by depositing a silicon oxide film of about 100 to 1000 nm by APCVD (Atmosphere Pressure CVD).

  Next, as shown in FIG. 20B, the planarization film 14 is polished by CMP to expose the n-type polysilicon film 5n and the p-type polysilicon film 5p that become the gate. If necessary, wet etching or etch back of the silicon oxide film which is the mask insulating film 24 is added.

Next, as shown in FIG. 21A, a silicon oxide film is deposited to a thickness of 10 to 70 nm, processed by lithography, and a silicide prevention film 15 is formed on the polysilicon film 5 that needs to block silicidation. To do. Thereafter, the resist is removed.
For simplification of the drawings, description will be made without distinguishing between pMOS and nMOS from the process. Therefore, the n well 3n and the p well 3p are simply the well 3, the n type source / drain region 9n and the p type source / drain region 9p are simply the source / drain region 9, the n type polysilicon film 5n and the p type polysilicon. The film 5p is simply shown as a polysilicon film 5.

Next, as shown in FIG. 21B, lithography is performed to form a resist mask 25 that exposes the polysilicon film 5 to be fully silicided, and the polysilicon film 5 exposed from the resist mask 25 is etched. Back to thin film.
In Non-Patent Document 2, since the polysilicon surface is already silicided, it is difficult to etch the silicide, and it is impossible to etch back as in this flow. Under the condition where 100% Co is deposited, the silicide film thickness of the polysilicon film is about 70 nm. Therefore, when CoSi ₂ is formed later as an example, the polysilicon film 5 is etched back so that the thickness of the polysilicon film 5 including the margin becomes about 50 nm. In this flow, an etch-back method is proposed to reduce the polysilicon film thickness, thereby facilitating full silicidation. In the conventional method, a relatively high temperature heat treatment is required for full silicide. The addition of heat treatment in this step is particularly effective when NiSi, which is monosilicide with low Si consumption, is difficult to achieve full silicidation. If the initial polysilicon films 5n and 5p are thinned in the step of FIG. 17B, full silicidation is facilitated, but there are the following problems.

Along with the miniaturization of elements, the thickness of polysilicon serving as a gate has been reduced from generation to generation in order to prevent gate collapse and improve gate processing accuracy. As an example, in the 0.18 μm generation, the polysilicon film thickness as a gate is about 200 nm, and in the 90 nm generation, it is about 160 nm. On the other hand, silicide techniques such as CoSi ₂ , NiSi, and TiSi ₂ are used to reduce the parasitic resistance of the gate electrode and the source / drain regions. However, if the silicide technique is used in the bulk MOS, the junction leakage of the source / drain region due to the silicide increases, so that it is difficult to reduce the junction depth of the source / drain region. In order to suppress junction leakage, the source / drain region needs to have a depth of about 120 to 150 nm. When the source / drain regions are formed by ion implantation, a certain thickness of polysilicon is required to prevent impurities from penetrating into the channel directly under the gate. Therefore, it is difficult to set a poly film thickness of about 50 nm from the beginning. Further, if the initial polysilicon films 5n and 5p are uniformly thinned, full silicidation and partial silicidation cannot be selectively performed as in this embodiment.

Next, the polysilicon film 5 is silicided. CoSi ₂ , NiSi, TiSi ₂ , PtSi, and WSi ₂ are formed as silicide. The silicidation temperature is about 700 ° C. when forming CoSi ₂ and about 500 ° C. when forming NiSi. An example of the silicide process is the same as that described in the step of FIG. As a result, as shown in FIG. 22A, the thinned polysilicon film 5 is fully silicided to form a silicide film 6. Further, the polysilicon film 5 that is still thick is silicided only on the surface layer, and a silicide film 6 is formed on the polysilicon film 5. Further, the polysilicon film 5 covered with the silicide prevention film 15 remains as polysilicon without being silicided. Thereby, a transistor having a full silicide gate FG, a gate SG with silicide, and a non-silicide gate NG is formed.

  Next, as shown in FIG. 22B, a silicon oxide film is deposited by CVD to form an interlayer insulating film 16. As the interlayer insulating film 16, a TEOS, PSG, BPSG, SOG film or the like is used. The film thickness is about 100 nm to 1000 nm. Next, CMP is performed to planarize. In order to simplify the drawing, the illustration of the silicide prevention film 15 made of silicon oxide coated on the interlayer insulating film 16 is omitted.

  Next, lithography is performed, and the interlayer insulating film 16, the planarizing film 14, and the stopper film 13 are etched using an RIE apparatus or the like to form contact holes reaching the source / drain regions 9. The amount of overetching can be reduced by using a 2Step etching method in which etching is stopped once by the stopper film 13. Next, TiN / Ti is deposited by sputtering or CVD as a barrier metal film of W (tungsten). Next, W is deposited by CVD. The film thickness is about 100 to 500 nm. Next, CMP of W is performed to embed only in the contact. An etch back method may be used instead of CMP. As a result, contacts 17 connected to the source / drain regions 9 are formed as shown in FIG.

  Next, Al is deposited by sputtering. As this material, Cu having a lower resistance may be used. Next, lithography is performed, and wiring is processed by an RIE apparatus or the like. Thereby, as shown in FIG. 23B, the first layer wiring 18 connected to the contact 17 is formed on the interlayer insulating film 16.

  Although the subsequent steps are omitted, the wiring layer can be multilayered into two layers, three layers, four layers,.

  According to the manufacturing method of the semiconductor device of Example 9 described above, in the step shown in FIG. 21B, only the polysilicon film 5 to be fully silicided is selectively thinned, whereby FIG. In the silicide process shown in FIG. 5A, the thinned polysilicon film 5 can be fully silicided, and the thick polysilicon film 5 can be silicided only on the surface layer. As a result, a transistor having a full silicide gate FG and a transistor having a silicided gate SG can be selectively formed on one semiconductor substrate.

  Further, in the step shown in FIG. 21A, the silicide prevention film 15 is formed on the polysilicon film 5 that is not silicided, thereby preventing silicidation in the step shown in FIG. In addition, a transistor having a non-silicide gate can be further formed.

The present invention is not limited to the description of the above embodiment.
The materials and numerical values given in Examples 1 to 9 above are examples, and the present invention is not limited to these.
In addition, various modifications can be made without departing from the scope of the present invention.

1 is a cross-sectional view of a semiconductor device according to Example 1. FIG. It is a figure which shows the gate length dependence of the threshold voltage in transistor Tr1 which has full silicide gate FG, and transistor Tr2 which has gate SG with a silicide. 7 is a cross-sectional view of a semiconductor device according to Example 3. FIG. (A) is a figure for demonstrating the short channel effect, (b) is a figure for demonstrating the effect of the semiconductor device which concerns on Example 3. FIG. 7 is a cross-sectional view of a semiconductor device according to Example 4. FIG. FIG. 10 is a diagram showing the gate length dependence of the threshold voltage of a transistor having a conventional gate with silicide (indicated by CV1 in the figure) and a transistor Tr5 having a gate with silicide SG in Example 4 (indicated by CV2 in the figure). is there. 7 is a plan view of a semiconductor device according to Example 5. FIG. 7 is a plan view of a semiconductor device having a CMOS transistor according to Example 6. FIG. It is sectional drawing in the X-X 'line | wire of FIG. FIG. 10 is a plan view of a semiconductor device according to Example 7. It is sectional drawing of the Y-Y 'line | wire of FIG. It is a principal part enlarged view of FIG. 10 is a cross-sectional view of a principal part of a resistance element according to Example 8. FIG. 11 is a process cross-sectional view of the method for manufacturing the semiconductor device according to Example 9. FIG. 11 is a process cross-sectional view of the method for manufacturing the semiconductor device according to Example 9. FIG. 11 is a process cross-sectional view of the method for manufacturing the semiconductor device according to Example 9. FIG. 11 is a process cross-sectional view of the method for manufacturing the semiconductor device according to Example 9. FIG. 11 is a process cross-sectional view of the method for manufacturing the semiconductor device according to Example 9. FIG. 11 is a process cross-sectional view of the method for manufacturing the semiconductor device according to Example 9. FIG. 11 is a process cross-sectional view of the method for manufacturing the semiconductor device according to Example 9. FIG. 11 is a process cross-sectional view of the method for manufacturing the semiconductor device according to Example 9. FIG. 11 is a process cross-sectional view of the method for manufacturing the semiconductor device according to Example 9. FIG. 11 is a process cross-sectional view of the method for manufacturing the semiconductor device according to Example 9. FIG.

Explanation of symbols

DESCRIPTION OF SYMBOLS 1 ... Semiconductor substrate, 2 ... Element isolation insulating film, 3 ... Well, 3p ... p well, 3n ... n well, 4 ... Gate insulating film, 4a ... Thick film gate insulating film, 4b ... Thin film gate insulating film, 5 ... Poly Silicon film, 5n ... n-type polysilicon film, 5p ... p-type polysilicon film, 6 ... silicide film, 7 ... offset spacer, 8 ... sidewall insulating film, 8a ... silicon oxide film, 8b ... silicon nitride film, 9 ... Source / drain region, 9n ... n-type source / drain region, 9p ... p-type source / drain region, 10 ... silicide layer, 11n ... n-type pocket region, 11p ... p-type pocket region, 12n ... n-type extension region, 12p ... p-type extension region, 13 ... stopper film, 14 ... flattening film, 15 ... silicide prevention film, 16 ... interlayer insulating film, 17 ... contact, 18 ... first layer arrangement 21 ... Pad oxide film, 22 ... Silicon nitride film, 23 ... Cover oxide film, 24 ... Insulating film for mask, 25 ... Resist mask, FG ... Full silicide gate, SG ... Gate with silicide, NG ... Non-silicide gate, GP ... Gate pad

Claims (8)

A plurality of gate electrodes formed on a semiconductor substrate via a gate insulating film; and a source region and a drain region formed on the semiconductor substrate with the gate electrode interposed therebetween, wherein a channel is formed under the gate electrode. Integrated field effect transistors
Among the plurality of field effect transistors, the gate electrode in a plurality of field effect transistors of the same conductivity type is selectively divided into a full silicide gate and a partially silicided gate with silicide,
A semiconductor device, wherein a gate length of a gate electrode formed by the gate with silicide is longer than a gate length of a gate electrode formed by a full silicide gate. The semiconductor device according to claim 1, wherein the plurality of field effect transistors having two kinds of threshold voltages are integrated by making the work function difference with respect to the semiconductor substrate different between the full silicide gate and the gate with silicide. 3. The field effect transistors having three or more types of threshold voltages are integrated by differentiating the channel impurity concentration, the gate insulating film thickness, or the applied voltage of the plurality of field effect transistors. Semiconductor device. The semiconductor device according to claim 1, wherein the gate with silicide is fully silicided in the vicinity of the impurity region. 2. The semiconductor device according to claim 1, wherein different power supply voltages are used for the plurality of field effect transistors, and a gate electrode of the high-voltage field effect transistor is formed by a gate with silicide. The plurality of field effect transistors are formed in an active region of the semiconductor substrate partitioned by an element isolation insulating film, and are formed integrally with the gate electrode on the element isolation insulating film and connected to an upper layer Have
The semiconductor device according to claim 1, wherein the gate pad is partially silicided. The plurality of field effect transistors are formed in an active region of the semiconductor substrate partitioned by an element isolation insulating film, and the gate electrode is formed to extend on the active region and the element isolation of the semiconductor substrate. And
The semiconductor device according to claim 1, wherein a boundary portion between the active region and the element isolation insulating film in the gate electrode is fully silicided. A resistance element using a gate electrode material of the field effect transistor is formed on the semiconductor substrate,
The semiconductor device according to claim 1, wherein the resistance element has a partially silicided region or a non-silicide region.

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