JP4458730B2 - Semiconductor memory device - Google Patents

Description

[0001]
BACKGROUND OF THE INVENTION
The present invention relates to a semiconductor memory device, and more particularly to a semiconductor memory device formed on a semiconductor substrate.
[0002]
[Prior art]
In recent years, in dynamic random access memories (hereinafter referred to as DRAMs), as a result of high integration, memory cell capacitors have a complicated three-dimensional structure. In order to mount such a DRAM in a system LSI, in addition to a normal CMOS logic process, a process step for forming a capacitor of a DRAM memory cell and a step between a capacitor having a three-dimensional structure and a peripheral circuit portion are provided. And a planarization step to reduce. For this reason, when the DRAM is mounted on the system LSI, there are problems that the process steps are greatly increased and the chip cost is increased.
[0003]
On the other hand, a memory cell of a static random access memory (hereinafter referred to as SRAM) does not have a capacitor and is formed only by a CMOS logic process. Therefore, if the SRAM is mounted on the system LSI, the problems associated with mounting the DRAM on the system LSI are solved.
[0004]
[Problems to be solved by the invention]
However, the SRAM has the following problems. That is, in the DRAM, as the microfabrication technology advances, the memory cell size is reduced. For example, in a 0.18 μm DRAM process, a 0.3 square μm memory cell is realized. On the other hand, in SRAM, a memory cell is composed of two P-channel MOS transistors and four N-channel MOS transistors, and is subject to restrictions on the separation distance between the P-type well and the N-type well. Even with progress, the memory cell size has not been reduced as much as DRAM. For example, an SRAM memory cell using a 0.18 μm CMOS logic process is about 7 square μm, which is 20 times or more that of a DRAM memory cell. Accordingly, since the chip size of the SRAM increases greatly as the memory capacity increases, it becomes extremely difficult to mount an SRAM having a memory capacity of 4 Mbits or more on the system LSI.
[0005]
For this reason, the SRAM has been conventionally used as a cache memory for a processor, a register file memory, and the like. However, since the complicated memory control related to the refresh of data essential to the DRAM is unnecessary, the main memory is used in a portable information terminal or the like. It is also used as.
[0006]
However, even in portable information terminals, moving images are handled and functions have been greatly improved, and a large-capacity memory is required.
[0007]
Therefore, a main object of the present invention is to provide a low-cost and large-capacity semiconductor memory device.
[0008]
[Means for Solving the Problems]
  A semiconductor memory device according to the present invention is a semiconductor memory device formed on a semiconductor substrate together with a logic circuit including a MOS transistor, and includes a MOS transistor and a capacitor connected in series, and a memory for storing a data signal A cell is provided. The MOS transistor includes a gate insulating film formed on the surface of the semiconductor substrate, a gate electrode formed on the surface of the gate insulating film, and an impurity diffusion region formed on the surface of the semiconductor substrate on both sides of the gate electrode. Including. The capacitor includes an impurity diffusion region formed on the surface of the semiconductor substrate, an insulating film formed on the surface of the impurity diffusion region, and a flat plate electrode formed on the surface of the insulating film and receiving a reference potential. Here, the MOS transistor of the logic circuitThickness of the gate insulating filmAnd memory cell MOS transistorThickness of the gate insulating filmAnd capacitorInsulating film thicknessWhat isThe sameIn addition, the gate electrode of the MOS transistor of the logic circuit, the gate electrode of the MOS transistor of the memory cell, and the plate electrode of the capacitor are formed in the same wiring layer.
[0010]
  The MOS transistor of the memory cell is an N channel MOS transistor. The semiconductor memory device further includes a word line connected to the gate of the N-channel MOS transistor, first and second bit lines, one of which is connected to the source of the N-channel MOS transistor, A first P-channel MOS transistor connected between one bit line and the first node; and a second P-channel MOS transistor connected between the second bit line and the second node; And a write circuit for writing a data signal to the memory cell. The write circuit includes a step of applying a ground potential to the gates of the first and second P-channel MOS transistors to make the first and second P-channel MOS transistors conductive, and a boosted potential higher than the power supply potential on the word line. To make the N channel MOS transistor of the memory cell conductive, and according to the externally applied write data signal, either one of the first and second nodes is set to the power supply potential and the other The step of setting the node to the ground potential and the step of applying a negative potential lower than the ground potential to the gates of the first and second P-channel MOS transistors and supplying the power supply potential to the word line are executed..
[0011]
Preferably, the absolute value of the threshold voltage of each of the first and second P-channel MOS transistors is set to be approximately equal to the voltage difference between the boosted potential and the power supply potential.
[0012]
Preferably, two memory cells are provided, and one data signal is stored in the two memory cells. Two word lines are provided, the gates of the N channel MOS transistors of the two memory cells are connected to the two word lines, respectively, and the sources of the N channel MOS transistors of the two memory cells are the first and second bits, respectively. Connected to the wire.
[0013]
Preferably, two memory cells are provided, and one data signal is stored in the two memory cells. The gates of the N channel MOS transistors of the two memory cells are both connected to the word line, and the sources of the N channel MOS transistors of the two memory cells are connected to the first and second bit lines, respectively.
[0014]
  Another semiconductor memory device according to the present invention is a semiconductor memory device formed on a semiconductor substrate together with a logic circuit including a MOS transistor, and has a MOS transistor and a capacitor connected in series to store a data signal. A memory cell is provided. The MOS transistor includes a gate insulating film formed on the surface of the semiconductor substrate, a gate electrode formed on the surface of the gate insulating film, and an impurity diffusion region formed on the surface of the semiconductor substrate on both sides of the gate electrode. Including. The capacitor includes an impurity diffusion region formed on the surface of the semiconductor substrate, an insulating film formed on the surface of the impurity diffusion region, and a flat plate electrode formed on the surface of the insulating film and receiving a reference potential. Here, the MOS transistor of the logic circuitThickness of the gate insulating filmAnd memory cell MOS transistorThickness of the gate insulating filmAnd capacitorInsulating film thicknessWhat isThe sameIn addition, the gate electrode of the MOS transistor of the logic circuit, the gate electrode of the MOS transistor of the memory cell, and the plate electrode of the capacitor are formed in the same wiring layer.
  The MOS transistor of the memory cell is a P channel MOS transistor. The semiconductor memory device further includes a word line connected to the gate of the P channel MOS transistor, first and second bit lines, one of which is connected to the source of the P channel MOS transistor, A first N-channel MOS transistor connected between one bit line and the first node; and a second N-channel MOS transistor connected between the second bit line and the second node; And a write circuit for writing a data signal to the memory cell. The write circuit includes a step of applying a power supply potential to the gates of the first and second N channel MOS transistors to make the first and second N channel MOS transistors conductive, and a negative potential lower than the ground potential on the word line. To make the P-channel MOS transistor of the memory cell conductive, and according to the externally applied write data signal, set one of the first and second nodes to the power supply potential and A step of setting the node to the ground potential and a step of applying a boosted potential higher than the power supply potential to the gates of the first and second N-channel MOS transistors and applying the ground potential to the word line are executed..
[0015]
Preferably, the threshold voltages of the first and second N-channel MOS transistors are set to be approximately equal to the voltage difference between the ground potential and the negative potential.
[0016]
Preferably, two memory cells are provided, and one data signal is stored in the two memory cells. Two word lines are provided, the gates of the P channel MOS transistors of the two memory cells are connected to the two word lines, respectively, and the sources of the P channel MOS transistors of the two memory cells are the first and second bits, respectively. Connected to the wire.
[0017]
Preferably, two memory cells are provided, and one data signal is stored in the two memory cells. The gates of the P channel MOS transistors of the two memory cells are both connected to the word line, and the sources of the P channel MOS transistors of the two memory cells are connected to the first and second bit lines, respectively.
[0018]
  Still another semiconductor memory device according to the present invention is a semiconductor memory device formed on a semiconductor substrate together with a logic circuit including a MOS transistor, having a MOS transistor and a capacitor connected in series, and receiving a data signal. A memory cell for storing is provided. The MOS transistor includes a gate insulating film formed on the surface of the semiconductor substrate, a gate electrode formed on the surface of the gate insulating film, and an impurity diffusion region formed on the surface of the semiconductor substrate on both sides of the gate electrode. Including. The capacitor includes an impurity diffusion region formed on the surface of the semiconductor substrate, an insulating film formed on the surface of the impurity diffusion region, and a flat plate electrode formed on the surface of the insulating film and receiving a reference potential. Here, the MOS transistor of the logic circuitThickness of the gate insulating filmAnd memory cell MOS transistorThickness of the gate insulating filmAnd capacitorInsulating film thicknessWhat isThe sameIn addition, the gate electrode of the MOS transistor of the logic circuit, the gate electrode of the MOS transistor of the memory cell, and the plate electrode of the capacitor are formed in the same wiring layer.
  The MOS transistor of the memory cell is an N channel MOS transistor. The semiconductor memory device further includes a word line connected to the gate of the N-channel MOS transistor, first and second bit lines, one of which is connected to the source of the N-channel MOS transistor, a memory And a writing circuit for writing a data signal to the cell. The writing circuit includes applying a boosted potential higher than the power supply potential to the word line to turn on the N-channel MOS transistor of the memory cell, supplying a power supply potential to the first and second bit lines, In accordance with a step of applying a power supply potential to one of the first and second bit lines according to an externally applied write data signal, one bit line is set to the power supply potential and the other bit line is set to the ground potential. And execute steps.
[0019]
Preferably, two memory cells are provided, and one data signal is stored in the two memory cells. Two word lines are provided, the gates of the N channel MOS transistors of the two memory cells are connected to the two word lines, respectively, and the sources of the N channel MOS transistors of the two memory cells are the first and second bits, respectively. Connected to the wire.
[0020]
Preferably, two memory cells are provided, and one data signal is stored in the two memory cells. The gates of the N channel MOS transistors of the two memory cells are both connected to the word line, and the sources of the N channel MOS transistors of the two memory cells are connected to the first and second bit lines, respectively.
[0021]
  Still another semiconductor memory device according to the present invention is a semiconductor memory device formed on a semiconductor substrate together with a logic circuit including a MOS transistor, having a MOS transistor and a capacitor connected in series, and receiving a data signal. A memory cell for storing is provided. The MOS transistor includes a gate insulating film formed on the surface of the semiconductor substrate, a gate electrode formed on the surface of the gate insulating film, and an impurity diffusion region formed on the surface of the semiconductor substrate on both sides of the gate electrode. Including. The capacitor includes an impurity diffusion region formed on the surface of the semiconductor substrate, an insulating film formed on the surface of the impurity diffusion region, and a flat plate electrode formed on the surface of the insulating film and receiving a reference potential. Here, the MOS transistor of the logic circuitThickness of the gate insulating filmAnd memory cell MOS transistorThickness of the gate insulating filmAnd capacitorInsulating film thicknessWhat isThe sameIn addition, the gate electrode of the MOS transistor of the logic circuit, the gate electrode of the MOS transistor of the memory cell, and the plate electrode of the capacitor are formed in the same wiring layer.
  The MOS transistor of the memory cell is a P channel MOS transistor. The semiconductor memory device further includes a word line connected to the gate of the P channel MOS transistor, first and second bit lines, one of which is connected to the source of the P channel MOS transistor, a memory And a writing circuit for writing a data signal to the cell. The write circuit includes applying a negative potential lower than the ground potential to the word line to turn on the N-channel MOS transistor of the memory cell, applying a ground potential to the first and second bit lines, And applying one of the first and second bit lines to the power supply potential and setting the other bit line to the ground potential in accordance with a step of applying a ground potential to the first and second write lines. And execute steps.
[0022]
Preferably, two memory cells are provided, and one data signal is stored in the two memory cells. Two word lines are provided, the gates of the P channel MOS transistors of the two memory cells are connected to the two word lines, respectively, and the sources of the P channel MOS transistors of the two memory cells are the first and second bits, respectively. Connected to the wire.
[0023]
Preferably, two memory cells are provided, and one data signal is stored in the two memory cells. The gates of the P channel MOS transistors of the two memory cells are both connected to the word line, and the sources of the P channel MOS transistors of the two memory cells are connected to the first and second bit lines, respectively.
[0024]
  Still another semiconductor memory device according to the present invention is a semiconductor memory device formed on a semiconductor substrate together with a logic circuit including a MOS transistor, having a MOS transistor and a capacitor connected in series, and receiving a data signal. A memory cell for storing is provided. The MOS transistor includes a gate insulating film formed on the surface of the semiconductor substrate, a gate electrode formed on the surface of the gate insulating film, and an impurity diffusion region formed on the surface of the semiconductor substrate on both sides of the gate electrode. Including. The capacitor includes an impurity diffusion region formed on the surface of the semiconductor substrate, an insulating film formed on the surface of the impurity diffusion region, and a flat plate electrode formed on the surface of the insulating film and receiving a reference potential. Here, the MOS transistor of the logic circuitThickness of the gate insulating filmAnd memory cell MOS transistorThickness of the gate insulating filmAnd capacitorInsulating film thicknessWhat isThe sameIn addition, the gate electrode of the MOS transistor of the logic circuit, the gate electrode of the MOS transistor of the memory cell, and the plate electrode of the capacitor are formed in the same wiring layer.
  Also, two memory cells are provided, and one data signal is stored in the two memory cells. The MOS transistor of one of the two memory cells is an N channel MOS transistor, and the MOS transistor of the other memory cell is a P channel MOS transistor. The semiconductor memory device further includes first and second word lines connected to the gate of the N channel MOS transistor and the gate of the P channel MOS transistor, respectively, and one of them is the source of the N channel MOS transistor and First and second bit lines connected to the source of a P-channel MOS transistor, and a write circuit for writing a data signal into two memory cells are provided. In accordance with the step of applying a power supply potential and a ground potential to the first and second word lines to make the N-channel MOS transistor and the P-channel MOS transistor conductive, and the write circuit in accordance with an externally applied write data signal A step of setting one of the first and second bit lines to a power supply potential and setting the other bit line to a ground potential..
[0025]
DETAILED DESCRIPTION OF THE INVENTION
[Embodiment 1]
FIG. 1 is a block diagram showing a configuration of a system LSI 1 according to the first embodiment of the present invention. In FIG. 1, the system LSI 1 includes a logic circuit unit 2 and a memory circuit unit 3 formed on a single silicon substrate.
[0026]
Logic circuit unit 2 operates in synchronization with external clock signal CLK, and performs a predetermined operation according to external control signals CNT0 to CNTm and external data signals D0 to Dn (where m and n are integers of 0 or more). . The memory circuit unit 3 is controlled by the logic circuit unit 2, stores the data supplied from the logic circuit unit 2, and supplies the read data to the logic circuit unit 2.
[0027]
FIG. 2 is a block diagram showing a configuration of the memory circuit unit 3 shown in FIG. In FIG. 2, the memory circuit section 3 is composed of a synchronous DRAM, and includes a clock buffer 4, a control signal buffer 5, an address buffer 6, a control circuit 8, and four memory arrays 9 to 12 (banks # 0 to # 3). And an IO buffer 13.
[0028]
The clock buffer 4 is activated by the control signal CKE from the logic circuit unit 2 and transmits the external clock signal CLK to the control signal buffer 5, the address buffer 6 and the control circuit 8. The control signal buffer 5 latches the control signals / CS, / RAS, / CAS, / WE, DQM from the logic circuit unit 2 in synchronization with the external clock signal CLK from the clock buffer 4 and supplies the latched signals to the control circuit 8. . The address buffer 6 receives the address signals A0 to Ai (where i is an integer of 0 or more) and the bank selection signals BA0 and BA1 from the logic circuit unit 2 in synchronization with the external clock signal CLK from the clock buffer 4. Latch and give to the control circuit 8.
[0029]
Each of memory arrays 9-12 includes a plurality of memory cells arranged in a matrix and each storing 1-bit data. A plurality of memory cells are grouped in advance by j + 1 (where j is an integer of 0 or more).
[0030]
The control circuit 8 generates various internal signals according to signals from the clock buffer 4, the control signal buffer 5 and the address buffer 6, and controls the entire memory circuit unit 3. Control circuit 8 selects one of the four memory arrays 9 to 12 in accordance with bank selection signals BA0 and BA1 during a write operation and a read operation, and the memory array in accordance with address signals A0 to Ai. J + 1 memory cells are selected. The selected j + 1 memory cells are activated and coupled to the IO buffer 13.
[0031]
IO buffer 13 supplies data D0 to Dj supplied from the outside to the selected j + 1 memory cells during the write operation, and outputs read data Q0 to Qj of the j + 1 memory cells to the outside during the read operation. To do.
[0032]
FIG. 3 is a block diagram showing a configuration of the memory array 9 shown in FIG. 2 and parts related thereto. In FIG. 3, the memory array 9 is divided into a plurality of memory array blocks MA0 to MAk (where k is an integer equal to or greater than 0), and a plurality of sense amplifiers are provided on both sides of and between the plurality of memory array blocks MA0 to MAk. Bands SA0 to SAk + 1 are arranged. Memory array blocks MA0-MAk and sense amplifier bands SA0-SAk + 1 constitute a rectangular memory mat 14.
[0033]
As shown in FIG. 4, memory array block MAk includes a plurality of memory cells MC arranged in a matrix, word lines WL provided corresponding to each row, and bit lines provided corresponding to each column. The pair BL, / BL is included. This memory cell MC is arranged at one of the two intersections of two bit lines BL, / BL and one word line WL orthogonal thereto.
[0034]
Each memory cell MC includes an N channel MOS transistor Q for access and a capacitor C for information storage. N channel MOS transistor Q and capacitor C are connected in series between corresponding bit line BL or / BL and the cell potential VCP line, and the gate of N channel MOS transistor Q is connected to corresponding word line WL. A node between N channel MOS transistor Q and capacitor C is called a storage node SN.
[0035]
As shown in FIG. 5, sense amplifier band SAk includes data input / output line pair IO, / IO, column selection line CSL provided corresponding to each odd column of memory array block MAk, transfer gates 21, 36, A column selection gate 24, a sense amplifier 27, and an equalizer 32 are included. Transfer gates 21 and 36, column selection gate 24, sense amplifier 27, and equalizer 32 on each even column of memory array block MAk are provided in sense amplifier band SAk + 1.
[0036]
Transfer gate 21 includes P channel MOS transistors 22 and 23. P-channel MOS transistors 22 and 23 are connected between input / output nodes N1 and N2 of sense amplifier 27 and corresponding bit line pair BL and / BL of memory array block MAk-1, respectively, and have their gates connected to a block selection signal. Receive BLIR.
[0037]
Transfer gate 36 includes P-channel MOS transistors 37 and 38. P channel MOS transistors 37, 38 are connected between input / output nodes N1, N2 and corresponding bit line pair BL, / BL of memory array block MAk, respectively, and have their gates receiving block select signal BLIL.
[0038]
A circuit in the sense amplifier band SAk is shared by the two memory array blocks MAk-1 and MAk on both sides thereof. When memory array block MAk is selected, signal BLIR is at "H" level and transfer gate 21 is cut off. When memory array block MAk-1 is selected, signal BLIL is at "H" level. Thus, the transfer gate 36 is shut off.
[0039]
Column select gate 24 includes N channel MOS transistors 25 and 26 connected between input / output nodes N1 and N2 and data input / output lines IO and / IO, respectively. N channel MOS transistors 25 and 26 have their gates connected to column select line CSL. When column select line CSL is raised to the select level “H” level, N channel MOS transistors 25 and 26 are rendered conductive, and input / output nodes N 1 and N 2, ie, bit line pairs BL, / of memory array block MAk−1 or MAk. BL and data input / output line pair IO, / IO are coupled. The other end of data input / output line pair IO, / IO is connected to one end of global data input / output line pair GIO, / GIO via a block selection switch (not shown). The other end of global data input / output line pair GIO, / GIO is connected to IO buffer 13 via a preamplifier / write driver and a data bus.
[0040]
Sense amplifier 27 includes P-channel MOS transistors 28 and 29 connected between input / output nodes N1 and N2 and node N3, respectively, and N-channel connected between input / output nodes N1 and N2 and node N4, respectively. MOS transistors 30 and 31 are included. The gates of MOS transistors 28 and 30 are both connected to node N2, and the gates of MOS transistors 29 and 31 are both connected to node N1. Nodes N3 and N4 receive sense amplifier activation signals SE and / SE, respectively. The sense amplifier 27 is connected between the nodes N1 and N2, that is, the bit line of the memory array block MAk-1 or MAk, in response to the sense amplifier activation signals SE and / SE becoming "H" level and "L" level, respectively. A minute potential difference between the pair BL and / BL is amplified to the power supply voltage VCC.
[0041]
Equalizer 32 includes an N channel MOS transistor 33 connected between input / output nodes N1 and N2, and N channel MOS transistors 34 and 35 connected between input / output nodes N1, N2 and node N6, respectively. . The gates of N channel MOS transistors 33-35 are all connected to node N5. Node N5 receives bit line equalize signal BLEQ, and node N6 receives bit line precharge potential VBL (= VCC / 2). The equalizer 32 determines the potential difference between the nodes N1 and N2, that is, the potential difference between the bit lines BL and / BL of the memory array block MAk-1 or MAk, in response to the activation of the bit line equalize signal BLEQ at the "H" level. Is equalized to the bit line precharge potential VBL.
[0042]
Returning to FIG. 3, the row decoder 15 is arranged along the long side of the rectangular memory mat 14, and the column decoder 16 is arranged along the short side of the memory mat 14. In accordance with row address signals RA0-RAi (address signals A0-Ai when signal / RAS is at "L" level), row decoder 15 selects one of the plurality of memory array blocks MA0-MAk (for example, MAk) and any one of the plurality of word lines WL belonging to the memory array block MAk are selected, and the corresponding word line WL is set to the “H” level of the selected level to correspond to each memory cell MC. To activate.
[0043]
Column decoder 16 applies one of column select lines CSL among a plurality of column select lines CSL according to column address signals CA0-CAi ′ (address signals A0-Ai ′ when signal / CAS is at “L” level). Then, the column selection line CSL is set to the “H” level of the selection level, and each corresponding column selection gate 24 is made conductive. However, i ′ is an integer of 0 or more and i or less.
[0044]
Next, the operation of the memory circuit unit 3 shown in FIGS. 2 to 5 will be described. In the standby state, the signals BLIR and BLIL are both at the “L” level, the signal BLEQ is at the “H” level, the signals SE and / SE are both at the intermediate level (VCC / 2), and the bit line BL , / BL are equalized to the bit line precharge potential VBL. Further, the word line WL and the column selection line CSL are at the “L” level of the non-selection level.
[0045]
In the write mode, first, bit line equalize signal BLEQ is lowered to "L" level, and equalization of bit lines BL, / BL is stopped. Next, memory array block (for example, MAk) designated by row address signals RA0-RAi is selected by row decoder 15, signals BLIR and BLIL are set to "H" level and "L" level, respectively, and memory array block MAk Are coupled to sense amplifier bands SAk and SAk + 1. The row decoder 15 raises the word line WL of the row corresponding to the row address signals RA0 to RAi to the “H” level of the selection level, and the N channel MOS transistor Q of the memory cell MC of the row is turned on.
[0046]
Next, the column decoder 16 raises the column selection line CSL of the column corresponding to the column address signals CA0 to CAi ′ to the “H” level of the selection level, and the selection gate 24 of that column is turned on. Write data signal Di applied from logic circuit portion 2 is applied to IO buffer 13, global data input / output line pair GIO, / GIO and bit line pair of a column selected via data input / output line pair IO, / IO. It is given to BL and / BL. In accordance with the write data signal Dj, the sense amplifier 27 makes the potentials of the bit lines BL and / BL full amplitude. The capacitor C of the selected memory cell MC stores an amount of charge corresponding to the potential (“H” level or “L” level) of the bit line BL or / BL.
[0047]
In the read mode, first, bit line equalize signal BLEQ is lowered to "L" level, and equalization of bit lines BL, / BL is stopped. Next, for example, memory array block MAk is selected by row decoder 15 to set signals BLIR and BLIL to “H” level and “L” level, respectively, and memory array block MAk and sense amplifier bands SAk and SAk + 1 are coupled. The word lines WL in the row corresponding to the row address signals RA0 to RAi are raised to the “H” level of the selection level. As a result, the potentials of the bit lines BL and / BL change by a minute amount according to the charge amount of the capacitor C of the activated memory cell MC.
[0048]
Then, sense amplifier activation signals SE and / SE are set to “H” level and “L” level, respectively, and sense amplifier 27 is activated. When the potential of the bit line BL is slightly higher than the potential of the bit line / BL, the resistance values of the MOS transistors 28 and 31 are smaller than the resistance values of the MOS transistors 29 and 30, and the potential of the bit line BL is “ While being raised to the “H” level (power supply potential VCC), the potential of the bit line / BL is lowered to the “L” level (ground potential GND). Conversely, when the potential of the bit line / BL is slightly higher than the potential of the bit line BL, the resistance values of the MOS transistors 29 and 30 become smaller than the resistance values of the MOS transistors 28 and 30, and the bit line / BL Is raised to the “H” level and the potential of the bit line BL is lowered to the “L” level.
[0049]
Next, the column decoder 16 raises the column selection line CSL of the column corresponding to the column address signals CA0 to CAi to the “H” level of the selection level, and the column selection gate 24 of that column is turned on. Data signal Qj of bit line pair BL, / BL of the selected column is passed through column selection gate 21, data input / output line pair IO, / IO, global data input / output line pair GIO, / GIO, and IO buffer 13. It is output to the logic circuit unit 2.
[0050]
Hereinafter, the configuration of the memory cell MC and the data writing method which are features of the present invention will be described in detail. FIGS. 6A and 6B are diagrams showing the configuration of the memory cell MC of the memory circuit section 3. 6B is a cross-sectional view taken along the line ZZ ′ of FIG. 6A, and the bit line BL is omitted in FIG. 6A.
[0051]
6A and 6B, a P-type well 41 is formed on both surfaces of the crystalline silicon substrate 40, and an N-channel MOS transistor Q and a capacitor C are formed on the surface of the P-type well 41. In the N channel MOS transistor Q, a gate electrode 43 is formed on the surface of a P-type well 41 via a gate insulating film 42, and a source region 44 and a drain region 45 are formed on both sides thereof. The gate electrode 43 constitutes a part of the word line WL. The source region 44 and the drain region 45 are composed of an N-type diffusion layer. The capacitor C has a so-called planar type capacitor structure, in which an N-type diffusion layer (or inversion layer) 46 (storage node SN) is formed on the surface of the P-type well 41, and a cell is formed on the surface via an insulating layer 47. A plate electrode 48 is formed.
[0052]
Here, the gate electrode 43 (word line WL) of the N channel MOS transistor Q of the memory cell MC and the cell plate electrode 48 of the capacitor C are formed in the same wiring layer. This wiring layer may be formed of polycrystalline silicon doped with impurities (doped polysilicon), may be formed of polycide using WSix, CoSix, or the like, or may be formed by so-called salicide technology. Also good. This wiring layer is also used for the gate electrode of the MOS transistor in the CMOS logic process.
[0053]
A bit line BL is formed above N-channel MOS transistor Q and capacitor C through insulating layer 49. Such a structure is called a CBU structure. The bit line BL is formed of a first metal wiring layer. Source region 44 of N channel MOS transistor Q is connected to bit line BL through contact hole 50.
[0054]
A plurality of memory cells MC connected to one bit line BL are grouped by two. The source region 44 and the contact hole 50 of the N channel MOS transistor Q are provided in common in the two memory cells MC forming a pair. Memory cell MC connected to bit line BL and memory cell MC connected to other bit line / BL are separated by element isolation layer 51.
[0055]
In the first embodiment, first, a planar capacitor C is employed, and the cell plate electrode 48 and the word line WL are formed in the same wiring layer. Therefore, the wiring layer for forming the cell plate electrode and the storage node is used. Need not be provided separately, and no step is generated between the memory arrays 9 to 12 and the peripheral circuit portion. Therefore, the system LSI 1 can be formed only by the CMOS logic process, and the price of the system LSI 1 can be reduced.
[0056]
By the way, in order to sufficiently write the data signal of “H” level (power supply potential VCC) to storage node SN of memory cell MC, or to sufficiently read the data signal of “H” level from storage node SN of memory cell MC. Therefore, it is necessary to apply to the word line WL a potential VPP sufficiently higher than a potential VCC + Vtn obtained by adding the threshold voltage Vtn of the N-channel MOS transistor Q of the memory cell MC to the power supply potential VCC. As shown in FIG. 7, when the boosted potential VPP is applied to the word line WL and the bit line BL is set to the ground potential GND (0 V) by the sense amplifier 27, the gate insulating film of the N channel MOS transistor Q has Vgs = VPP is applied. Therefore, it is necessary to set the film thickness of the gate insulating film of the N channel MOS transistor Q so that it can withstand the high voltage VPP. On the other hand, the insulating film of the capacitor C needs to be set thin so that a large capacitance can be obtained.
[0057]
For this purpose, a dual gate insulating film process in which gate insulating films having different thicknesses are mixed is employed, and a thick insulating film is formed in the region A of the N-channel MOS transistor Q as shown in FIG. It is necessary to form a thin insulating film in this region. However, when such a structure is adopted, it is necessary to increase the distance between the word line WL and the cell plate electrode 48, and the size of the memory cell MC increases.
[0058]
Therefore, in the first embodiment, secondly, even if the gate insulating film 42 of the N channel MOS transistor Q is set to the same thin film thickness as the insulating film 47 of the capacitor C, the gate insulating film 42 of the N channel MOS transistor Q is used. A data writing method is employed so that the dielectric breakdown does not occur, and an increase in the size of the memory cell MC is prevented.
[0059]
FIG. 9 is a circuit diagram showing a configuration of the word driver 55 of the memory circuit unit 3. The word driver 55 is a circuit included in the row decoder 15 of FIG. 3, and is provided corresponding to each word line WL. Word driver 55 includes a level shifter 56, a switching circuit 57 and an inverter 58.
[0060]
The level shifter 56 converts the signal Xa whose “H” level is the power supply potential VCC and “L” level to the ground potential GND, into the signal whose “H” level is the boost potential VPP and “L” level is the ground potential GND, Invert. Signal Xa is predecoded and activated when row address signals RA0 to RAi designating the corresponding word line WL are input.
[0061]
That is, level shifter 56 includes P-channel MOS transistors 59 and 60, N-channel MOS transistors 64 and 65, and an inverter 67. P channel MOS transistors 59 and 60 are connected between a line of boosted potential VPP and nodes N59 and N60, respectively, and their gates are connected to nodes N60 and N59, respectively. N channel MOS transistors 64 and 65 are connected between nodes N59 and N60 and a line of ground potential GND, respectively. Signal Xa is directly input to the gate of N channel MOS transistor 64 and is also input to the gate of N channel MOS transistor 65 via inverter 67. The signal appearing at the node N59 becomes the output signal φP of the level shifter 56.
[0062]
When signal Xa is at the “L” level of the inactivation level, N channel MOS transistor 64 is turned off and N channel MOS transistor 65 is turned on. As a result, node N60 attains "L" level and P channel MOS transistor 59 becomes conductive, and the potential of node N59, that is, signal φP becomes boosted potential VPP and P channel MOS transistor 60 becomes nonconductive.
[0063]
When signal Xa is at the activation level “H” level, N-channel MOS transistor 64 becomes conductive and N-channel MOS transistor 65 becomes non-conductive. As a result, signal φP attains “L” level and P channel MOS transistor 60 becomes conductive, node N60 attains boosted potential VPP and P channel MOS transistor 59 becomes nonconductive.
[0064]
Switch circuit 57 includes P channel MOS transistors 61 and 62 and an inverter 68. P channel MOS transistor 61 is connected between a line of boosted potential VPP and power supply node N 63 of inverter 58. P channel MOS transistor 62 is connected between a power supply potential VCC line and a power supply node N 63 of inverter 58. Signal φACT is directly input to the gate of P channel MOS transistor 61 and is also input to the gate of P channel MOS transistor 62 via inverter 68.
[0065]
When signal φACT is at “H” level, P channel MOS transistor 61 is turned off and P channel MOS transistor 62 is turned on, and power supply potential VCC is applied to power supply node N 63 of inverter 58. When signal φACT is at “L” level, P channel MOS transistor 61 is turned on and P channel MOS transistor 62 is turned off, and boosted potential VPP is applied to power supply node N 63 of inverter 58.
[0066]
Inverter 58 includes a P channel MOS transistor 63 and an N channel MOS transistor 66. P channel MOS transistor 63 is connected between power supply node N 63 and corresponding word line WL, and has its gate receiving output signal φP of level shifter 56. N channel MOS transistor 66 is connected between a corresponding word line WL and a ground potential GND line, and has a gate receiving signal φP.
[0067]
When signal φP is at “L” level, P channel MOS transistor 63 is turned on and N channel MOS transistor 66 is turned off, and potential VPP or VCC of power supply node N63 is applied to word line WL. When signal φP is at “H” level, P channel MOS transistor 63 is turned off and N channel MOS transistor 66 is turned on, and ground potential GND is applied to word line WL.
[0068]
FIG. 10 is a time chart showing the operation of the word driver 55 shown in FIG. In the standby state, signal φACT is set to “H” level, P channel MOS transistor 61 is turned off and P channel MOS transistor 62 is turned on, and power supply potential VCC is applied to power supply node N63 of inverter 58. ing. Further, the signal Xa is set to the “L” level, the signal φP becomes the boosted potential VPP, the P-channel MOS transistor 63 is turned off, the N-channel MOS transistor 66 is turned on, and the word line WL is connected to the ground potential GND. Has been.
[0069]
When active command ACT is input by control signals / RAS, / CAS,... At a certain time, signal φACT falls to “L” level in the selected memory array block (for example, MAk). As a result, P channel MOS transistor 61 becomes conductive and P channel MOS transistor 62 becomes nonconductive, and boosted potential VPP is applied to power supply node N63 of inverter 58.
[0070]
The signal Xa is raised to the “H” level of the activation level after the elapse of a predetermined time from the input of the active command ACT, and the signal φP is lowered to the “L” level. As a result, N channel MOS transistor 66 is rendered non-conductive, P channel MOS transistor 63 is rendered conductive, and word line WL is set to boosted potential VPP.
[0071]
In the memory circuit section 3, as shown in FIG. 11, a local control circuit 70 is provided corresponding to each memory array block MA, and two signal generating circuits 71, 72 are provided corresponding to each sense amplifier band SA. Is provided. In FIG. 11, local control circuits 70. k-1,70. k, corresponding to the sense amplifier band SAk, the signal generating circuit 71. k, 72. A state in which k is provided is shown.
[0072]
Local control circuit 70. k−1 indicates that each of the signals φEk−1 and φFk−1 is activated at “H” at a predetermined timing in response to selection of the corresponding memory array block MAk−1 by the row address signals RA0 to RAi. To the level.
[0073]
Local control circuit 70. k sets each of the signals φEk and φFk to the activation level “H” level at a predetermined timing in response to selection of the corresponding memory array block MAk by the row address signals RA0 to RAi.
[0074]
Signal generation circuit 71. k indicates that the signal BLIR is set to the ground potential GND when the signals φEk and φFk−1 are at the “L” level, the signal BLIR is set to the power supply potential VCC when the signal φEk is set to the “H” level, and the signal φFk−1 is When it is set to “H” level, signal BLIR is set to negative potential VBB.
[0075]
Signal generation circuit 72. k indicates that the signal BLIL is set to the ground potential GND when the signals φEk−1 and φFk are at the “L” level, and the signal BLIL is set to the power supply potential VCC when the signal φEk−1 is set to the “H” level. When it is set to “H” level, signal BLIL is set to negative potential VBB.
[0076]
12 shows the signal generation circuit 71. It is a circuit block diagram which shows the structure of k. In FIG. 12, signal generation circuit 71. k includes inverters 73 and 74, P channel MOS transistor 75, N channel MOS transistors 76 to 78, and level shifter 79. MOS transistors 75-77 are connected in series between a power supply potential VCC line and a ground potential GND line. N channel MOS transistor 78 is connected between a node N78 between MOS transistors 75 and 76 and a line of negative potential VBB. Signal φEk is input to the gates of MOS transistors 75 and 76 via inverter 73. Signal φFk−1 is input to the gate of N-channel MOS transistor 77 via inverter 74 and input to the gate of N-channel MOS transistor 78 via level shifter 79. Note that the negative potential VBB may be the same as the potential applied to the P-type well 41 in FIG. 6 or may be at a different potential level.
[0077]
The level shifter 79 converts the signal φFk−1 whose “H” level is the power supply potential VCC and “L” level to the ground potential GND, and into the signal φ79 whose “H” level is the power supply potential VCC and whose “L” level is the negative potential VBB. To do.
[0078]
That is, level shifter 79 includes P channel MOS transistors 80 and 81, N channel MOS transistors 82 and 83, and an inverter 84 as shown in FIG. P channel MOS transistors 80 and 81 are connected between a power supply potential VCC line and nodes N80 and N81, respectively. Signal φFk−1 is directly input to the gate of P channel MOS transistor 80 and also input to the gate of P channel MOS transistor 81 via inverter 84. N channel MOS transistors 82 and 83 are connected between nodes N80 and N81 and the line of negative potential VBB, respectively, and their gates are connected to nodes N81 and N80, respectively. A signal appearing at the node N81 becomes an output signal φ79 of the level shifter 79.
[0079]
When signal φFk−1 is at “L” level, P channel MOS transistor 80 is turned on and P channel MOS transistor 81 is turned off. As a result, node N80 attains "H" level and N channel MOS transistor 83 becomes conductive, node N81 attains "L" level (negative potential VBB) and N channel MOS transistor 82 becomes nonconductive. Therefore, signal φ79 becomes negative potential VBB.
[0080]
When signal φFk−1 is at “H” level, P channel MOS transistor 80 is turned off and P channel MOS transistor 81 is turned on. As a result, node N81 attains "H" level (power supply potential VCC) and N channel MOS transistor 82 becomes conductive, and node N80 attains "L" level and N channel MOS transistor 83 becomes nonconductive. Therefore, the signal φ79 becomes the power supply potential VCC.
[0081]
Referring back to FIG. 12, when both signals φEk and φFk−1 are at “L” level, N channel MOS transistors 76 and 77 are turned on, and P channel MOS transistor 75 and N channel MOS transistor 78 are turned off. The signal BLIR becomes the ground potential GND. When signals φEk and φFk−1 are at “H” level and “L” level, respectively, P channel MOS transistor 75 and N channel MOS transistor 77 are turned on, and N channel MOS transistors 76 and 78 are turned off. BLIR becomes the power supply potential VCC. When signals φEk and φFk−1 are at “L” level and “H” level, respectively, N channel MOS transistors 76 and 78 are turned on, and P channel MOS transistor 75 and N channel MOS transistor 77 are turned off. BLIR becomes a negative potential VBB. There is no case where the signals φEk and φFk−1 both attain “H” level.
[0082]
Signal generation circuit 72. k, as shown in FIG. The same configuration as k. However, signals φEk−1 and φFk are input instead of signals φEk and φFk−1, respectively, and signal BLIL is output instead of signal BLIR. When signals φEk−1 and φFk are both at “L” level, signal BLIL is at ground potential GND, and when signals φEk−1 and φFk are at “H” level and “L” level, signal BLIL is at power supply potential VCC. When signals φEk−1 and φFk are at “L” level and “H” level, respectively, signal BLIL is at negative potential VBB. Signals φEk−1 and φFk are never at “H” level.
[0083]
FIG. 15 shows the local control circuit 70. k-1,70. k and signal generation circuit 71. k, 72. It is a time chart which shows operation | movement of k. A case where memory array block MAk is selected by row address signals RA0-RAi will be described.
[0084]
In the standby state, signals φEk−1, φEk, φFk−1, and φFk are all at “L” level, and signals BLIR and BLIL are both at ground potential GND. When an active command ACT is input at a certain time and the memory array block MAk is selected, the local control circuit 70. k raises signal φEk to “H” level, and signal generating circuit 71. The signal BLIR is raised to the power supply potential VCC by k. Next, when the precharge command PRE is input, the local control circuit 70. k raises signal φFk to “H” level, and signal generating circuit 70. The signal BLIL is lowered to the negative potential VBB by k. When a predetermined time elapses after the input of the precharge command PRE, the signals φEk and φFk are both lowered to the “L” level, and the signals BLIR and BLIL are both set to the ground potential GND.
[0085]
FIG. 16 is a time chart showing a data writing method of the memory circuit unit 3 shown in FIGS. In FIG. 16, in the standby state, the word line WL is set to the ground potential GND, and the N channel MOS transistor Q of the memory cell MC is non-conductive. The storage node SN of the memory cell MC holds the power supply potential VCC or the ground potential GND. Signals BLIR and BLIL are both at the ground potential GND, and both transfer gates 21 and 36 in FIG. 5 are conductive. Further, the signal BLEQ is set to the “H” level, and the bit line pair BL, / BL is equalized to the bit line precharge potential VBL = VCC / 2 by the equalizer 32 of FIG.
[0086]
When active command ACT is input at a certain time and, for example, memory array block MAk is selected, signal BLIR is raised to “H” level, transfer gate 21 in FIG. 5 becomes non-conductive, and sense amplifier 27 is turned on. Disconnected from memory array block MAk-1. Further, the signal BLEQ is set to the “L” level, and the equalization of the potentials of the bit lines BL and / BL is stopped.
[0087]
Next, the word line WL in the row corresponding to the row address signals RA0 to RAi is raised to the boosted potential VPP. As a result, the N channel MOS transistor Q of the memory cell MC connected to the word line WL becomes conductive, and a minute potential difference corresponding to the stored data of the memory cell MC is generated between the bit line pair BL, / BL. At this time, for example, the potential of the bit line BL is assumed to be slightly higher than the potential of the bit line / BL. Next, the sense amplifier activation signals SE and / SE in FIG. 5 are respectively set to the “H” level and the “L” level to activate the sense amplifier 27, and a minute potential difference between the nodes N1 and N2 is amplified to the power supply voltage VCC. Is done.
[0088]
At this time, nodes N1 and N2 are set to power supply potential VCC and ground potential GND, respectively, but bit lines BL and / BL are set to power supply potential VCC and threshold voltage | Vtp | of P channel MOS transistor 38, respectively. This is because even if node N1 and signal BLIL are set to ground potential GND, P-channel MOS transistor 38 becomes non-conductive when bit line / BL becomes | Vtp |.
[0089]
For this reason, as shown in FIG. 17A, the voltage Vgs applied to the gate insulating film of the N-channel MOS transistor Q of the memory cell MC is suppressed to the maximum Vgs = VPP− | Vtp |. The threshold voltage | Vtp | of the P-channel MOS transistors 22, 23, 37, and 38 of the transfer gates 21 and 36 is set to satisfy VPP− | Vtp | ≈VCC. Therefore, there is no problem in reliability even if the gate insulating film of the N channel MOS transistor Q of the memory cell MC is as thin as the insulating film of the capacitor C.
[0090]
Next, the column selection line CSL of the column corresponding to the column address signals CA0 to CAi is raised to the “H” level of the selection level, and the column selection gate 24 of FIG. 5 is turned on. Then, one data input / output line (for example, / IO) of data input / output line pair IO, / IO is set to "H" level according to the write data signal, and the other data input / output line (IO in this case) is set. It is set to “L” level. In response, node N2 is raised to power supply potential VCC by sense amplifier 27, and node N1 is lowered to ground voltage GND. Even at this time, nodes N1 and N2 are at ground voltage GND and power supply potential VCC, respectively, but bit lines BL and / BL are at threshold voltage | Vtp | and power supply potential VCC of P channel MOS transistor 37, respectively. Therefore, the voltage Vgs applied to the gate insulating film of the N channel MOS transistor Q of the memory cell MC can be suppressed to the maximum Vgs = VPP− | Vtp |.
[0091]
During this period, when the “H” level is written to the storage node SN of the memory cell MC, the storage node SN can be set to the power supply potential VCC, and the “H” level data can be sufficiently written. However, when “L” level data is written, storage node SN cannot be set to ground potential GND, and data writing becomes insufficient. Therefore, the “L” level restoration is performed next.
[0092]
That is, the precharge command PRE is input to lower the word line WL from the boosted potential VPP to the power supply potential VCC and to lower the signal BLIL from the ground potential GND to the negative potential VBB. Thereby, P channel MOS transistor 37 of transfer gate 36 in FIG. 5 is turned on again, and bit line BL and storage node SN are lowered to ground potential GND. At this time, as shown in FIG. 17B, the voltage Vgs applied to the gate insulating film of the N-channel MOS transistor Q of the memory cell MC is Vgs = VCC, and there is no possibility that the gate insulating film is broken down. .
[0093]
The period for restoring the “L” level may be short. When restoration of “L” level is completed, word line WL is raised to “L” level, N channel MOS transistor Q of memory cell MC is turned off, and the level of storage node SN is maintained. Signals BLIR and BLIL are both set to ground potential GND, transfer gates 21 and 36 are turned on, signals SE and / SE are both set to the bit line precharge potential level (VCC / 2), and sense amplifier 27 is inactivated. Then, signal BLEQ is set to “H” level, and bit line pair BL, / BL is equalized to bit line potential VBL.
[0094]
In the first embodiment, since VPP− | Vtp | ≈VCC is set, the gate insulating film of the N-channel MOS transistor Q of the memory cell MC can be made as thin as the insulating film of the capacitor C, and the size Small memory cells MC can be configured. Further, since the "L" level restoration is performed after the data writing, the level of the data signal can be sufficiently written in storage node SN of memory cell MC.
[0095]
In the first embodiment, boosted potential VPP is applied to one word line WL, and one memory cell MC connected to one bit line BL or / BL is set to “H” level or “L” level. And 1-bit data was stored. However, in the present invention, as shown in FIG. 18, a boosted potential VPP is applied to two word lines WL, and one memory cell MC of two memory cells MC connected to bit lines BL and / BL, respectively. Needless to say, the present invention can also be applied to a memory storing 1-bit data by writing the “H” level to the other memory cell MC. Further, as shown in FIG. 19, boosted potential VPP is applied to one word line WL, and “H” is applied to one of the two memory cells MC connected to bit lines BL and / BL. It is also applicable to a memory that stores 1-bit data by writing the level and writing the “L” level in the other memory cell MC.
[0096]
[Embodiment 2]
FIG. 20 is a circuit diagram showing the main part of the memory circuit part of the system LSI according to the second embodiment of the present invention, which is compared with FIG. Referring to FIG. 20, the memory circuit portion is different from the memory circuit portion of FIG. 5 in that memory cell MC is replaced with memory cell MC ′, and transfer gates 21 and 36 are replaced with transfer gates 90 and 93. It is a point.
[0097]
Memory cell MC ′ is obtained by replacing N channel MOS transistor Q of memory cell MC with P channel MOS transistor Q ′. In the standby state, the word line WL is held at the “H” level which is a non-selected level. When row address signals RA0-RAi are input, the designated word line WL is lowered to the "L" level of the selection level. When the word line WL falls to the “L” level, the P channel MOS transistor Q ′ of the memory cell MC ′ connected to the word line WL becomes conductive, and the storage node SN and the bit line BL of the memory cell MC ′. Or, / BL is combined. The structure of the memory cell MC ′ is the same as that of the memory cell MC shown in FIG. However, memory cell MC ′ is formed on the surface of an N-type well, and the source region and drain region of P-channel MOS transistor Q ′ and storage node SN are formed of a P-type diffusion layer.
[0098]
Transfer gate 90 is obtained by replacing P channel MOS transistors 22 and 23 of transfer gate 21 with N channel MOS transistors 91 and 92. In the standby state, signal BLIR is held at “H” level. When memory array block MAk is selected, signal BLIR falls to "L" level, transfer gate 90 is rendered non-conductive, and memory array block MAk-1 and sense amplifier band SAk are disconnected.
[0099]
Transfer gate 93 is obtained by replacing P channel MOS transistors 37 and 38 of transfer gate 36 with N channel MOS transistors 94 and 95. In the standby state, signal BLIL is held at “H” level. When memory array block MAk-1 is selected, signal BLIL falls to "L" level, transfer gate 93 is rendered non-conductive, and memory array block MAk and sense amplifier band SAk are disconnected.
[0100]
FIG. 21 is a time chart showing the data writing method of the memory circuit unit described with reference to FIG. 20, and is a diagram compared with FIG. In FIG. 21, in the standby state, the word line WL is set to the power supply potential VCC, and the P channel MOS transistor Q ′ of the memory cell MC ′ is non-conductive. The storage node SN of the memory cell MC ′ holds the power supply potential VCC or the ground potential GND. Signals BLIR and BLIL are both at power supply potential VCC, and both transfer gates 90 and 93 are conductive. Further, the signal BLEQ is set to “H” level, and the equalizer 32 equalizes the bit line pair BL, / BL to the bit line potential VBL = VCC / 2.
[0101]
When active command ACT is input at a certain time and, for example, memory array block MAk is selected, signal BLIR is raised to ground potential GND, transfer gate 90 is rendered non-conductive, and sense amplifier 27 is connected to memory array block MAk. Disconnected from -1. Further, the signal BLEQ is set to the “L” level, and the equalization of the potentials of the bit lines BL and / BL is stopped.
[0102]
Next, the word line WL of the row corresponding to the row address signals RA0 to RAi is lowered to the negative potential VBB. As a result, the P channel MOS transistor Q ′ of the memory cell MC ′ connected to the word line WL becomes conductive, and a minute potential difference corresponding to the stored data of the memory cell MC ′ is generated between the bit line pair BL, / BL. . At this time, for example, the potential of the bit line BL is assumed to be slightly higher than the potential of the bit line / BL. Next, sense amplifier activation signals SE and / SE are respectively set to “H” level and “L” level to activate sense amplifier 27, and a minute potential difference between nodes N1 and N2 is amplified to power supply potential VCC.
[0103]
At this time, the nodes N1 and N2 are set to the power supply potential VCC and the ground potential GND, respectively, but the bit lines BL and / BL are set to VCC−Vtn and GND, respectively. Vtn is a threshold voltage of N channel MOS transistor 94. This is because even if the node N1 and the signal BLIL are set to the power supply potential VCC, the N channel MOS transistor 94 becomes non-conductive when the bit line BL becomes VCC-Vtn.
[0104]
Therefore, the voltage Vgs applied to the gate insulating film of the P channel MOS transistor Q ′ of the memory cell MC ′ is suppressed to the maximum Vgs = | VBB | + VCC−Vtn. The threshold voltage Vtn of the N-channel MOS transistors 91, 92, 94, 95 of the transfer gates 90, 93 is set so that | VBB | + VCC−Vtn≈VCC. Therefore, there is no problem in reliability even if the gate insulating film of the P-channel MOS transistor Q ′ of the memory cell MC ′ is as thin as the insulating film of the capacitor C.
[0105]
Next, the column selection line CSL of the column corresponding to the column address signals CA0 to CAi is raised to the “H” level of the selection level, and the column selection gate 24 becomes conductive. Then, according to the write data signal, one data input / output line (for example, / IO) of data input / output line pair IO, / IO is set to "H" level and the other data input / output line (IO in this case) is set to " L ”level. In response, node N2 is raised to power supply potential VCC by sense amplifier 27, and node N1 is lowered to ground potential GND. Even at this time, the nodes N1 and N2 become the ground potential GND and the power supply potential VCC, respectively, but the bit lines BL and / BL become VCC-Vtn and GND, respectively. Therefore, the voltage Vgs applied to the gate insulating film of the P channel MOS transistor Q ′ of the memory cell MC ′ is suppressed to the maximum Vgs = | VBB | + VCC−Vtn. During this period, when the “L” level is written to the storage node SN of the memory cell MC ′, the storage node SN can be set to the ground potential GND, and the “L” level data can be sufficiently written. . However, when “H” level data is written, storage node SN cannot be set to power supply potential VCC, and data writing is insufficient. Therefore, the “H” level restoration is performed next.
[0106]
That is, the precharge command PRE is input to raise the word line WL from the negative potential VBB to the ground potential GND and to raise the signal BLIL from the power supply potential VCC to the boosted potential VPP. Thereby, N channel MOS transistor 94 of transfer gate 93 is rendered conductive again, and bit line BL and storage node SN are raised to power supply potential VCC. At this time, the voltage Vgs applied to the gate insulating film of the P-channel MOS transistor Q ′ of the memory cell MC ′ becomes Vgs = VCC, and there is no possibility that the gate insulating film is broken down.
[0107]
The period for restoring the “H” level may be short. When restoration of "H" level is completed, word line WL is raised to power supply potential VCC, P channel MOS transistor Q 'of memory cell MC' is turned off, and the level of storage node SN is maintained. Further, both the signals BLIR and BLIL are set to the power supply potential VCC, the transfer gates 90 and 93 are turned on, the signals SE and / SE are both set to the bit line precharge potential VCC / 2, and the sense amplifier 27 is deactivated. BLEQ is set to “H” level, and the bit line pair BL, / BL is equalized to the bit line potential VBL.
[0108]
In the second embodiment, since | VBB | + VCC−Vtn≈VCC is set, the gate insulating film of the P-channel MOS transistor Q ′ of the memory cell MC ′ should be made as thin as the insulating film of the capacitor C. The memory cell MC ′ having a small size can be formed. In addition, since the “H” level restore is performed after the data writing, the level of the data signal can be sufficiently written in storage node SN of memory cell MC ′.
[0109]
Needless to say, this second embodiment can also be applied to a system in which 1-bit data is stored in two memory cells MC ′ as described in FIGS. 18 and 19.
[0110]
[Embodiment 3]
FIG. 22 is a circuit block diagram showing the main part of the memory circuit part of the system LSI according to the third embodiment of the present invention, and is a figure compared with FIG. Referring to FIG. 22, this memory circuit portion is different from the memory circuit portion of FIG. 20 in that two memory cells MC are arranged at the intersection of word line WL and bit line pair BL, / BL. The equalizer 32 is removed, and two equalizers 100 and 104 are provided.
[0111]
The gates of the N channel MOS transistors Q of the two memory cells MC are both connected to the corresponding word line WL, and the sources of the N channel MOS transistors Q of the two memory cells MC are respectively connected to the corresponding bit lines BL and / BL. Connected. The “H” level is written in one of the two memory cells MC, and the “L” level is written in the other memory cell MC. 1-bit data is stored in two memory cells MC.
[0112]
Equalizer 100 includes three P channel MOS transistors 101-103. P channel MOS transistor 101 is connected between corresponding bit lines BL and / BL of memory array block MAk-1. P channel MOS transistors 102 and 103 are respectively connected between corresponding bit lines BL and / BL and node N8. The gates of P channel MOS transistors 101-103 are all connected to node N7. Node N7 receives bit line equalize signal BLEQ, and node N8 receives bit line precharge potential VBL = VCC. When signal BLEQ is set to the “L” level of the activation level, P channel MOS transistors 101-103 are rendered conductive, and bit line pair BL, / BL is equalized to bit line potential VBL.
[0113]
Equalizer 104 includes three P channel MOS transistors 105-107. P channel MOS transistor 105 is connected between corresponding bit lines BL and / BL of memory array block MAk. P channel MOS transistors 106 and 107 are connected between corresponding bit lines BL and / BL and node N10, respectively. The gates of P channel MOS transistors 105-107 are all connected to node N9. Node N9 receives bit line equalize signal BLEQ, and node N10 receives bit line precharge potential VBL = VCC. When signal BLEQ is set to the “L” level of the activation level, P channel MOS transistors 105-107 are rendered conductive, and bit line pair BL, / BL is equalized to bit line precharge potential VBL.
[0114]
FIG. 23 is a time chart showing the data writing method of the memory circuit portion described in FIG. In FIG. 23, in the standby state, the word line WL is set to the ground potential GND, and the N channel MOS transistors Q of the two memory cells MC in FIG. 22 are both non-conductive. The power supply potential VCC is written in one of the two memory cells MC, and the ground potential GND is held in the other memory cell MC. The signals BLIR and BLIL are both set to the boosted potential VPP, and the transfer gates 90 and 93 are both conductive. Further, the signal BLEQ is set to the “L” level, and the equalizers 100 and 104 equalize the bit line pair BL and / BL to the bit line precharge potential VBL = VCC.
[0115]
When active command ACT is input at a certain time and, for example, memory array block MAk is selected, signal BLIR falls to ground potential GND, transfer gate 90 becomes non-conductive, and sense amplifier 27 is connected to memory array block MAk. Disconnected from -1. Further, the signal BLEQ is set to the “H” level, and the equalization of the potentials of the bit lines BL and / BL is stopped.
[0116]
Next, the word line WL of the row corresponding to the row address signals RA0 to RAi is raised to the boosted potential VPP. As a result, the N-channel MOS transistor Q of the two memory cells MC of FIG. 22 connected to the word line WL is turned on, and a minute amount corresponding to the stored data of the two memory cells MC between the bit line pair BL, / BL. A potential difference occurs. At this time, for example, the potential of the bit line BL is assumed to be slightly higher than the potential of the bit line / BL.
[0117]
Next, signals BLIL and BLIR are both set to ground potential GND, transfer gates 90 and 93 are rendered non-conductive, and sense amplifier 27 and two memory array blocks MAk-1 and MAk are disconnected. Further, the signal BLEQ is lowered to “L” level to activate the equalizers 100 and 104, and the bit line pairs BL and / BL of the memory array blocks MAk−1 and MAk are set to the bit line precharge potential VBL = VCC. Equalized. At this time, the ground potential GND is applied to the gates of the P-channel MOS transistors 101 to 103 and 105 to 107 of the equalizers 100 and 104, and the boosted potential VPP is applied to the word line WL in FIG. Sufficient “H” level (power supply potential VCC) is applied to the storage node SN of MC.
[0118]
Sense amplifier activation signals SE and / SE are set to “H” level and “L” level, respectively, to activate sense amplifier 27, and a small potential difference between nodes N1 and N2 is amplified to power supply potential VCC.
[0119]
At this time, since the voltage Vgs applied to the gate insulating film of the N channel MOS transistor Q of the memory cell MC is Vgs = VPP−VCC, the gate insulating film of the N channel MOS transistor Q of the memory cell MC is insulated from the capacitor C. Even if it is as thin as the film, there is no problem in reliability.
[0120]
Next, the column selection line CSL of the column corresponding to the column address signals CA0 to CAi ′ is raised to the “H” level of the selection level, and the column selection gate 24 becomes conductive. Then, according to the write data signal, one data input / output line (for example, / IO) of data input / output line pair IO, / IO is set to "H" level and the other data input / output line (IO in this case) is set to " L ”level. In response, node N2 is raised to power supply potential VCC by sense amplifier 27, and node N1 is lowered to ground voltage GND.
[0121]
Next, when the precharge command PRE is input, the word line WL is lowered from the boosted potential VPP to the power supply potential VCC, the signal BLEQ is raised to the “H” level, and the equalizers 100 and 104 are deactivated. Is done. Further, the signal BLIL is raised to the boosted potential VPP and the transfer gate 93 becomes conductive, and the potentials GND and VCC of the nodes N1 and N2 are transmitted to the bit lines BL and / BL of the memory array block MAk, respectively. It is written to the storage node SN of the MC. At this time, since signal BLIL is set to boosted potential VPP, sufficient “L” level is written to storage node SN of memory cell MC. At this time, the voltage Vgs applied to the gate insulating film of the N-channel MOS transistor Q of the memory cell MC is Vgs = VCC, and there is no possibility that the gate insulating film is broken down.
[0122]
When "L" level writing is completed, word line WL is lowered to ground potential GND, N channel MOS transistor Q of memory cell MC is turned off, and the level of storage node SN is maintained. Signals BLIR and BLIL are both set to boosted potential VPP, transfer gates 90 and 93 are turned on, signals SE and / SE are set to the bit line precharge potential level of VCC / 2, and sense amplifier 27 is deactivated. Signal BLEQ is set to “L” level to equalize bit line pair BL, / BL to bit line precharge potential VBL.
[0123]
In the third embodiment, first, the word line WL is set to the boosted potential VPP and the “H” level data is written to one memory cell MC, and then the word line WL is set to the power supply potential VCC and the “L” level data is written. Write to the other memory cell MC. Therefore, voltage Vgs applied to the gate insulating film of N channel MOS transistor Q of memory cell MC can be reduced to VCC or less, and the gate insulating film of N channel MOS transistor Q of memory cell MC can be used as the insulating film of capacitor C. The same thin film thickness can be obtained, and as a result, a small-sized memory cell MC can be configured. Further, “H” level or “L” level can be sufficiently written to storage node SN of memory cell MC.
[0124]
In the third embodiment, the present invention is applied to a system in which 1-bit data signal is stored in two memory cells MC and the two memory cells MC are connected to one word line WL. Can be applied to a method of storing 1-bit data in one memory cell MC, and, as shown in FIG. 8, two memory cells MC store a 1-bit data signal and store two memories. Needless to say, the present invention is also applicable to a system in which each cell MC is connected to two word lines WL.
[0125]
[Embodiment 4]
FIG. 24 is a circuit block diagram showing the main part of the memory circuit part of the system LSI according to the fourth embodiment of the present invention, which is compared with FIG. Referring to FIG. 24, this memory circuit portion is different from the memory circuit portion of FIG. 22 in that memory cell MC is replaced by memory cell MC ′ and equalizers 100 and 104 are replaced by equalizers 110 and 114. It is a point that has been.
[0126]
The gates of the P channel MOS transistors Q ′ of the two memory cells MC ′ are both connected to the corresponding word line WL, and the sources of the P channel MOS transistors Q ′ of the two memory cells MC ′ are respectively connected to the corresponding bit lines BL. , / BL. "H" level is written in one memory cell MC 'of the two memory cells MC', and "L" level is written in the other memory cell MC '. 1-bit data is stored in the two memory cells MC ′.
[0127]
Equalizer 110 includes three N channel MOS transistors 111-113. N channel MOS transistor 111 is connected between corresponding bit lines BL and / BL of memory array block MAk-1. N channel MOS transistors 112 and 113 are connected between corresponding bit lines BL and / BL and node N8, respectively. The gates of N channel MOS transistors 111-113 are all connected to node N7. Node N7 receives bit line equalize signal BLEQ, and node N8 receives bit line precharge potential VBL = GND. When signal BLEQ is set to the “H” level of the activation level, N channel MOS transistors 111-113 are rendered conductive, and bit line pair BL, / BL is equalized to bit line potential VBL.
[0128]
Equalizer 114 includes three N channel MOS transistors 115-117. N channel MOS transistor 115 is connected between corresponding bit lines BL and / BL of memory array block MAk. N channel MOS transistors 116 and 117 are respectively connected between corresponding bit lines BL and / BL and node N10. The gates of N channel MOS transistors 115-117 are all connected to node N9. Node N9 receives bit line equalize signal BLEQ, and node N10 receives bit line precharge potential VBL = GND. When signal BLEQ is set to the activation level “H” level, N channel MOS transistors 115 to 117 are rendered conductive, and bit line pair BL, / BL is equalized to bit line precharge potential VBL.
[0129]
FIG. 25 is a time chart showing a data writing method of the memory circuit portion described in FIG. In FIG. 25, in the standby state, the word line WL is set to the power supply potential VCC, and the P channel MOS transistors Q ′ of the two memory cells MC ′ of FIG. 24 are both non-conductive. The power supply potential VCC is written in one of the two memory cells MC ′, and the ground potential GND is held in the other memory cell MC ′. The signals BLIR and BLIL are both set to the boosted potential VPP, and the transfer gates 90 and 93 are both conductive. The signal BLEQ is set to “H” level, and the equalizers 110 and 114 equalize the bit line pair BL and / BL to the bit line precharge potential VBL = GND.
[0130]
When active command ACT is input at a certain time and, for example, memory array block MAk is selected, signal BLIR falls to ground potential GND, transfer gate 90 becomes non-conductive, and sense amplifier 27 is connected to memory array block MAk. Disconnected from -1. Further, the signal BLEQ is set to the “L” level, and the equalization of the potentials of the bit lines BL and / BL is stopped.
[0131]
Next, the word line WL of the row corresponding to the row address signals RA0 to RAi is lowered to the negative potential VBB. As a result, the P channel MOS transistor Q ′ of the two memory cells MC ′ of FIG. 24 connected to the word line WL becomes conductive, and the data stored in the two memory cells MC ′ is transferred between the bit line pair BL and / BL. A corresponding minute potential difference is generated. At this time, for example, the potential of the bit line BL is assumed to be slightly higher than the potential of the bit line / BL.
[0132]
Next, signals BLIL and BLIR are both set to ground potential GND, transfer gates 90 and 93 are rendered non-conductive, and sense amplifier 27 and two memory array blocks MAk-1 and MAk are disconnected. Further, signal BLEQ is raised to “H” level to activate equalizers 110 and 114, and each bit line pair BL and / BL of memory array blocks MAk−1 and MAk is set to bit line precharge potential VBL = GND. Equalized. At this time, the power supply potential VCC is applied to the gates of the N-channel MOS transistors 111 to 113 and 115 to 117 of the equalizers 110 and 114, and the negative potential VBB is applied to the word line WL of FIG. Sufficient “L” level (ground potential GND) is applied to the storage node SN of MC ′.
[0133]
Sense amplifier activation signals SE and / SE are set to “H” level and “L” level, respectively, to activate sense amplifier 27, and a small potential difference between nodes N1 and N2 is amplified to power supply voltage VCC.
[0134]
At this time, the voltage Vgs applied to the gate insulating film of the P channel MOS transistor Q ′ of the memory cell MC ′ is Vgs = VBB−GND. Therefore, the gate insulating film of the P channel MOS transistor Q ′ of the memory cell MC ′ Even if it is as thin as the insulating film of the capacitor C, there is no problem in reliability.
[0135]
Next, the column selection line CSL of the column corresponding to the column address signals CA0 to CAi ′ is raised to the “H” level of the selection level, and the column selection gate 24 becomes conductive. Then, according to the write data signal, one data input / output line (for example, / IO) of data input / output line pair IO, / IO is set to "H" level and the other data input / output line (IO in this case) is set to " L ”level. In response, node N2 is raised to power supply potential VCC by sense amplifier 27, and node N1 is lowered to ground potential GND.
[0136]
Next, when the precharge command PRE is input, the word line WL is raised from the negative potential VBB to the ground potential GND, the signal BLEQ is lowered to the “L” level, and the equalizers 110 and 114 are deactivated. Is done. Further, the signal BLIL is raised to the boosted potential VPP and the transfer gate 93 becomes conductive, and the potentials GND and VCC of the nodes N1 and N2 are transmitted to the bit lines BL and / BL of the memory array block MAk, respectively. It is written in the storage node SN of MC ′. At this time, since signal BLIL is set to boosted potential VPP, a sufficient “H” level is written in storage node SN of memory cell MC ′. At this time, the voltage Vgs applied to the gate insulating film of the P-channel MOS transistor Q ′ of the memory cell MC ′ is Vgs = VCC, and there is no possibility that the gate insulating film is broken down.
[0137]
When "H" level writing is completed, word line WL is raised to power supply potential VCC, P channel MOS transistor Q 'of memory cell MC' is turned off, and the level of storage node SN is maintained. Signals BLIR and BLIL are both set to boosted potential VPP, transfer gates 90 and 93 are turned on, signals SE and / SE are set to the bit line precharge potential level of VCC / 2, and sense amplifier 27 is deactivated. Signal BLEQ is set to “H” level to equalize bit line pair BL, / BL to bit line precharge potential VBL.
[0138]
In the fourth embodiment, first, the word line WL is set to the negative potential VBB, and the “L” level data is written to one memory cell MC ′. Next, the word line WL is set to the ground potential GND and the “H” level data is written. Is written into the other memory cell MC ′. Therefore, voltage Vgs applied to the gate insulating film of P channel MOS transistor Q ′ of memory cell MC ′ can be made equal to or lower than VCC, and the gate insulating film of P channel MOS transistor Q ′ of memory cell MC ′ can be used as capacitor C. Therefore, the memory cell MC ′ having a small size can be formed. Further, “H” level or “L” level can be sufficiently written to storage node SN of memory cell MC ′.
[0139]
In the fourth embodiment, the 1-bit data signal is stored in the two memory cells MC ′, and the two memory cells MC ′ are connected to one word line WL. This method can also be applied to a method in which 1-bit data is stored in one memory cell MC ′. Further, as shown in FIG. 8, a 1-bit data signal is stored in two memory cells MC ′. Needless to say, the present invention is also applicable to a system in which two memory cells MC ′ are connected to two word lines WL, respectively.
[0140]
[Embodiment 5]
FIG. 26 is a circuit diagram showing the main part of the memory circuit part of the system LSI according to the fifth embodiment of the present invention, and is a figure compared with FIG. Referring to FIG. 26, the memory circuit portion is different from the memory circuit portion of FIG. 5 in that a memory array block MA ′ adjacent to memory array block MA is added. FIG. 26 shows a memory array block MAk ′ adjacent to the memory array block MAk.
[0141]
Memory array block MAk ′ has the same number of rows and columns as memory array block MAk, a plurality of memory cells MC ′ arranged in a matrix, word line / WL provided corresponding to each row, Bit line pairs BL and / BL provided corresponding to the columns are included. Memory cell MC ′ is obtained by replacing N channel MOS transistor Q of memory cell MC with P channel MOS transistor Q ′. The plurality of word lines / WL of the memory array block MAk ′ are provided corresponding to the plurality of word lines WL of the memory array block MAk, respectively. The word line WL and the corresponding word line / WL are paired. When the word line WL is set to the “H” level (power supply voltage VCC) of the selection level, the corresponding word line / WL is set to “ L "level (ground potential GND). Bit lines BL, / BL of memory array block MAk and bit lines BL, / BL of memory array block MAk ′ are connected. The activation level of signals BLIR and BLIL is negative potential VBB, and the inactivation level thereof is power supply potential VCC.
[0142]
Now, it is assumed that the memory array blocks MAk and MAk ′ are selected and the signal BLIL is set to the negative potential VBB of the activation level. In the write mode, a pair of word lines WL, / WL designated by row address signals RA0-RAi are set to power supply potential VCC and ground potential GND, respectively, and memory cells corresponding to these word lines WL, / WL MC N channel MOS transistor Q and memory cell MC ′ P channel MOS transistor Q ′ are rendered conductive. Then, one of bit lines BL and / BL is set to power supply potential VCC and the other is set to ground potential GND according to the write data signal.
[0143]
When bit line BL is set to power supply potential VCC, a sufficient “H” level (power supply potential VCC) is written to storage node SN of memory cell MC ′, while VCC− is applied to storage node SN of memory cell MC. Vtn is written. When bit line BL is set to ground potential GND, a sufficient “L” level (ground potential GND) is written to storage node SN of memory cell MC, while | Vtp is stored in storage node SN of memory cell MC ′. | Is written.
[0144]
In the read mode, if "H" level is written in memory cells MC and MC ', when word lines WL and / WL are set to power supply potential VCC and ground potential GND, respectively, memory cell MC' P channel MOS transistor Q 'is sufficiently turned on to sufficiently read "H" level data from memory cell MC', while N channel MOS transistor Q of memory cell MC is not sufficiently turned on to start from memory cell MC. "H" level data is not sufficiently read out.
[0145]
In addition, when “L” level is written in memory cells MC and MC ′, N-channel MOS transistor of memory cell MC when word lines WL and / WL are set to power supply potential VCC and ground potential GND, respectively. Q is sufficiently turned on to read “L” level data sufficiently from memory cell MC, while P-channel MOS transistor Q ′ of memory cell MC ′ is not sufficiently turned on and from memory cell MC ′ to “L”. "Level data is not fully read out.
[0146]
In the fifth embodiment, reading / writing of “L” level data is performed in memory cell MC, and reading / writing of “H” level data is performed in memory cell MC ′. Therefore, word lines WL, / Data can be sufficiently read / written even if the amplitude voltage of WL is the power supply voltage VCC. Therefore, the gate insulating films of the N channel MOS transistor Q and the P channel MOS transistor Q ′ of the memory cells MC and MC ′ can be made as thin as the insulating film of the capacitor C. 'Can be configured.
[0147]
The embodiment disclosed this time should be considered as illustrative in all points and not restrictive. The scope of the present invention is defined by the terms of the claims, rather than the description above, and is intended to include any modifications within the scope and meaning equivalent to the terms of the claims.
[0148]
【The invention's effect】
  As described above, in the semiconductor memory device according to the present invention, the semiconductor memory device is formed on the semiconductor substrate together with the logic circuit including the MOS transistor, has the MOS transistor and the capacitor connected in series, and stores the data signal. The MOS transistor is formed on the surface of the semiconductor substrate on both sides of the gate electrode, the gate electrode formed on the surface of the gate insulating film, and the gate electrode formed on the surface of the gate insulating film. The capacitor includes an impurity diffusion region formed on the surface of the semiconductor substrate, an insulating film formed on the surface of the impurity diffusion region, and a reference potential formed on the surface of the insulating film. A flat plate electrode for receiving,The logic circuit MOS transistor, the memory cell MOS transistor and the capacitor are formed by the same CMOS process, andThe gate electrode of the MOS transistor of the logic circuit, the gate electrode of the MOS transistor of the memory cell, and the plate electrode of the capacitor are formed in the same wiring layer. Therefore, it is not necessary to separately provide a wiring layer for storage nodes and capacitor electrodes, and a system LSI including a semiconductor memory device and a logic circuit can be manufactured only by a CMOS logic process, so that the chip cost can be reduced. . In addition, since the gate insulating film of the MOS transistor and the insulating film of the capacitor have the same thickness, the distance between the MOS transistor and the capacitor can be shortened, and the chip size can be reduced. Further, since the dynamic memory cell is employed, the memory capacity can be increased as compared with the case where the static memory cell is employed.
[0150]
  MaTheThe MOS transistor of the memory cell is an N channel MOS transistor, and the semiconductor memory device further includes a word line connected to the gate of the N channel MOS transistor and one of them connected to the source of the N channel MOS transistor. Between the first and second bit lines, the first P-channel MOS transistor connected between the first bit line and the first node, and between the second bit line and the second node A second P-channel MOS transistor connected to, and a write circuit for writing a data signal to the memory cell. The write circuit includes a step of applying a ground potential to the gates of the first and second P-channel MOS transistors to make the first and second P-channel MOS transistors conductive, and a boosted potential higher than the power supply potential on the word line. To make the N channel MOS transistor of the memory cell conductive, and according to the externally applied write data signal, either one of the first and second nodes is set to the power supply potential and the other The step of setting the node to the ground potential and the step of applying a negative potential lower than the ground potential to the gates of the first and second P-channel MOS transistors and supplying the power supply potential to the word line are executed. ThisByData can be written into the memory cell without destroying the gate insulating film of the N channel MOS transistor of the memory cell.
[0151]
Preferably, the absolute value of the threshold voltage of each of the first and second P-channel MOS transistors is set to be approximately equal to the voltage difference between the boosted potential and the power supply potential. In this case, a data signal can be sufficiently written into the memory cell while limiting the voltage applied to the gate insulating film of the N-channel MOS transistor of the memory cell to the power supply voltage or less.
[0152]
Preferably, two memory cells are provided to store one data signal in two memory cells, two word lines are provided, and two N-channel MOS transistors have two gates respectively. Connected to the word line, the sources of the N-channel MOS transistors of the two memory cells are connected to the first and second bit lines, respectively. In this case, the data signal can be written / read more reliably.
[0153]
Preferably, two memory cells are provided to store one data signal in the two memory cells, and the gates of the N-channel MOS transistors of the two memory cells are both connected to the word line, and the N of the two memory cells The sources of the channel MOS transistors are connected to the first and second bit lines, respectively. Also in this case, the data signal can be written / read more reliably.
[0154]
  AlsoIn another semiconductor memory device according to the present inventionThe MOS transistor of the memory cell is a P-channel MOS transistor. The semiconductor memory device further includes a word line connected to the gate of the P-channel MOS transistor, and one of them is the source of the P-channel MOS transistor. First and second bit lines connected to each other, a first N-channel MOS transistor connected between the first bit line and the first node, a second bit line and a second node And a second N-channel MOS transistor connected between and a write circuit for writing a data signal to the memory cell. The write circuit includes a step of applying a power supply potential to the gates of the first and second N channel MOS transistors to make the first and second N channel MOS transistors conductive, and a negative potential lower than the ground potential on the word line. To make the P-channel MOS transistor of the memory cell conductive, and according to the externally applied write data signal, set one of the first and second nodes to the power supply potential and A step of setting the node to the ground potential and a step of applying a boosted potential higher than the power supply potential to the gates of the first and second N-channel MOS transistors and a ground potential to the word line are executed. ThisByData can be written into the memory cell without destroying the gate insulating film of the P channel MOS transistor of the memory cell.
[0155]
Preferably, the threshold voltages of the first and second N-channel MOS transistors are set to be approximately equal to the voltage difference between the ground potential and the negative potential. In this case, a data signal can be sufficiently written into the memory cell while limiting the voltage applied to the gate insulating film of the P-channel MOS transistor of the memory cell to the power supply voltage or less.
[0156]
Preferably, two memory cells are provided to store one data signal in two memory cells, two word lines are provided, and the gates of the P-channel MOS transistors of the two memory cells are each two words. The sources of the P channel MOS transistors of the two memory cells are connected to the first and second bit lines, respectively. In this case, the data signal can be written / read more reliably.
[0157]
Preferably, two memory cells are provided to store one data signal in the two memory cells, and the gates of the P channel MOS transistors of the two memory cells are both connected to the word line, and the P of the two memory cells are connected. The sources of the channel MOS transistors are connected to the first and second bit lines, respectively. In this case, the data signal can be written / read more reliably.
[0158]
  AlsoIn yet another semiconductor memory device according to the present inventionThe MOS transistor of the memory cell is a P-channel MOS transistor. The semiconductor memory device further includes a word line connected to the gate of the P-channel MOS transistor, and one of them is the source of the P-channel MOS transistor. And a write circuit for writing a data signal to the memory cell. The write circuit includes applying a negative potential lower than the ground potential to the word line to turn on the P-channel MOS transistor of the memory cell, applying a ground potential to the first and second bit lines, And applying one of the first and second bit lines to the power supply potential and setting the other bit line to the ground potential in accordance with a step of applying a ground potential to the first and second write lines. To perform the steps. ThisByData can be written into the memory cell without destroying the gate insulating film of the P channel MOS transistor of the memory cell.
[0159]
Preferably, two memory cells are provided to store one data signal in two memory cells, two word lines are provided, and the gates of the P-channel MOS transistors of the two memory cells are each two words. The sources of the P channel MOS transistors of the two memory cells are connected to the first and second bit lines, respectively. In this case, the data signal can be written / read more reliably.
[0160]
Preferably, two memory cells are provided to store one data signal in the two memory cells, and the gates of the P channel MOS transistors of the two memory cells are both connected to the word line, and the P of the two memory cells are connected. The sources of the channel MOS transistors are connected to the first and second bit lines, respectively. Also in this case, the data signal can be written / read more reliably.
[0161]
  AlsoIn yet another semiconductor memory device according to the present inventionThe MOS transistor of the memory cell is a P-channel MOS transistor. The semiconductor memory device further includes a word line connected to the gate of the P-channel MOS transistor, and one of them is the source of the P-channel MOS transistor. And a write circuit for writing a data signal to the memory cell. The write circuit includes applying a negative potential lower than the ground potential to the word line to turn on the P-channel MOS transistor of the memory cell, applying a ground potential to the first and second bit lines, And applying one of the first and second bit lines to the power supply potential and setting the other bit line to the ground potential in accordance with a step of applying a ground potential to the first and second write lines. And performing the steps. ThisByData can be written into the memory cell without destroying the gate insulating film of the P channel MOS transistor of the memory cell.
[0162]
Preferably, two memory cells are provided to store one data signal in two memory cells, two word lines are provided, and the gates of the P-channel MOS transistors of the two memory cells are each two words. The sources of the P channel MOS transistors of the two memory cells are connected to the first and second bit lines, respectively. In this case, the data signal can be written / read more reliably.
[0163]
Preferably, two memory cells are provided to store one data signal in the two memory cells, and the gates of the P channel MOS transistors of the two memory cells are both connected to the word line, and the P of the two memory cells are connected. The sources of the channel MOS transistors are connected to the first and second bit lines, respectively. Also in this case, the data signal can be written / read more reliably.
[0164]
  AlsoIn yet another semiconductor memory device according to the present inventionIs provided with two memory cells, and one memory signal is stored in two memory cells. The MOS transistor of one of the two memory cells is an N-channel MOS transistor, and the other memory cell has The MOS transistor is a P-channel MOS transistor, and the semiconductor memory device further includes first and second word lines connected to the gate of the N-channel MOS transistor and the gate of the P-channel MOS transistor, respectively. One of them includes first and second bit lines connected to the source of the N-channel MOS transistor and the source of the P-channel MOS transistor, and a write circuit for writing a data signal to the two memory cells. In accordance with the step of applying a power supply potential and a ground potential to the first and second word lines to make the N-channel MOS transistor and the P-channel MOS transistor conductive, and the write circuit in accordance with an externally applied write data signal The step of setting one of the first and second bit lines to the power supply potential and setting the other bit line to the ground potential is executed. ThisByData can be written into the memory cell without destroying the gate insulating film of the MOS transistor of the memory cell.
[Brief description of the drawings]
FIG. 1 is a block diagram showing a configuration of a system LSI according to a first embodiment of the present invention.
2 is a block diagram showing a configuration of a memory circuit section shown in FIG. 1; FIG.
3 is a block diagram showing a configuration of a memory array and related parts shown in FIG. 2;
4 is a circuit block diagram showing a configuration of a memory array block shown in FIG. 3. FIG.
FIG. 5 is a circuit diagram showing a main part of the sense amplifier band shown in FIG. 3;
6 is a diagram showing a configuration of a memory cell shown in FIG. 4;
7 is a diagram for explaining problems of the memory cell shown in FIG. 6; FIG.
FIG. 8 is another diagram for explaining problems of the memory cell shown in FIG. 6;
9 is a circuit diagram showing a configuration of a word driver included in the row decoder shown in FIG. 3;
10 is a time chart showing an operation of the word driver shown in FIG. 9. FIG.
11 is a block diagram showing a signal generation circuit and a local control circuit provided corresponding to the sense amplifier band and the memory array block shown in FIG. 3;
12 shows a signal generation circuit 71. It is a circuit block diagram which shows the structure of k.
13 is a circuit diagram showing a configuration of the level shifter shown in FIG. 12. FIG.
14 shows a signal generation circuit 72. It is a circuit block diagram which shows the structure of k.
FIG. 15 is a time chart showing operations of the signal generation circuit and the local control circuit shown in FIGS.
FIG. 16 is a time chart showing a data writing method of the memory circuit section shown in FIGS.
17 is a diagram for explaining an effect of the data writing method shown in FIG. 16; FIG.
FIG. 18 is a block diagram illustrating a modification of the first embodiment.
FIG. 19 is a block diagram showing another modification of the first embodiment.
FIG. 20 is a circuit diagram showing a main part of a memory circuit part of a system LSI according to a second embodiment of the present invention.
FIG. 21 is a time chart showing a data writing method of the memory circuit section shown in FIG. 20;
FIG. 22 is a circuit block diagram showing a main part of a memory circuit part of a system LSI according to a third embodiment of the invention.
23 is a time chart showing a data writing method of the memory circuit section shown in FIG. 22;
FIG. 24 is a circuit block diagram showing a main part of a memory circuit part of a system LSI according to a fourth embodiment of the invention.
25 is a time chart showing a data writing method for the memory circuit section shown in FIG. 24;
FIG. 26 is a circuit block diagram showing a main part of a memory circuit part of a system LSI according to a fifth embodiment of the present invention.
[Explanation of symbols]
1 system LSI, 2 logic circuit unit, 3 memory circuit unit, 4 clock buffer, 5 control signal buffer, 6 address buffer, 7 mode register, 8 control circuit, 9-12 memory array, 13 IO buffer, MA memory array block, SA sense amplifier band, 14 memory mat, 15 row decoder, 16 column decoder, MC, MC 'memory cell, WL, / WL word line, BL, / BL bit line pair, C capacitor, SN storage node, Q, 25, 26, 30, 31, 33 to 35, 64 to 66, 76 to 78, 82, 83 N-channel MOS transistor, 21 column selection gate, Q ', 22, 23, 28, 29, 37, 38, 59 to 63, 75, 80, 81, 101 to 103, 105 to 107 P-channel MOS transistors 24, 36, 90, 93 Transfer gate, 27 Sense amplifier, 32, 100, 104 Equalizer, 40 Crystal silicon substrate, 41 P-type well, 42 Gate insulating film, 43 Gate electrode, 44 Source region, 45 Drain region, 46 N-type diffusion layer or inversion layer, 47 insulating film, 48 cell plate electrode, 49 insulating layer, 50 contact hole, 51 element isolation film, 55 word driver, 56, 79 level shifter, 57 switching circuit, 58, 67, 68, 73 , 74, 84 Inverter, 70 Local control circuit, 71, 72 Signal generation circuit.

Claims (15)

A semiconductor memory device formed on a semiconductor substrate together with a logic circuit including a MOS transistor,
A memory cell having a MOS transistor and a capacitor connected in series, and storing a data signal,
The MOS transistor includes a gate insulating film formed on the surface of the semiconductor substrate, a gate electrode formed on the surface of the gate insulating film, and an impurity diffusion formed on the surface of the semiconductor substrate on both sides of the gate electrode. Area and
The capacitor includes an impurity diffusion region formed on the surface of the semiconductor substrate, an insulating film formed on the surface of the impurity diffusion region, and a plate electrode formed on the surface of the insulating film and receiving a reference potential. ,
The thickness of the gate insulating film of the MOS transistor of the logic circuit, the thickness of the gate insulating film of the MOS transistor of the memory cell, and the thickness of the insulating film of the capacitor are the same, and the thickness of the MOS transistor of the logic circuit The gate electrode, the gate electrode of the MOS transistor of the memory cell, and the plate electrode of the capacitor are formed in the same wiring layer,
The MOS transistor of the memory cell is an N channel MOS transistor,
The semiconductor memory device
A word line connected to the gate of the N-channel MOS transistor;
First and second bit lines, any one of which is connected to the source of the N-channel MOS transistor;
A first P-channel MOS transistor connected between the first bit line and a first node;
A second P-channel MOS transistor connected between the second bit line and a second node; and a write circuit for writing a data signal to the memory cell;
The writing circuit includes:
Applying a ground potential to the gates of the first and second P-channel MOS transistors to make the first and second P-channel MOS transistors conductive;
Applying a boosted potential higher than a power supply potential to the word line to make the N-channel MOS transistor of the memory cell conductive;
According to an externally applied write data signal, the step of setting one of the first and second nodes to the power supply potential and the other node to the ground potential; and A semiconductor memory device that executes a step of applying a negative potential lower than the ground potential to the gate of a second P-channel MOS transistor and supplying the power supply potential to the word line. The absolute values of the first and second of each of the threshold voltage of the P-channel MOS transistor is set to be substantially equal to the voltage of the difference of the power supply potential and the boosted potential, according to claim 1 Semiconductor memory device. Two memory cells are provided to store one data signal in two memory cells;
Two word lines are provided,
The gates of the N channel MOS transistors of the two memory cells are connected to two word lines, respectively.
The source of N-channel MOS transistors of the two memory cells are connected to each of the first and second bit lines, the semiconductor memory device according to claim 1 or claim 2. Two memory cells are provided to store one data signal in two memory cells;
The gates of the N-channel MOS transistors of the two memory cells are both connected to the word line,
The source of N-channel MOS transistors of the two memory cells are connected to each of the first and second bit lines, the semiconductor memory device according to claim 1 or claim 2. A semiconductor memory device formed on a semiconductor substrate together with a logic circuit including a MOS transistor,
A memory cell having a MOS transistor and a capacitor connected in series, and storing a data signal,
The MOS transistor includes a gate insulating film formed on the surface of the semiconductor substrate, a gate electrode formed on the surface of the gate insulating film, and an impurity diffusion formed on the surface of the semiconductor substrate on both sides of the gate electrode. Area and
The capacitor includes an impurity diffusion region formed on the surface of the semiconductor substrate, an insulating film formed on the surface of the impurity diffusion region, and a plate electrode formed on the surface of the insulating film and receiving a reference potential. ,
The thickness of the gate insulating film of the MOS transistor of the logic circuit, the thickness of the gate insulating film of the MOS transistor of the memory cell, and the thickness of the insulating film of the capacitor are the same, and the thickness of the MOS transistor of the logic circuit The gate electrode, the gate electrode of the MOS transistor of the memory cell, and the plate electrode of the capacitor are formed in the same wiring layer,
The MOS transistor of the memory cell is a P-channel MOS transistor,
The semiconductor memory device
A word line connected to the gate of the P-channel MOS transistor;
First and second bit lines, any one of which is connected to the source of the P-channel MOS transistor;
A first N-channel MOS transistor connected between the first bit line and a first node;
A second N-channel MOS transistor connected between the second bit line and a second node; and a write circuit for writing a data signal to the memory cell;
The writing circuit includes:
Applying a power supply potential to the gates of the first and second N-channel MOS transistors to make the first and second N-channel MOS transistors conductive;
Applying a negative potential lower than a ground potential to the word line to make the P-channel MOS transistor of the memory cell conductive;
According to an externally applied write data signal, the step of setting one of the first and second nodes to the power supply potential and the other node to the ground potential; and A semiconductor memory device that executes a step of applying a boosted potential higher than the power supply potential to the gate of a second N-channel MOS transistor and applying the ground potential to the word line. 6. The semiconductor memory device according to claim 5 , wherein threshold voltages of said first and second N-channel MOS transistors are set to be substantially equal to a difference voltage between said ground potential and said negative potential. Two memory cells are provided to store one data signal in two memory cells;
Two word lines are provided,
The gates of the P channel MOS transistors of the two memory cells are connected to two word lines, respectively.
The source of the P-channel MOS transistors of the two memory cells are connected to each of the first and second bit lines, the semiconductor memory device according to claim 5 or claim 6. Two memory cells are provided to store one data signal in two memory cells;
The gates of the P-channel MOS transistors of the two memory cells are both connected to the word line,
The source of the P-channel MOS transistors of the two memory cells are connected to each of the first and second bit lines, the semiconductor memory device according to claim 5 or claim 6. A semiconductor memory device formed on a semiconductor substrate together with a logic circuit including a MOS transistor,
A memory cell having a MOS transistor and a capacitor connected in series, and storing a data signal,
The MOS transistor includes a gate insulating film formed on the surface of the semiconductor substrate, a gate electrode formed on the surface of the gate insulating film, and an impurity diffusion formed on the surface of the semiconductor substrate on both sides of the gate electrode. Area and
The capacitor includes an impurity diffusion region formed on the surface of the semiconductor substrate, an insulating film formed on the surface of the impurity diffusion region, and a plate electrode formed on the surface of the insulating film and receiving a reference potential. ,
The thickness of the gate insulating film of the MOS transistor of the logic circuit, the thickness of the gate insulating film of the MOS transistor of the memory cell, and the thickness of the insulating film of the capacitor are the same, and the thickness of the MOS transistor of the logic circuit The gate electrode, the gate electrode of the MOS transistor of the memory cell, and the plate electrode of the capacitor are formed in the same wiring layer,
The MOS transistor of the memory cell is an N channel MOS transistor,
The semiconductor memory device
A word line connected to the gate of the N-channel MOS transistor;
Any one of them includes first and second bit lines connected to the source of the N-channel MOS transistor, and a write circuit for writing a data signal to the memory cell,
The writing circuit includes:
Applying a boosted potential higher than a power supply potential to the word line to make the N-channel MOS transistor of the memory cell conductive;
Applying the power supply potential to the first and second bit lines;
In accordance with the step of applying the power supply potential to the word line and the externally applied write data signal, one of the first and second bit lines is set to the power supply potential and the other A semiconductor memory device that executes a step of setting a bit line to a ground potential. Two memory cells are provided to store one data signal in two memory cells;
Two word lines are provided,
The gates of the N channel MOS transistors of the two memory cells are connected to two word lines, respectively.
The semiconductor memory device according to claim 9 , wherein sources of N-channel MOS transistors of two memory cells are connected to the first and second bit lines, respectively. Two memory cells are provided to store one data signal in two memory cells;
The gates of the N-channel MOS transistors of the two memory cells are both connected to the word line,
The semiconductor memory device according to claim 9 , wherein sources of N-channel MOS transistors of two memory cells are connected to the first and second bit lines, respectively. A semiconductor memory device formed on a semiconductor substrate together with a logic circuit including a MOS transistor,
A memory cell having a MOS transistor and a capacitor connected in series, and storing a data signal,
The MOS transistor includes a gate insulating film formed on the surface of the semiconductor substrate, a gate electrode formed on the surface of the gate insulating film, and an impurity diffusion formed on the surface of the semiconductor substrate on both sides of the gate electrode. Area and
The capacitor includes an impurity diffusion region formed on the surface of the semiconductor substrate, an insulating film formed on the surface of the impurity diffusion region, and a plate electrode formed on the surface of the insulating film and receiving a reference potential. ,
The thickness of the gate insulating film of the MOS transistor of the logic circuit, the thickness of the gate insulating film of the MOS transistor of the memory cell, and the thickness of the insulating film of the capacitor are the same, and the thickness of the MOS transistor of the logic circuit The gate electrode, the gate electrode of the MOS transistor of the memory cell, and the plate electrode of the capacitor are formed in the same wiring layer,
The MOS transistor of the memory cell is a P-channel MOS transistor,
The semiconductor memory device
A word line connected to the gate of the P-channel MOS transistor;
Any one of them includes first and second bit lines connected to the source of the P-channel MOS transistor, and a write circuit for writing a data signal to the memory cell,
The writing circuit includes:
Applying a negative potential lower than a ground potential to the word line to make the P-channel MOS transistor of the memory cell conductive;
Applying the ground potential to the first and second bit lines;
Applying the ground potential to the word line, and setting one of the first and second bit lines to the power supply potential and the other bit in accordance with an externally applied write data signal A semiconductor memory device that executes a step of setting a line to the ground potential. Two memory cells are provided to store one data signal in two memory cells;
Two word lines are provided,
The gates of the P channel MOS transistors of the two memory cells are connected to two word lines, respectively.
The source of the P-channel MOS transistors of the two memory cells are connected to each of the first and second bit lines, the semiconductor memory device according to claim 1 2. Two memory cells are provided to store one data signal in two memory cells;
The gates of the P-channel MOS transistors of the two memory cells are both connected to the word line,
The source of the P-channel MOS transistors of the two memory cells are connected to each of the first and second bit lines, the semiconductor memory device according to claim 1 2. A semiconductor memory device formed on a semiconductor substrate together with a logic circuit including a MOS transistor,
A memory cell having a MOS transistor and a capacitor connected in series, and storing a data signal,
The MOS transistor includes a gate insulating film formed on the surface of the semiconductor substrate, a gate electrode formed on the surface of the gate insulating film, and an impurity diffusion formed on the surface of the semiconductor substrate on both sides of the gate electrode. Area and
The capacitor includes an impurity diffusion region formed on the surface of the semiconductor substrate, an insulating film formed on the surface of the impurity diffusion region, and a plate electrode formed on the surface of the insulating film and receiving a reference potential. ,
The thickness of the gate insulating film of the MOS transistor of the logic circuit, the thickness of the gate insulating film of the MOS transistor of the memory cell, and the thickness of the insulating film of the capacitor are the same, and the thickness of the MOS transistor of the logic circuit The gate electrode, the gate electrode of the MOS transistor of the memory cell, and the plate electrode of the capacitor are formed in the same wiring layer,
Two memory cells are provided to store one data signal in two memory cells;
The MOS transistor of one of the two memory cells is an N channel MOS transistor, the MOS transistor of the other memory cell is a P channel MOS transistor,
The semiconductor memory device
A first word line and a second word line connected to the gate of the N channel MOS transistor and the gate of the P channel MOS transistor, respectively;
One of them for writing data signals to the first and second bit lines connected to the source of the N-channel MOS transistor and the source of the P-channel MOS transistor, and the two memory cells A writing circuit,
The writing circuit includes:
Applying a power supply potential and a ground potential to the first and second word lines, respectively, to turn on the N-channel MOS transistor and the P-channel MOS transistor, and according to an externally applied write data signal And a step of setting one of the second bit lines to the power supply potential and setting the other bit line to the ground potential.

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