JP4458807B2 - DIGITAL SIGNAL PROCESSING DEVICE, SYSTEM, METHOD, AND HOST DEVICE - Google Patents

Description

  The present invention relates to a digital signal processing apparatus, system and method, and a host apparatus.

  A digital signal processing system in which predetermined signal processing is applied to each input signal input from a plurality of channels and applied to a host device is widely used in various electronic devices. Examples of electronic equipment corresponding to this include test equipment, audio equipment, vehicle-mounted computer control equipment, and the like.

  In order to facilitate understanding of the present invention, the latter in-vehicle computer control device will be described as an example. In this device, sensors (throttle opening sensor, vehicle speed sensor, water temperature sensor, mode provided in each part of the vehicle) Analog signals from the changeover switch status sensor, steering sensor, etc.) are input individually, that is, for each channel, to one host device, ie, a microcomputer, where digital arithmetic processing is performed for optimal control of the vehicle. Is done.

  In this case, since the host device (microcomputer) cannot directly receive the input signal from each channel as it is unprocessed, each input signal before being input to the host device is compared with each input signal. The predetermined signal processing described above according to the property must be performed. The aforementioned “digital signal processing device” performs the predetermined signal processing. Here, an ECU (Electronic Control Unit), that is, the above-described “digital signal processing system” is constructed by the host device, the digital signal processing device, and the input terminal group in the preceding stage of the digital signal processing device.

  In addition, there exist the following patent documents 1-4 as a well-known technique relevant to this invention. However, as will become clear from the following description, any of the known techniques “select one or a plurality of functional modules for each of a plurality of channels selected in a predetermined order and configure ( The present invention is clearly distinguished from the present invention based on the idea of “configuring a digital signal processing device in a configurable manner”.

Japanese Patent No. 3015722 Japanese Patent Laid-Open No. 3-203422 JP-A-1-232458 Japanese Patent No. 3335482

  There are two types of conventional digital signal processing devices implemented by the present applicant.

  In the first embodiment, the digital signal processing device is configured by a dedicated hardware circuit in accordance with the channel configuration described above.

  In the second embodiment, the digital signal processing apparatus includes a fixed hardware circuit such as a microcomputer or a DSP (Digital Signal Processor), and software for operating the hardware circuit in accordance with the channel configuration described above. And a processing unit.

  However, in the digital signal processing device according to the second embodiment, when the digital signal processing system is changed or when the channel configuration is changed (for example, the addition of the input terminal, etc.), it is flexible. There is a problem that there is a limit in processing speed by software processing, while there is convenience that it can cope with.

  In the digital signal processing apparatus according to the first embodiment, although the above processing speed is sufficiently satisfied, one digital signal processing circuit is required for each channel, resulting in an increase in circuit scale. Therefore, there is a problem of high cost. Further, when the configuration of the channel is changed, there is a problem that a digital signal processing circuit corresponding to the channel configuration must be newly recreated.

  Therefore, in view of the above problems, the present invention can flexibly cope with a change in the configuration of the digital signal processing system or channel without changing the hardware, and has a small circuit scale. It is an object of the present invention to provide a digital signal processing apparatus, system and method, and a host apparatus that can perform high-speed processing as they are.

  FIG. 1 is a diagram showing a basic configuration of a digital signal processing apparatus according to the present invention.

The basic configuration of the digital signal processing apparatus 1 according to the present invention includes an input unit 2, a plurality of functional modules 3 (A, B, C... N), and a module selection / control unit 4. In particular,
The input unit 2 receives each input signal IN from a plurality of channels CH1, CH2,.
Each of the plurality of functional modules 3 can receive the signal in from the input unit 2 in common, and performs signal processing on each of the signals in received in a predetermined order by a function unique to each of them. ,
The module selection / control unit 4 sequentially selects one or a plurality of function modules 3 corresponding to each of the plurality of channels CH1, CH2,..., And causes the selected function module to perform signal processing of the input signal in. .

  More preferably, the memory means 5 is provided.

  This memory means 5 has a sequence memory 6 that holds rewritable processing sequence information for designating one or a plurality of functional modules 3 to be selected corresponding to each channel (CH1, CH2,...).

  More preferably, the memory means 5 has a parameter memory 7 that holds rewritable parameter information for modifying the contents of signal processing in each functional module 3.

  In the figure, reference numeral 8 is an output unit, and 9 is a shared bus.

  In this way, it is possible to sequentially select one or a plurality of functional modules 3 for each channel and form the digital signal processing device 1 in a configurable manner.

  For this reason, even if there is a change in the system configuration or channel configuration, this can be flexibly dealt with, and high-speed signal processing can be realized with a small circuit scale.

  FIG. 2 is a diagram more specifically showing the basic configuration of FIG. Throughout the drawings, similar components are denoted by the same reference numerals or symbols.

  The input unit 2 receives an input signal IN corresponding to each channel (CH) and converts the analog (A) input signal IN into digital (D) data (in) and a separation unit (MPX: multiplexer) 11 that performs time division processing. The digital data is transferred to the shared bus 9.

  The selection / control unit 4 causes the functional modules (3A, 3B,...) To perform signal processing corresponding to the channel through the shared bus 9 while referring to the contents of the memories 6 and 7. The processing result is temporarily stored in the processing result buffer 13 and then transmitted to the outside from the output distribution unit 14. An example of the outside is the host device described above. Here, the shared bus 9 transfers address signals, data signals, control signals, and the like. Next, the processing operation will be described.

  FIG. 3 is a time chart for explaining the processing operation of FIG.

  In this figure, the horizontal axis shows time. Each vertical dot-and-dash line represents a sampling interval in the AD converter 12, and sequentially AD-converts each input signal in (represented by ch1, ch2,...) On the channels CH1, CH2,... At each sampling interval. (Refer to “AD of ch1”, “AD of ch2”...)

  Further, “A”, “B”, “C”... In FIG. 2 respectively indicate the functional modules 3A, 3B, 3C... In FIG. The signals are sequentially processed in 3A and 3B (see “ch1 processing” in FIG. 3). That is, the data (in) that has undergone the ch1 AD is signal-processed by the functional module 3A, and then the signal-processed data is signal-processed by the functional module 3B. At the same time, AD conversion of the input signal (IN) on the channel CH2 is performed in parallel (see “AD of ch2” in FIG. 3), and the data (in) of ch2 after this AD conversion is, for example, Signal processing is sequentially performed in the functional modules 3A, 3C, and 3D (see “ch2 processing” in FIG. 3). The same applies hereinafter.

  In summary, according to the present invention, in the processing system for a plurality of digital input signals, the data (memory 6 and the memory 6 and the data including the plurality of arithmetic modules (3)) and how to process the digital input signals are provided. Based on 7), one or a plurality of arithmetic modules (3) are selected and processed. Here, a configurable processing system is realized.

  Here, “configurable” means that processing can be rewritten at the function level in the processing system. For this purpose, a processing module (functional block) prepared in advance is operated by switching the processing module for each input signal based on data (configuration data) describing processing contents.

  Hereinafter, each embodiment according to the present invention will be described in detail. In order to facilitate understanding of the present invention, a specific example of the above-described “system for processing a plurality of digital input signals” will be described. This is merely an example, but it is the “vehicle-mounted computer control system” described above. Of course, the present invention can also be applied to a general digital data processing system.

  FIG. 4 is a diagram showing an example of a system to which the present invention is applied.

  In this figure, the entire block is an ECU (Electronic Control Unit), and analog signals from various sensors (throttle opening sensors, etc.) are applied as channel signals to the input terminal group of the ECU.

  These channel signals are subjected to preprocessing necessary for arithmetic processing in the microcomputer 10. This is a preprocessing IC and corresponds to the digital signal processing apparatus 1 of the present invention. The microcomputer corresponds to a host device described in detail later.

  In this case, the plurality of functional modules (3) in the preprocessing IC (1) are, for example, an LPF (low-pass filter), a BPF (band-pass filter), a peak hold circuit, a comparator, and the like.

  That is, the sequence memory 6 stores a sequence map that defines which function (calculation) module 3 is used to process each input signal in.

  The signal processing operation in each functional module 3 according to this sequence map is as shown in FIG. However, the way of viewing FIG. 7 is exactly the same as FIG. 3 described above.

  FIG. 5 is a diagram showing a writing means according to the present invention to be added to FIG.

  The newly added components in this figure are a sequence writing means 71 and a parameter writing means 72, a sequence memory (flash memory etc.) 73 and a parameter memory (flash memory etc.) 74 in the host device 10.

The sequence writing means 71 rewrites processing sequence information to be held in the sequence memory 7 of FIG. 2 from the outside of the apparatus (ECU),
The parameter writing means 72 rewrites the parameter information to be held in the parameter memory 6 of FIG. 2 from the outside of the apparatus (ECU) (refer to the route indicated by the solid arrow in FIG. 5).

Further, as shown in FIG. 5, in the case of cooperating with the host device 10 that receives the data of the processing result obtained by performing the signal processing on the input signal, the processing sequence information is written to the sequence memory 7 of FIG. Done via
Also, the parameter information is written into the parameter memory 6 of FIG. 2 via the host device 10 (see the route indicated by the dotted arrow in FIG. 5).

Alternatively, predetermined types of processing sequence information are held in the sequence memory 73 in the host device 10, and the sequence writing means 71 designates desired processing sequence information for the memory 73 and stores it in the sequence memory. Transfer to 7 and write
Similarly, a plurality of types of parameter information determined in advance are held in the parameter memory 74 in the host device 10, and the parameter writing means 72 designates desired parameter information for the memory 74 and stores it in the parameter memory 6. The data is transferred to and written in (refer to the route of the alternate long and short dash line in FIG. 5).

  The writing means 71 and 72 can also be used as means for inputting an original control program to be installed in the host device (microcomputer) 10.

  A memory that should be further noted in FIG. 5 is a channel order memory 75.

  Each input signal from the channels CH1, CH2,..., CHk described above may be processed in order, such as CH1 → CH2 → CH3 →, or any predetermined order (for example, CH1 → CH3 → Signal processing may be performed according to CH2 →. For this purpose, the channel order memory 75 holds processing order information for each signal to be processed. A specific example of the processing order of this channel will be described later.

  FIG. 6 is a diagram more specifically showing the selection / control unit 4 shown in FIG. 2 and its periphery. For convenience of explanation, the arrangement of the functional modules 3 is different from that in FIG. Further, the above-described channel order memory 75 is placed at the illustrated position as an example.

  The module selection / control unit 4 shown in FIG. 6 includes a memory reading unit 81 and a module control unit 82 that controls each functional module 3 (A, B... N) according to read information from the memory reading unit 81. Comprising. Here, the memory reading unit 81 reads information from the sequence memory 7.

  On the other hand, the module control unit 82 controls each functional module 3 (A, B... N) according to the parameter information from the parameter memory 6.

  The memory reading unit 81 reads information from the channel order memory 75.

  The module selection / control unit 4 shown in FIG. 6 will be described in more detail below with reference to a flowchart and a time chart. Before that, a case of an in-vehicle device will be taken as an example to facilitate understanding. A specific example of each input signal of CH1, CH2,... And a specific example of one or a plurality of functional modules 3 that process each input signal will be described.

  FIG. 7 is a diagram showing an example of input signals of each channel and an example of functional modules that process the signals.

  In the figure, the left end corresponds to the input unit 2 described above, and input signals from a plurality of channels CH1, CH2, CH3.

  On the other hand, the upper end 3 of this figure represents the above-mentioned plurality of functional modules.

  As an example, the processing target of each channel is as follows.

CH1: Engine speed CH2: Water temperature CH3: Stop (brake) lamp CH4: Knock CH5: Differential sensor The engine speed signal from the channel CH1 is first input to the low-pass filter (LPF) of the first-stage functional module. The output is input to a comparator, which is a functional module at the next stage, to obtain a processing result OUT1. However, when going from the low-pass filter (LPF) to the comparator, the filter output from the low-pass filter (LPF) is temporarily buffered, and then the comparator is selected by the module control unit (82 in FIG. 6). The filter output is read from the buffer and applied to the comparator. The buffer mentioned here may be in the selection / control means (4 in FIG. 6), in the output unit (8 in FIG. 6), or connected to the shared bus in FIG. May be provided independently.

  A unique parameter a11 is supplied from the parameter memory 6 side to the low-pass filter (LPF) via the module control unit 82, and a unique parameter a12 is also supplied to the comparator from the parameter memory 6 side via the module control unit 82. Supplied. These parameters a11, a12, etc. will be described again later in FIG. 22, etc., but a11, a12 in FIG. 7 and a11, a12 in FIG. 22 are merely symbols for distinction, and a11 and a12 are both figures. They do not have the same meaning.

  In FIG. 7, the parameter a11 sets a filter constant suitable for removing noise in a low-pass filter (LPF). The parameter a12 sets a comparison reference value for the comparator.

  The water temperature signal from the channel CH2 is also subjected to signal processing by the LPF, which is a functional module for taking noise.

  The stop (brake) lamp signal from the channel CH3 is subjected to noise removal (LPF) and then turned on / off by a comparator (OUT3).

  Since the knock signal from CH4, that is, the output signal from the knock sensor, first needs to extract a signal in a required frequency band, it is input to a band pass filter (BPF) which is another functional module, and its output In order to hold a peak value from among a large number of sample values constituting the above, it is further input to a peak hold (P / H) circuit, which is a functional module, and becomes OUT4.

  The channel CH5 is differential signals S + and S− which are output signals from a specific sensor, and the difference between them is output from the adder circuit and becomes OUT5.

  FIG. 7 shows the input signal of each channel (CH1, CH2, CH3...) And specific examples of each functional module. Next, based on this, an operation example of the selection / control unit 4 of FIG. This will be described with reference to FIGS.

FIG. 8 is a flowchart showing an operation example of the selection / control unit 4 shown in FIG.
FIG. 9 is a time chart corresponding to the flowchart of FIG.
In FIG. 7, the case of channel CH1, the corresponding functional module “LPF” (3A) and the functional module “comparator” (3B) will be described as an example (the same applies hereinafter).

With reference to FIGS.
Step S <b> 11 (FIG. 8): The module selection / control unit 4 reads the channel order information in the channel order memory 75 by the memory reading unit 81.

  Step S12: In this example, channel CH1 is designated, and IDch1 is output (see (2) in FIG. 9).

  Step S 13: The selection / control unit 4 outputs the IDch 1 to the input unit 2 and the input data “CH 1 data” of the channel CH 1 is transferred onto the shared bus 9.

  Step S14: The selection / control unit 4 reads the sequence information in the sequence memory 7 by the memory reading unit 81.

  Step S15: In this assumed example, the first sequence read in step S11 is the functional module 3 (A), which is represented as IDa (see (1) in FIG. 9).

  Step S16: The module 3 (A) that has received the IDa via the shared bus 9 is activated (see (1) in FIG. 9).

  Step S17: The functional module 3 (A) takes in the “CH1 data” on the shared bus 9 therein.

  Step S18: The means 4 reads the corresponding parameter from the parameter memory 6 and transfers it to the shared bus 9 (see (2) in FIG. 9). In the above example, this parameter is a11 (FIG. 7).

  Step S19: The target signal processing is executed in the functional module 3 (A) using the CH1 data and a11 (see “Calculation A” in (2) of FIG. 9). Then, the calculation result is output (see “OUTa” in (2) of FIG. 9).

  Step S20: At this time, the functional module 3 (A) outputs a calculation end signal indicating the end of the calculation to the shared bus 9 (see Ea in (3) of FIG. 9). Here, the calculation by the LPF in FIG. 7 ends, and the calculation shifts to the next-stage comparator.

  Step S21: The selection / control unit 4 reads the sequence information in the sequence memory 7 by the memory reading unit 81.

  Step S22: In this assumed example, the second sequence read in step S21 is the functional module 3 (B), which is represented as IDb (see (1) in FIG. 9).

  Step S23: The module 3 (B) that has received the IDb via the shared bus 9 is activated (see (1) in FIG. 9).

  Step S24: The functional module 3 (B) reads and takes in the calculation result OUTa from the buffer described above.

  Step S25: The means 4 reads the corresponding parameter from the parameter memory 6 and transfers it to the shared bus 9 (see (2) in FIG. 9). In the above example, this parameter is a12 (FIG. 7).

  Step S26: The target signal processing is executed in the functional module 3 (B) using OUTa and a12 (see “Calculation B” in (2) of FIG. 9). Then, the calculation result is output (see (2) in FIG. 9 and “OUT1” in FIG. 7).

  Step S27: At this time, the functional module 3 (B) outputs a calculation end signal indicating the end of the calculation to the shared bus 9 (see Eb in (3) of FIG. 9).

  Here, a supplementary explanation will be given of step S14 in FIG. This channel order reading is for setting the order of channels to be signal-processed. As described above, each input signal from the channels CH1, CH2,..., CHk may be processed in order, such as CH1 → CH2 → CH3 →, or may be processed according to a predetermined arbitrary order. May be.

  A specific example of the latter will be described with reference to FIG.

  Channel CH1 is an input signal related to the engine speed and requires frequent signal processing such as every two samples, while channel CH3 is a stop (brake) ramp signal, CH4 is a knock sensor signal, and every 12 samples, etc. Signal processing may be performed at a relatively slow timing. The intermediate channel CH2 is a water temperature signal, and signal processing may be performed at the timing of every six intermediate samples. This is illustrated in FIG.

  FIG. 10 is a diagram illustrating an example of the channel processing order. The designation of the channel processing order such as every 2 samples, every 6 samples, and every 12 samples is shown in an easy-to-understand manner. In addition, the sampling of FIG. 10 is made into 1 cycle, and this is repeated for every cycle.

  In the setting of the channel processing order and the sequential setting of the function modules 3 (FIG. 7), an optimal one is appropriately set for each of various vehicle types in the case of a car. According to the present invention, it is possible to easily cope with any vehicle type by simply rewriting the contents of the parameter memory 6, the sequence memory 7 and the channel order memory 75 from the outside. That is, there is no need to remake the “pre-processing IC” shown in FIGS. 4 and 5 for each of various vehicle types.

[Example 1]
FIG. 11 is an apparatus configuration diagram for explaining the first embodiment according to the present invention.
FIG. 12 is a diagram showing the contents of the sequence memory 6 of FIG.
FIG. 13 is a time chart showing a processing operation based on the processing sequence of FIG.

  An example of the processing sequence map shown in FIG. 12 is shown in the sequence memory 6 of FIG. In the processing order 1, it is instructed to perform signal processing in the functional module 3A and further perform signal processing in the functional module 3B for the input channel CH1. The same applies to processing order 2 and later.

That is, in the first embodiment, the processing content for the input signal in of each channel is described in advance in the sequence memory 6, and processing is performed while reading this data. The data is a map describing the processing contents for each operation cycle (processing order). Thus, by changing the description content in the memory 6, it is possible to flexibly deal with an external system (ECU).
[Example 2]
FIG. 14 is a diagram showing the contents of the sequence memory 6 for explaining the second embodiment according to the present invention.
FIG. 15 is a time chart showing a processing operation based on the processing sequence of FIG.

  In the second embodiment, the module selection / control unit 4 rewrites the contents of one or both of the sequence memory 6 and the parameter memory 7 even during the operation of the digital signal processing apparatus 1. . However, in FIG. 8 and FIG. 9, only the content change of the sequence memory 6 is shown.

  In this example, the module A → B for the input channel CH1 is changed from the middle to the module A → C. The processing order 1 'in FIG. 15 represents the operation by this change.

That is, according to the second embodiment, in the system of FIG. 11, the processing contents are changed by rewriting the contents of the sequence memory 6 during the system operation. For example, the contents of the memory 6 are directly rewritten from the selection / control unit 4 while each function (calculation) module 3 does not use the shared bus 9.
Example 3
FIG. 16 is an apparatus configuration diagram for explaining a third embodiment according to the present invention.
FIG. 17 is a diagram showing the contents of the sequence memory 6 of FIG.
FIG. 18 is a time chart showing processing operations based on the processing sequence of FIG.

  In the third embodiment, the module selection / control unit 4 selects the function module 3 to be selected corresponding to each channel (CH1, CH2,...) According to a specified series of processing sequences, and a new interrupt as the input signal IN. When an input signal is generated, an interrupt processing sequence is inserted into the designated series of processing sequences. Reference numeral 15 shown at the lower end of FIG. 17 is the interrupt processing sequence.

  In this case, an empty processing content 16 is appropriately inserted in the sequence memory 6 in advance, and when an interrupt occurs, the interrupt sequence is executed using the empty space closest to the interrupt. Referring to FIG. 18, the interrupt processing sequence is executed in the empty part of processing order 4.

  That is, according to the third embodiment, the system of FIG. 11 cannot cope with a case where there is an input signal IN to be processed at a timing that cannot be defined by the sequence map. For this reason, such an input signal is received by a predetermined input and processed for interruption.

The interrupt input may be a separate system from other inputs, or other inputs may be used as interrupts.
Example 4
FIG. 19 is a processing operation time chart for explaining the fourth embodiment according to the present invention.

  The fourth embodiment is characterized in that the processing for the input signal of the channel that should have been processed in one processing sequence overlapped with the insertion of the interrupt processing sequence 15 (FIG. 17) is stopped. To do.

  In FIG. 19, the processing of ch2 is skipped by the above cancellation.

However, in this case, only the processing that does not significantly affect the processing result is skipped.
Example 5
FIG. 20 is a processing operation time chart for explaining the fifth embodiment according to the present invention.

  In the fifth embodiment, the processing for the input signal of the channel that should have been processed in one processing sequence overlapped with the insertion of the interrupt processing sequence 15 described above is temporarily suspended, and as soon as the interrupt processing sequence ends, The process is started.

Referring to FIG. 20, hatched “BC” represents signal processing by interruption, and thereby signal processing after ch2 is postponed. An interrupt can be accepted with some delay in processing time.
Example 6
FIG. 21 is an apparatus configuration diagram of Embodiment 6 according to the present invention.
FIG. 22 shows the contents of the parameter memory 7 of FIG.

  In the sixth embodiment, the parameter memory 7 holds parameter information set for each channel (CH1, CH2,...) In advance, and the parameter memory 7 is a shared memory that is referenced by all the functional modules 3. It is a feature.

  According to the example shown in FIG. 22, the number of parameters constituting the parameter information is 3, and these parameters are used for input signals from the input channels CH1 and CH3.

  That is, according to the present invention, in the processing in the function (calculation) module 3, for example, in the case of a filter, if the filter constant is set from the outside as a parameter, the same filter calculation module can be used. Depending on the channel, it can be operated at different cutoff frequencies.

According to the sixth embodiment, parameters (constant data) necessary for execution of processing in the function (calculation) module 3 defined for the input signal IN of each channel are described in the parameter memory 7 in advance for each input signal IN. This is read and processed. This memory 7 is a shared memory that can be referenced from each module 3. By setting the parameter information of all the function (calculation) modules 3 in the shared memory, the parameters can be set all at once.
Example 7
FIG. 23 is an apparatus configuration diagram of Embodiment 7 according to the present invention.

  In the seventh embodiment, the parameter memory 7 (FIG. 21) is individual memory 7A, 7B, 7C built in each functional module 3, and these individual memories hold parameter information set for each channel in advance. It is characterized by this.

According to the seventh embodiment, each module 3 has an area for storing parameters of each input (contents of the parameter memory 7), so that the shared memory (FIG. 21) is accessed through the shared bus 9. Can also save time.
Example 8
The eighth embodiment is characterized in that the operation characteristics in the signal processing are changed by modifying the signal processing content described above.

That is, it is a dynamic change of parameters for each input signal. In the systems of the sixth and seventh embodiments, the operation characteristics of the processing can be obtained by rewriting the contents (parameters) of the memory 7 (7A, 7B...) During the system operation. (For example, the cutoff frequency of the filter) can be changed.
Example 9
FIG. 24 is a diagram showing a device configuration of Embodiment 9 according to the present invention.

  The ninth embodiment includes a shared bus 9 that connects at least the input unit 2, the functional module 3, and the module selection / control unit 4, and the shared bus 9 is provided for each data type handled in signal processing. It comprises a plurality of separated individual buses 21 to 23.

  Specifically, there are an inter-module bus 21, a parameter bus 22, and a temporary data 23.

The system of the present invention is composed of a plurality of function (arithmetic) modules, a memory, an overall operation control unit, and the like, and the configuration of the bus necessary for data transfer is as in the ninth embodiment. Can do. In other words, data can be transferred via a plurality of buses, and the time required to transfer data necessary for each function (arithmetic) module can be shortened. That is, a bus for transferring data for each type of data, such as data exchange between modules (21), parameter read / write (22), and temporary data (previous value in internal calculation, etc.) (23). have.
Example 10
FIG. 25 is a diagram showing a device configuration of Embodiment 10 according to the present invention.

  The tenth embodiment includes a shared bus 9 that connects at least the input unit 2, the functional module 3, and the module selection / control unit 4, and the shared bus 9 includes a plurality of types of data handled in signal processing. It is characterized by comprising a single bus 24 for transferring the data in a time-sharing manner.

In other words, data is transferred through a single bus. In other words, in order to reduce the circuit scale of the bus for passing the necessary data to each function (arithmetic) module, it is configured with one bus and used in time division to deliver all types of data. To do.
Example 11
FIG. 26 is an apparatus configuration diagram for explaining Example 11 according to the present invention.
FIG. 27A is a time chart illustrating processing operations not according to the eleventh embodiment, and FIG. 27B is a time chart illustrating processing operations according to the eleventh embodiment.

  In the eleventh embodiment, when at least two functional modules 3A and 3B are sequentially selected ("1" → "2") and each signal processing is executed, during the signal processing in the preceding functional module 3A, The parameter information to be used in the function module 3B in the row is acquired, and immediately after the signal processing in the preceding function module 3A is completed, the function module 3B in the subsequent row uses the acquired parameter information. The signal processing is started.

  Considering the data input / output method in the functional module of the present invention, it is necessary to read the configuration data every time in order to switch the operation for each input signal IN. However, if it takes time for this operation, the operation speed of the entire system is reduced. A first method for realizing this with a small number of clocks is the eleventh embodiment. This is a method for the case where the same module is not used continuously.

Referring particularly to FIG. 27 (b), when setting a module, a module A that performs the current process and a module B that performs the next process are specified as a pair. After the parameter setting for the current module A is completed, the parameter setting for the next module B is started immediately (time t1), so that the parameter setting for the next module B is omitted after the current module A processing is completed. The time can be reduced. That is, when the module A is used when performing the current process and then the module B is used, parameters necessary for the module A are transmitted by the control bus 9c (FIG. 26). Thereafter, the data is read from the data bus 9d (FIG. 26) to perform arithmetic processing. In this case, since the control bus 9c is not used during the calculation of the module A, the parameters for the module B can be set during the calculation of the module A. Thereby, when the calculation result is output from the module A, the module B can start the operation immediately.
Example 12
FIG. 28 is an apparatus configuration diagram for explaining Example 12 of the present invention.
FIG. 29A is a time chart illustrating processing operations not according to the twelfth embodiment, and FIG. 29B is a time chart illustrating processing operations according to the twelfth embodiment.

  In the twelfth embodiment, when the first signal processing “1” and the second signal processing “2” are sequentially executed sequentially in the same functional module (for example, A in FIG. 18), the first signal processing “ During execution of “1”, parameter information to be used in the second signal processing “2” is acquired, and immediately after the completion of the first signal processing “1”, the acquired parameter information is used. The second signal processing “2” is started.

  This is a case where the same module is continuously used. Each module 3 has a plurality of parameter storage registers 26, and after the current parameter setting value of the module A is taken in, the next parameter setting is continuously performed. It is. When the module A performs the next process, the setting is completed immediately by switching the register 26, so that the setting time can be shortened.

Depending on the process, the same module may be used multiple times, but if the setting parameters are different, it is necessary to discard the previously used parameters and set new parameters. Therefore, first, the parameter of the first module A is transmitted, and during the calculation process, the second parameter is transmitted from the vacant control bus 9c, and the parameter is stored in a plurality of registers 26 for storage. Save the value. When the module A performs the second calculation, it is not necessary to perform a bus access for fetching the parameter value, so that the operation can be performed with a small number of clocks. During the second operation of module A, another register 26 can be written, so that a free control bus 9c can be used. Therefore, even when the same module is used three times or more, it can be operated with a small number of clocks.
Example 13
FIG. 30 is an apparatus configuration diagram for explaining an embodiment 13 in accordance with the present invention.

  In the thirteenth embodiment, when the output data obtained in the first signal processing described above is returned to the functional module 3 and used for the second signal processing described above, the output data is not sent out of the functional module. For example, the gate 25 is opened by an enable signal EN and returned by a signal path 27 in the functional module. Note that BD is a bus driver.

In the thirteenth embodiment, the same module is continuously used as in the twelfth embodiment. Once the output value is output to the bus 9, <1> the data bus 9d is output, and <2> the data bus 9d is input. It is necessary to access the data bus. Therefore, when the same module 3 is used a plurality of times, a wiring (27) coupled internally is provided, and the bus 9 is not used for data input / output. Naturally, the processing speed is improved.
Example 14
FIG. 31 is an apparatus configuration diagram for explaining an embodiment 14 in accordance with the present invention.

  Example 14 and Examples 15 and 16 to be described later include a low-speed communication line 28 and a high-speed communication line 29 as communication lines for transmitting a processing result by signal processing to the external host device 10. It is characterized by.

  More specifically, the low-speed communication line 28 is a communication line that performs the above transmission at a fixed period when the transmission request REQ1 is received from the host device 10, while the high-speed communication line 29 is transmitted from the host device 10. This is a communication line that performs the above transmission in response to a transmission request REQ2.

In this way, the data transmitted at a fixed period and the data transmitted when requested from the outside (10) do not overlap, and the communication speed, the amount of communication data, and the like can be suppressed.
Example 15
According to the fifteenth embodiment, the low-speed communication line 28 and the high-speed communication line 29 are each configured by a parallel line.

  The fifteenth embodiment is a case having a parallel port output interface (I / F), and the I / F that outputs the processing result of the system (1) to the outside (10) is constituted by a parallel port, and the outside (10 ) Can be used to extract arbitrary data by designating a signal (address, ID code, etc.) that can identify the data to be extracted.

In this embodiment, communication can be performed at high speed, and the clock speed of the communication line can be suppressed.
Example 16
According to the sixteenth embodiment, the low-speed communication line 28 and the high-speed communication line 29 are each constituted by a serial line.

  The sixteenth embodiment has a serial port output interface I / F. Since the I / F that outputs the processing result of the system (1) to the outside (10) is composed of a serial port, the outside ( From 10), a signal for identifying the data to be extracted is received and the corresponding data is output, or the data is output in a predetermined order.

In the case of this embodiment, the number of communication lines can be suppressed.
Example 17
FIG. 32 is an apparatus configuration diagram for explaining Example 17 according to the present invention.
FIG. 33 is a diagram showing a communication data format on the communication line 30 of FIG.

  The output unit 8 (see FIG. 1) according to the seventeenth embodiment uses an ID indicating which of the plurality of channels (CH1, CH2,...) Is the processing result for the input signal IN as the processing result. Further, the data is further added to the data and transmitted.

  The ID is shown as “ID code” at the left end of the lower column of FIG.

  According to the seventeenth embodiment, it is possible to identify which input signal is the result of processing, and therefore it is not necessary to determine the transmission order.

  Further, only necessary data can be output to the host device 10.

Referring to FIG. 32, the processing result data from each functional module 3 is once captured by the processing result capturing unit 32. At this time, the selection / control unit 4 knows which channel's input signal the processing result currently taken in, and transmits the channel signal to the ID code generation unit 31. This ID code indicates the channel, which is added to the data of the fetched processing result in the transmission unit 33 and further transmitted to the communication line 30.
Example 18
FIG. 34 is an apparatus configuration diagram for explaining Example 18 according to the present invention.

  The eighteenth embodiment provides the same effect as the seventeenth embodiment described above, but in this eighteenth embodiment, the output unit 8 (see FIG. 1) outputs the processing results for the input signals of a plurality of channels to the respective output signals. The transmission is performed sequentially according to the transmission order assigned to the channels.

  According to the eighteenth embodiment, there is no need to add data for identifying which input signal IN is the result of processing, and only the processing result needs to be transmitted. Further, the amount of transmission data can be reduced to the extent that the ID code is no longer required.

Referring to FIG. 34, the difference from FIG. 32 is that a transmission order storage memory 34 has been introduced. When the means 4 instructs the start of transmission, the acquisition unit 32 has a predetermined transmission order in the memory 34. Are sent to the communication line 30.
Example 19
FIG. 35 is an apparatus configuration diagram for explaining an embodiment 19 in accordance with the present invention.

  Example 19 and Examples 20 to 23 to be described later deal with a case where it is required to always process with accurate data even when a failure occurs in the system. Can be maintained.

  First, in the nineteenth embodiment, the shared bus 9 for connecting at least a plurality of functional modules 3 is provided, and when the plurality of functional modules 3 are defined as an active function module group 41, the active function module group 41 and a mirror are provided. When the spare function module group 42 is connected via the shared bus 9 and it is determined that any function module 3 (for example, A) in the active function module group 41 has a failure, the spare function module group 42 The corresponding functional module 3 '(A) is selected and used.

  That is, when two or more of the same modules are connected as spares to the shared bus 9 and the receiver side (for example, the host device 10) or itself (1) detects a failure of the system, the failure is immediately caused. The use of the module (A) determined to be stopped is stopped, and the spare module is used.

Referring to FIG. 35, when “abnormality detection” occurs, the sequencer 43 issues a command for instructing which module should be used for signal processing. In the example of this figure, since an abnormality is detected in the current module 3A, only this (3A) is replaced with a spare module 3 '(A).
Example 20
FIG. 36 is an apparatus configuration diagram for explaining an embodiment 20 of the present invention.

In the twentieth embodiment, a shared bus 9 for connecting at least a plurality of function modules 3 is provided, and when these function modules 3 are defined as an active function module group 41, a spare functioning as a mirror with the active function module group 41 is provided. When the functional module group 42 is connected via the shared bus 9 and it is determined that any functional module 3 (for example, A) in the active functional module group 41 has a failure, the functional module group 42 is switched to the spare functional module group 42. It is characterized by being used. In other words, all the currently used modules 3 in use are replaced with the spare module 3 '.
Example 21
In the twenty-first embodiment, when the signal processing in the digital signal processing device 1 is finished, a record about the functional module having a failure is retained, and the recording is also performed when the digital signal processing device 1 is restarted. In addition, a normal function module is selected and used.

That is, even when the system is restarted after the failure is detected after the failure is detected, the failure information can be stored and the module can be operated using the module without the failure.
[Example 22]
In the twenty-second embodiment, when there is an external host device 10 to which a processing result by signal processing is to be transmitted, an ID indicating the module that generated each processing result is added to the data of each processing result and transmitted to the host device 10. The host device 10 determines whether or not there is a failure and receives specific information from the host device 10 that identifies the functional module having the failure.

That is, information (ID code or the like) that can identify the module used for the processing is added to the output data to the receiver side (10), the faulty module is identified on the receiver side (10), Information for switching to the module is transmitted from the receiver side (10) to the apparatus 1.
Example 23
FIG. 37 is a diagram showing various data for explaining Example 23 of the present invention.

  In the twenty-third embodiment, when there is an external host device 10 to which the processing result by the signal processing described above is to be transmitted, the processing sequence information to be held in the sequence memory 6 is read from the host device 10 and when the reading is completed, The host device 10 gives predetermined data to the digital signal processing device 1 and runs the read processing sequence. The host device 10 receives the processing result and compares it with a predetermined expected value to obtain a match. When the data is read, it is confirmed that the reading processing sequence is normal.

  Example 23 and Examples 24 to 26 described later relate to failure diagnosis.

  When the sequence data is read from the outside (10) of the system (1), it is necessary to check whether the sequence data has been received correctly. This is the check method of the twenty-third embodiment. That is, in order to confirm whether or not the sequence data has been downloaded correctly, the predetermined data is used, the sequence is operated one or more times, and the data received on the receiver side (10) is compared with the expected value stored in advance. Take.

  Referring to FIG. 37, reference numeral 44 denotes sequence data transmitted from the host device (receiver side) 10. This sequence is run in the digital signal processing device (system) 1, and the result is sent back to the host device 10 to return the host device. 10 is compared with the processing result expected value data prepared in advance. That is, since the output result when the predetermined data is input can be calculated in advance, it is stored on the receiver side as an expected value, and it is checked whether it matches the actual output result.

Note that the lower left part of FIG. 37 shows the contents of signal processing in the functional module 3. However, this is an example.
Example 24
The twenty-fourth embodiment is characterized in that, in the above-described twenty-third embodiment, when the above-described comparison does not match, the processing sequence information is retransmitted from the host device 10 and the same confirmation is performed again. Thereby, the detection accuracy can be improved.
Example 25
The twenty-fifth embodiment is characterized in that, in the twenty-fourth embodiment, when the above inconsistency is not resolved, an alarm is sent to an external user. The user referred to here is, for example, a driver of a vehicle equipped with the ECU, or a product inspector in a production factory of the ECU or a product inspector in a production factory of a vehicle equipped with the ECU.
Example 26
In the twenty-sixth embodiment, the processing sequence information read from the host device 10 in the twenty-third embodiment is used as it is, and the check means (check program) in the host device 10 or an external device having a function equivalent to the function of this check means is used. It is returned to the apparatus, and when the returned processing sequence information matches the transmitted processing sequence information, it is confirmed that the aforementioned reading processing sequence is normal.
Example 27
FIG. 38 is an apparatus configuration diagram for explaining an embodiment 27 according to the present invention.
FIG. 39 shows an example of the data structure of the data used in FIG.

  Example 27 and Examples 28 to 30 described later relate to failure diagnosis for determining whether or not the functional module 3 has been used correctly.

  First, in the twenty-seventh embodiment, at the end of signal processing in each selected functional module 3, an individual module check bit 47 (FIG. 39) indicating normal termination of the signal processing is set to each functional module (A, B, C). , D) and determining whether or not the functional module 3 is faulty by determining whether or not the bit string matches the expected bit string.

  That is, this is a failure diagnosis method in which a passing module check bit is provided in the data string 46 to determine whether the function module 3 has been used correctly.

  When the module 3 is operated in an arbitrary combination as in the present invention, it is necessary to grasp whether the module 3 to be used is used correctly. However, it is difficult to confirm during actual operation.

  Therefore, in the present invention, a dedicated bit for failure determination is provided, and a module failure or non-passage can be detected by checking when the module passes.

Referring to FIG. 38, after the calculation in each module 3 is completed, when the resulting data is sent to the data bus 9d, each check bit 47 is set.
Example 28
In the twenty-eighth embodiment, the individual module check bit 47 in the twenty-seventh embodiment is replaced with a cumulative module check bit 48.

That is, at the end of the signal processing in each selected function module 3, the accumulated module check bit 48 (FIG. 39) indicating the accumulated value sequentially added or subtracted every time the signal processing is normally completed in each function module 3. And determining whether or not the accumulated value matches the expected accumulated value, thereby determining the failure of the functional module 3.
Example 29
In the twenty-ninth embodiment, when there is an external host device 10 to which the processing result by the signal processing described above is to be transmitted in the twenty-seventh or twenty-eighth embodiment, the expected value of the failure determination described above is transmitted from the host device 10. It is obtained based on a processing sequence.

That is, since the host apparatus 10 instructs which channel (CH1, CH2,...) Which module 3 is to be used, the result of giving it indicates whether the module has been used as instructed. Can check.
Example 30
The thirtieth embodiment is characterized in that the expected value of the failure determination described above in the twenty-seventh or twenty-eighth embodiment is obtained based on the processing sequence that the digital signal processing device 1 originally has.
Example 31
FIG. 40 is a sequence diagram for explaining an embodiment 31 according to the present invention.

  Example 31 and Examples 32 to 35 to be described later relate to failure detection in the digital signal processing apparatus 1 and incorporate a so-called test pattern to detect failure.

In the thirty-first embodiment, a test processing sequence 50 (FIG. 40) is incorporated in the above-described processing sequence information, and the test processing sequence 50 is run at a predetermined cycle, so that a plurality of functional modules 3 It is characterized by performing an operation check. That is, since each process is executed at intervals of time, a sequence for performing a test is incorporated in advance so that the test is executed at regular intervals. The cycle in which the test is performed need not be limited to one cycle of the process 51 necessary for control, and may be executed anywhere in the process. It may be executed a plurality of times.
[Example 32]
FIG. 41 is a sequence diagram for explaining an embodiment 32 according to the present invention.

  In the thirty-second embodiment, a test processing sequence 50 is incorporated in the above-described processing sequence information, and a signal processing pause period is set between two adjacent signal processing (“processing 2” and “processing 3”). When 52 exists, the test processing sequence 50 is run during the suspension period 52 to check the operation of the plurality of functional modules 3.

That is, the test sequence operation is performed when there is a margin in processing. If there is a margin in processing, if there is a time vacancy between processes, the test sequence can be operated using the margin time.
Example 33
FIG. 42 is a sequence diagram for explaining Example 33 according to the present invention.

  In the thirty-third embodiment, when the test processing sequence 50 is incorporated in the processing sequence information described above and a test command (command) is applied from the outside (for example, the host device 10), it coincides with the application timing. The signal processing is stopped (stop period 53), the test processing sequence is forcibly executed, and the operation of the plurality of functional modules 3 is confirmed.

That is, an operation is confirmed by receiving a command (instruction) from outside at an arbitrary timing. During the operation, a test is forcibly executed by an instruction from the outside, and other processing is stopped.
Example 34
FIG. 43 is a sequence diagram for explaining an embodiment 34 according to the present invention.

  In the thirty-fourth embodiment, a test processing sequence 50 is incorporated in the processing sequence information described above, and when a test command (command) is applied from the outside, this is applied to signal processing that matches the application timing. The test process sequence 50 is forcibly executed in advance (arrow 54 in FIG. 43), and the operation of the plurality of functional modules 3 is confirmed.

That is, a command (instruction) is received at an arbitrary timing from the outside to check the operation. During the operation, for example, a test is forcibly executed by an instruction from the host device 10 to delay other processing. Is.
Example 35
FIG. 44 is a sequence diagram for explaining an embodiment 35 according to the present invention.

  In the thirty-fifth embodiment, a test processing sequence 50 is incorporated in the processing sequence information described above, and when a test command is applied from the outside, the test is waited for the arrival of a pause period 52 during which signal processing is paused. The processing sequence 50 is executed, and the operation of a plurality of functional modules 3 is confirmed.

That is, a command (instruction) is received at an arbitrary timing from the outside to check the operation. During the operation, for example, a test is forcibly executed by an instruction from the host device 10, for example, and the next pause period ( The test is executed after waiting for a free time.
Example 36
As described above, various aspects of the digital signal processing apparatus 1 based on the present invention have been described in detail through the first to thirty-fifth embodiments. Here, the present invention will be grasped from another viewpoint.

The technical idea of the present invention can be grasped not only as a device configuration but also as a signal processing technique. The first point is the following point, that is, in the digital signal processing apparatus 1 including at least the input unit 2 and the plurality of functional modules 3.
(I) giving each of the plurality of functional modules 3 a unique signal processing function;
(Ii) Applying an input signal IN for each of a plurality of channels (CH1, CH2,...) Input to the input unit 2 to one or a plurality of functional modules 3 selected for each channel, and performing signal processing; It is in.

further,
A series of processing sequences for designating one or a plurality of functional modules 3 to be used for each channel described above are stored in advance (sequence memory 6), and the series of processing sequences are sequentially read to execute signal processing. To do.

Furthermore, parameter information for modifying the contents of the signal processing in each functional module 3 is held in advance (parameter memory 7), and corresponding parameter information according to the nature of the input signal IN for each channel. Are read out and signal processing is executed.
Example 37
If the technical idea of the present invention shown in the above embodiment 36 is further developed, a digital signal processing system can be further constructed.

  A thirty-seventh embodiment and a thirty-eighth embodiment described below relate to such a digital signal processing system.

  FIG. 45 is a diagram showing a first digital signal processing system according to Embodiment 37 of the present invention.

  The first digital signal processing system 61 according to the thirty-seventh embodiment is provided with a communication interface 66 capable of transmitting and receiving signal processing results to the digital signal processing device 1 described above, and is similar to the digital signal processing device. The digital signal processing system 1 includes a plurality of digital signal processing apparatuses 1 (1-1, 1-2, 1-3,... In FIG. 45), and these are cascade-connected via respective communication interfaces 66.

  Referring to FIG. 45, when there are a plurality of processing apparatuses 1, one is set as a master apparatus 1-1 and the other as slave apparatuses 1-2, 1-3. The devices are connected, and the processing results of all the slave devices 1-2, 1-3,... Are collected in the master device 1-1. Therefore, the processing results from all the devices 1-2, 1-3,... Can be taken out only by connecting only the master device 1-1 to the outside (10).

  When each processing apparatus 1 is an IC, as shown in FIG. 45, each IC has a processing circuit 63 (corresponding to module 3), a memory 64 (for example, corresponding to 13 in FIG. 2), and a data reading circuit 65 (for example, FIG. 2). 14) and the previous communication interface 66, a transmission request is sent from the master IC (1-1) to the processing results of the slave ICs (1-2, 1-3,...). By sending a signal, the processing result data can be read out.

In this way, even if a plurality of ICs (1-1, 1-2, 1-3,...) Are used, the number of communication lines 30 with the external (10) is required for the number of these ICs. Only one system is sufficient. The number of slave ICs is not limited as long as the propagation delay on the signal line 67 allows.
Example 38
FIG. 46 is a diagram showing a second digital signal processing system according to the thirty-eighth embodiment of the present invention.

  The second digital signal processing system 62 according to the thirty-eighth embodiment is provided with a communication interface 68 capable of transmitting and receiving signal processing results to the digital signal processing apparatus 1 described above, and with the digital signal processing apparatus 1. A plurality of similar digital signal processing apparatuses 1 are provided (1-1, 1-2, 1-3 in FIG. 40), one of which is the master digital signal processing apparatus 1-1, and the other is a slave digital. The signal processing devices (1-2, 1-3,...) Are connected in a star connection with the master / digital signal processing device 1-1 as the center through the respective communication interfaces 68. is there.

  Referring to FIG. 46, when there are a plurality of processing apparatuses 1, one is a master apparatus 1-1, the other is a slave apparatus 1-2, 1-3..., And each apparatus using a star connection line 69. (1-1, 1-2, 1-3,...) Are connected, and the processing results of all the slave devices 1-2, 1-3,. Therefore, the processing results from all the devices 1-2, 1-3,... Can be taken out only by connecting only the master device 1-1 to the outside (10).

here,
When each processing apparatus 1 is an IC, as shown in FIG. 46, each IC has the above-described circuits 63, 64, 65 and the previous communication interface 68. From the master IC (1-1), By directly sending a transmission request signal for the processing result of each slave IC, the data of the processing result can be read out.

In this way, even if a plurality of ICs (1-1, 1-2, 1-3,...) Are used, the number of communication lines 30 with the external (10) is required for the number of these ICs. Only one system is sufficient. Further, the results of any IC can be acquired at the same response speed as compared to the system 61 (FIG. 45).
Example 39
Examples 1 to 38 so far have been mainly directed to a preprocessing IC (digital signal processing device 1), for example, referring to FIG.

  This embodiment 39 and embodiments 40 to 42 described later are directed to the microcomputer (host device 10) itself with reference to FIG.

  FIG. 47 is a flowchart showing the operation of the host device 10 according to the embodiment 39 of the present invention.

  The 39th embodiment and the 40th embodiment described below are mainly for realizing fail-safe.

  Even when the system, for example, the ECU of FIG. 4 fails, it is necessary to perform the minimum necessary operation. For example, when the ECU is used for engine control of an automobile, even if optimal fuel injection control or the like cannot be performed if the ECU fails, it is sufficient if an operation that can somehow reach the repair shop is possible. In such a case, the data in the process may not necessarily be an accurate value.

  Whether or not the value output from the device 1 is normal is determined by the host device 10 on the receiving side, and when it is determined that there is an abnormality, the abnormality is notified to the device 1 from the receiving side (10). Thereafter, the product (automobile) in which the apparatus 1 is mounted can ensure the minimum necessary operation.

  FIG. 47 shows that for the data determined to be abnormal, the output value from the apparatus 1 is discarded and the default value prepared in advance by the receiver apparatus 10 is used.

  That is, the host device 10 according to the thirty-ninth embodiment is a host device that receives processing result data by signal processing transmitted from the digital signal processing device 1 described above. Is used, and instead of this, a default value held in advance is used.

Referring to FIG.
Step S11: The host device 10 receives the data N transmitted from the device 1. The data N is data calculated by the signal processing N (N = 1, 2, 3, 4,...) Described above.

Step S12: If the host device 10 determines that the data N is within the normal range (YES),
Step S13: The host device 10 performs a predetermined calculation process using the data N.

  Step S14: If the result of step S12 is NO, the received data N is discarded, and the predetermined calculation process is performed using the default value D instead. The point of the embodiment 39 is in this step S14.

Step S15: Further, the data (N + 1) is received and the next calculation process is started.
Example 40
FIG. 48 is a flowchart showing the operation of the host apparatus 10 in the embodiment 40 of the invention.
FIG. 49 is a flowchart showing the operation of the signal processing apparatus 1 in cooperation with the operation of FIG.

  48 and FIG. 49, the default value of the output value is output from the apparatus 1 by informing the apparatus side (1) from the receiver side (10) which output value is determined to be abnormal. Represents what to do.

  That is, when the host apparatus 10 according to the fortieth embodiment is a host apparatus that receives processing result data by signal processing transmitted from the digital signal processing apparatus 1 described above, and determines that the processing result data is abnormal. The signal processing that caused the abnormal data is specified, the specified information is returned to the signal processing device 1, and the default value D previously stored in the device 1 corresponding to the specified signal processing is specified. To use.

  Referring to FIG. 48, step S21 is a feature of the present embodiment 40. The “notification” in S21 activates the flowchart of FIG.

Referring to FIG.
Step S31: The device 1 receives a signal transmitted from the host device 10 that is the recipient of the processing result.

Step S32: It is determined whether the received signal is an abnormal signal due to step S21 in FIG.
Step S33: The processing sequence described above (for example, refer to the processing order 1, 2, 3,... In FIG. 14) for processing the data N determined by the host device 10 as abnormal is based on the subsequent processing sequence. As a processing result, a default value prepared in advance in the apparatus 1 is output.

Step S34: The apparatus 1 enters a further subsequent processing sequence.
Example 41
The forty-first embodiment corresponds to the above-described twenty-second embodiment, but the host apparatus 10 in the forty-first embodiment receives data of the processing result by the signal processing transmitted from the digital signal processing apparatus 1 described above. The host device receives an ID indicating the functional module 3 that has generated each processing result and is transmitted from the device 1 in addition to each processing result data. When it is determined that a certain functional module 3 (for example, B) has a failure, the ID of the functional module (B) is transmitted to the apparatus 1 to identify the failure location.
Example 42
The last example 42 corresponds to the example 23 described above, but the host device 10 in this example 42 receives the data of the processing result by the signal processing transmitted from the digital signal processing device 1 described above. A host apparatus that receives the above-described processing sequence information for designating one or a plurality of functional modules 3 to be selected corresponding to each channel (CH1, CH2,...) Is transmitted to the apparatus 1 for reading. Further, predetermined data is transmitted to execute the processing sequence. The apparatus 10 receives the processing result data from the apparatus 1 and compares it with a predetermined expected value. The normality of the read processing sequence information is determined based on the comparison result.

  The digital signal processing circuit according to the present invention can be used in a system that needs to perform desired signal processing on a plurality of types of input signals using a plurality of types of functional modules. In this case, a single IC can flexibly handle any combination of input signals and functional modules.

It is a figure which shows the basic composition of the digital signal processing apparatus based on this invention. It is a figure which shows more specifically the basic composition of FIG. It is a time chart for demonstrating the processing operation of FIG. It is a figure which shows 1 system example to which this invention is applied. It is a figure which shows the writing means based on this invention which should be added with respect to FIG. It is a figure which shows the selection / control means 4 shown in FIG. 2 and its periphery more concretely. It is a figure which shows the example of the input signal of each channel, and the example of the functional module which processes it. It is a flowchart which shows the operation example of the selection / control means 4 shown in FIG. It is a time chart corresponding to the flowchart of FIG. It is a figure showing an example of a channel processing order. It is a device block diagram for demonstrating Example 1 by this invention. It is a figure which shows the content of the sequence memory 6 of FIG. It is a time chart which shows the processing operation based on the processing sequence of FIG. It is a figure which shows the content of the sequence memory 6 for demonstrating Example 2 by this invention. It is a time chart which shows the processing operation based on the processing sequence of FIG. It is an apparatus block diagram for demonstrating Example 3 by this invention. It is a figure which shows the content of the sequence memory 6 of FIG. It is a time chart which shows the processing operation based on the processing sequence of FIG. It is a processing operation time chart for demonstrating Example 4 by this invention. It is a processing operation time chart for explaining Example 5 by the present invention. It is an apparatus block diagram of Example 6 by this invention. It is a figure which shows the content of the parameter memory 7 of FIG. It is an apparatus block diagram of Example 7 by this invention. It is a figure which shows the apparatus structure of Example 9 by this invention. It is a figure which shows the apparatus structure of Example 10 by this invention. It is an apparatus block diagram for demonstrating Example 11 by this invention. (A) is a time chart showing processing operations not according to the eleventh embodiment, and (b) is a time chart showing processing operations according to the eleventh embodiment. It is an apparatus block diagram for demonstrating Example 12 by this invention. (A) is a time chart showing a processing operation not according to the twelfth embodiment, and (b) is a time chart showing a processing operation according to the twelfth embodiment. It is an apparatus block diagram for demonstrating Example 13 by this invention. It is an apparatus block diagram for demonstrating Example 14 by this invention. It is an apparatus block diagram for demonstrating Example 17 by this invention. It is a figure which shows the communication data format on the communication line 30 of FIG. It is an apparatus block diagram for demonstrating Example 18 by this invention. It is an apparatus block diagram for demonstrating Example 19 by this invention. It is an apparatus block diagram for demonstrating Example 20 by this invention. It is a figure which shows the various data for demonstrating Example 23 by this invention. It is an apparatus block diagram for demonstrating Example 27 by this invention. It is a figure which shows an example of the data structure of the data used in FIG. It is a sequence diagram for demonstrating Example 31 by this invention. It is a sequence diagram for demonstrating Example 32 by this invention. It is a sequence diagram for demonstrating Example 33 by this invention. It is a sequence diagram for demonstrating Example 34 by this invention. It is a sequence diagram for demonstrating Example 35 by this invention. It is a figure which shows the 1st digital signal processing system by Example 37 of this invention. It is a figure which shows the 2nd digital signal processing system by Example 38 of this invention. It is a flowchart showing operation | movement of the host apparatus 10 in Example 39 of this invention. It is a flowchart showing operation | movement of the host apparatus 10 in Example 40 of this invention. It is a flowchart showing operation | movement of the signal processing apparatus 1 cooperated with operation | movement of FIG.

Explanation of symbols

DESCRIPTION OF SYMBOLS 1 ... Digital signal processor 2 ... Input part 3 ... Function module 4 ... Selection / control means 5 ... Memory means 6 ... Sequence memory 7, 7A, 7B, 7C ... Parameter memory 8 ... Output part 9 ... Shared bus 10 ... Host device (Microcomputer)
11 ... Separation part (MPX)
DESCRIPTION OF SYMBOLS 12 ... AD conversion part 13 ... Processing result buffer 14 ... Output distribution part 15 ... Interrupt processing sequence 21, 22, 23 ... Individual bus 24 ... Single bus 26 ... Parameter storage register 27 ... Signal path 28 ... Low-speed communication line 29 ... high-speed communication line 30 ... communication line 41 ... active module group 42 ... spare module group 47 ... individual module check bit 50 ... test processing sequence 52 ... pause period 53 ... stop period 61 ... first digital signal processing system 62 ... Second digital signal processing system 66 ... communication interface 67 ... cascade connection line 68 ... communication interface 69 ... star connection line 71 ... sequence writing means 72 ... parameter writing means 73 ... sequence memory 74 ... parameter memory 75 ... channel order memory 81 ... Memory read 82 ... module control unit

Claims (18)

An input unit for receiving each input signal from a plurality of channels;
A plurality of functional modules, each of which is capable of receiving a signal from the input unit in common, and performing signal processing with a function specific to each of the signals received in a predetermined order;
Module selection / control means for sequentially selecting one or a plurality of the functional modules corresponding to each of the plurality of channels and causing the selected functional modules to perform signal processing of the input signal;
A digital signal processing apparatus comprising:   The memory means further includes a sequence memory that holds rewritable processing sequence information for designating the one or more functional modules to be selected corresponding to each channel. The digital signal processing apparatus according to claim 1.   2. The digital memory according to claim 1, further comprising a memory unit, wherein the memory unit includes a parameter memory that rewrites and retains parameter information for modifying the content of the signal processing in each functional module. Signal processing device.   The digital signal processing apparatus according to claim 1, further comprising a channel order memory that holds processing order information of each signal to be subjected to the signal processing.   The module selection / control means selects the functional module to be selected for each channel according to a specified series of processing sequences, and when a new interrupt input signal is generated as the input signal, the module selection / control means is specified. 2. The digital signal processing apparatus according to claim 1, wherein an interrupt processing sequence is inserted into the series of processing sequences.   A shared bus that connects at least the input unit, the functional module, and the module selection / control unit, and the shared bus is a plurality of individual buses separated for each data type handled in the signal processing The digital signal processing apparatus according to claim 1, comprising:   A shared bus connecting at least the input unit, the functional module, and the module selection / control unit, and the shared bus transfers a plurality of types of data handled in the signal processing in a time-sharing manner The digital signal processing apparatus according to claim 1, comprising a single bus.   An output unit that transmits the processing result of the signal processing to the outside; and the output unit includes an ID indicating a processing result for the input signal from which of the plurality of channels, the ID The digital signal processing apparatus according to claim 1, wherein the digital signal processing apparatus further transmits the processed result data.   An output unit configured to transmit the processing result of the signal processing to the outside; and the output unit sequentially transmits the processing result for each of the input signals of the plurality of channels according to a transmission order assigned to each of the channels. The digital signal processing apparatus according to claim 1.   A shared bus connecting at least the plurality of functional modules is provided, and when the plurality of functional modules are defined as an active function module group, a spare function module group that forms a mirror with the active function module group is provided via the shared bus. 2. When one of the function modules in the active function module group is determined to be faulty, the corresponding function module in the spare function module group is selected and used. A digital signal processing apparatus according to 1.   A shared bus connecting at least the plurality of functional modules is provided, and when the plurality of functional modules are defined as an active function module group, a spare function module group that forms a mirror with the active function module group is provided via the shared bus. 2. The digital signal processing device according to claim 1, wherein, when it is determined that there is a failure in any of the function modules in the active function module group, the digital signal processing apparatus is used by switching to the spare function module group. .   The digital signal processing device according to claim 1, wherein a communication interface capable of transmitting and receiving the processing result of the signal processing is provided, and a plurality of digital signal processing devices similar to the digital signal processing device are provided, and each of the communication A digital signal processing system characterized by cascading them through an interface.   The digital signal processing device according to claim 1, wherein a communication interface capable of transmitting and receiving the processing result of the signal processing is provided, and a plurality of digital signal processing devices similar to the digital signal processing device are provided. The master digital signal processing device and the others are slave digital signal processing devices, and these are star-connected with the master digital signal processing device as a center through the respective communication interfaces. Digital signal processing system. In a digital signal processing device comprising at least an input unit and a plurality of functional modules,
Each of the plurality of functional modules has a unique signal processing function,
A digital signal processing method, wherein an input signal for each of a plurality of channels input to the input unit is provided to one or a plurality of the functional modules selected corresponding to each channel to perform signal processing. A host device that receives data of a processing result by the signal processing transmitted from the digital signal processing device is further added to the digital signal processing device according to claim 1,
When the host device has an abnormality in the processing result data , the host device discards the data and uses a default value stored in advance instead of the data . A host device that receives data of a processing result by the signal processing transmitted from the digital signal processing device is further added to the digital signal processing device according to claim 1,
When the host device determines that the data of the processing result is abnormal , the host device identifies the signal processing that caused the abnormal data, and returns the identification information to the digital signal processing device to identify the data. A digital signal processing apparatus that uses a default value stored in advance corresponding to the signal processing . A host device that receives data of a processing result by the signal processing transmitted from the digital signal processing device is further added to the digital signal processing device according to claim 1,
The host device receives an ID indicating the functional module that generated each processing result, which is transmitted from the digital signal processing device in addition to each processing result data, and there is a failure in the functional module. when it is determined, a digital signal processor, characterized in that to identify the fault location by sending the ID of the function module to the digital signal processor. A host device that receives data of a processing result by the signal processing transmitted from the digital signal processing device is further added to the digital signal processing device according to claim 1,
The host device transmits processing sequence information for designating the one or more functional modules to be selected corresponding to each channel to the digital signal processing device, and further transmits predetermined data. The processing sequence is run, and the data of the processing result is received from the digital signal processing device and compared with a predetermined expected value, thereby determining the normality of the read processing sequence information. Digital signal processing device .

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